1135669Scognet/*	$NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $	*/
2135669Scognet
3139735Simp/*-
4135669Scognet * Copyright (c) 2002 Wasabi Systems, Inc.
5135669Scognet * All rights reserved.
6135669Scognet *
7135669Scognet * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8135669Scognet *
9135669Scognet * Redistribution and use in source and binary forms, with or without
10135669Scognet * modification, are permitted provided that the following conditions
11135669Scognet * are met:
12135669Scognet * 1. Redistributions of source code must retain the above copyright
13135669Scognet *    notice, this list of conditions and the following disclaimer.
14135669Scognet * 2. Redistributions in binary form must reproduce the above copyright
15135669Scognet *    notice, this list of conditions and the following disclaimer in the
16135669Scognet *    documentation and/or other materials provided with the distribution.
17135669Scognet * 3. All advertising materials mentioning features or use of this software
18135669Scognet *    must display the following acknowledgement:
19135669Scognet *	This product includes software developed for the NetBSD Project by
20135669Scognet *	Wasabi Systems, Inc.
21135669Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22135669Scognet *    or promote products derived from this software without specific prior
23135669Scognet *    written permission.
24135669Scognet *
25135669Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26135669Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27135669Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28135669Scognet * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29135669Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30135669Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31135669Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32135669Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33135669Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34135669Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35135669Scognet * POSSIBILITY OF SUCH DAMAGE.
36135669Scognet *
37135669Scognet * $FreeBSD$
38135669Scognet *
39135669Scognet */
40135669Scognet
41236987Simp#ifndef _ARM_XSCALE_I80321REG_H_
42236987Simp#define _ARM_XSCALE_I80321REG_H_
43135669Scognet
44135669Scognet/*
45135669Scognet * Register definitions for the Intel 80321 (``Verde'') I/O processor,
46135669Scognet * based on the XScale core.
47135669Scognet */
48135669Scognet
49135669Scognet/*
50135669Scognet * Base i80321 memory map:
51135669Scognet *
52135669Scognet *	0x0000.0000 - 0x7fff.ffff	ATU Outbound Direct Addressing Window
53135669Scognet *	0x8000.0000 - 0x9001.ffff	ATU Outbound Translation Windows
54135669Scognet *	0x9002.0000 - 0xffff.dfff	External Memory
55135669Scognet *	0xffff.e000 - 0xffff.e8ff	Peripheral Memory Mapped Registers
56135669Scognet *	0xffff.e900 - 0xffff.ffff	Reserved
57135669Scognet */
58135669Scognet
59135669Scognet#define	VERDE_OUT_DIRECT_WIN_BASE	0x00000000UL
60135669Scognet#define	VERDE_OUT_DIRECT_WIN_SIZE	0x80000000UL
61135669Scognet
62135669Scognet#define	VERDE_OUT_XLATE_MEM_WIN_SIZE	0x04000000UL
63135669Scognet#define	VERDE_OUT_XLATE_IO_WIN_SIZE	0x00010000UL
64135669Scognet
65135669Scognet#define	VERDE_OUT_XLATE_MEM_WIN0_BASE	0x80000000UL
66135669Scognet#define	VERDE_OUT_XLATE_MEM_WIN1_BASE	0x84000000UL
67135669Scognet
68135669Scognet#define	VERDE_OUT_XLATE_IO_WIN0_BASE	0x90000000UL
69135669Scognet
70135669Scognet#define	VERDE_EXTMEM_BASE		0x90020000UL
71135669Scognet
72135669Scognet#define	VERDE_PMMR_BASE			0xffffe000UL
73135669Scognet#define	VERDE_PMMR_SIZE			0x00001700UL
74135669Scognet
75135669Scognet/*
76135669Scognet * Peripheral Memory Mapped Registers.  Defined as offsets
77135669Scognet * from the VERDE_PMMR_BASE.
78135669Scognet */
79135669Scognet#define	VERDE_ATU_BASE			0x0100
80135669Scognet#define	VERDE_ATU_SIZE			0x0100
81135669Scognet
82135669Scognet#define	VERDE_MU_BASE			0x0300
83135669Scognet#define	VERDE_MU_SIZE			0x0100
84135669Scognet
85135669Scognet#define	VERDE_DMA_BASE			0x0400
86135669Scognet#define	VERDE_DMA_BASE0			(VERDE_DMA_BASE + 0x00)
87135669Scognet#define	VERDE_DMA_BASE1			(VERDE_DMA_BASE + 0x40)
88135669Scognet#define	VERDE_DMA_SIZE			0x0100
89135669Scognet#define	VERDE_DMA_CHSIZE		0x0040
90135669Scognet
91135669Scognet#define	VERDE_MCU_BASE			0x0500
92135669Scognet#define	VERDE_MCU_SIZE			0x0100
93135669Scognet
94135669Scognet#define	VERDE_PBIU_BASE			0x0680
95135669Scognet#define	VERDE_PBIU_SIZE			0x0080
96135669Scognet
97135669Scognet#define	VERDE_I2C_BASE			0x1680
98135669Scognet#define	VERDE_I2C_BASE0			(VERDE_I2C_BASE + 0x00)
99135669Scognet#define	VERDE_I2C_BASE1			(VERDE_I2C_BASE + 0x20)
100135669Scognet#define	VERDE_I2C_SIZE			0x0080
101135669Scognet#define	VERDE_I2C_CHSIZE		0x0020
102135669Scognet
103135669Scognet/*
104135669Scognet * Address Translation Unit
105135669Scognet */
106135669Scognet	/* 0x00 - 0x38 -- PCI configuration space header */
107135669Scognet#define	ATU_IALR0	0x40	/* Inbound ATU Limit 0 */
108135669Scognet#define	ATU_IATVR0	0x44	/* Inbound ATU Xlate Value 0 */
109135669Scognet#define	ATU_ERLR	0x48	/* Expansion ROM Limit */
110135669Scognet#define	ATU_ERTVR	0x4c	/* Expansion ROM Xlate Value */
111135669Scognet#define	ATU_IALR1	0x50	/* Inbound ATU Limit 1 */
112135669Scognet#define	ATU_IALR2	0x54	/* Inbound ATU Limit 2 */
113135669Scognet#define	ATU_IATVR2	0x58	/* Inbound ATU Xlate Value 2 */
114135669Scognet#define	ATU_OIOWTVR	0x5c	/* Outbound I/O Window Xlate Value */
115135669Scognet#define	ATU_OMWTVR0	0x60	/* Outbound Mem Window Xlate Value 0 */
116135669Scognet#define	ATU_OUMWTVR0	0x64	/* Outbound Mem Window Xlate Value 0 Upper */
117135669Scognet#define	ATU_OMWTVR1	0x68	/* Outbound Mem Window Xlate Value 1 */
118135669Scognet#define	ATU_OUMWTVR1	0x6c	/* Outbound Mem Window Xlate Value 1 Upper */
119135669Scognet#define	ATU_OUDWTVR	0x78	/* Outbound Mem Direct Xlate Value Upper */
120135669Scognet#define	ATU_ATUCR	0x80	/* ATU Configuration */
121135669Scognet#define	ATU_PCSR	0x84	/* PCI Configuration and Status */
122135669Scognet#define	ATU_ATUISR	0x88	/* ATU Interrupt Status */
123135669Scognet#define	ATU_ATUIMR	0x8c	/* ATU Interrupt Mask */
124135669Scognet#define	ATU_IABAR3	0x90	/* Inbound ATU Base Address 3 */
125135669Scognet#define	ATU_IAUBAR3	0x94	/* Inbound ATU Base Address 3 Upper */
126135669Scognet#define	ATU_IALR3	0x98	/* Inbound ATU Limit 3 */
127135669Scognet#define	ATU_IATVR3	0x9c	/* Inbound ATU Xlate Value 3 */
128135669Scognet#define	ATU_OCCAR	0xa4	/* Outbound Configuration Cycle Address */
129135669Scognet#define	ATU_OCCDR	0xac	/* Outbound Configuration Cycle Data */
130135669Scognet#define	ATU_MSI_PORT	0xb4	/* MSI port */
131135669Scognet#define	ATU_PDSCR	0xbc	/* PCI Bus Drive Strength Control */
132135669Scognet#define	ATU_PCI_X_CAP_ID 0xe0	/* (1) */
133135669Scognet#define	ATU_PCI_X_NEXT	0xe1	/* (1) */
134135669Scognet#define	ATU_PCIXCMD	0xe2	/* PCI-X Command Register (2) */
135135669Scognet#define	ATU_PCIXSR	0xe4	/* PCI-X Status Register */
136135669Scognet
137135669Scognet#define	ATUCR_DRC_ALIAS		(1U << 19)
138135669Scognet#define	ATUCR_DAU2GXEN		(1U << 18)
139135669Scognet#define	ATUCR_P_SERR_MA		(1U << 16)
140135669Scognet#define	ATUCR_DTS		(1U << 15)
141135669Scognet#define	ATUCR_P_SERR_DIE	(1U << 9)
142135669Scognet#define	ATUCR_DAE		(1U << 8)
143135669Scognet#define	ATUCR_BIST_IE		(1U << 3)
144135669Scognet#define	ATUCR_OUT_EN		(1U << 1)
145135669Scognet
146135669Scognet#define	PCSR_DAAAPE		(1U << 18)
147135669Scognet#define	PCSR_PCI_X_CAP		(3U << 16)
148135669Scognet#define	PCSR_PCI_X_CAP_BORING	(0 << 16)
149135669Scognet#define	PCSR_PCI_X_CAP_66	(1U << 16)
150135669Scognet#define	PCSR_PCI_X_CAP_100	(2U << 16)
151135669Scognet#define	PCSR_PCI_X_CAP_133	(3U << 16)
152135669Scognet#define	PCSR_OTQB		(1U << 15)
153135669Scognet#define	PCSR_IRTQB		(1U << 14)
154135669Scognet#define	PCSR_DTV		(1U << 12)
155135669Scognet#define	PCSR_BUS66		(1U << 10)
156135669Scognet#define	PCSR_BUS64		(1U << 8)
157135669Scognet#define	PCSR_RIB		(1U << 5)
158135669Scognet#define	PCSR_RPB		(1U << 4)
159135669Scognet#define	PCSR_CCR		(1U << 2)
160135669Scognet#define	PCSR_CPR		(1U << 1)
161135669Scognet
162135669Scognet#define	ATUISR_IMW1BU		(1U << 14)
163135669Scognet#define	ATUISR_ISCEM		(1U << 13)
164135669Scognet#define	ATUISR_RSCEM		(1U << 12)
165135669Scognet#define	ATUISR_PST		(1U << 11)
166135669Scognet#define	ATUISR_P_SERR_ASRT	(1U << 10)
167135669Scognet#define	ATUISR_DPE		(1U << 9)
168135669Scognet#define	ATUISR_BIST		(1U << 8)
169135669Scognet#define	ATUISR_IBMA		(1U << 7)
170135669Scognet#define	ATUISR_P_SERR_DET	(1U << 4)
171135669Scognet#define	ATUISR_PMA		(1U << 3)
172135669Scognet#define	ATUISR_PTAM		(1U << 2)
173135669Scognet#define	ATUISR_PTAT		(1U << 1)
174135669Scognet#define	ATUISR_PMPE		(1U << 0)
175135669Scognet
176135669Scognet#define	ATUIMR_IMW1BU		(1U << 11)
177135669Scognet#define	ATUIMR_ISCEM		(1U << 10)
178135669Scognet#define	ATUIMR_RSCEM		(1U << 9)
179135669Scognet#define	ATUIMR_PST		(1U << 8)
180135669Scognet#define	ATUIMR_DPE		(1U << 7)
181135669Scognet#define	ATUIMR_P_SERR_ASRT	(1U << 6)
182135669Scognet#define	ATUIMR_PMA		(1U << 5)
183135669Scognet#define	ATUIMR_PTAM		(1U << 4)
184135669Scognet#define	ATUIMR_PTAT		(1U << 3)
185135669Scognet#define	ATUIMR_PMPE		(1U << 2)
186135669Scognet#define	ATUIMR_IE_SERR_EN	(1U << 1)
187135669Scognet#define	ATUIMR_ECC_TAE		(1U << 0)
188135669Scognet
189135669Scognet#define	PCIXCMD_MOST_1		(0 << 4)
190135669Scognet#define	PCIXCMD_MOST_2		(1 << 4)
191135669Scognet#define	PCIXCMD_MOST_3		(2 << 4)
192135669Scognet#define	PCIXCMD_MOST_4		(3 << 4)
193135669Scognet#define	PCIXCMD_MOST_8		(4 << 4)
194135669Scognet#define	PCIXCMD_MOST_12		(5 << 4)
195135669Scognet#define	PCIXCMD_MOST_16		(6 << 4)
196135669Scognet#define	PCIXCMD_MOST_32		(7 << 4)
197135669Scognet#define	PCIXCMD_MOST_MASK	(7 << 4)
198135669Scognet#define	PCIXCMD_MMRBC_512	(0 << 2)
199135669Scognet#define	PCIXCMD_MMRBC_1024	(1 << 2)
200135669Scognet#define	PCIXCMD_MMRBC_2048	(2 << 2)
201135669Scognet#define	PCIXCMD_MMRBC_4096	(3 << 2)
202135669Scognet#define	PCIXCMD_MMRBC_MASK	(3 << 2)
203135669Scognet#define	PCIXCMD_ERO		(1U << 1)
204135669Scognet#define	PCIXCMD_DPERE		(1U << 0)
205135669Scognet
206135669Scognet#define	PCIXSR_RSCEM		(1U << 29)
207135669Scognet#define	PCIXSR_DMCRS_MASK	(7 << 26)
208135669Scognet#define	PCIXSR_DMOST_MASK	(7 << 23)
209135669Scognet#define	PCIXSR_COMPLEX		(1U << 20)
210135669Scognet#define	PCIXSR_USC		(1U << 19)
211135669Scognet#define	PCIXSR_SCD		(1U << 18)
212135669Scognet#define	PCIXSR_133_CAP		(1U << 17)
213135669Scognet#define	PCIXSR_32PCI		(1U << 16)	/* 0 = 32, 1 = 64 */
214135669Scognet#define	PCIXSR_BUSNO(x)		(((x) & 0xff00) >> 8)
215135669Scognet#define	PCIXSR_DEVNO(x)		(((x) & 0xf8) >> 3)
216135669Scognet#define	PCIXSR_FUNCNO(x)	((x) & 0x7)
217135669Scognet
218135669Scognet/*
219135669Scognet * Memory Controller Unit
220135669Scognet */
221135669Scognet#define	MCU_SDIR		0x00	/* DDR SDRAM Init. Register */
222135669Scognet#define	MCU_SDCR		0x04	/* DDR SDRAM Control Register */
223135669Scognet#define	MCU_SDBR		0x08	/* SDRAM Base Register */
224135669Scognet#define	MCU_SBR0		0x0c	/* SDRAM Boundary 0 */
225135669Scognet#define	MCU_SBR1		0x10	/* SDRAM Boundary 1 */
226135669Scognet#define	MCU_ECCR		0x34	/* ECC Control Register */
227135669Scognet#define	MCU_ELOG0		0x38	/* ECC Log 0 */
228135669Scognet#define	MCU_ELOG1		0x3c	/* ECC Log 1 */
229135669Scognet#define	MCU_ECAR0		0x40	/* ECC address 0 */
230135669Scognet#define	MCU_ECAR1		0x44	/* ECC address 1 */
231135669Scognet#define	MCU_ECTST		0x48	/* ECC test register */
232135669Scognet#define	MCU_MCISR		0x4c	/* MCU Interrupt Status Register */
233135669Scognet#define	MCU_RFR			0x50	/* Refresh Frequency Register */
234135669Scognet#define	MCU_DBUDSR		0x54	/* Data Bus Pull-up Drive Strength */
235135669Scognet#define	MCU_DBDDSR		0x58	/* Data Bus Pull-down Drive Strength */
236135669Scognet#define	MCU_CUDSR		0x5c	/* Clock Pull-up Drive Strength */
237135669Scognet#define	MCU_CDDSR		0x60	/* Clock Pull-down Drive Strength */
238135669Scognet#define	MCU_CEUDSR		0x64	/* Clock En Pull-up Drive Strength */
239135669Scognet#define	MCU_CEDDSR		0x68	/* Clock En Pull-down Drive Strength */
240135669Scognet#define	MCU_CSUDSR		0x6c	/* Chip Sel Pull-up Drive Strength */
241135669Scognet#define	MCU_CSDDSR		0x70	/* Chip Sel Pull-down Drive Strength */
242135669Scognet#define	MCU_REUDSR		0x74	/* Rx En Pull-up Drive Strength */
243135669Scognet#define	MCU_REDDSR		0x78	/* Rx En Pull-down Drive Strength */
244135669Scognet#define	MCU_ABUDSR		0x7c	/* Addr Bus Pull-up Drive Strength */
245135669Scognet#define	MCU_ABDDSR		0x80	/* Addr Bus Pull-down Drive Strength */
246135669Scognet#define	MCU_DSDR		0x84	/* Data Strobe Delay Register */
247135669Scognet#define	MCU_REDR		0x88	/* Rx Enable Delay Register */
248135669Scognet
249135669Scognet#define	SDCR_DIMMTYPE		(1U << 1)	/* 0 = unbuf, 1 = reg */
250135669Scognet#define	SDCR_BUSWIDTH		(1U << 2)	/* 0 = 64, 1 = 32 */
251135669Scognet
252135669Scognet#define	SBRx_TECH		(1U << 31)
253135669Scognet#define	SBRx_BOUND		0x0000003f
254135669Scognet
255135669Scognet#define	ECCR_SBERE		(1U << 0)
256135669Scognet#define	ECCR_MBERE		(1U << 1)
257135669Scognet#define	ECCR_SBECE		(1U << 2)
258135669Scognet#define	ECCR_ECCEN		(1U << 3)
259135669Scognet
260135669Scognet#define	ELOGx_SYNDROME		0x000000ff
261135669Scognet#define	ELOGx_ERRTYPE		(1U << 8)	/* 1 = multi-bit */
262135669Scognet#define	ELOGx_RW		(1U << 12)	/* 1 = write error */
263135669Scognet	/*
264135669Scognet	 * Dev ID	Func		Requester
265135669Scognet	 * 2		0		XScale core
266135669Scognet	 * 2		1		ATU
267135669Scognet	 * 13		0		DMA channel 0
268135669Scognet	 * 13		1		DMA channel 1
269135669Scognet	 * 26		0		ATU
270135669Scognet	 */
271135669Scognet#define	ELOGx_REQ_DEV(x)	(((x) >> 19) & 0x1f)
272135669Scognet#define	ELOGx_REQ_FUNC(x)	(((x) >> 16) & 0x3)
273135669Scognet
274135669Scognet#define	MCISR_ECC_ERR0		(1U << 0)
275135669Scognet#define	MCISR_ECC_ERR1		(1U << 1)
276135669Scognet#define	MCISR_ECC_ERRN		(1U << 2)
277135669Scognet
278135669Scognet/*
279135669Scognet * Timers
280135669Scognet *
281135669Scognet * The i80321 timer registers are available in both memory-mapped
282135669Scognet * and coprocessor spaces.  Most of the registers are read-only
283135669Scognet * if memory-mapped, so we access them via coprocessor space.
284135669Scognet *
285135669Scognet *	TMR0	cp6 c0,1	0xffffe7e0
286135669Scognet *	TMR1	cp6 c1,1	0xffffe7e4
287135669Scognet *	TCR0	cp6 c2,1	0xffffe7e8
288135669Scognet *	TCR1	cp6 c3,1	0xffffe7ec
289135669Scognet *	TRR0	cp6 c4,1	0xffffe7f0
290135669Scognet *	TRR1	cp6 c5,1	0xffffe7f4
291135669Scognet *	TISR	cp6 c6,1	0xffffe7f8
292135669Scognet *	WDTCR	cp6 c7,1	0xffffe7fc
293135669Scognet */
294135669Scognet
295135669Scognet#define	TMRx_TC			(1U << 0)
296135669Scognet#define	TMRx_ENABLE		(1U << 1)
297135669Scognet#define	TMRx_RELOAD		(1U << 2)
298135669Scognet#define	TMRx_CSEL_CORE		(0 << 4)
299135669Scognet#define	TMRx_CSEL_CORE_div4	(1 << 4)
300135669Scognet#define	TMRx_CSEL_CORE_div8	(2 << 4)
301135669Scognet#define	TMRx_CSEL_CORE_div16	(3 << 4)
302135669Scognet
303135669Scognet#define	TISR_TMR0		(1U << 0)
304135669Scognet#define	TISR_TMR1		(1U << 1)
305135669Scognet
306135669Scognet#define	WDTCR_ENABLE1		0x1e1e1e1e
307135669Scognet#define	WDTCR_ENABLE2		0xe1e1e1e1
308135669Scognet
309135669Scognet/*
310135669Scognet * Interrupt Controller Unit.
311135669Scognet *
312135669Scognet *	INTCTL	cp6 c0,0	0xffffe7d0
313135669Scognet *	INTSTR	cp6 c4,0	0xffffe7d4
314135669Scognet *	IINTSRC	cp6 c8,0	0xffffe7d8
315135669Scognet *	FINTSRC	cp6 c9,0	0xffffe7dc
316135669Scognet *	PIRSR			0xffffe1ec
317135669Scognet */
318135669Scognet
319135669Scognet#define	ICU_PIRSR		0x01ec
320135669Scognet#define	ICU_GPOE		0x07c4
321135669Scognet#define	ICU_GPID		0x07c8
322135669Scognet#define	ICU_GPOD		0x07cc
323135669Scognet
324135669Scognet/*
325135669Scognet * NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE
326135669Scognet * INTERRUPTS.  See i80321_icu.c
327135669Scognet */
328135669Scognet#define	ICU_INT_HPI		31	/* high priority interrupt */
329135669Scognet#define	ICU_INT_XINT0		27	/* external interrupts */
330135669Scognet#define	ICU_INT_XINT(x)		((x) + ICU_INT_XINT0)
331135669Scognet#define	ICU_INT_bit26		26
332161592Scognet
333161592Scognet/* CPU_XSCALE_80321 */
334295201Smmel#define	ICU_INT_SSP		25	/* SSP serial port */
335161592Scognet
336135669Scognet#define	ICU_INT_MUE		24	/* msg unit error */
337161592Scognet
338161592Scognet/* CPU_XSCALE_80321 */
339295201Smmel#define	ICU_INT_AAUE		23	/* AAU error */
340161592Scognet
341135669Scognet#define	ICU_INT_bit22		22
342135669Scognet#define	ICU_INT_DMA1E		21	/* DMA Ch 1 error */
343135669Scognet#define	ICU_INT_DMA0E		20	/* DMA Ch 0 error */
344135669Scognet#define	ICU_INT_MCUE		19	/* memory controller error */
345135669Scognet#define	ICU_INT_ATUE		18	/* ATU error */
346135669Scognet#define	ICU_INT_BIUE		17	/* bus interface unit error */
347135669Scognet#define	ICU_INT_PMU		16	/* XScale PMU */
348135669Scognet#define	ICU_INT_PPM		15	/* peripheral PMU */
349135669Scognet#define	ICU_INT_BIST		14	/* ATU Start BIST */
350135669Scognet#define	ICU_INT_MU		13	/* messaging unit */
351135669Scognet#define	ICU_INT_I2C1		12	/* i2c unit 1 */
352135669Scognet#define	ICU_INT_I2C0		11	/* i2c unit 0 */
353135669Scognet#define	ICU_INT_TMR1		10	/* timer 1 */
354135669Scognet#define	ICU_INT_TMR0		9	/* timer 0 */
355135669Scognet#define	ICU_INT_CPPM		8	/* core processor PMU */
356161592Scognet
357161592Scognet/* CPU_XSCALE_80321 */
358295201Smmel#define	ICU_INT_AAU_EOC		7	/* AAU end-of-chain */
359295201Smmel#define	ICU_INT_AAU_EOT		6	/* AAU end-of-transfer */
360161592Scognet
361135669Scognet#define	ICU_INT_bit5		5
362135669Scognet#define	ICU_INT_bit4		4
363135669Scognet#define	ICU_INT_DMA1_EOC	3	/* DMA1 end-of-chain */
364135669Scognet#define	ICU_INT_DMA1_EOT	2	/* DMA1 end-of-transfer */
365135669Scognet#define	ICU_INT_DMA0_EOC	1	/* DMA0 end-of-chain */
366135669Scognet#define	ICU_INT_DMA0_EOT	0	/* DMA0 end-of-transfer */
367135669Scognet
368161592Scognet/* CPU_XSCALE_80321 */
369295201Smmel#define	ICU_INT_HWMASK		(0xffffffff & \
370295201Smmel					~((1 << ICU_INT_bit26) | \
371295201Smmel					  (1 << ICU_INT_bit22) | \
372295201Smmel					  (1 << ICU_INT_bit5)  | \
373295201Smmel					  (1 << ICU_INT_bit4)))
374135669Scognet
375135669Scognet/*
376135669Scognet * Peripheral Bus Interface Unit
377135669Scognet */
378135669Scognet
379135669Scognet#define PBIU_PBCR		0x00	/* PBIU Control Register */
380135669Scognet#define PBIU_PBBAR0		0x08	/* PBIU Base Address Register 0 */
381135669Scognet#define PBIU_PBLR0		0x0c	/* PBIU Limit Register 0 */
382135669Scognet#define PBIU_PBBAR1		0x10	/* PBIU Base Address Register 1 */
383135669Scognet#define PBIU_PBLR1		0x14	/* PBIU Limit Register 1 */
384135669Scognet#define PBIU_PBBAR2		0x18	/* PBIU Base Address Register 2 */
385135669Scognet#define PBIU_PBLR2		0x1c	/* PBIU Limit Register 2 */
386135669Scognet#define PBIU_PBBAR3		0x20	/* PBIU Base Address Register 3 */
387135669Scognet#define PBIU_PBLR3		0x24	/* PBIU Limit Register 3 */
388135669Scognet#define PBIU_PBBAR4		0x28	/* PBIU Base Address Register 4 */
389135669Scognet#define PBIU_PBLR4		0x2c	/* PBIU Limit Register 4 */
390135669Scognet#define PBIU_PBBAR5		0x30	/* PBIU Base Address Register 5 */
391135669Scognet#define PBIU_PBLR5		0x34	/* PBIU Limit Register 5 */
392135669Scognet#define PBIU_DSCR		0x38	/* PBIU Drive Strength Control Reg. */
393135669Scognet#define PBIU_MBR0		0x40	/* PBIU Memory-less Boot Reg. 0 */
394135669Scognet#define PBIU_MBR1		0x60	/* PBIU Memory-less Boot Reg. 1 */
395135669Scognet#define PBIU_MBR2		0x64	/* PBIU Memory-less Boot Reg. 2 */
396135669Scognet
397135669Scognet#define	PBIU_PBCR_PBIEN		(1 << 0)
398135669Scognet#define	PBIU_PBCR_PBI100	(1 << 1)
399135669Scognet#define	PBIU_PBCR_PBI66		(2 << 1)
400135669Scognet#define	PBIU_PBCR_PBI33		(3 << 1)
401135669Scognet#define	PBIU_PBCR_PBBEN		(1 << 3)
402135669Scognet
403135669Scognet#define	PBIU_PBARx_WIDTH8	(0 << 0)
404135669Scognet#define	PBIU_PBARx_WIDTH16	(1 << 0)
405135669Scognet#define	PBIU_PBARx_WIDTH32	(2 << 0)
406135669Scognet#define	PBIU_PBARx_ADWAIT4	(0 << 2)
407135669Scognet#define	PBIU_PBARx_ADWAIT8	(1 << 2)
408135669Scognet#define	PBIU_PBARx_ADWAIT12	(2 << 2)
409135669Scognet#define	PBIU_PBARx_ADWAIT16	(3 << 2)
410135669Scognet#define	PBIU_PBARx_ADWAIT20	(4 << 2)
411135669Scognet#define	PBIU_PBARx_RCWAIT1	(0 << 6)
412135669Scognet#define	PBIU_PBARx_RCWAIT4	(1 << 6)
413135669Scognet#define	PBIU_PBARx_RCWAIT8	(2 << 6)
414135669Scognet#define	PBIU_PBARx_RCWAIT12	(3 << 6)
415135669Scognet#define	PBIU_PBARx_RCWAIT16	(4 << 6)
416135669Scognet#define	PBIU_PBARx_RCWAIT20	(5 << 6)
417135669Scognet#define	PBIU_PBARx_FWE		(1 << 9)
418135669Scognet#define	PBIU_BASE_MASK		0xfffff000U
419135669Scognet
420135669Scognet#define	PBIU_PBLRx_SIZE(x)	(~((x) - 1))
421135669Scognet
422135669Scognet/*
423135669Scognet * Messaging Unit
424135669Scognet */
425135669Scognet#define MU_IMR0			0x0010	/* MU Inbound Message Register 0 */
426135669Scognet#define MU_IMR1			0x0014	/* MU Inbound Message Register 1 */
427135669Scognet#define MU_OMR0			0x0018	/* MU Outbound Message Register 0 */
428135669Scognet#define MU_OMR1			0x001c	/* MU Outbound Message Register 1 */
429135669Scognet#define MU_IDR			0x0020	/* MU Inbound Doorbell Register */
430135669Scognet#define MU_IISR			0x0024	/* MU Inbound Interrupt Status Reg */
431135669Scognet#define MU_IIMR			0x0028	/* MU Inbound Interrupt Mask Reg */
432135669Scognet#define MU_ODR			0x002c	/* MU Outbound Doorbell Register */
433135669Scognet#define MU_OISR			0x0030	/* MU Outbound Interrupt Status Reg */
434135669Scognet#define MU_OIMR			0x0034	/* MU Outbound Interrupt Mask Reg */
435135669Scognet#define MU_MUCR			0x0050	/* MU Configuration Register */
436135669Scognet#define MU_QBAR			0x0054	/* MU Queue Base Address Register */
437135669Scognet#define MU_IFHPR		0x0060	/* MU Inbound Free Head Pointer Reg */
438135669Scognet#define MU_IFTPR		0x0064	/* MU Inbound Free Tail Pointer Reg */
439135669Scognet#define MU_IPHPR		0x0068	/* MU Inbound Post Head Pointer Reg */
440135669Scognet#define MU_IPTPR		0x006c	/* MU Inbound Post Tail Pointer Reg */
441135669Scognet#define MU_OFHPR		0x0070	/* MU Outbound Free Head Pointer Reg */
442135669Scognet#define MU_OFTPR		0x0074	/* MU Outbound Free Tail Pointer Reg */
443135669Scognet#define MU_OPHPR		0x0078	/* MU Outbound Post Head Pointer Reg */
444135669Scognet#define MU_OPTPR		0x007c	/* MU Outbound Post Tail Pointer Reg */
445135669Scognet#define MU_IAR			0x0080	/* MU Index Address Register */
446135669Scognet
447135669Scognet#define MU_IIMR_IRI	(1 << 6)	/* Index Register Interrupt */
448135669Scognet#define MU_IIMR_OFQFI	(1 << 5)	/* Outbound Free Queue Full Int. */
449135669Scognet#define MU_IIMR_IPQI	(1 << 4)	/* Inbound Post Queue Interrupt */
450135669Scognet#define MU_IIMR_EDI	(1 << 3)	/* Error Doorbell Interrupt */
451135669Scognet#define MU_IIMR_IDI	(1 << 2)	/* Inbound Doorbell Interrupt */
452135669Scognet#define MU_IIMR_IM1I	(1 << 1)	/* Inbound Message 1 Interrupt */
453135669Scognet#define MU_IIMR_IM0I	(1 << 0)	/* Inbound Message 0 Interrupt */
454135669Scognet
455135669Scognet#endif /* _ARM_XSCALE_I80321REG_H_ */
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