1/*-
2 * Copyright (c) 2013 Thomas Skibo.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25#include <sys/cdefs.h>
26__FBSDID("$FreeBSD: stable/11/sys/arm/xilinx/zy7_mp.c 307344 2016-10-15 08:27:54Z mmel $");
27#include <sys/param.h>
28#include <sys/systm.h>
29#include <sys/bus.h>
30#include <sys/lock.h>
31#include <sys/mutex.h>
32#include <sys/smp.h>
33
34#include <vm/vm.h>
35#include <vm/pmap.h>
36
37#include <machine/cpu.h>
38#include <machine/smp.h>
39#include <machine/fdt.h>
40#include <machine/intr.h>
41
42#include <arm/xilinx/zy7_reg.h>
43
44#define	ZYNQ7_CPU1_ENTRY	0xfffffff0
45
46#define	SCU_CONTROL_REG		0xf8f00000
47#define	   SCU_CONTROL_ENABLE	(1 << 0)
48
49void
50platform_mp_setmaxid(void)
51{
52
53	mp_maxid = 1;
54	mp_ncpus = 2;
55}
56
57void
58platform_mp_start_ap(void)
59{
60	bus_space_handle_t scu_handle;
61	bus_space_handle_t ocm_handle;
62	uint32_t scu_ctrl;
63
64	/* Map in SCU control register. */
65	if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
66			  0, &scu_handle) != 0)
67		panic("platform_mp_start_ap: Couldn't map SCU config reg\n");
68
69	/* Set SCU enable bit. */
70	scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
71	scu_ctrl |= SCU_CONTROL_ENABLE;
72	bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
73
74	bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
75
76	/* Map in magic location to give entry address to CPU1. */
77	if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
78	    0, &ocm_handle) != 0)
79		panic("platform_mp_start_ap: Couldn't map OCM\n");
80
81	/* Write start address for CPU1. */
82	bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
83	    pmap_kextract((vm_offset_t)mpentry));
84
85	bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
86
87	/*
88	 * The SCU is enabled above but I think the second CPU doesn't
89	 * turn on filtering until after the wake-up below. I think that's why
90	 * things don't work if I don't put these cache ops here.  Also, the
91	 * magic location, 0xfffffff0, isn't in the SCU's filtering range so it
92	 * needs a write-back too.
93	 */
94	dcache_wbinv_poc_all();
95
96	/* Wake up CPU1. */
97	dsb();
98	sev();
99}
100