am335x_lcd.c revision 284534
1251018Sgonzo/*- 2251018Sgonzo * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3251018Sgonzo * All rights reserved. 4251018Sgonzo * 5251018Sgonzo * Redistribution and use in source and binary forms, with or without 6251018Sgonzo * modification, are permitted provided that the following conditions 7251018Sgonzo * are met: 8251018Sgonzo * 1. Redistributions of source code must retain the above copyright 9251018Sgonzo * notice, this list of conditions and the following disclaimer. 10251018Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11251018Sgonzo * notice, this list of conditions and the following disclaimer in the 12251018Sgonzo * documentation and/or other materials provided with the distribution. 13251018Sgonzo * 14251018Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15251018Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16251018Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17251018Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18251018Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19251018Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20251018Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21251018Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22251018Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23251018Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24251018Sgonzo * SUCH DAMAGE. 25251018Sgonzo */ 26251018Sgonzo 27251018Sgonzo#include <sys/cdefs.h> 28251018Sgonzo__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_lcd.c 284534 2015-06-18 00:57:52Z gonzo $"); 29251018Sgonzo 30277716Sgonzo#include "opt_syscons.h" 31251018Sgonzo#include <sys/param.h> 32251018Sgonzo#include <sys/systm.h> 33251018Sgonzo#include <sys/kernel.h> 34251018Sgonzo#include <sys/module.h> 35251018Sgonzo#include <sys/clock.h> 36251018Sgonzo#include <sys/time.h> 37251018Sgonzo#include <sys/bus.h> 38251018Sgonzo#include <sys/lock.h> 39251018Sgonzo#include <sys/mutex.h> 40251018Sgonzo#include <sys/resource.h> 41251018Sgonzo#include <sys/rman.h> 42251018Sgonzo#include <sys/sysctl.h> 43251018Sgonzo#include <vm/vm.h> 44251018Sgonzo#include <vm/pmap.h> 45252282Sgonzo#include <sys/fbio.h> 46252282Sgonzo#include <sys/consio.h> 47252282Sgonzo 48251018Sgonzo#include <machine/bus.h> 49251018Sgonzo 50251018Sgonzo#include <dev/fdt/fdt_common.h> 51251018Sgonzo#include <dev/ofw/openfirm.h> 52251018Sgonzo#include <dev/ofw/ofw_bus.h> 53251018Sgonzo#include <dev/ofw/ofw_bus_subr.h> 54251018Sgonzo 55284534Sgonzo#include <arm/ti/am335x/hdmi.h> 56284534Sgonzo#include <dev/videomode/videomode.h> 57284534Sgonzo#include <dev/videomode/edidvar.h> 58284534Sgonzo 59252282Sgonzo#include <dev/fb/fbreg.h> 60277716Sgonzo#ifdef DEV_SC 61252282Sgonzo#include <dev/syscons/syscons.h> 62277716Sgonzo#else /* VT */ 63277716Sgonzo#include <dev/vt/vt.h> 64277716Sgonzo#endif 65252282Sgonzo 66251018Sgonzo#include <arm/ti/ti_prcm.h> 67251018Sgonzo#include <arm/ti/ti_scm.h> 68251018Sgonzo 69251018Sgonzo#include "am335x_lcd.h" 70251018Sgonzo#include "am335x_pwm.h" 71251018Sgonzo 72277716Sgonzo#include "fb_if.h" 73284534Sgonzo#include "hdmi_if.h" 74277716Sgonzo 75251018Sgonzo#define LCD_PID 0x00 76251018Sgonzo#define LCD_CTRL 0x04 77251018Sgonzo#define CTRL_DIV_MASK 0xff 78251018Sgonzo#define CTRL_DIV_SHIFT 8 79251018Sgonzo#define CTRL_AUTO_UFLOW_RESTART (1 << 1) 80251018Sgonzo#define CTRL_RASTER_MODE 1 81251018Sgonzo#define CTRL_LIDD_MODE 0 82251018Sgonzo#define LCD_LIDD_CTRL 0x0C 83251018Sgonzo#define LCD_LIDD_CS0_CONF 0x10 84251018Sgonzo#define LCD_LIDD_CS0_ADDR 0x14 85251018Sgonzo#define LCD_LIDD_CS0_DATA 0x18 86251018Sgonzo#define LCD_LIDD_CS1_CONF 0x1C 87251018Sgonzo#define LCD_LIDD_CS1_ADDR 0x20 88251018Sgonzo#define LCD_LIDD_CS1_DATA 0x24 89251018Sgonzo#define LCD_RASTER_CTRL 0x28 90251018Sgonzo#define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 91251018Sgonzo#define RASTER_CTRL_TFT24 (1 << 25) 92251018Sgonzo#define RASTER_CTRL_STN565 (1 << 24) 93251018Sgonzo#define RASTER_CTRL_TFTPMAP (1 << 23) 94251018Sgonzo#define RASTER_CTRL_NIBMODE (1 << 22) 95251018Sgonzo#define RASTER_CTRL_PALMODE_SHIFT 20 96251018Sgonzo#define PALETTE_PALETTE_AND_DATA 0x00 97251018Sgonzo#define PALETTE_PALETTE_ONLY 0x01 98251018Sgonzo#define PALETTE_DATA_ONLY 0x02 99251018Sgonzo#define RASTER_CTRL_REQDLY_SHIFT 12 100251018Sgonzo#define RASTER_CTRL_MONO8B (1 << 9) 101251018Sgonzo#define RASTER_CTRL_RBORDER (1 << 8) 102251018Sgonzo#define RASTER_CTRL_LCDTFT (1 << 7) 103251018Sgonzo#define RASTER_CTRL_LCDBW (1 << 1) 104251018Sgonzo#define RASTER_CTRL_LCDEN (1 << 0) 105251018Sgonzo#define LCD_RASTER_TIMING_0 0x2C 106251018Sgonzo#define RASTER_TIMING_0_HBP_SHIFT 24 107251018Sgonzo#define RASTER_TIMING_0_HFP_SHIFT 16 108251018Sgonzo#define RASTER_TIMING_0_HSW_SHIFT 10 109251018Sgonzo#define RASTER_TIMING_0_PPLLSB_SHIFT 4 110251018Sgonzo#define RASTER_TIMING_0_PPLMSB_SHIFT 3 111251018Sgonzo#define LCD_RASTER_TIMING_1 0x30 112251018Sgonzo#define RASTER_TIMING_1_VBP_SHIFT 24 113251018Sgonzo#define RASTER_TIMING_1_VFP_SHIFT 16 114251018Sgonzo#define RASTER_TIMING_1_VSW_SHIFT 10 115251018Sgonzo#define RASTER_TIMING_1_LPP_SHIFT 0 116251018Sgonzo#define LCD_RASTER_TIMING_2 0x34 117251018Sgonzo#define RASTER_TIMING_2_HSWHI_SHIFT 27 118251018Sgonzo#define RASTER_TIMING_2_LPP_B10_SHIFT 26 119251018Sgonzo#define RASTER_TIMING_2_PHSVS (1 << 25) 120251018Sgonzo#define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 121251018Sgonzo#define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 122251018Sgonzo#define RASTER_TIMING_2_IOE (1 << 23) 123251018Sgonzo#define RASTER_TIMING_2_IPC (1 << 22) 124251018Sgonzo#define RASTER_TIMING_2_IHS (1 << 21) 125251018Sgonzo#define RASTER_TIMING_2_IVS (1 << 20) 126251018Sgonzo#define RASTER_TIMING_2_ACBI_SHIFT 16 127251018Sgonzo#define RASTER_TIMING_2_ACB_SHIFT 8 128251018Sgonzo#define RASTER_TIMING_2_HBPHI_SHIFT 4 129251018Sgonzo#define RASTER_TIMING_2_HFPHI_SHIFT 0 130251018Sgonzo#define LCD_RASTER_SUBPANEL 0x38 131251018Sgonzo#define LCD_RASTER_SUBPANEL2 0x3C 132251018Sgonzo#define LCD_LCDDMA_CTRL 0x40 133251018Sgonzo#define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 134251018Sgonzo#define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 135251018Sgonzo#define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 136251018Sgonzo#define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 137251018Sgonzo#define LCDDMA_CTRL_BE (1 << 1) 138251018Sgonzo#define LCDDMA_CTRL_FB0_ONLY 0 139251018Sgonzo#define LCDDMA_CTRL_FB0_FB1 (1 << 0) 140251018Sgonzo#define LCD_LCDDMA_FB0_BASE 0x44 141251018Sgonzo#define LCD_LCDDMA_FB0_CEILING 0x48 142251018Sgonzo#define LCD_LCDDMA_FB1_BASE 0x4C 143251018Sgonzo#define LCD_LCDDMA_FB1_CEILING 0x50 144251018Sgonzo#define LCD_SYSCONFIG 0x54 145251018Sgonzo#define SYSCONFIG_STANDBY_FORCE (0 << 4) 146251018Sgonzo#define SYSCONFIG_STANDBY_NONE (1 << 4) 147251018Sgonzo#define SYSCONFIG_STANDBY_SMART (2 << 4) 148251018Sgonzo#define SYSCONFIG_IDLE_FORCE (0 << 2) 149251018Sgonzo#define SYSCONFIG_IDLE_NONE (1 << 2) 150251018Sgonzo#define SYSCONFIG_IDLE_SMART (2 << 2) 151251018Sgonzo#define LCD_IRQSTATUS_RAW 0x58 152251018Sgonzo#define LCD_IRQSTATUS 0x5C 153251018Sgonzo#define LCD_IRQENABLE_SET 0x60 154251018Sgonzo#define LCD_IRQENABLE_CLEAR 0x64 155251018Sgonzo#define IRQ_EOF1 (1 << 9) 156251018Sgonzo#define IRQ_EOF0 (1 << 8) 157251018Sgonzo#define IRQ_PL (1 << 6) 158251018Sgonzo#define IRQ_FUF (1 << 5) 159251018Sgonzo#define IRQ_ACB (1 << 3) 160251018Sgonzo#define IRQ_SYNC_LOST (1 << 2) 161251018Sgonzo#define IRQ_RASTER_DONE (1 << 1) 162251018Sgonzo#define IRQ_FRAME_DONE (1 << 0) 163277405Sgonzo#define LCD_END_OF_INT_IND 0x68 164251018Sgonzo#define LCD_CLKC_ENABLE 0x6C 165251018Sgonzo#define CLKC_ENABLE_DMA (1 << 2) 166251018Sgonzo#define CLKC_ENABLE_LDID (1 << 1) 167251018Sgonzo#define CLKC_ENABLE_CORE (1 << 0) 168251018Sgonzo#define LCD_CLKC_RESET 0x70 169251018Sgonzo#define CLKC_RESET_MAIN (1 << 3) 170251018Sgonzo#define CLKC_RESET_DMA (1 << 2) 171251018Sgonzo#define CLKC_RESET_LDID (1 << 1) 172251018Sgonzo#define CLKC_RESET_CORE (1 << 0) 173251018Sgonzo 174251018Sgonzo#define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 175251018Sgonzo#define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 176251018Sgonzo#define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 177251018Sgonzo device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 178251018Sgonzo#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 179251018Sgonzo 180251018Sgonzo#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 181251018Sgonzo#define LCD_WRITE4(_sc, reg, value) \ 182251018Sgonzo bus_write_4((_sc)->sc_mem_res, reg, value); 183251018Sgonzo 184251018Sgonzo/* Backlight is controlled by eCAS interface on PWM unit 0 */ 185251018Sgonzo#define PWM_UNIT 0 186251018Sgonzo#define PWM_PERIOD 100 187251018Sgonzo 188284534Sgonzo#define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) 189284534Sgonzo#define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) 190284534Sgonzo#define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) 191284534Sgonzo#define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) 192284534Sgonzo#define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) 193284534Sgonzo#define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) 194284534Sgonzo 195284534Sgonzo#define MAX_PIXEL_CLOCK 126000 196284534Sgonzo#define MAX_BANDWIDTH (1280*1024*60) 197284534Sgonzo 198251018Sgonzostruct am335x_lcd_softc { 199251018Sgonzo device_t sc_dev; 200277716Sgonzo struct fb_info sc_fb_info; 201251018Sgonzo struct resource *sc_mem_res; 202251018Sgonzo struct resource *sc_irq_res; 203251018Sgonzo void *sc_intr_hl; 204251018Sgonzo struct mtx sc_mtx; 205251018Sgonzo int sc_backlight; 206251018Sgonzo struct sysctl_oid *sc_oid; 207251018Sgonzo 208284534Sgonzo struct panel_info sc_panel; 209284534Sgonzo 210251018Sgonzo /* Framebuffer */ 211251018Sgonzo bus_dma_tag_t sc_dma_tag; 212251018Sgonzo bus_dmamap_t sc_dma_map; 213251018Sgonzo size_t sc_fb_size; 214251018Sgonzo bus_addr_t sc_fb_phys; 215251018Sgonzo uint8_t *sc_fb_base; 216284534Sgonzo 217284534Sgonzo /* HDMI framer */ 218284534Sgonzo phandle_t sc_hdmi_framer; 219284534Sgonzo eventhandler_tag sc_hdmi_evh; 220251018Sgonzo}; 221251018Sgonzo 222251018Sgonzostatic void 223251018Sgonzoam335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 224251018Sgonzo{ 225251018Sgonzo bus_addr_t *addr; 226251018Sgonzo 227251018Sgonzo if (err) 228251018Sgonzo return; 229251018Sgonzo 230251018Sgonzo addr = (bus_addr_t*)arg; 231251018Sgonzo *addr = segs[0].ds_addr; 232251018Sgonzo} 233251018Sgonzo 234251018Sgonzostatic uint32_t 235251018Sgonzoam335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 236251018Sgonzo{ 237284534Sgonzo uint32_t div, i; 238284534Sgonzo uint32_t delta, min_delta; 239284534Sgonzo 240284534Sgonzo min_delta = freq; 241284534Sgonzo div = 255; 242284534Sgonzo 243251018Sgonzo /* Raster mode case: divisors are in range from 2 to 255 */ 244284534Sgonzo for (i = 2; i < 255; i++) { 245284534Sgonzo delta = abs(reference/i - freq); 246284534Sgonzo if (delta < min_delta) { 247284534Sgonzo div = i; 248284534Sgonzo min_delta = delta; 249284534Sgonzo } 250284534Sgonzo } 251251018Sgonzo 252284534Sgonzo return (div); 253251018Sgonzo} 254251018Sgonzo 255251018Sgonzostatic int 256251018Sgonzoam335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 257251018Sgonzo{ 258251018Sgonzo struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 259251018Sgonzo int error; 260251018Sgonzo int backlight; 261284534Sgonzo 262267171Skevlo backlight = sc->sc_backlight; 263251018Sgonzo error = sysctl_handle_int(oidp, &backlight, 0, req); 264251018Sgonzo 265251018Sgonzo if (error != 0 || req->newptr == NULL) 266251018Sgonzo return (error); 267251018Sgonzo 268251018Sgonzo if (backlight < 0) 269251018Sgonzo backlight = 0; 270251018Sgonzo if (backlight > 100) 271251018Sgonzo backlight = 100; 272251018Sgonzo 273251018Sgonzo LCD_LOCK(sc); 274283276Sgonzo error = am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, 275251018Sgonzo backlight*PWM_PERIOD/100); 276251018Sgonzo if (error == 0) 277251018Sgonzo sc->sc_backlight = backlight; 278251018Sgonzo LCD_UNLOCK(sc); 279251018Sgonzo 280251018Sgonzo return (error); 281251018Sgonzo} 282251018Sgonzo 283284534Sgonzostatic uint32_t 284284534Sgonzoam335x_mode_vrefresh(const struct videomode *mode) 285284534Sgonzo{ 286284534Sgonzo uint32_t refresh; 287284534Sgonzo 288284534Sgonzo /* Calculate vertical refresh rate */ 289284534Sgonzo refresh = (mode->dot_clock * 1000 / mode->htotal); 290284534Sgonzo refresh = (refresh + mode->vtotal / 2) / mode->vtotal; 291284534Sgonzo 292284534Sgonzo if (mode->flags & VID_INTERLACE) 293284534Sgonzo refresh *= 2; 294284534Sgonzo if (mode->flags & VID_DBLSCAN) 295284534Sgonzo refresh /= 2; 296284534Sgonzo 297284534Sgonzo return refresh; 298284534Sgonzo} 299284534Sgonzo 300251018Sgonzostatic int 301284534Sgonzoam335x_mode_is_valid(const struct videomode *mode) 302284534Sgonzo{ 303284534Sgonzo uint32_t hbp, hfp, hsw; 304284534Sgonzo uint32_t vbp, vfp, vsw; 305284534Sgonzo 306284534Sgonzo if (mode->dot_clock > MAX_PIXEL_CLOCK) 307284534Sgonzo return (0); 308284534Sgonzo 309284534Sgonzo if (mode->hdisplay & 0xf) 310284534Sgonzo return (0); 311284534Sgonzo 312284534Sgonzo if (mode->vdisplay > 2048) 313284534Sgonzo return (0); 314284534Sgonzo 315284534Sgonzo /* Check ranges for timing parameters */ 316284534Sgonzo hbp = MODE_HBP(mode) - 1; 317284534Sgonzo hfp = MODE_HFP(mode) - 1; 318284534Sgonzo hsw = MODE_HSW(mode) - 1; 319284534Sgonzo vbp = MODE_VBP(mode); 320284534Sgonzo vfp = MODE_VFP(mode); 321284534Sgonzo vsw = MODE_VSW(mode) - 1; 322284534Sgonzo 323284534Sgonzo if (hbp > 0x3ff) 324284534Sgonzo return (0); 325284534Sgonzo if (hfp > 0x3ff) 326284534Sgonzo return (0); 327284534Sgonzo if (hsw > 0x3ff) 328284534Sgonzo return (0); 329284534Sgonzo 330284534Sgonzo if (vbp > 0xff) 331284534Sgonzo return (0); 332284534Sgonzo if (vfp > 0xff) 333284534Sgonzo return (0); 334284534Sgonzo if (vsw > 0x3f) 335284534Sgonzo return (0); 336284534Sgonzo if (mode->vdisplay*mode->hdisplay*am335x_mode_vrefresh(mode) 337284534Sgonzo > MAX_BANDWIDTH) 338284534Sgonzo return (0); 339284534Sgonzo 340284534Sgonzo return (1); 341284534Sgonzo} 342284534Sgonzo 343284534Sgonzostatic void 344284534Sgonzoam335x_read_hdmi_property(device_t dev) 345284534Sgonzo{ 346284534Sgonzo phandle_t node; 347284534Sgonzo phandle_t hdmi_xref; 348284534Sgonzo struct am335x_lcd_softc *sc; 349284534Sgonzo 350284534Sgonzo sc = device_get_softc(dev); 351284534Sgonzo node = ofw_bus_get_node(dev); 352284534Sgonzo if (OF_getencprop(node, "hdmi", &hdmi_xref, sizeof(hdmi_xref)) == -1) 353284534Sgonzo sc->sc_hdmi_framer = 0; 354284534Sgonzo else 355284534Sgonzo sc->sc_hdmi_framer = hdmi_xref; 356284534Sgonzo} 357284534Sgonzo 358284534Sgonzostatic int 359283276Sgonzoam335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *val) 360251018Sgonzo{ 361251018Sgonzo pcell_t cell; 362251018Sgonzo 363251018Sgonzo if ((OF_getprop(node, name, &cell, sizeof(cell))) <= 0) { 364251018Sgonzo device_printf(dev, "missing '%s' attribute in LCD panel info\n", 365251018Sgonzo name); 366251018Sgonzo return (ENXIO); 367251018Sgonzo } 368251018Sgonzo 369251018Sgonzo *val = fdt32_to_cpu(cell); 370251018Sgonzo 371251018Sgonzo return (0); 372251018Sgonzo} 373251018Sgonzo 374251018Sgonzostatic int 375283276Sgonzoam335x_read_timing(device_t dev, phandle_t node, struct panel_info *panel) 376251018Sgonzo{ 377251018Sgonzo int error; 378283276Sgonzo phandle_t timings_node, timing_node, native; 379251018Sgonzo 380283503Sgonzo timings_node = ofw_bus_find_child(node, "display-timings"); 381283276Sgonzo if (timings_node == 0) { 382283276Sgonzo device_printf(dev, "no \"display-timings\" node\n"); 383283276Sgonzo return (-1); 384283276Sgonzo } 385283276Sgonzo 386283276Sgonzo if (OF_searchencprop(timings_node, "native-mode", &native, 387283276Sgonzo sizeof(native)) == -1) { 388283276Sgonzo device_printf(dev, "no \"native-mode\" reference in \"timings\" node\n"); 389283276Sgonzo return (-1); 390283276Sgonzo } 391283276Sgonzo 392283276Sgonzo timing_node = OF_node_from_xref(native); 393283276Sgonzo 394251018Sgonzo error = 0; 395283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 396283276Sgonzo "hactive", &panel->panel_width))) 397251018Sgonzo goto out; 398251018Sgonzo 399283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 400283276Sgonzo "vactive", &panel->panel_height))) 401251018Sgonzo goto out; 402251018Sgonzo 403283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 404283276Sgonzo "hfront-porch", &panel->panel_hfp))) 405251018Sgonzo goto out; 406251018Sgonzo 407283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 408283276Sgonzo "hback-porch", &panel->panel_hbp))) 409251018Sgonzo goto out; 410251018Sgonzo 411283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 412283276Sgonzo "hsync-len", &panel->panel_hsw))) 413251018Sgonzo goto out; 414251018Sgonzo 415283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 416283276Sgonzo "vfront-porch", &panel->panel_vfp))) 417251018Sgonzo goto out; 418251018Sgonzo 419283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 420283276Sgonzo "vback-porch", &panel->panel_vbp))) 421251018Sgonzo goto out; 422251018Sgonzo 423283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 424283276Sgonzo "vsync-len", &panel->panel_vsw))) 425251018Sgonzo goto out; 426251018Sgonzo 427283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 428283276Sgonzo "clock-frequency", &panel->panel_pxl_clk))) 429251018Sgonzo goto out; 430251018Sgonzo 431283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 432283276Sgonzo "pixelclk-active", &panel->pixelclk_active))) 433251018Sgonzo goto out; 434251018Sgonzo 435283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 436283276Sgonzo "hsync-active", &panel->hsync_active))) 437251018Sgonzo goto out; 438251018Sgonzo 439283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 440283276Sgonzo "vsync-active", &panel->vsync_active))) 441251018Sgonzo goto out; 442251018Sgonzo 443283276Sgonzoout: 444283276Sgonzo return (error); 445283276Sgonzo} 446283276Sgonzo 447283276Sgonzostatic int 448283276Sgonzoam335x_read_panel_info(device_t dev, phandle_t node, struct panel_info *panel) 449283276Sgonzo{ 450283276Sgonzo phandle_t panel_info_node; 451283276Sgonzo 452283503Sgonzo panel_info_node = ofw_bus_find_child(node, "panel-info"); 453283276Sgonzo if (panel_info_node == 0) 454283276Sgonzo return (-1); 455283276Sgonzo 456284534Sgonzo am335x_read_property(dev, panel_info_node, 457284534Sgonzo "ac-bias", &panel->ac_bias); 458283276Sgonzo 459284534Sgonzo am335x_read_property(dev, panel_info_node, 460284534Sgonzo "ac-bias-intrpt", &panel->ac_bias_intrpt); 461251018Sgonzo 462284534Sgonzo am335x_read_property(dev, panel_info_node, 463284534Sgonzo "dma-burst-sz", &panel->dma_burst_sz); 464251018Sgonzo 465284534Sgonzo am335x_read_property(dev, panel_info_node, 466284534Sgonzo "bpp", &panel->bpp); 467251018Sgonzo 468284534Sgonzo am335x_read_property(dev, panel_info_node, 469284534Sgonzo "fdd", &panel->fdd); 470251018Sgonzo 471284534Sgonzo am335x_read_property(dev, panel_info_node, 472284534Sgonzo "sync-edge", &panel->sync_edge); 473251018Sgonzo 474284534Sgonzo am335x_read_property(dev, panel_info_node, 475283276Sgonzo "sync-ctrl", &panel->sync_ctrl); 476251018Sgonzo 477284534Sgonzo return (0); 478251018Sgonzo} 479251018Sgonzo 480251018Sgonzostatic void 481251018Sgonzoam335x_lcd_intr(void *arg) 482251018Sgonzo{ 483251018Sgonzo struct am335x_lcd_softc *sc = arg; 484251018Sgonzo uint32_t reg; 485251018Sgonzo 486251018Sgonzo reg = LCD_READ4(sc, LCD_IRQSTATUS); 487251018Sgonzo LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 488277632Sgonzo /* Read value back to make sure it reached the hardware */ 489277632Sgonzo reg = LCD_READ4(sc, LCD_IRQSTATUS); 490251018Sgonzo 491251018Sgonzo if (reg & IRQ_SYNC_LOST) { 492251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 493251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 494251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 495251018Sgonzo 496251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 497251018Sgonzo reg |= RASTER_CTRL_LCDEN; 498251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 499277522Sgonzo goto done; 500251018Sgonzo } 501251018Sgonzo 502251018Sgonzo if (reg & IRQ_PL) { 503251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 504251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 505251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 506251018Sgonzo 507251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 508251018Sgonzo reg |= RASTER_CTRL_LCDEN; 509251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 510277522Sgonzo goto done; 511251018Sgonzo } 512251018Sgonzo 513251018Sgonzo if (reg & IRQ_EOF0) { 514251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 515251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 516251018Sgonzo reg &= ~IRQ_EOF0; 517251018Sgonzo } 518251018Sgonzo 519251018Sgonzo if (reg & IRQ_EOF1) { 520251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 521251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 522251018Sgonzo reg &= ~IRQ_EOF1; 523251018Sgonzo } 524251018Sgonzo 525251018Sgonzo if (reg & IRQ_FUF) { 526251018Sgonzo /* TODO: Handle FUF */ 527251018Sgonzo } 528251018Sgonzo 529251018Sgonzo if (reg & IRQ_ACB) { 530251018Sgonzo /* TODO: Handle ACB */ 531251018Sgonzo } 532277405Sgonzo 533277522Sgonzodone: 534277405Sgonzo LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0); 535277632Sgonzo /* Read value back to make sure it reached the hardware */ 536277632Sgonzo reg = LCD_READ4(sc, LCD_END_OF_INT_IND); 537251018Sgonzo} 538251018Sgonzo 539284534Sgonzostatic const struct videomode * 540284534Sgonzoam335x_lcd_pick_mode(struct edid_info *ei) 541251018Sgonzo{ 542284534Sgonzo const struct videomode *videomode; 543284534Sgonzo const struct videomode *m; 544284534Sgonzo int n; 545252282Sgonzo 546284534Sgonzo /* Get standard VGA as default */ 547284534Sgonzo videomode = NULL; 548261410Sian 549284534Sgonzo /* 550284534Sgonzo * Pick a mode. 551284534Sgonzo */ 552284534Sgonzo if (ei->edid_preferred_mode != NULL) { 553284534Sgonzo if (am335x_mode_is_valid(ei->edid_preferred_mode)) 554284534Sgonzo videomode = ei->edid_preferred_mode; 555284534Sgonzo } 556251018Sgonzo 557284534Sgonzo if (videomode == NULL) { 558284534Sgonzo m = ei->edid_modes; 559251018Sgonzo 560284534Sgonzo sort_modes(ei->edid_modes, 561284534Sgonzo &ei->edid_preferred_mode, 562284534Sgonzo ei->edid_nmodes); 563284534Sgonzo for (n = 0; n < ei->edid_nmodes; n++) 564284534Sgonzo if (am335x_mode_is_valid(&m[n])) { 565284534Sgonzo videomode = &m[n]; 566284534Sgonzo break; 567284534Sgonzo } 568284534Sgonzo } 569252282Sgonzo 570284534Sgonzo return videomode; 571251018Sgonzo} 572251018Sgonzo 573251018Sgonzostatic int 574284534Sgonzoam335x_lcd_configure(struct am335x_lcd_softc *sc) 575251018Sgonzo{ 576251018Sgonzo int div; 577251018Sgonzo uint32_t reg, timing0, timing1, timing2; 578251018Sgonzo uint32_t burst_log; 579251018Sgonzo size_t dma_size; 580277313Sgonzo uint32_t hbp, hfp, hsw; 581277313Sgonzo uint32_t vbp, vfp, vsw; 582277313Sgonzo uint32_t width, height; 583284534Sgonzo unsigned int ref_freq; 584284534Sgonzo int err; 585251018Sgonzo 586284534Sgonzo /* 587284534Sgonzo * try to adjust clock to get double of requested frequency 588284534Sgonzo * HDMI/DVI displays are very sensitive to error in frequncy value 589284534Sgonzo */ 590284534Sgonzo if (ti_prcm_clk_set_source_freq(LCDC_CLK, sc->sc_panel.panel_pxl_clk*2)) { 591284534Sgonzo device_printf(sc->sc_dev, "can't set source frequency\n"); 592251018Sgonzo return (ENXIO); 593283276Sgonzo } 594251018Sgonzo 595251018Sgonzo if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 596284534Sgonzo device_printf(sc->sc_dev, "can't get reference frequency\n"); 597251018Sgonzo return (ENXIO); 598251018Sgonzo } 599251018Sgonzo 600251018Sgonzo /* Panle initialization */ 601284534Sgonzo dma_size = round_page(sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8); 602251018Sgonzo 603251018Sgonzo /* 604251018Sgonzo * Now allocate framebuffer memory 605251018Sgonzo */ 606251018Sgonzo err = bus_dma_tag_create( 607284534Sgonzo bus_get_dma_tag(sc->sc_dev), 608251018Sgonzo 4, 0, /* alignment, boundary */ 609251018Sgonzo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 610251018Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 611251018Sgonzo NULL, NULL, /* filter, filterarg */ 612251018Sgonzo dma_size, 1, /* maxsize, nsegments */ 613251018Sgonzo dma_size, 0, /* maxsegsize, flags */ 614251018Sgonzo NULL, NULL, /* lockfunc, lockarg */ 615251018Sgonzo &sc->sc_dma_tag); 616251018Sgonzo if (err) 617284534Sgonzo goto done; 618251018Sgonzo 619251018Sgonzo err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 620252282Sgonzo BUS_DMA_COHERENT, &sc->sc_dma_map); 621251018Sgonzo 622251018Sgonzo if (err) { 623284534Sgonzo device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); 624284534Sgonzo goto done; 625251018Sgonzo } 626251018Sgonzo 627251018Sgonzo err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 628251018Sgonzo dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 629251018Sgonzo 630251018Sgonzo if (err) { 631284534Sgonzo device_printf(sc->sc_dev, "cannot load DMA map\n"); 632284534Sgonzo goto done; 633251018Sgonzo } 634251018Sgonzo 635251018Sgonzo /* Make sure it's blank */ 636284534Sgonzo memset(sc->sc_fb_base, 0x0, dma_size); 637251018Sgonzo 638251018Sgonzo /* Calculate actual FB Size */ 639284534Sgonzo sc->sc_fb_size = sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8; 640251018Sgonzo 641251018Sgonzo /* Only raster mode is supported */ 642251018Sgonzo reg = CTRL_RASTER_MODE; 643284534Sgonzo div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk); 644251018Sgonzo reg |= (div << CTRL_DIV_SHIFT); 645251018Sgonzo LCD_WRITE4(sc, LCD_CTRL, reg); 646251018Sgonzo 647251018Sgonzo /* Set timing */ 648251018Sgonzo timing0 = timing1 = timing2 = 0; 649251018Sgonzo 650284534Sgonzo hbp = sc->sc_panel.panel_hbp - 1; 651284534Sgonzo hfp = sc->sc_panel.panel_hfp - 1; 652284534Sgonzo hsw = sc->sc_panel.panel_hsw - 1; 653277313Sgonzo 654284534Sgonzo vbp = sc->sc_panel.panel_vbp; 655284534Sgonzo vfp = sc->sc_panel.panel_vfp; 656284534Sgonzo vsw = sc->sc_panel.panel_vsw - 1; 657277313Sgonzo 658284534Sgonzo height = sc->sc_panel.panel_height - 1; 659284534Sgonzo width = sc->sc_panel.panel_width - 1; 660277313Sgonzo 661251018Sgonzo /* Horizontal back porch */ 662277313Sgonzo timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 663277313Sgonzo timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 664251018Sgonzo /* Horizontal front porch */ 665277313Sgonzo timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 666277313Sgonzo timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 667251018Sgonzo /* Horizontal sync width */ 668277313Sgonzo timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 669277313Sgonzo timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 670251018Sgonzo 671251018Sgonzo /* Vertical back porch, front porch, sync width */ 672277313Sgonzo timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 673277313Sgonzo timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 674277313Sgonzo timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 675251018Sgonzo 676251018Sgonzo /* Pixels per line */ 677277313Sgonzo timing0 |= ((width >> 10) & 1) 678251018Sgonzo << RASTER_TIMING_0_PPLMSB_SHIFT; 679277313Sgonzo timing0 |= ((width >> 4) & 0x3f) 680251018Sgonzo << RASTER_TIMING_0_PPLLSB_SHIFT; 681251018Sgonzo 682251018Sgonzo /* Lines per panel */ 683277313Sgonzo timing1 |= (height & 0x3ff) 684251018Sgonzo << RASTER_TIMING_1_LPP_SHIFT; 685277313Sgonzo timing2 |= ((height >> 10 ) & 1) 686251018Sgonzo << RASTER_TIMING_2_LPP_B10_SHIFT; 687251018Sgonzo 688251018Sgonzo /* clock signal settings */ 689284534Sgonzo if (sc->sc_panel.sync_ctrl) 690251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS; 691284534Sgonzo if (sc->sc_panel.sync_edge) 692251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_RISE; 693251018Sgonzo else 694251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_FALL; 695284534Sgonzo if (sc->sc_panel.hsync_active == 0) 696251018Sgonzo timing2 |= RASTER_TIMING_2_IHS; 697284534Sgonzo if (sc->sc_panel.vsync_active == 0) 698251018Sgonzo timing2 |= RASTER_TIMING_2_IVS; 699284534Sgonzo if (sc->sc_panel.pixelclk_active == 0) 700251018Sgonzo timing2 |= RASTER_TIMING_2_IPC; 701251018Sgonzo 702251018Sgonzo /* AC bias */ 703284534Sgonzo timing2 |= (sc->sc_panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 704284534Sgonzo timing2 |= (sc->sc_panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 705251018Sgonzo 706251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 707251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 708251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 709251018Sgonzo 710251018Sgonzo /* DMA settings */ 711251018Sgonzo reg = LCDDMA_CTRL_FB0_FB1; 712251018Sgonzo /* Find power of 2 for current burst size */ 713284534Sgonzo switch (sc->sc_panel.dma_burst_sz) { 714251018Sgonzo case 1: 715251018Sgonzo burst_log = 0; 716251018Sgonzo break; 717251018Sgonzo case 2: 718251018Sgonzo burst_log = 1; 719251018Sgonzo break; 720251018Sgonzo case 4: 721251018Sgonzo burst_log = 2; 722251018Sgonzo break; 723251018Sgonzo case 8: 724251018Sgonzo burst_log = 3; 725251018Sgonzo break; 726251018Sgonzo case 16: 727251018Sgonzo default: 728251018Sgonzo burst_log = 4; 729251018Sgonzo break; 730251018Sgonzo } 731251018Sgonzo reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 732251018Sgonzo /* XXX: FIFO TH */ 733251018Sgonzo reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 734251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 735251018Sgonzo 736251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 737251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 738251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 739251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 740251018Sgonzo 741251018Sgonzo /* Enable LCD */ 742251018Sgonzo reg = RASTER_CTRL_LCDTFT; 743284534Sgonzo reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 744251018Sgonzo reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 745284534Sgonzo if (sc->sc_panel.bpp >= 24) 746251018Sgonzo reg |= RASTER_CTRL_TFT24; 747284534Sgonzo if (sc->sc_panel.bpp == 32) 748251018Sgonzo reg |= RASTER_CTRL_TFT24_UNPACKED; 749251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 750251018Sgonzo 751251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_ENABLE, 752251018Sgonzo CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 753251018Sgonzo 754251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 755251018Sgonzo DELAY(100); 756251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 757251018Sgonzo 758251018Sgonzo reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 759251018Sgonzo IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 760251018Sgonzo IRQ_FRAME_DONE; 761251018Sgonzo LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 762251018Sgonzo 763251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 764251018Sgonzo reg |= RASTER_CTRL_LCDEN; 765251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 766251018Sgonzo 767251018Sgonzo LCD_WRITE4(sc, LCD_SYSCONFIG, 768251018Sgonzo SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 769251018Sgonzo 770277716Sgonzo sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); 771277716Sgonzo sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; 772277716Sgonzo sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; 773277716Sgonzo sc->sc_fb_info.fb_size = sc->sc_fb_size; 774284534Sgonzo sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = sc->sc_panel.bpp; 775284534Sgonzo sc->sc_fb_info.fb_stride = sc->sc_panel.panel_width*sc->sc_panel.bpp / 8; 776284534Sgonzo sc->sc_fb_info.fb_width = sc->sc_panel.panel_width; 777284534Sgonzo sc->sc_fb_info.fb_height = sc->sc_panel.panel_height; 778277716Sgonzo 779277716Sgonzo#ifdef DEV_SC 780284534Sgonzo err = (sc_attach_unit(device_get_unit(sc->sc_dev), 781284534Sgonzo device_get_flags(sc->sc_dev) | SC_AUTODETECT_KBD)); 782252282Sgonzo 783252282Sgonzo if (err) { 784284534Sgonzo device_printf(sc->sc_dev, "failed to attach syscons\n"); 785252282Sgonzo goto fail; 786252282Sgonzo } 787252282Sgonzo 788251018Sgonzo am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 789277716Sgonzo#else /* VT */ 790284534Sgonzo device_t fbd = device_add_child(sc->sc_dev, "fbd", 791284534Sgonzo device_get_unit(sc->sc_dev)); 792284534Sgonzo if (fbd != NULL) { 793284534Sgonzo if (device_probe_and_attach(fbd) != 0) 794284534Sgonzo device_printf(sc->sc_dev, "failed to attach fbd device\n"); 795284534Sgonzo } else 796284534Sgonzo device_printf(sc->sc_dev, "failed to add fbd child\n"); 797284534Sgonzo#endif 798284534Sgonzo 799284534Sgonzodone: 800284534Sgonzo return (err); 801284534Sgonzo} 802284534Sgonzo 803284534Sgonzostatic void 804284534Sgonzoam335x_lcd_hdmi_event(void *arg) 805284534Sgonzo{ 806284534Sgonzo struct am335x_lcd_softc *sc; 807284534Sgonzo const struct videomode *videomode; 808284534Sgonzo struct videomode hdmi_mode; 809284534Sgonzo device_t hdmi_dev; 810284534Sgonzo uint8_t *edid; 811284534Sgonzo uint32_t edid_len; 812284534Sgonzo struct edid_info ei; 813284534Sgonzo 814284534Sgonzo sc = arg; 815284534Sgonzo 816284534Sgonzo /* Nothing to work with */ 817284534Sgonzo if (!sc->sc_hdmi_framer) { 818284534Sgonzo device_printf(sc->sc_dev, "HDMI event without HDMI framer set\n"); 819284534Sgonzo return; 820277716Sgonzo } 821284534Sgonzo 822284534Sgonzo hdmi_dev = OF_device_from_xref(sc->sc_hdmi_framer); 823284534Sgonzo if (!hdmi_dev) { 824284534Sgonzo device_printf(sc->sc_dev, "no actual device for \"hdmi\" property\n"); 825284534Sgonzo return; 826277716Sgonzo } 827284534Sgonzo 828284534Sgonzo edid = NULL; 829284534Sgonzo edid_len = 0; 830284534Sgonzo if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { 831284534Sgonzo device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); 832284534Sgonzo return; 833284534Sgonzo } 834284534Sgonzo 835284534Sgonzo videomode = NULL; 836284534Sgonzo 837284534Sgonzo if (edid_parse(edid, &ei) == 0) { 838284534Sgonzo edid_print(&ei); 839284534Sgonzo videomode = am335x_lcd_pick_mode(&ei); 840284534Sgonzo } else 841284534Sgonzo device_printf(sc->sc_dev, "failed to parse EDID\n"); 842284534Sgonzo 843284534Sgonzo /* Use standard VGA as fallback */ 844284534Sgonzo if (videomode == NULL) 845284534Sgonzo videomode = pick_mode_by_ref(640, 480, 60); 846284534Sgonzo 847284534Sgonzo if (videomode == NULL) { 848284534Sgonzo device_printf(sc->sc_dev, "failed to find usable videomode"); 849284534Sgonzo return; 850284534Sgonzo } 851284534Sgonzo 852284534Sgonzo device_printf(sc->sc_dev, "detected videomode: %dx%d @ %dKHz\n", videomode->hdisplay, 853284534Sgonzo videomode->vdisplay, am335x_mode_vrefresh(videomode)); 854284534Sgonzo 855284534Sgonzo sc->sc_panel.panel_width = videomode->hdisplay; 856284534Sgonzo sc->sc_panel.panel_height = videomode->vdisplay; 857284534Sgonzo sc->sc_panel.panel_hfp = videomode->hsync_start - videomode->hdisplay; 858284534Sgonzo sc->sc_panel.panel_hbp = videomode->htotal - videomode->hsync_end; 859284534Sgonzo sc->sc_panel.panel_hsw = videomode->hsync_end - videomode->hsync_start; 860284534Sgonzo sc->sc_panel.panel_vfp = videomode->vsync_start - videomode->vdisplay; 861284534Sgonzo sc->sc_panel.panel_vbp = videomode->vtotal - videomode->vsync_end; 862284534Sgonzo sc->sc_panel.panel_vsw = videomode->vsync_end - videomode->vsync_start; 863284534Sgonzo sc->sc_panel.pixelclk_active = 1; 864284534Sgonzo 865284534Sgonzo /* logic for HSYNC should be reversed */ 866284534Sgonzo if (videomode->flags & VID_NHSYNC) 867284534Sgonzo sc->sc_panel.hsync_active = 1; 868284534Sgonzo else 869284534Sgonzo sc->sc_panel.hsync_active = 0; 870284534Sgonzo 871284534Sgonzo if (videomode->flags & VID_NVSYNC) 872284534Sgonzo sc->sc_panel.vsync_active = 0; 873284534Sgonzo else 874284534Sgonzo sc->sc_panel.vsync_active = 1; 875284534Sgonzo 876284534Sgonzo sc->sc_panel.panel_pxl_clk = videomode->dot_clock * 1000; 877284534Sgonzo 878284534Sgonzo am335x_lcd_configure(sc); 879284534Sgonzo 880284534Sgonzo memcpy(&hdmi_mode, videomode, sizeof(hdmi_mode)); 881284534Sgonzo hdmi_mode.hskew = videomode->hsync_end - videomode->hsync_start; 882284534Sgonzo hdmi_mode.flags |= VID_HSKEW; 883284534Sgonzo 884284534Sgonzo HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); 885284534Sgonzo} 886284534Sgonzo 887284534Sgonzostatic int 888284534Sgonzoam335x_lcd_probe(device_t dev) 889284534Sgonzo{ 890284534Sgonzo#ifdef DEV_SC 891284534Sgonzo int err; 892277716Sgonzo#endif 893251018Sgonzo 894284534Sgonzo if (!ofw_bus_status_okay(dev)) 895284534Sgonzo return (ENXIO); 896251018Sgonzo 897284534Sgonzo if (!ofw_bus_is_compatible(dev, "ti,am33xx-tilcdc")) 898284534Sgonzo return (ENXIO); 899284534Sgonzo 900284534Sgonzo device_set_desc(dev, "AM335x LCD controller"); 901284534Sgonzo 902284534Sgonzo#ifdef DEV_SC 903284534Sgonzo err = sc_probe_unit(device_get_unit(dev), 904284534Sgonzo device_get_flags(dev) | SC_AUTODETECT_KBD); 905284534Sgonzo if (err != 0) 906284534Sgonzo return (err); 907284534Sgonzo#endif 908284534Sgonzo 909284534Sgonzo return (BUS_PROBE_DEFAULT); 910251018Sgonzo} 911251018Sgonzo 912251018Sgonzostatic int 913284534Sgonzoam335x_lcd_attach(device_t dev) 914284534Sgonzo{ 915284534Sgonzo struct am335x_lcd_softc *sc; 916284534Sgonzo 917284534Sgonzo int err; 918284534Sgonzo int rid; 919284534Sgonzo struct sysctl_ctx_list *ctx; 920284534Sgonzo struct sysctl_oid *tree; 921284534Sgonzo phandle_t root, panel_node; 922284534Sgonzo 923284534Sgonzo err = 0; 924284534Sgonzo sc = device_get_softc(dev); 925284534Sgonzo sc->sc_dev = dev; 926284534Sgonzo 927284534Sgonzo am335x_read_hdmi_property(dev); 928284534Sgonzo 929284534Sgonzo root = OF_finddevice("/"); 930284534Sgonzo if (root == 0) { 931284534Sgonzo device_printf(dev, "failed to get FDT root node\n"); 932284534Sgonzo return (ENXIO); 933284534Sgonzo } 934284534Sgonzo 935284534Sgonzo sc->sc_panel.ac_bias = 255; 936284534Sgonzo sc->sc_panel.ac_bias_intrpt = 0; 937284534Sgonzo sc->sc_panel.dma_burst_sz = 16; 938284534Sgonzo sc->sc_panel.bpp = 16; 939284534Sgonzo sc->sc_panel.fdd = 128; 940284534Sgonzo sc->sc_panel.sync_edge = 0; 941284534Sgonzo sc->sc_panel.sync_ctrl = 1; 942284534Sgonzo 943284534Sgonzo panel_node = fdt_find_compatible(root, "ti,tilcdc,panel", 1); 944284534Sgonzo if (panel_node != 0) { 945284534Sgonzo device_printf(dev, "using static panel info\n"); 946284534Sgonzo if (am335x_read_panel_info(dev, panel_node, &sc->sc_panel)) { 947284534Sgonzo device_printf(dev, "failed to read panel info\n"); 948284534Sgonzo return (ENXIO); 949284534Sgonzo } 950284534Sgonzo 951284534Sgonzo if (am335x_read_timing(dev, panel_node, &sc->sc_panel)) { 952284534Sgonzo device_printf(dev, "failed to read timings\n"); 953284534Sgonzo return (ENXIO); 954284534Sgonzo } 955284534Sgonzo } 956284534Sgonzo 957284534Sgonzo ti_prcm_clk_enable(LCDC_CLK); 958284534Sgonzo 959284534Sgonzo rid = 0; 960284534Sgonzo sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 961284534Sgonzo RF_ACTIVE); 962284534Sgonzo if (!sc->sc_mem_res) { 963284534Sgonzo device_printf(dev, "cannot allocate memory window\n"); 964284534Sgonzo return (ENXIO); 965284534Sgonzo } 966284534Sgonzo 967284534Sgonzo rid = 0; 968284534Sgonzo sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 969284534Sgonzo RF_ACTIVE); 970284534Sgonzo if (!sc->sc_irq_res) { 971284534Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 972284534Sgonzo device_printf(dev, "cannot allocate interrupt\n"); 973284534Sgonzo return (ENXIO); 974284534Sgonzo } 975284534Sgonzo 976284534Sgonzo if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 977284534Sgonzo NULL, am335x_lcd_intr, sc, 978284534Sgonzo &sc->sc_intr_hl) != 0) { 979284534Sgonzo bus_release_resource(dev, SYS_RES_IRQ, rid, 980284534Sgonzo sc->sc_irq_res); 981284534Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, rid, 982284534Sgonzo sc->sc_mem_res); 983284534Sgonzo device_printf(dev, "Unable to setup the irq handler.\n"); 984284534Sgonzo return (ENXIO); 985284534Sgonzo } 986284534Sgonzo 987284534Sgonzo LCD_LOCK_INIT(sc); 988284534Sgonzo 989284534Sgonzo /* Init backlight interface */ 990284534Sgonzo ctx = device_get_sysctl_ctx(sc->sc_dev); 991284534Sgonzo tree = device_get_sysctl_tree(sc->sc_dev); 992284534Sgonzo sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 993284534Sgonzo "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 994284534Sgonzo am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 995284534Sgonzo sc->sc_backlight = 0; 996284534Sgonzo /* Check if eCAS interface is available at this point */ 997284534Sgonzo if (am335x_pwm_config_ecap(PWM_UNIT, 998284534Sgonzo PWM_PERIOD, PWM_PERIOD) == 0) 999284534Sgonzo sc->sc_backlight = 100; 1000284534Sgonzo 1001284534Sgonzo sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, 1002284534Sgonzo am335x_lcd_hdmi_event, sc, 0); 1003284534Sgonzo 1004284534Sgonzo return (0); 1005284534Sgonzo} 1006284534Sgonzo 1007284534Sgonzostatic int 1008251018Sgonzoam335x_lcd_detach(device_t dev) 1009251018Sgonzo{ 1010251018Sgonzo /* Do not let unload driver */ 1011251018Sgonzo return (EBUSY); 1012251018Sgonzo} 1013251018Sgonzo 1014277716Sgonzostatic struct fb_info * 1015277716Sgonzoam335x_lcd_fb_getinfo(device_t dev) 1016277716Sgonzo{ 1017277716Sgonzo struct am335x_lcd_softc *sc; 1018277716Sgonzo 1019277716Sgonzo sc = device_get_softc(dev); 1020277716Sgonzo 1021277716Sgonzo return (&sc->sc_fb_info); 1022277716Sgonzo} 1023277716Sgonzo 1024251018Sgonzostatic device_method_t am335x_lcd_methods[] = { 1025251018Sgonzo DEVMETHOD(device_probe, am335x_lcd_probe), 1026251018Sgonzo DEVMETHOD(device_attach, am335x_lcd_attach), 1027251018Sgonzo DEVMETHOD(device_detach, am335x_lcd_detach), 1028251018Sgonzo 1029277716Sgonzo /* Framebuffer service methods */ 1030277716Sgonzo DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo), 1031277716Sgonzo 1032251018Sgonzo DEVMETHOD_END 1033251018Sgonzo}; 1034251018Sgonzo 1035251018Sgonzostatic driver_t am335x_lcd_driver = { 1036277716Sgonzo "fb", 1037251018Sgonzo am335x_lcd_methods, 1038251018Sgonzo sizeof(struct am335x_lcd_softc), 1039251018Sgonzo}; 1040251018Sgonzo 1041251018Sgonzostatic devclass_t am335x_lcd_devclass; 1042251018Sgonzo 1043251018SgonzoDRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 1044251018SgonzoMODULE_VERSION(am335x_lcd, 1); 1045251018SgonzoMODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 1046