am335x_lcd.c revision 284534
1/*- 2 * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_lcd.c 284534 2015-06-18 00:57:52Z gonzo $"); 29 30#include "opt_syscons.h" 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/clock.h> 36#include <sys/time.h> 37#include <sys/bus.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/resource.h> 41#include <sys/rman.h> 42#include <sys/sysctl.h> 43#include <vm/vm.h> 44#include <vm/pmap.h> 45#include <sys/fbio.h> 46#include <sys/consio.h> 47 48#include <machine/bus.h> 49 50#include <dev/fdt/fdt_common.h> 51#include <dev/ofw/openfirm.h> 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55#include <arm/ti/am335x/hdmi.h> 56#include <dev/videomode/videomode.h> 57#include <dev/videomode/edidvar.h> 58 59#include <dev/fb/fbreg.h> 60#ifdef DEV_SC 61#include <dev/syscons/syscons.h> 62#else /* VT */ 63#include <dev/vt/vt.h> 64#endif 65 66#include <arm/ti/ti_prcm.h> 67#include <arm/ti/ti_scm.h> 68 69#include "am335x_lcd.h" 70#include "am335x_pwm.h" 71 72#include "fb_if.h" 73#include "hdmi_if.h" 74 75#define LCD_PID 0x00 76#define LCD_CTRL 0x04 77#define CTRL_DIV_MASK 0xff 78#define CTRL_DIV_SHIFT 8 79#define CTRL_AUTO_UFLOW_RESTART (1 << 1) 80#define CTRL_RASTER_MODE 1 81#define CTRL_LIDD_MODE 0 82#define LCD_LIDD_CTRL 0x0C 83#define LCD_LIDD_CS0_CONF 0x10 84#define LCD_LIDD_CS0_ADDR 0x14 85#define LCD_LIDD_CS0_DATA 0x18 86#define LCD_LIDD_CS1_CONF 0x1C 87#define LCD_LIDD_CS1_ADDR 0x20 88#define LCD_LIDD_CS1_DATA 0x24 89#define LCD_RASTER_CTRL 0x28 90#define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 91#define RASTER_CTRL_TFT24 (1 << 25) 92#define RASTER_CTRL_STN565 (1 << 24) 93#define RASTER_CTRL_TFTPMAP (1 << 23) 94#define RASTER_CTRL_NIBMODE (1 << 22) 95#define RASTER_CTRL_PALMODE_SHIFT 20 96#define PALETTE_PALETTE_AND_DATA 0x00 97#define PALETTE_PALETTE_ONLY 0x01 98#define PALETTE_DATA_ONLY 0x02 99#define RASTER_CTRL_REQDLY_SHIFT 12 100#define RASTER_CTRL_MONO8B (1 << 9) 101#define RASTER_CTRL_RBORDER (1 << 8) 102#define RASTER_CTRL_LCDTFT (1 << 7) 103#define RASTER_CTRL_LCDBW (1 << 1) 104#define RASTER_CTRL_LCDEN (1 << 0) 105#define LCD_RASTER_TIMING_0 0x2C 106#define RASTER_TIMING_0_HBP_SHIFT 24 107#define RASTER_TIMING_0_HFP_SHIFT 16 108#define RASTER_TIMING_0_HSW_SHIFT 10 109#define RASTER_TIMING_0_PPLLSB_SHIFT 4 110#define RASTER_TIMING_0_PPLMSB_SHIFT 3 111#define LCD_RASTER_TIMING_1 0x30 112#define RASTER_TIMING_1_VBP_SHIFT 24 113#define RASTER_TIMING_1_VFP_SHIFT 16 114#define RASTER_TIMING_1_VSW_SHIFT 10 115#define RASTER_TIMING_1_LPP_SHIFT 0 116#define LCD_RASTER_TIMING_2 0x34 117#define RASTER_TIMING_2_HSWHI_SHIFT 27 118#define RASTER_TIMING_2_LPP_B10_SHIFT 26 119#define RASTER_TIMING_2_PHSVS (1 << 25) 120#define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 121#define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 122#define RASTER_TIMING_2_IOE (1 << 23) 123#define RASTER_TIMING_2_IPC (1 << 22) 124#define RASTER_TIMING_2_IHS (1 << 21) 125#define RASTER_TIMING_2_IVS (1 << 20) 126#define RASTER_TIMING_2_ACBI_SHIFT 16 127#define RASTER_TIMING_2_ACB_SHIFT 8 128#define RASTER_TIMING_2_HBPHI_SHIFT 4 129#define RASTER_TIMING_2_HFPHI_SHIFT 0 130#define LCD_RASTER_SUBPANEL 0x38 131#define LCD_RASTER_SUBPANEL2 0x3C 132#define LCD_LCDDMA_CTRL 0x40 133#define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 134#define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 135#define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 136#define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 137#define LCDDMA_CTRL_BE (1 << 1) 138#define LCDDMA_CTRL_FB0_ONLY 0 139#define LCDDMA_CTRL_FB0_FB1 (1 << 0) 140#define LCD_LCDDMA_FB0_BASE 0x44 141#define LCD_LCDDMA_FB0_CEILING 0x48 142#define LCD_LCDDMA_FB1_BASE 0x4C 143#define LCD_LCDDMA_FB1_CEILING 0x50 144#define LCD_SYSCONFIG 0x54 145#define SYSCONFIG_STANDBY_FORCE (0 << 4) 146#define SYSCONFIG_STANDBY_NONE (1 << 4) 147#define SYSCONFIG_STANDBY_SMART (2 << 4) 148#define SYSCONFIG_IDLE_FORCE (0 << 2) 149#define SYSCONFIG_IDLE_NONE (1 << 2) 150#define SYSCONFIG_IDLE_SMART (2 << 2) 151#define LCD_IRQSTATUS_RAW 0x58 152#define LCD_IRQSTATUS 0x5C 153#define LCD_IRQENABLE_SET 0x60 154#define LCD_IRQENABLE_CLEAR 0x64 155#define IRQ_EOF1 (1 << 9) 156#define IRQ_EOF0 (1 << 8) 157#define IRQ_PL (1 << 6) 158#define IRQ_FUF (1 << 5) 159#define IRQ_ACB (1 << 3) 160#define IRQ_SYNC_LOST (1 << 2) 161#define IRQ_RASTER_DONE (1 << 1) 162#define IRQ_FRAME_DONE (1 << 0) 163#define LCD_END_OF_INT_IND 0x68 164#define LCD_CLKC_ENABLE 0x6C 165#define CLKC_ENABLE_DMA (1 << 2) 166#define CLKC_ENABLE_LDID (1 << 1) 167#define CLKC_ENABLE_CORE (1 << 0) 168#define LCD_CLKC_RESET 0x70 169#define CLKC_RESET_MAIN (1 << 3) 170#define CLKC_RESET_DMA (1 << 2) 171#define CLKC_RESET_LDID (1 << 1) 172#define CLKC_RESET_CORE (1 << 0) 173 174#define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 175#define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 176#define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 177 device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 178#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 179 180#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 181#define LCD_WRITE4(_sc, reg, value) \ 182 bus_write_4((_sc)->sc_mem_res, reg, value); 183 184/* Backlight is controlled by eCAS interface on PWM unit 0 */ 185#define PWM_UNIT 0 186#define PWM_PERIOD 100 187 188#define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) 189#define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) 190#define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) 191#define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) 192#define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) 193#define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) 194 195#define MAX_PIXEL_CLOCK 126000 196#define MAX_BANDWIDTH (1280*1024*60) 197 198struct am335x_lcd_softc { 199 device_t sc_dev; 200 struct fb_info sc_fb_info; 201 struct resource *sc_mem_res; 202 struct resource *sc_irq_res; 203 void *sc_intr_hl; 204 struct mtx sc_mtx; 205 int sc_backlight; 206 struct sysctl_oid *sc_oid; 207 208 struct panel_info sc_panel; 209 210 /* Framebuffer */ 211 bus_dma_tag_t sc_dma_tag; 212 bus_dmamap_t sc_dma_map; 213 size_t sc_fb_size; 214 bus_addr_t sc_fb_phys; 215 uint8_t *sc_fb_base; 216 217 /* HDMI framer */ 218 phandle_t sc_hdmi_framer; 219 eventhandler_tag sc_hdmi_evh; 220}; 221 222static void 223am335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 224{ 225 bus_addr_t *addr; 226 227 if (err) 228 return; 229 230 addr = (bus_addr_t*)arg; 231 *addr = segs[0].ds_addr; 232} 233 234static uint32_t 235am335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 236{ 237 uint32_t div, i; 238 uint32_t delta, min_delta; 239 240 min_delta = freq; 241 div = 255; 242 243 /* Raster mode case: divisors are in range from 2 to 255 */ 244 for (i = 2; i < 255; i++) { 245 delta = abs(reference/i - freq); 246 if (delta < min_delta) { 247 div = i; 248 min_delta = delta; 249 } 250 } 251 252 return (div); 253} 254 255static int 256am335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 257{ 258 struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 259 int error; 260 int backlight; 261 262 backlight = sc->sc_backlight; 263 error = sysctl_handle_int(oidp, &backlight, 0, req); 264 265 if (error != 0 || req->newptr == NULL) 266 return (error); 267 268 if (backlight < 0) 269 backlight = 0; 270 if (backlight > 100) 271 backlight = 100; 272 273 LCD_LOCK(sc); 274 error = am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, 275 backlight*PWM_PERIOD/100); 276 if (error == 0) 277 sc->sc_backlight = backlight; 278 LCD_UNLOCK(sc); 279 280 return (error); 281} 282 283static uint32_t 284am335x_mode_vrefresh(const struct videomode *mode) 285{ 286 uint32_t refresh; 287 288 /* Calculate vertical refresh rate */ 289 refresh = (mode->dot_clock * 1000 / mode->htotal); 290 refresh = (refresh + mode->vtotal / 2) / mode->vtotal; 291 292 if (mode->flags & VID_INTERLACE) 293 refresh *= 2; 294 if (mode->flags & VID_DBLSCAN) 295 refresh /= 2; 296 297 return refresh; 298} 299 300static int 301am335x_mode_is_valid(const struct videomode *mode) 302{ 303 uint32_t hbp, hfp, hsw; 304 uint32_t vbp, vfp, vsw; 305 306 if (mode->dot_clock > MAX_PIXEL_CLOCK) 307 return (0); 308 309 if (mode->hdisplay & 0xf) 310 return (0); 311 312 if (mode->vdisplay > 2048) 313 return (0); 314 315 /* Check ranges for timing parameters */ 316 hbp = MODE_HBP(mode) - 1; 317 hfp = MODE_HFP(mode) - 1; 318 hsw = MODE_HSW(mode) - 1; 319 vbp = MODE_VBP(mode); 320 vfp = MODE_VFP(mode); 321 vsw = MODE_VSW(mode) - 1; 322 323 if (hbp > 0x3ff) 324 return (0); 325 if (hfp > 0x3ff) 326 return (0); 327 if (hsw > 0x3ff) 328 return (0); 329 330 if (vbp > 0xff) 331 return (0); 332 if (vfp > 0xff) 333 return (0); 334 if (vsw > 0x3f) 335 return (0); 336 if (mode->vdisplay*mode->hdisplay*am335x_mode_vrefresh(mode) 337 > MAX_BANDWIDTH) 338 return (0); 339 340 return (1); 341} 342 343static void 344am335x_read_hdmi_property(device_t dev) 345{ 346 phandle_t node; 347 phandle_t hdmi_xref; 348 struct am335x_lcd_softc *sc; 349 350 sc = device_get_softc(dev); 351 node = ofw_bus_get_node(dev); 352 if (OF_getencprop(node, "hdmi", &hdmi_xref, sizeof(hdmi_xref)) == -1) 353 sc->sc_hdmi_framer = 0; 354 else 355 sc->sc_hdmi_framer = hdmi_xref; 356} 357 358static int 359am335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *val) 360{ 361 pcell_t cell; 362 363 if ((OF_getprop(node, name, &cell, sizeof(cell))) <= 0) { 364 device_printf(dev, "missing '%s' attribute in LCD panel info\n", 365 name); 366 return (ENXIO); 367 } 368 369 *val = fdt32_to_cpu(cell); 370 371 return (0); 372} 373 374static int 375am335x_read_timing(device_t dev, phandle_t node, struct panel_info *panel) 376{ 377 int error; 378 phandle_t timings_node, timing_node, native; 379 380 timings_node = ofw_bus_find_child(node, "display-timings"); 381 if (timings_node == 0) { 382 device_printf(dev, "no \"display-timings\" node\n"); 383 return (-1); 384 } 385 386 if (OF_searchencprop(timings_node, "native-mode", &native, 387 sizeof(native)) == -1) { 388 device_printf(dev, "no \"native-mode\" reference in \"timings\" node\n"); 389 return (-1); 390 } 391 392 timing_node = OF_node_from_xref(native); 393 394 error = 0; 395 if ((error = am335x_read_property(dev, timing_node, 396 "hactive", &panel->panel_width))) 397 goto out; 398 399 if ((error = am335x_read_property(dev, timing_node, 400 "vactive", &panel->panel_height))) 401 goto out; 402 403 if ((error = am335x_read_property(dev, timing_node, 404 "hfront-porch", &panel->panel_hfp))) 405 goto out; 406 407 if ((error = am335x_read_property(dev, timing_node, 408 "hback-porch", &panel->panel_hbp))) 409 goto out; 410 411 if ((error = am335x_read_property(dev, timing_node, 412 "hsync-len", &panel->panel_hsw))) 413 goto out; 414 415 if ((error = am335x_read_property(dev, timing_node, 416 "vfront-porch", &panel->panel_vfp))) 417 goto out; 418 419 if ((error = am335x_read_property(dev, timing_node, 420 "vback-porch", &panel->panel_vbp))) 421 goto out; 422 423 if ((error = am335x_read_property(dev, timing_node, 424 "vsync-len", &panel->panel_vsw))) 425 goto out; 426 427 if ((error = am335x_read_property(dev, timing_node, 428 "clock-frequency", &panel->panel_pxl_clk))) 429 goto out; 430 431 if ((error = am335x_read_property(dev, timing_node, 432 "pixelclk-active", &panel->pixelclk_active))) 433 goto out; 434 435 if ((error = am335x_read_property(dev, timing_node, 436 "hsync-active", &panel->hsync_active))) 437 goto out; 438 439 if ((error = am335x_read_property(dev, timing_node, 440 "vsync-active", &panel->vsync_active))) 441 goto out; 442 443out: 444 return (error); 445} 446 447static int 448am335x_read_panel_info(device_t dev, phandle_t node, struct panel_info *panel) 449{ 450 phandle_t panel_info_node; 451 452 panel_info_node = ofw_bus_find_child(node, "panel-info"); 453 if (panel_info_node == 0) 454 return (-1); 455 456 am335x_read_property(dev, panel_info_node, 457 "ac-bias", &panel->ac_bias); 458 459 am335x_read_property(dev, panel_info_node, 460 "ac-bias-intrpt", &panel->ac_bias_intrpt); 461 462 am335x_read_property(dev, panel_info_node, 463 "dma-burst-sz", &panel->dma_burst_sz); 464 465 am335x_read_property(dev, panel_info_node, 466 "bpp", &panel->bpp); 467 468 am335x_read_property(dev, panel_info_node, 469 "fdd", &panel->fdd); 470 471 am335x_read_property(dev, panel_info_node, 472 "sync-edge", &panel->sync_edge); 473 474 am335x_read_property(dev, panel_info_node, 475 "sync-ctrl", &panel->sync_ctrl); 476 477 return (0); 478} 479 480static void 481am335x_lcd_intr(void *arg) 482{ 483 struct am335x_lcd_softc *sc = arg; 484 uint32_t reg; 485 486 reg = LCD_READ4(sc, LCD_IRQSTATUS); 487 LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 488 /* Read value back to make sure it reached the hardware */ 489 reg = LCD_READ4(sc, LCD_IRQSTATUS); 490 491 if (reg & IRQ_SYNC_LOST) { 492 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 493 reg &= ~RASTER_CTRL_LCDEN; 494 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 495 496 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 497 reg |= RASTER_CTRL_LCDEN; 498 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 499 goto done; 500 } 501 502 if (reg & IRQ_PL) { 503 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 504 reg &= ~RASTER_CTRL_LCDEN; 505 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 506 507 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 508 reg |= RASTER_CTRL_LCDEN; 509 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 510 goto done; 511 } 512 513 if (reg & IRQ_EOF0) { 514 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 515 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 516 reg &= ~IRQ_EOF0; 517 } 518 519 if (reg & IRQ_EOF1) { 520 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 521 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 522 reg &= ~IRQ_EOF1; 523 } 524 525 if (reg & IRQ_FUF) { 526 /* TODO: Handle FUF */ 527 } 528 529 if (reg & IRQ_ACB) { 530 /* TODO: Handle ACB */ 531 } 532 533done: 534 LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0); 535 /* Read value back to make sure it reached the hardware */ 536 reg = LCD_READ4(sc, LCD_END_OF_INT_IND); 537} 538 539static const struct videomode * 540am335x_lcd_pick_mode(struct edid_info *ei) 541{ 542 const struct videomode *videomode; 543 const struct videomode *m; 544 int n; 545 546 /* Get standard VGA as default */ 547 videomode = NULL; 548 549 /* 550 * Pick a mode. 551 */ 552 if (ei->edid_preferred_mode != NULL) { 553 if (am335x_mode_is_valid(ei->edid_preferred_mode)) 554 videomode = ei->edid_preferred_mode; 555 } 556 557 if (videomode == NULL) { 558 m = ei->edid_modes; 559 560 sort_modes(ei->edid_modes, 561 &ei->edid_preferred_mode, 562 ei->edid_nmodes); 563 for (n = 0; n < ei->edid_nmodes; n++) 564 if (am335x_mode_is_valid(&m[n])) { 565 videomode = &m[n]; 566 break; 567 } 568 } 569 570 return videomode; 571} 572 573static int 574am335x_lcd_configure(struct am335x_lcd_softc *sc) 575{ 576 int div; 577 uint32_t reg, timing0, timing1, timing2; 578 uint32_t burst_log; 579 size_t dma_size; 580 uint32_t hbp, hfp, hsw; 581 uint32_t vbp, vfp, vsw; 582 uint32_t width, height; 583 unsigned int ref_freq; 584 int err; 585 586 /* 587 * try to adjust clock to get double of requested frequency 588 * HDMI/DVI displays are very sensitive to error in frequncy value 589 */ 590 if (ti_prcm_clk_set_source_freq(LCDC_CLK, sc->sc_panel.panel_pxl_clk*2)) { 591 device_printf(sc->sc_dev, "can't set source frequency\n"); 592 return (ENXIO); 593 } 594 595 if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 596 device_printf(sc->sc_dev, "can't get reference frequency\n"); 597 return (ENXIO); 598 } 599 600 /* Panle initialization */ 601 dma_size = round_page(sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8); 602 603 /* 604 * Now allocate framebuffer memory 605 */ 606 err = bus_dma_tag_create( 607 bus_get_dma_tag(sc->sc_dev), 608 4, 0, /* alignment, boundary */ 609 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 610 BUS_SPACE_MAXADDR, /* highaddr */ 611 NULL, NULL, /* filter, filterarg */ 612 dma_size, 1, /* maxsize, nsegments */ 613 dma_size, 0, /* maxsegsize, flags */ 614 NULL, NULL, /* lockfunc, lockarg */ 615 &sc->sc_dma_tag); 616 if (err) 617 goto done; 618 619 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 620 BUS_DMA_COHERENT, &sc->sc_dma_map); 621 622 if (err) { 623 device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); 624 goto done; 625 } 626 627 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 628 dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 629 630 if (err) { 631 device_printf(sc->sc_dev, "cannot load DMA map\n"); 632 goto done; 633 } 634 635 /* Make sure it's blank */ 636 memset(sc->sc_fb_base, 0x0, dma_size); 637 638 /* Calculate actual FB Size */ 639 sc->sc_fb_size = sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8; 640 641 /* Only raster mode is supported */ 642 reg = CTRL_RASTER_MODE; 643 div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk); 644 reg |= (div << CTRL_DIV_SHIFT); 645 LCD_WRITE4(sc, LCD_CTRL, reg); 646 647 /* Set timing */ 648 timing0 = timing1 = timing2 = 0; 649 650 hbp = sc->sc_panel.panel_hbp - 1; 651 hfp = sc->sc_panel.panel_hfp - 1; 652 hsw = sc->sc_panel.panel_hsw - 1; 653 654 vbp = sc->sc_panel.panel_vbp; 655 vfp = sc->sc_panel.panel_vfp; 656 vsw = sc->sc_panel.panel_vsw - 1; 657 658 height = sc->sc_panel.panel_height - 1; 659 width = sc->sc_panel.panel_width - 1; 660 661 /* Horizontal back porch */ 662 timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 663 timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 664 /* Horizontal front porch */ 665 timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 666 timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 667 /* Horizontal sync width */ 668 timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 669 timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 670 671 /* Vertical back porch, front porch, sync width */ 672 timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 673 timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 674 timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 675 676 /* Pixels per line */ 677 timing0 |= ((width >> 10) & 1) 678 << RASTER_TIMING_0_PPLMSB_SHIFT; 679 timing0 |= ((width >> 4) & 0x3f) 680 << RASTER_TIMING_0_PPLLSB_SHIFT; 681 682 /* Lines per panel */ 683 timing1 |= (height & 0x3ff) 684 << RASTER_TIMING_1_LPP_SHIFT; 685 timing2 |= ((height >> 10 ) & 1) 686 << RASTER_TIMING_2_LPP_B10_SHIFT; 687 688 /* clock signal settings */ 689 if (sc->sc_panel.sync_ctrl) 690 timing2 |= RASTER_TIMING_2_PHSVS; 691 if (sc->sc_panel.sync_edge) 692 timing2 |= RASTER_TIMING_2_PHSVS_RISE; 693 else 694 timing2 |= RASTER_TIMING_2_PHSVS_FALL; 695 if (sc->sc_panel.hsync_active == 0) 696 timing2 |= RASTER_TIMING_2_IHS; 697 if (sc->sc_panel.vsync_active == 0) 698 timing2 |= RASTER_TIMING_2_IVS; 699 if (sc->sc_panel.pixelclk_active == 0) 700 timing2 |= RASTER_TIMING_2_IPC; 701 702 /* AC bias */ 703 timing2 |= (sc->sc_panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 704 timing2 |= (sc->sc_panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 705 706 LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 707 LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 708 LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 709 710 /* DMA settings */ 711 reg = LCDDMA_CTRL_FB0_FB1; 712 /* Find power of 2 for current burst size */ 713 switch (sc->sc_panel.dma_burst_sz) { 714 case 1: 715 burst_log = 0; 716 break; 717 case 2: 718 burst_log = 1; 719 break; 720 case 4: 721 burst_log = 2; 722 break; 723 case 8: 724 burst_log = 3; 725 break; 726 case 16: 727 default: 728 burst_log = 4; 729 break; 730 } 731 reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 732 /* XXX: FIFO TH */ 733 reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 734 LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 735 736 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 737 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 738 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 739 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 740 741 /* Enable LCD */ 742 reg = RASTER_CTRL_LCDTFT; 743 reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 744 reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 745 if (sc->sc_panel.bpp >= 24) 746 reg |= RASTER_CTRL_TFT24; 747 if (sc->sc_panel.bpp == 32) 748 reg |= RASTER_CTRL_TFT24_UNPACKED; 749 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 750 751 LCD_WRITE4(sc, LCD_CLKC_ENABLE, 752 CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 753 754 LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 755 DELAY(100); 756 LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 757 758 reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 759 IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 760 IRQ_FRAME_DONE; 761 LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 762 763 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 764 reg |= RASTER_CTRL_LCDEN; 765 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 766 767 LCD_WRITE4(sc, LCD_SYSCONFIG, 768 SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 769 770 sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); 771 sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; 772 sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; 773 sc->sc_fb_info.fb_size = sc->sc_fb_size; 774 sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = sc->sc_panel.bpp; 775 sc->sc_fb_info.fb_stride = sc->sc_panel.panel_width*sc->sc_panel.bpp / 8; 776 sc->sc_fb_info.fb_width = sc->sc_panel.panel_width; 777 sc->sc_fb_info.fb_height = sc->sc_panel.panel_height; 778 779#ifdef DEV_SC 780 err = (sc_attach_unit(device_get_unit(sc->sc_dev), 781 device_get_flags(sc->sc_dev) | SC_AUTODETECT_KBD)); 782 783 if (err) { 784 device_printf(sc->sc_dev, "failed to attach syscons\n"); 785 goto fail; 786 } 787 788 am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 789#else /* VT */ 790 device_t fbd = device_add_child(sc->sc_dev, "fbd", 791 device_get_unit(sc->sc_dev)); 792 if (fbd != NULL) { 793 if (device_probe_and_attach(fbd) != 0) 794 device_printf(sc->sc_dev, "failed to attach fbd device\n"); 795 } else 796 device_printf(sc->sc_dev, "failed to add fbd child\n"); 797#endif 798 799done: 800 return (err); 801} 802 803static void 804am335x_lcd_hdmi_event(void *arg) 805{ 806 struct am335x_lcd_softc *sc; 807 const struct videomode *videomode; 808 struct videomode hdmi_mode; 809 device_t hdmi_dev; 810 uint8_t *edid; 811 uint32_t edid_len; 812 struct edid_info ei; 813 814 sc = arg; 815 816 /* Nothing to work with */ 817 if (!sc->sc_hdmi_framer) { 818 device_printf(sc->sc_dev, "HDMI event without HDMI framer set\n"); 819 return; 820 } 821 822 hdmi_dev = OF_device_from_xref(sc->sc_hdmi_framer); 823 if (!hdmi_dev) { 824 device_printf(sc->sc_dev, "no actual device for \"hdmi\" property\n"); 825 return; 826 } 827 828 edid = NULL; 829 edid_len = 0; 830 if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { 831 device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); 832 return; 833 } 834 835 videomode = NULL; 836 837 if (edid_parse(edid, &ei) == 0) { 838 edid_print(&ei); 839 videomode = am335x_lcd_pick_mode(&ei); 840 } else 841 device_printf(sc->sc_dev, "failed to parse EDID\n"); 842 843 /* Use standard VGA as fallback */ 844 if (videomode == NULL) 845 videomode = pick_mode_by_ref(640, 480, 60); 846 847 if (videomode == NULL) { 848 device_printf(sc->sc_dev, "failed to find usable videomode"); 849 return; 850 } 851 852 device_printf(sc->sc_dev, "detected videomode: %dx%d @ %dKHz\n", videomode->hdisplay, 853 videomode->vdisplay, am335x_mode_vrefresh(videomode)); 854 855 sc->sc_panel.panel_width = videomode->hdisplay; 856 sc->sc_panel.panel_height = videomode->vdisplay; 857 sc->sc_panel.panel_hfp = videomode->hsync_start - videomode->hdisplay; 858 sc->sc_panel.panel_hbp = videomode->htotal - videomode->hsync_end; 859 sc->sc_panel.panel_hsw = videomode->hsync_end - videomode->hsync_start; 860 sc->sc_panel.panel_vfp = videomode->vsync_start - videomode->vdisplay; 861 sc->sc_panel.panel_vbp = videomode->vtotal - videomode->vsync_end; 862 sc->sc_panel.panel_vsw = videomode->vsync_end - videomode->vsync_start; 863 sc->sc_panel.pixelclk_active = 1; 864 865 /* logic for HSYNC should be reversed */ 866 if (videomode->flags & VID_NHSYNC) 867 sc->sc_panel.hsync_active = 1; 868 else 869 sc->sc_panel.hsync_active = 0; 870 871 if (videomode->flags & VID_NVSYNC) 872 sc->sc_panel.vsync_active = 0; 873 else 874 sc->sc_panel.vsync_active = 1; 875 876 sc->sc_panel.panel_pxl_clk = videomode->dot_clock * 1000; 877 878 am335x_lcd_configure(sc); 879 880 memcpy(&hdmi_mode, videomode, sizeof(hdmi_mode)); 881 hdmi_mode.hskew = videomode->hsync_end - videomode->hsync_start; 882 hdmi_mode.flags |= VID_HSKEW; 883 884 HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); 885} 886 887static int 888am335x_lcd_probe(device_t dev) 889{ 890#ifdef DEV_SC 891 int err; 892#endif 893 894 if (!ofw_bus_status_okay(dev)) 895 return (ENXIO); 896 897 if (!ofw_bus_is_compatible(dev, "ti,am33xx-tilcdc")) 898 return (ENXIO); 899 900 device_set_desc(dev, "AM335x LCD controller"); 901 902#ifdef DEV_SC 903 err = sc_probe_unit(device_get_unit(dev), 904 device_get_flags(dev) | SC_AUTODETECT_KBD); 905 if (err != 0) 906 return (err); 907#endif 908 909 return (BUS_PROBE_DEFAULT); 910} 911 912static int 913am335x_lcd_attach(device_t dev) 914{ 915 struct am335x_lcd_softc *sc; 916 917 int err; 918 int rid; 919 struct sysctl_ctx_list *ctx; 920 struct sysctl_oid *tree; 921 phandle_t root, panel_node; 922 923 err = 0; 924 sc = device_get_softc(dev); 925 sc->sc_dev = dev; 926 927 am335x_read_hdmi_property(dev); 928 929 root = OF_finddevice("/"); 930 if (root == 0) { 931 device_printf(dev, "failed to get FDT root node\n"); 932 return (ENXIO); 933 } 934 935 sc->sc_panel.ac_bias = 255; 936 sc->sc_panel.ac_bias_intrpt = 0; 937 sc->sc_panel.dma_burst_sz = 16; 938 sc->sc_panel.bpp = 16; 939 sc->sc_panel.fdd = 128; 940 sc->sc_panel.sync_edge = 0; 941 sc->sc_panel.sync_ctrl = 1; 942 943 panel_node = fdt_find_compatible(root, "ti,tilcdc,panel", 1); 944 if (panel_node != 0) { 945 device_printf(dev, "using static panel info\n"); 946 if (am335x_read_panel_info(dev, panel_node, &sc->sc_panel)) { 947 device_printf(dev, "failed to read panel info\n"); 948 return (ENXIO); 949 } 950 951 if (am335x_read_timing(dev, panel_node, &sc->sc_panel)) { 952 device_printf(dev, "failed to read timings\n"); 953 return (ENXIO); 954 } 955 } 956 957 ti_prcm_clk_enable(LCDC_CLK); 958 959 rid = 0; 960 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 961 RF_ACTIVE); 962 if (!sc->sc_mem_res) { 963 device_printf(dev, "cannot allocate memory window\n"); 964 return (ENXIO); 965 } 966 967 rid = 0; 968 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 969 RF_ACTIVE); 970 if (!sc->sc_irq_res) { 971 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 972 device_printf(dev, "cannot allocate interrupt\n"); 973 return (ENXIO); 974 } 975 976 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 977 NULL, am335x_lcd_intr, sc, 978 &sc->sc_intr_hl) != 0) { 979 bus_release_resource(dev, SYS_RES_IRQ, rid, 980 sc->sc_irq_res); 981 bus_release_resource(dev, SYS_RES_MEMORY, rid, 982 sc->sc_mem_res); 983 device_printf(dev, "Unable to setup the irq handler.\n"); 984 return (ENXIO); 985 } 986 987 LCD_LOCK_INIT(sc); 988 989 /* Init backlight interface */ 990 ctx = device_get_sysctl_ctx(sc->sc_dev); 991 tree = device_get_sysctl_tree(sc->sc_dev); 992 sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 993 "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 994 am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 995 sc->sc_backlight = 0; 996 /* Check if eCAS interface is available at this point */ 997 if (am335x_pwm_config_ecap(PWM_UNIT, 998 PWM_PERIOD, PWM_PERIOD) == 0) 999 sc->sc_backlight = 100; 1000 1001 sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, 1002 am335x_lcd_hdmi_event, sc, 0); 1003 1004 return (0); 1005} 1006 1007static int 1008am335x_lcd_detach(device_t dev) 1009{ 1010 /* Do not let unload driver */ 1011 return (EBUSY); 1012} 1013 1014static struct fb_info * 1015am335x_lcd_fb_getinfo(device_t dev) 1016{ 1017 struct am335x_lcd_softc *sc; 1018 1019 sc = device_get_softc(dev); 1020 1021 return (&sc->sc_fb_info); 1022} 1023 1024static device_method_t am335x_lcd_methods[] = { 1025 DEVMETHOD(device_probe, am335x_lcd_probe), 1026 DEVMETHOD(device_attach, am335x_lcd_attach), 1027 DEVMETHOD(device_detach, am335x_lcd_detach), 1028 1029 /* Framebuffer service methods */ 1030 DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo), 1031 1032 DEVMETHOD_END 1033}; 1034 1035static driver_t am335x_lcd_driver = { 1036 "fb", 1037 am335x_lcd_methods, 1038 sizeof(struct am335x_lcd_softc), 1039}; 1040 1041static devclass_t am335x_lcd_devclass; 1042 1043DRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 1044MODULE_VERSION(am335x_lcd, 1); 1045MODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 1046