1296936Smmel/*- 2296936Smmel * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3296936Smmel * All rights reserved. 4296936Smmel * 5296936Smmel * Redistribution and use in source and binary forms, with or without 6296936Smmel * modification, are permitted provided that the following conditions 7296936Smmel * are met: 8296936Smmel * 1. Redistributions of source code must retain the above copyright 9296936Smmel * notice, this list of conditions and the following disclaimer. 10296936Smmel * 2. Redistributions in binary form must reproduce the above copyright 11296936Smmel * notice, this list of conditions and the following disclaimer in the 12296936Smmel * documentation and/or other materials provided with the distribution. 13296936Smmel * 14296936Smmel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15296936Smmel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16296936Smmel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17296936Smmel * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18296936Smmel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19296936Smmel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20296936Smmel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21296936Smmel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22296936Smmel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23296936Smmel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24296936Smmel * SUCH DAMAGE. 25296936Smmel * 26296936Smmel * $FreeBSD$ 27296936Smmel */ 28296936Smmel 29296936Smmel#ifndef _TEGRA124_CAR_ 30296936Smmel#define _TEGRA124_CAR_ 31296936Smmel 32296936Smmel#include "clkdev_if.h" 33296936Smmel 34296936Smmel#define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val) 35296936Smmel#define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val) 36296936Smmel#define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set) 37296936Smmel#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) 38296936Smmel#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) 39296936Smmel 40296936Smmel#define RST_DEVICES_L 0x004 41296936Smmel#define RST_DEVICES_H 0x008 42296936Smmel#define RST_DEVICES_U 0x00C 43296936Smmel#define CLK_OUT_ENB_L 0x010 44296936Smmel#define CLK_OUT_ENB_H 0x014 45296936Smmel#define CLK_OUT_ENB_U 0x018 46296936Smmel#define CCLK_BURST_POLICY 0x020 47296936Smmel#define SUPER_CCLK_DIVIDER 0x024 48296936Smmel#define SCLK_BURST_POLICY 0x028 49296936Smmel#define SUPER_SCLK_DIVIDER 0x02c 50296936Smmel#define CLK_SYSTEM_RATE 0x030 51296936Smmel 52296936Smmel#define OSC_CTRL 0x050 53296936Smmel #define OSC_CTRL_OSC_FREQ_SHIFT 28 54296936Smmel #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 55296936Smmel 56296936Smmel#define PLLE_SS_CNTL 0x068 57296936Smmel#define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24) 58296936Smmel#define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24) 59296936Smmel#define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16) 60296936Smmel#define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16) 61296936Smmel#define PLLE_SS_CNTL_SSCINVERT (1 << 15) 62296936Smmel#define PLLE_SS_CNTL_SSCCENTER (1 << 14) 63296936Smmel#define PLLE_SS_CNTL_SSCBYP (1 << 12) 64296936Smmel#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 65296936Smmel#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 66296936Smmel#define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff 67296936Smmel#define PLLE_SS_CNTL_SSCMAX_VAL 0x25 68296936Smmel#define PLLE_SS_CNTL_DISABLE (PLLE_SS_CNTL_BYPASS_SS | \ 69296936Smmel PLLE_SS_CNTL_INTERP_RESET | \ 70296936Smmel PLLE_SS_CNTL_SSCBYP) 71296936Smmel#define PLLE_SS_CNTL_COEFFICIENTS_MASK (PLLE_SS_CNTL_SSCMAX_MASK | \ 72296936Smmel PLLE_SS_CNTL_SSCINC_MASK | \ 73296936Smmel PLLE_SS_CNTL_SSCINCINTRV_MASK) 74296936Smmel#define PLLE_SS_CNTL_COEFFICIENTS_VAL (PLLE_SS_CNTL_SSCMAX_VAL | \ 75296936Smmel PLLE_SS_CNTL_SSCINC_VAL | \ 76296936Smmel PLLE_SS_CNTL_SSCINCINTRV_VAL) 77296936Smmel 78296936Smmel#define PLLC_BASE 0x080 79296936Smmel#define PLLC_OUT 0x084 80296936Smmel#define PLLC_MISC2 0x088 81296936Smmel#define PLLC_MISC 0x08c 82296936Smmel#define PLLM_BASE 0x090 83296936Smmel#define PLLM_OUT 0x094 84296936Smmel#define PLLM_MISC 0x09c 85296936Smmel#define PLLP_BASE 0x0a0 86296936Smmel#define PLLP_MISC 0x0ac 87296936Smmel#define PLLP_OUTA 0x0a4 88296936Smmel#define PLLP_OUTB 0x0a8 89296936Smmel#define PLLA_BASE 0x0b0 90296936Smmel#define PLLA_OUT 0x0b4 91296936Smmel#define PLLA_MISC 0x0bc 92296936Smmel#define PLLU_BASE 0x0c0 93296936Smmel#define PLLU_MISC 0x0cc 94296936Smmel#define PLLD_BASE 0x0d0 95296936Smmel#define PLLD_MISC 0x0dc 96296936Smmel#define PLLX_BASE 0x0e0 97296936Smmel#define PLLX_MISC 0x0e4 98296936Smmel#define PLLE_BASE 0x0e8 99296936Smmel#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 100296936Smmel#define PLLE_BASE_DIVCML_SHIFT 24 101296936Smmel#define PLLE_BASE_DIVCML_MASK 0xf 102296936Smmel 103296936Smmel#define PLLE_MISC 0x0ec 104296936Smmel#define PLLE_MISC_SETUP_BASE_SHIFT 16 105296936Smmel#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 106296936Smmel#define PLLE_MISC_READY (1 << 15) 107296936Smmel#define PLLE_MISC_IDDQ_SWCTL (1 << 14) 108296936Smmel#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) 109296936Smmel#define PLLE_MISC_LOCK (1 << 11) 110296936Smmel#define PLLE_MISC_REF_ENABLE (1 << 10) 111296936Smmel#define PLLE_MISC_LOCK_ENABLE (1 << 9) 112296936Smmel#define PLLE_MISC_PTS (1 << 8) 113296936Smmel#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 114296936Smmel#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 115296936Smmel#define PLLE_MISC_VREG_CTRL_SHIFT 2 116296936Smmel#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 117296936Smmel 118296936Smmel#define CLK_SOURCE_I2S1 0x100 119296936Smmel#define CLK_SOURCE_I2S2 0x104 120296936Smmel#define CLK_SOURCE_SPDIF_OUT 0x108 121296936Smmel#define CLK_SOURCE_SPDIF_IN 0x10c 122296936Smmel#define CLK_SOURCE_PWM 0x110 123296936Smmel#define CLK_SOURCE_SPI2 0x118 124296936Smmel#define CLK_SOURCE_SPI3 0x11c 125296936Smmel#define CLK_SOURCE_I2C1 0x124 126296936Smmel#define CLK_SOURCE_I2C5 0x128 127296936Smmel#define CLK_SOURCE_SPI1 0x134 128296936Smmel#define CLK_SOURCE_DISP1 0x138 129296936Smmel#define CLK_SOURCE_DISP2 0x13c 130296936Smmel#define CLK_SOURCE_ISP 0x144 131296936Smmel#define CLK_SOURCE_VI 0x148 132296936Smmel#define CLK_SOURCE_SDMMC1 0x150 133296936Smmel#define CLK_SOURCE_SDMMC2 0x154 134296936Smmel#define CLK_SOURCE_SDMMC4 0x164 135296936Smmel#define CLK_SOURCE_VFIR 0x168 136296936Smmel#define CLK_SOURCE_HSI 0x174 137296936Smmel#define CLK_SOURCE_UARTA 0x178 138296936Smmel#define CLK_SOURCE_UARTB 0x17c 139296936Smmel#define CLK_SOURCE_HOST1X 0x180 140296936Smmel#define CLK_SOURCE_HDMI 0x18c 141296936Smmel#define CLK_SOURCE_I2C2 0x198 142296936Smmel#define CLK_SOURCE_EMC 0x19c 143296936Smmel#define CLK_SOURCE_UARTC 0x1a0 144296936Smmel#define CLK_SOURCE_VI_SENSOR 0x1a8 145296936Smmel#define CLK_SOURCE_SPI4 0x1b4 146296936Smmel#define CLK_SOURCE_I2C3 0x1b8 147296936Smmel#define CLK_SOURCE_SDMMC3 0x1bc 148296936Smmel#define CLK_SOURCE_UARTD 0x1c0 149296936Smmel#define CLK_SOURCE_VDE 0x1c8 150296936Smmel#define CLK_SOURCE_OWR 0x1cc 151296936Smmel#define CLK_SOURCE_NOR 0x1d0 152296936Smmel#define CLK_SOURCE_CSITE 0x1d4 153296936Smmel#define CLK_SOURCE_I2S0 0x1d8 154296936Smmel#define CLK_SOURCE_DTV 0x1dc 155296936Smmel#define CLK_SOURCE_MSENC 0x1f0 156296936Smmel#define CLK_SOURCE_TSEC 0x1f4 157296936Smmel#define CLK_SOURCE_SPARE2 0x1f8 158296936Smmel 159296936Smmel#define CLK_OUT_ENB_X 0x280 160296936Smmel#define RST_DEVICES_X 0x28C 161296936Smmel 162296936Smmel#define RST_DEVICES_V 0x358 163296936Smmel#define RST_DEVICES_W 0x35C 164296936Smmel#define CLK_OUT_ENB_V 0x360 165296936Smmel#define CLK_OUT_ENB_W 0x364 166296936Smmel#define CCLKG_BURST_POLICY 0x368 167296936Smmel#define SUPER_CCLKG_DIVIDER 0x36C 168296936Smmel#define CCLKLP_BURST_POLICY 0x370 169296936Smmel#define SUPER_CCLKLP_DIVIDER 0x374 170296936Smmel 171296936Smmel#define CLK_SOURCE_MSELECT 0x3b4 172296936Smmel#define CLK_SOURCE_TSENSOR 0x3b8 173296936Smmel#define CLK_SOURCE_I2S3 0x3bc 174296936Smmel#define CLK_SOURCE_I2S4 0x3c0 175296936Smmel#define CLK_SOURCE_I2C4 0x3c4 176296936Smmel#define CLK_SOURCE_SPI5 0x3c8 177296936Smmel#define CLK_SOURCE_SPI6 0x3cc 178296936Smmel#define CLK_SOURCE_AUDIO 0x3d0 179296936Smmel#define CLK_SOURCE_DAM0 0x3d8 180296936Smmel#define CLK_SOURCE_DAM1 0x3dc 181296936Smmel#define CLK_SOURCE_DAM2 0x3e0 182296936Smmel#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 183296936Smmel#define CLK_SOURCE_ACTMON 0x3e8 184296936Smmel#define CLK_SOURCE_EXTPERIPH1 0x3ec 185296936Smmel#define CLK_SOURCE_EXTPERIPH2 0x3f0 186296936Smmel#define CLK_SOURCE_EXTPERIPH3 0x3f4 187296936Smmel#define CLK_SOURCE_I2C_SLOW 0x3fc 188296936Smmel 189296936Smmel#define CLK_SOURCE_SYS 0x400 190296936Smmel#define CLK_SOURCE_SOR0 0x414 191296936Smmel#define CLK_SOURCE_SATA_OOB 0x420 192296936Smmel#define CLK_SOURCE_SATA 0x424 193296936Smmel#define CLK_SOURCE_HDA 0x428 194296936Smmel#define UTMIP_PLL_CFG0 0x480 195296936Smmel#define UTMIP_PLL_CFG1 0x484 196296936Smmel#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17) 197296936Smmel#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) 198296936Smmel#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15) 199296936Smmel#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) 200296936Smmel#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) 201296936Smmel#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 202296936Smmel#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 203296936Smmel 204296936Smmel#define UTMIP_PLL_CFG2 0x488 205296936Smmel#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 206296936Smmel#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 207296936Smmel#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) 208296936Smmel#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) 209296936Smmel#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) 210296936Smmel 211296936Smmel#define PLLE_AUX 0x48c 212296936Smmel#define PLLE_AUX_PLLRE_SEL (1 << 28) 213296936Smmel#define PLLE_AUX_SEQ_START_STATE (1 << 25) 214296936Smmel#define PLLE_AUX_SEQ_ENABLE (1 << 24) 215296936Smmel#define PLLE_AUX_SS_SWCTL (1 << 6) 216296936Smmel#define PLLE_AUX_ENABLE_SWCTL (1 << 4) 217296936Smmel#define PLLE_AUX_USE_LOCKDET (1 << 3) 218296936Smmel#define PLLE_AUX_PLLP_SEL (1 << 2) 219296936Smmel 220296936Smmel#define SATA_PLL_CFG0 0x490 221296936Smmel#define SATA_PLL_CFG0_SEQ_START_STATE (1 << 25) 222296936Smmel#define SATA_PLL_CFG0_SEQ_ENABLE (1 << 24) 223296936Smmel#define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7) 224296936Smmel#define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6) 225296936Smmel#define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 226296936Smmel#define SATA_PLL_CFG0_SEQ_IN_SWCTL (1 << 4) 227296936Smmel#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 2) 228296936Smmel#define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE (1 << 1) 229296936Smmel#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 230296936Smmel 231296936Smmel#define SATA_PLL_CFG1 0x494 232296936Smmel#define PCIE_PLL_CFG0 0x498 233296936Smmel#define PCIE_PLL_CFG0_SEQ_START_STATE (1 << 25) 234296936Smmel#define PCIE_PLL_CFG0_SEQ_ENABLE (1 << 24) 235296936Smmel 236296936Smmel#define PLLD2_BASE 0x4b8 237296936Smmel#define PLLD2_MISC 0x4bc 238296936Smmel#define UTMIP_PLL_CFG3 0x4c0 239296936Smmel#define PLLRE_BASE 0x4c4 240296936Smmel#define PLLRE_MISC 0x4c8 241296936Smmel#define PLLC2_BASE 0x4e8 242296936Smmel#define PLLC2_MISC 0x4ec 243296936Smmel#define PLLC3_BASE 0x4fc 244296936Smmel 245296936Smmel#define PLLC3_MISC 0x500 246296936Smmel#define PLLX_MISC2 0x514 247296936Smmel#define PLLX_MISC2 0x514 248296936Smmel#define PLLX_MISC3 0x518 249296936Smmel#define PLLX_MISC3_DYNRAMP_STEPB_MASK 0xFF 250296936Smmel#define PLLX_MISC3_DYNRAMP_STEPB_SHIFT 24 251296936Smmel#define PLLX_MISC3_DYNRAMP_STEPA_MASK 0xFF 252296936Smmel#define PLLX_MISC3_DYNRAMP_STEPA_SHIFT 16 253296936Smmel#define PLLX_MISC3_NDIV_NEW_MASK 0xFF 254296936Smmel#define PLLX_MISC3_NDIV_NEW_SHIFT 8 255296936Smmel#define PLLX_MISC3_EN_FSTLCK (1 << 5) 256296936Smmel#define PLLX_MISC3_LOCK_OVERRIDE (1 << 4) 257296936Smmel#define PLLX_MISC3_PLL_FREQLOCK (1 << 3) 258296936Smmel#define PLLX_MISC3_DYNRAMP_DONE (1 << 2) 259296936Smmel#define PLLX_MISC3_CLAMP_NDIV (1 << 1) 260296936Smmel#define PLLX_MISC3_EN_DYNRAMP (1 << 0) 261296936Smmel#define XUSBIO_PLL_CFG0 0x51c 262296936Smmel#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25) 263296936Smmel#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) 264296936Smmel#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) 265296936Smmel#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) 266296936Smmel#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 267296936Smmel 268296936Smmel#define PLLP_RESHIFT 0x528 269296936Smmel#define UTMIPLL_HW_PWRDN_CFG0 0x52c 270296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1 << 25) 271296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24) 272296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6) 273296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 274296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1 << 4) 275296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2) 276296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1 << 1) 277296936Smmel#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0) 278296936Smmel 279296936Smmel#define PLLDP_BASE 0x590 280296936Smmel#define PLLDP_MISC 0x594 281296936Smmel#define PLLC4_BASE 0x5a4 282296936Smmel#define PLLC4_MISC 0x5a8 283296936Smmel 284296936Smmel#define CLK_SOURCE_XUSB_CORE_HOST 0x600 285296936Smmel#define CLK_SOURCE_XUSB_FALCON 0x604 286296936Smmel#define CLK_SOURCE_XUSB_FS 0x608 287296936Smmel#define CLK_SOURCE_XUSB_CORE_DEV 0x60c 288296936Smmel#define CLK_SOURCE_XUSB_SS 0x610 289296936Smmel#define CLK_SOURCE_CILAB 0x614 290296936Smmel#define CLK_SOURCE_CILCD 0x618 291296936Smmel#define CLK_SOURCE_CILE 0x61c 292296936Smmel#define CLK_SOURCE_DSIA_LP 0x620 293296936Smmel#define CLK_SOURCE_DSIB_LP 0x624 294296936Smmel#define CLK_SOURCE_ENTROPY 0x628 295296936Smmel#define CLK_SOURCE_DVFS_REF 0x62c 296296936Smmel#define CLK_SOURCE_DVFS_SOC 0x630 297296936Smmel#define CLK_SOURCE_TRACECLKIN 0x634 298296936Smmel#define CLK_SOURCE_ADX 0x638 299296936Smmel#define CLK_SOURCE_AMX 0x63c 300296936Smmel#define CLK_SOURCE_EMC_LATENCY 0x640 301296936Smmel#define CLK_SOURCE_SOC_THERM 0x644 302296936Smmel#define CLK_SOURCE_VI_SENSOR2 0x658 303296936Smmel#define CLK_SOURCE_I2C6 0x65c 304296936Smmel#define CLK_SOURCE_EMC_DLL 0x664 305296936Smmel#define CLK_SOURCE_HDMI_AUDIO 0x668 306296936Smmel#define CLK_SOURCE_CLK72MHZ 0x66c 307296936Smmel#define CLK_SOURCE_ADX1 0x670 308296936Smmel#define CLK_SOURCE_AMX1 0x674 309296936Smmel#define CLK_SOURCE_VIC 0x678 310296936Smmel#define PLLP_OUTC 0x67c 311296936Smmel#define PLLP_MISC1 0x680 312296936Smmel 313296936Smmel 314296936Smmelstruct tegra124_car_softc { 315296936Smmel device_t dev; 316296936Smmel struct resource * mem_res; 317296936Smmel struct mtx mtx; 318296936Smmel struct clkdom *clkdom; 319296936Smmel int type; 320296936Smmel}; 321296936Smmel 322296936Smmelstruct tegra124_init_item { 323296936Smmel char *name; 324296936Smmel char *parent; 325296936Smmel uint64_t frequency; 326296936Smmel int enable; 327296936Smmel}; 328296936Smmel 329296936Smmelvoid tegra124_init_plls(struct tegra124_car_softc *sc); 330296936Smmel 331296936Smmelvoid tegra124_periph_clock(struct tegra124_car_softc *sc); 332296936Smmelvoid tegra124_super_mux_clock(struct tegra124_car_softc *sc); 333296936Smmel 334296936Smmelint tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, 335296936Smmel bool reset); 336296936Smmel 337296936Smmel#endif /*_TEGRA124_CAR_*/