1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef _TEGRA124_CAR_ 30#define _TEGRA124_CAR_ 31 32#include "clkdev_if.h" 33 34#define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val) 35#define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val) 36#define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set) 37#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) 38#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) 39 40#define RST_DEVICES_L 0x004 41#define RST_DEVICES_H 0x008 42#define RST_DEVICES_U 0x00C 43#define CLK_OUT_ENB_L 0x010 44#define CLK_OUT_ENB_H 0x014 45#define CLK_OUT_ENB_U 0x018 46#define CCLK_BURST_POLICY 0x020 47#define SUPER_CCLK_DIVIDER 0x024 48#define SCLK_BURST_POLICY 0x028 49#define SUPER_SCLK_DIVIDER 0x02c 50#define CLK_SYSTEM_RATE 0x030 51 52#define OSC_CTRL 0x050 53 #define OSC_CTRL_OSC_FREQ_SHIFT 28 54 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 55 56#define PLLE_SS_CNTL 0x068 57#define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24) 58#define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24) 59#define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16) 60#define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16) 61#define PLLE_SS_CNTL_SSCINVERT (1 << 15) 62#define PLLE_SS_CNTL_SSCCENTER (1 << 14) 63#define PLLE_SS_CNTL_SSCBYP (1 << 12) 64#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 65#define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 66#define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff 67#define PLLE_SS_CNTL_SSCMAX_VAL 0x25 68#define PLLE_SS_CNTL_DISABLE (PLLE_SS_CNTL_BYPASS_SS | \ 69 PLLE_SS_CNTL_INTERP_RESET | \ 70 PLLE_SS_CNTL_SSCBYP) 71#define PLLE_SS_CNTL_COEFFICIENTS_MASK (PLLE_SS_CNTL_SSCMAX_MASK | \ 72 PLLE_SS_CNTL_SSCINC_MASK | \ 73 PLLE_SS_CNTL_SSCINCINTRV_MASK) 74#define PLLE_SS_CNTL_COEFFICIENTS_VAL (PLLE_SS_CNTL_SSCMAX_VAL | \ 75 PLLE_SS_CNTL_SSCINC_VAL | \ 76 PLLE_SS_CNTL_SSCINCINTRV_VAL) 77 78#define PLLC_BASE 0x080 79#define PLLC_OUT 0x084 80#define PLLC_MISC2 0x088 81#define PLLC_MISC 0x08c 82#define PLLM_BASE 0x090 83#define PLLM_OUT 0x094 84#define PLLM_MISC 0x09c 85#define PLLP_BASE 0x0a0 86#define PLLP_MISC 0x0ac 87#define PLLP_OUTA 0x0a4 88#define PLLP_OUTB 0x0a8 89#define PLLA_BASE 0x0b0 90#define PLLA_OUT 0x0b4 91#define PLLA_MISC 0x0bc 92#define PLLU_BASE 0x0c0 93#define PLLU_MISC 0x0cc 94#define PLLD_BASE 0x0d0 95#define PLLD_MISC 0x0dc 96#define PLLX_BASE 0x0e0 97#define PLLX_MISC 0x0e4 98#define PLLE_BASE 0x0e8 99#define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 100#define PLLE_BASE_DIVCML_SHIFT 24 101#define PLLE_BASE_DIVCML_MASK 0xf 102 103#define PLLE_MISC 0x0ec 104#define PLLE_MISC_SETUP_BASE_SHIFT 16 105#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 106#define PLLE_MISC_READY (1 << 15) 107#define PLLE_MISC_IDDQ_SWCTL (1 << 14) 108#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) 109#define PLLE_MISC_LOCK (1 << 11) 110#define PLLE_MISC_REF_ENABLE (1 << 10) 111#define PLLE_MISC_LOCK_ENABLE (1 << 9) 112#define PLLE_MISC_PTS (1 << 8) 113#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 114#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 115#define PLLE_MISC_VREG_CTRL_SHIFT 2 116#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 117 118#define CLK_SOURCE_I2S1 0x100 119#define CLK_SOURCE_I2S2 0x104 120#define CLK_SOURCE_SPDIF_OUT 0x108 121#define CLK_SOURCE_SPDIF_IN 0x10c 122#define CLK_SOURCE_PWM 0x110 123#define CLK_SOURCE_SPI2 0x118 124#define CLK_SOURCE_SPI3 0x11c 125#define CLK_SOURCE_I2C1 0x124 126#define CLK_SOURCE_I2C5 0x128 127#define CLK_SOURCE_SPI1 0x134 128#define CLK_SOURCE_DISP1 0x138 129#define CLK_SOURCE_DISP2 0x13c 130#define CLK_SOURCE_ISP 0x144 131#define CLK_SOURCE_VI 0x148 132#define CLK_SOURCE_SDMMC1 0x150 133#define CLK_SOURCE_SDMMC2 0x154 134#define CLK_SOURCE_SDMMC4 0x164 135#define CLK_SOURCE_VFIR 0x168 136#define CLK_SOURCE_HSI 0x174 137#define CLK_SOURCE_UARTA 0x178 138#define CLK_SOURCE_UARTB 0x17c 139#define CLK_SOURCE_HOST1X 0x180 140#define CLK_SOURCE_HDMI 0x18c 141#define CLK_SOURCE_I2C2 0x198 142#define CLK_SOURCE_EMC 0x19c 143#define CLK_SOURCE_UARTC 0x1a0 144#define CLK_SOURCE_VI_SENSOR 0x1a8 145#define CLK_SOURCE_SPI4 0x1b4 146#define CLK_SOURCE_I2C3 0x1b8 147#define CLK_SOURCE_SDMMC3 0x1bc 148#define CLK_SOURCE_UARTD 0x1c0 149#define CLK_SOURCE_VDE 0x1c8 150#define CLK_SOURCE_OWR 0x1cc 151#define CLK_SOURCE_NOR 0x1d0 152#define CLK_SOURCE_CSITE 0x1d4 153#define CLK_SOURCE_I2S0 0x1d8 154#define CLK_SOURCE_DTV 0x1dc 155#define CLK_SOURCE_MSENC 0x1f0 156#define CLK_SOURCE_TSEC 0x1f4 157#define CLK_SOURCE_SPARE2 0x1f8 158 159#define CLK_OUT_ENB_X 0x280 160#define RST_DEVICES_X 0x28C 161 162#define RST_DEVICES_V 0x358 163#define RST_DEVICES_W 0x35C 164#define CLK_OUT_ENB_V 0x360 165#define CLK_OUT_ENB_W 0x364 166#define CCLKG_BURST_POLICY 0x368 167#define SUPER_CCLKG_DIVIDER 0x36C 168#define CCLKLP_BURST_POLICY 0x370 169#define SUPER_CCLKLP_DIVIDER 0x374 170 171#define CLK_SOURCE_MSELECT 0x3b4 172#define CLK_SOURCE_TSENSOR 0x3b8 173#define CLK_SOURCE_I2S3 0x3bc 174#define CLK_SOURCE_I2S4 0x3c0 175#define CLK_SOURCE_I2C4 0x3c4 176#define CLK_SOURCE_SPI5 0x3c8 177#define CLK_SOURCE_SPI6 0x3cc 178#define CLK_SOURCE_AUDIO 0x3d0 179#define CLK_SOURCE_DAM0 0x3d8 180#define CLK_SOURCE_DAM1 0x3dc 181#define CLK_SOURCE_DAM2 0x3e0 182#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 183#define CLK_SOURCE_ACTMON 0x3e8 184#define CLK_SOURCE_EXTPERIPH1 0x3ec 185#define CLK_SOURCE_EXTPERIPH2 0x3f0 186#define CLK_SOURCE_EXTPERIPH3 0x3f4 187#define CLK_SOURCE_I2C_SLOW 0x3fc 188 189#define CLK_SOURCE_SYS 0x400 190#define CLK_SOURCE_SOR0 0x414 191#define CLK_SOURCE_SATA_OOB 0x420 192#define CLK_SOURCE_SATA 0x424 193#define CLK_SOURCE_HDA 0x428 194#define UTMIP_PLL_CFG0 0x480 195#define UTMIP_PLL_CFG1 0x484 196#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17) 197#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) 198#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15) 199#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) 200#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) 201#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 202#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 203 204#define UTMIP_PLL_CFG2 0x488 205#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 206#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 207#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) 208#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) 209#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) 210 211#define PLLE_AUX 0x48c 212#define PLLE_AUX_PLLRE_SEL (1 << 28) 213#define PLLE_AUX_SEQ_START_STATE (1 << 25) 214#define PLLE_AUX_SEQ_ENABLE (1 << 24) 215#define PLLE_AUX_SS_SWCTL (1 << 6) 216#define PLLE_AUX_ENABLE_SWCTL (1 << 4) 217#define PLLE_AUX_USE_LOCKDET (1 << 3) 218#define PLLE_AUX_PLLP_SEL (1 << 2) 219 220#define SATA_PLL_CFG0 0x490 221#define SATA_PLL_CFG0_SEQ_START_STATE (1 << 25) 222#define SATA_PLL_CFG0_SEQ_ENABLE (1 << 24) 223#define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7) 224#define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6) 225#define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 226#define SATA_PLL_CFG0_SEQ_IN_SWCTL (1 << 4) 227#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 2) 228#define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE (1 << 1) 229#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 230 231#define SATA_PLL_CFG1 0x494 232#define PCIE_PLL_CFG0 0x498 233#define PCIE_PLL_CFG0_SEQ_START_STATE (1 << 25) 234#define PCIE_PLL_CFG0_SEQ_ENABLE (1 << 24) 235 236#define PLLD2_BASE 0x4b8 237#define PLLD2_MISC 0x4bc 238#define UTMIP_PLL_CFG3 0x4c0 239#define PLLRE_BASE 0x4c4 240#define PLLRE_MISC 0x4c8 241#define PLLC2_BASE 0x4e8 242#define PLLC2_MISC 0x4ec 243#define PLLC3_BASE 0x4fc 244 245#define PLLC3_MISC 0x500 246#define PLLX_MISC2 0x514 247#define PLLX_MISC2 0x514 248#define PLLX_MISC3 0x518 249#define PLLX_MISC3_DYNRAMP_STEPB_MASK 0xFF 250#define PLLX_MISC3_DYNRAMP_STEPB_SHIFT 24 251#define PLLX_MISC3_DYNRAMP_STEPA_MASK 0xFF 252#define PLLX_MISC3_DYNRAMP_STEPA_SHIFT 16 253#define PLLX_MISC3_NDIV_NEW_MASK 0xFF 254#define PLLX_MISC3_NDIV_NEW_SHIFT 8 255#define PLLX_MISC3_EN_FSTLCK (1 << 5) 256#define PLLX_MISC3_LOCK_OVERRIDE (1 << 4) 257#define PLLX_MISC3_PLL_FREQLOCK (1 << 3) 258#define PLLX_MISC3_DYNRAMP_DONE (1 << 2) 259#define PLLX_MISC3_CLAMP_NDIV (1 << 1) 260#define PLLX_MISC3_EN_DYNRAMP (1 << 0) 261#define XUSBIO_PLL_CFG0 0x51c 262#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25) 263#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) 264#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) 265#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) 266#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 267 268#define PLLP_RESHIFT 0x528 269#define UTMIPLL_HW_PWRDN_CFG0 0x52c 270#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1 << 25) 271#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24) 272#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6) 273#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 274#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1 << 4) 275#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2) 276#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1 << 1) 277#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0) 278 279#define PLLDP_BASE 0x590 280#define PLLDP_MISC 0x594 281#define PLLC4_BASE 0x5a4 282#define PLLC4_MISC 0x5a8 283 284#define CLK_SOURCE_XUSB_CORE_HOST 0x600 285#define CLK_SOURCE_XUSB_FALCON 0x604 286#define CLK_SOURCE_XUSB_FS 0x608 287#define CLK_SOURCE_XUSB_CORE_DEV 0x60c 288#define CLK_SOURCE_XUSB_SS 0x610 289#define CLK_SOURCE_CILAB 0x614 290#define CLK_SOURCE_CILCD 0x618 291#define CLK_SOURCE_CILE 0x61c 292#define CLK_SOURCE_DSIA_LP 0x620 293#define CLK_SOURCE_DSIB_LP 0x624 294#define CLK_SOURCE_ENTROPY 0x628 295#define CLK_SOURCE_DVFS_REF 0x62c 296#define CLK_SOURCE_DVFS_SOC 0x630 297#define CLK_SOURCE_TRACECLKIN 0x634 298#define CLK_SOURCE_ADX 0x638 299#define CLK_SOURCE_AMX 0x63c 300#define CLK_SOURCE_EMC_LATENCY 0x640 301#define CLK_SOURCE_SOC_THERM 0x644 302#define CLK_SOURCE_VI_SENSOR2 0x658 303#define CLK_SOURCE_I2C6 0x65c 304#define CLK_SOURCE_EMC_DLL 0x664 305#define CLK_SOURCE_HDMI_AUDIO 0x668 306#define CLK_SOURCE_CLK72MHZ 0x66c 307#define CLK_SOURCE_ADX1 0x670 308#define CLK_SOURCE_AMX1 0x674 309#define CLK_SOURCE_VIC 0x678 310#define PLLP_OUTC 0x67c 311#define PLLP_MISC1 0x680 312 313 314struct tegra124_car_softc { 315 device_t dev; 316 struct resource * mem_res; 317 struct mtx mtx; 318 struct clkdom *clkdom; 319 int type; 320}; 321 322struct tegra124_init_item { 323 char *name; 324 char *parent; 325 uint64_t frequency; 326 int enable; 327}; 328 329void tegra124_init_plls(struct tegra124_car_softc *sc); 330 331void tegra124_periph_clock(struct tegra124_car_softc *sc); 332void tegra124_super_mux_clock(struct tegra124_car_softc *sc); 333 334int tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, 335 bool reset); 336 337#endif /*_TEGRA124_CAR_*/