lpc_timer.c revision 239278 
1/*-
2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/arm/lpc/lpc_timer.c 239278 2012-08-15 05:37:10Z gonzo $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/malloc.h>
36#include <sys/rman.h>
37#include <sys/timetc.h>
38#include <sys/timeet.h>
39#include <machine/bus.h>
40#include <machine/cpu.h>
41#include <machine/frame.h>
42#include <machine/intr.h>
43
44#include <dev/fdt/fdt_common.h>
45#include <dev/ofw/ofw_bus.h>
46#include <dev/ofw/ofw_bus_subr.h>
47
48#include <arm/lpc/lpcreg.h>
49#include <arm/lpc/lpcvar.h>
50
51struct lpc_timer_softc {
52	device_t		lt_dev;
53	struct eventtimer	lt_et;
54	struct resource	*	lt_res[5];
55	bus_space_tag_t		lt_bst0;
56	bus_space_handle_t	lt_bsh0;
57	bus_space_tag_t		lt_bst1;
58	bus_space_handle_t	lt_bsh1;
59	int			lt_oneshot;
60	uint32_t		lt_period;
61};
62
63static struct resource_spec lpc_timer_spec[] = {
64	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
65	{ SYS_RES_MEMORY,	1,	RF_ACTIVE },
66	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
67	{ SYS_RES_IRQ,		1,	RF_ACTIVE },
68	{ -1, 0 }
69};
70
71static struct lpc_timer_softc *timer_softc = NULL;
72static int lpc_timer_initialized = 0;
73static int lpc_timer_probe(device_t);
74static int lpc_timer_attach(device_t);
75static int lpc_timer_start(struct eventtimer *, struct bintime *first,
76    struct bintime *);
77static int lpc_timer_stop(struct eventtimer *et);
78static unsigned lpc_get_timecount(struct timecounter *);
79static int lpc_hardclock(void *);
80
81#define	timer0_read_4(sc, reg)			\
82    bus_space_read_4(sc->lt_bst0, sc->lt_bsh0, reg)
83#define	timer0_write_4(sc, reg, val)		\
84    bus_space_write_4(sc->lt_bst0, sc->lt_bsh0, reg, val)
85#define	timer0_clear(sc)			\
86    do {					\
87	    timer0_write_4(sc, LPC_TIMER_TC, 0);	\
88	    timer0_write_4(sc, LPC_TIMER_PR, 0);	\
89	    timer0_write_4(sc, LPC_TIMER_PC, 0);	\
90    } while(0)
91
92#define	timer1_read_4(sc, reg)			\
93    bus_space_read_4(sc->lt_bst1, sc->lt_bsh1, reg)
94#define	timer1_write_4(sc, reg, val)		\
95    bus_space_write_4(sc->lt_bst1, sc->lt_bsh1, reg, val)
96#define	timer1_clear(sc)			\
97    do {					\
98	    timer1_write_4(sc, LPC_TIMER_TC, 0);	\
99	    timer1_write_4(sc, LPC_TIMER_PR, 0);	\
100	    timer1_write_4(sc, LPC_TIMER_PC, 0);	\
101    } while(0)
102
103static struct timecounter lpc_timecounter = {
104	.tc_get_timecount = lpc_get_timecount,
105	.tc_name = "LPC32x0 Timer1",
106	.tc_frequency = 0, /* will be filled later */
107	.tc_counter_mask = ~0u,
108	.tc_quality = 1000,
109};
110
111static int
112lpc_timer_probe(device_t dev)
113{
114
115	if (!ofw_bus_is_compatible(dev, "lpc,timer"))
116		return (ENXIO);
117
118	device_set_desc(dev, "LPC32x0 timer");
119	return (BUS_PROBE_DEFAULT);
120}
121
122static int
123lpc_timer_attach(device_t dev)
124{
125	void *intrcookie;
126	struct lpc_timer_softc *sc = device_get_softc(dev);
127	phandle_t node;
128	uint32_t freq;
129
130	if (timer_softc)
131		return (ENXIO);
132
133	timer_softc = sc;
134
135	if (bus_alloc_resources(dev, lpc_timer_spec, sc->lt_res)) {
136		device_printf(dev, "could not allocate resources\n");
137		return (ENXIO);
138	}
139
140	sc->lt_bst0 = rman_get_bustag(sc->lt_res[0]);
141	sc->lt_bsh0 = rman_get_bushandle(sc->lt_res[0]);
142	sc->lt_bst1 = rman_get_bustag(sc->lt_res[1]);
143	sc->lt_bsh1 = rman_get_bushandle(sc->lt_res[1]);
144
145	if (bus_setup_intr(dev, sc->lt_res[2], INTR_TYPE_CLK,
146	    lpc_hardclock, NULL, sc, &intrcookie)) {
147		device_printf(dev, "could not setup interrupt handler\n");
148		bus_release_resources(dev, lpc_timer_spec, sc->lt_res);
149		return (ENXIO);
150	}
151
152	/* Enable timer clock */
153	lpc_pwr_write(dev, LPC_CLKPWR_TIMCLK_CTRL1,
154	    LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 |
155	    LPC_CLKPWR_TIMCLK_CTRL1_TIMER1);
156
157	/* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */
158	node = ofw_bus_get_node(dev);
159	if (OF_getprop(OF_parent(node), "bus-frequency", &freq,
160	    sizeof(pcell_t)) <= 0) {
161		bus_release_resources(dev, lpc_timer_spec, sc->lt_res);
162		bus_teardown_intr(dev, sc->lt_res[2], intrcookie);
163		device_printf(dev, "could not obtain base clock frequency\n");
164		return (ENXIO);
165	}
166
167	freq = fdt32_to_cpu(freq);
168
169	/* Set desired frequency in event timer and timecounter */
170	sc->lt_et.et_frequency = (uint64_t)freq;
171	lpc_timecounter.tc_frequency = (uint64_t)freq;
172
173	sc->lt_et.et_name = "LPC32x0 Timer0";
174	sc->lt_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
175	sc->lt_et.et_quality = 1000;
176	sc->lt_et.et_min_period.sec = 0;
177	sc->lt_et.et_min_period.frac =
178	    ((0x00000002LLU << 32) / sc->lt_et.et_frequency) << 32;
179	sc->lt_et.et_max_period.sec = 0xfffffff0U / sc->lt_et.et_frequency;
180	sc->lt_et.et_max_period.frac =
181	    ((0xfffffffeLLU << 32) / sc->lt_et.et_frequency) << 32;
182	sc->lt_et.et_start = lpc_timer_start;
183	sc->lt_et.et_stop = lpc_timer_stop;
184	sc->lt_et.et_priv = sc;
185
186	et_register(&sc->lt_et);
187	tc_init(&lpc_timecounter);
188
189	/* Reset and enable timecounter */
190	timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET);
191	timer1_write_4(sc, LPC_TIMER_TCR, 0);
192	timer1_clear(sc);
193	timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE);
194
195	/* DELAY() now can work properly */
196	lpc_timer_initialized = 1;
197
198	return (0);
199}
200
201static int
202lpc_timer_start(struct eventtimer *et, struct bintime *first,
203    struct bintime *period)
204{
205	struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv;
206	uint32_t ticks;
207
208	if (period == NULL)
209		sc->lt_oneshot = 1;
210	else {
211		sc->lt_oneshot = 0;
212		sc->lt_period = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32;
213			sc->lt_period += sc->lt_et.et_frequency * first->sec;
214	}
215
216	if (first == NULL)
217		ticks = sc->lt_period;
218	else {
219		ticks = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32;
220		if (first->sec != 0)
221			ticks += sc->lt_et.et_frequency * first->sec;
222	}
223
224	/* Reset timer */
225	timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET);
226	timer0_write_4(sc, LPC_TIMER_TCR, 0);
227
228	/* Start timer */
229	timer0_clear(sc);
230	timer0_write_4(sc, LPC_TIMER_MR0, ticks);
231	timer0_write_4(sc, LPC_TIMER_MCR, LPC_TIMER_MCR_MR0I | LPC_TIMER_MCR_MR0S);
232	timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE);
233	return (0);
234}
235
236static int
237lpc_timer_stop(struct eventtimer *et)
238{
239	struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv;
240
241	timer0_write_4(sc, LPC_TIMER_TCR, 0);
242	return (0);
243}
244
245static device_method_t lpc_timer_methods[] = {
246	DEVMETHOD(device_probe,		lpc_timer_probe),
247	DEVMETHOD(device_attach,	lpc_timer_attach),
248	{ 0, 0 }
249};
250
251static driver_t lpc_timer_driver = {
252	"timer",
253	lpc_timer_methods,
254	sizeof(struct lpc_timer_softc),
255};
256
257static devclass_t lpc_timer_devclass;
258
259DRIVER_MODULE(timer, simplebus, lpc_timer_driver, lpc_timer_devclass, 0, 0);
260
261static int
262lpc_hardclock(void *arg)
263{
264	struct lpc_timer_softc *sc = (struct lpc_timer_softc *)arg;
265
266	/* Reset pending interrupt */
267	timer0_write_4(sc, LPC_TIMER_IR, 0xffffffff);
268
269	/* Start timer again */
270	if (!sc->lt_oneshot) {
271		timer0_clear(sc);
272		timer0_write_4(sc, LPC_TIMER_MR0, sc->lt_period);
273		timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE);
274	}
275
276	if (sc->lt_et.et_active)
277		sc->lt_et.et_event_cb(&sc->lt_et, sc->lt_et.et_arg);
278
279	return (FILTER_HANDLED);
280}
281
282static unsigned
283lpc_get_timecount(struct timecounter *tc)
284{
285	return timer1_read_4(timer_softc, LPC_TIMER_TC);
286}
287
288void
289cpu_initclocks(void)
290{
291	cpu_initclocks_bsp();
292}
293
294void
295DELAY(int usec)
296{
297	uint32_t counter;
298	uint32_t first, last;
299	int val = (lpc_timecounter.tc_frequency / 1000000 + 1) * usec;
300
301	/* Timer is not initialized yet */
302	if (!lpc_timer_initialized) {
303		for (; usec > 0; usec--)
304			for (counter = 100; counter > 0; counter--)
305				;
306		return;
307	}
308
309	first = lpc_get_timecount(&lpc_timecounter);
310	while (val > 0) {
311		last = lpc_get_timecount(&lpc_timecounter);
312		if (last < first) {
313			/* Timer rolled over */
314			last = first;
315		}
316
317		val -= (last - first);
318		first = last;
319	}
320}
321