1/*- 2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/lpc/lpc_timer.c 314503 2017-03-01 18:53:05Z ian $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/rman.h> 37#include <sys/timetc.h> 38#include <sys/timeet.h> 39#include <machine/bus.h> 40#include <machine/cpu.h> 41#include <machine/intr.h> 42 43#include <dev/ofw/ofw_bus.h> 44#include <dev/ofw/ofw_bus_subr.h> 45 46#include <arm/lpc/lpcreg.h> 47#include <arm/lpc/lpcvar.h> 48 49struct lpc_timer_softc { 50 device_t lt_dev; 51 struct eventtimer lt_et; 52 struct resource * lt_res[5]; 53 bus_space_tag_t lt_bst0; 54 bus_space_handle_t lt_bsh0; 55 bus_space_tag_t lt_bst1; 56 bus_space_handle_t lt_bsh1; 57 int lt_oneshot; 58 uint32_t lt_period; 59}; 60 61static struct resource_spec lpc_timer_spec[] = { 62 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 63 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 64 { SYS_RES_IRQ, 0, RF_ACTIVE }, 65 { SYS_RES_IRQ, 1, RF_ACTIVE }, 66 { -1, 0 } 67}; 68 69static struct lpc_timer_softc *timer_softc = NULL; 70static int lpc_timer_initialized = 0; 71static int lpc_timer_probe(device_t); 72static int lpc_timer_attach(device_t); 73static int lpc_timer_start(struct eventtimer *, 74 sbintime_t first, sbintime_t period); 75static int lpc_timer_stop(struct eventtimer *et); 76static unsigned lpc_get_timecount(struct timecounter *); 77static int lpc_hardclock(void *); 78 79#define timer0_read_4(sc, reg) \ 80 bus_space_read_4(sc->lt_bst0, sc->lt_bsh0, reg) 81#define timer0_write_4(sc, reg, val) \ 82 bus_space_write_4(sc->lt_bst0, sc->lt_bsh0, reg, val) 83#define timer0_clear(sc) \ 84 do { \ 85 timer0_write_4(sc, LPC_TIMER_TC, 0); \ 86 timer0_write_4(sc, LPC_TIMER_PR, 0); \ 87 timer0_write_4(sc, LPC_TIMER_PC, 0); \ 88 } while(0) 89 90#define timer1_read_4(sc, reg) \ 91 bus_space_read_4(sc->lt_bst1, sc->lt_bsh1, reg) 92#define timer1_write_4(sc, reg, val) \ 93 bus_space_write_4(sc->lt_bst1, sc->lt_bsh1, reg, val) 94#define timer1_clear(sc) \ 95 do { \ 96 timer1_write_4(sc, LPC_TIMER_TC, 0); \ 97 timer1_write_4(sc, LPC_TIMER_PR, 0); \ 98 timer1_write_4(sc, LPC_TIMER_PC, 0); \ 99 } while(0) 100 101static struct timecounter lpc_timecounter = { 102 .tc_get_timecount = lpc_get_timecount, 103 .tc_name = "LPC32x0 Timer1", 104 .tc_frequency = 0, /* will be filled later */ 105 .tc_counter_mask = ~0u, 106 .tc_quality = 1000, 107}; 108 109static int 110lpc_timer_probe(device_t dev) 111{ 112 113 if (!ofw_bus_status_okay(dev)) 114 return (ENXIO); 115 116 if (!ofw_bus_is_compatible(dev, "lpc,timer")) 117 return (ENXIO); 118 119 device_set_desc(dev, "LPC32x0 timer"); 120 return (BUS_PROBE_DEFAULT); 121} 122 123static int 124lpc_timer_attach(device_t dev) 125{ 126 void *intrcookie; 127 struct lpc_timer_softc *sc = device_get_softc(dev); 128 phandle_t node; 129 uint32_t freq; 130 131 if (timer_softc) 132 return (ENXIO); 133 134 timer_softc = sc; 135 136 if (bus_alloc_resources(dev, lpc_timer_spec, sc->lt_res)) { 137 device_printf(dev, "could not allocate resources\n"); 138 return (ENXIO); 139 } 140 141 sc->lt_bst0 = rman_get_bustag(sc->lt_res[0]); 142 sc->lt_bsh0 = rman_get_bushandle(sc->lt_res[0]); 143 sc->lt_bst1 = rman_get_bustag(sc->lt_res[1]); 144 sc->lt_bsh1 = rman_get_bushandle(sc->lt_res[1]); 145 146 if (bus_setup_intr(dev, sc->lt_res[2], INTR_TYPE_CLK, 147 lpc_hardclock, NULL, sc, &intrcookie)) { 148 device_printf(dev, "could not setup interrupt handler\n"); 149 bus_release_resources(dev, lpc_timer_spec, sc->lt_res); 150 return (ENXIO); 151 } 152 153 /* Enable timer clock */ 154 lpc_pwr_write(dev, LPC_CLKPWR_TIMCLK_CTRL1, 155 LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 | 156 LPC_CLKPWR_TIMCLK_CTRL1_TIMER1); 157 158 /* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */ 159 node = ofw_bus_get_node(dev); 160 if (OF_getencprop(OF_parent(node), "bus-frequency", &freq, 161 sizeof(pcell_t)) <= 0) { 162 bus_release_resources(dev, lpc_timer_spec, sc->lt_res); 163 bus_teardown_intr(dev, sc->lt_res[2], intrcookie); 164 device_printf(dev, "could not obtain base clock frequency\n"); 165 return (ENXIO); 166 } 167 168 /* Set desired frequency in event timer and timecounter */ 169 sc->lt_et.et_frequency = (uint64_t)freq; 170 lpc_timecounter.tc_frequency = (uint64_t)freq; 171 172 sc->lt_et.et_name = "LPC32x0 Timer0"; 173 sc->lt_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 174 sc->lt_et.et_quality = 1000; 175 sc->lt_et.et_min_period = (0x00000002LLU << 32) / sc->lt_et.et_frequency; 176 sc->lt_et.et_max_period = (0xfffffffeLLU << 32) / sc->lt_et.et_frequency; 177 sc->lt_et.et_start = lpc_timer_start; 178 sc->lt_et.et_stop = lpc_timer_stop; 179 sc->lt_et.et_priv = sc; 180 181 et_register(&sc->lt_et); 182 tc_init(&lpc_timecounter); 183 184 /* Reset and enable timecounter */ 185 timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET); 186 timer1_write_4(sc, LPC_TIMER_TCR, 0); 187 timer1_clear(sc); 188 timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); 189 190 /* DELAY() now can work properly */ 191 lpc_timer_initialized = 1; 192 193 return (0); 194} 195 196static int 197lpc_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 198{ 199 struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv; 200 uint32_t ticks; 201 202 if (period == 0) { 203 sc->lt_oneshot = 1; 204 sc->lt_period = 0; 205 } else { 206 sc->lt_oneshot = 0; 207 sc->lt_period = ((uint32_t)et->et_frequency * period) >> 32; 208 } 209 210 if (first == 0) 211 ticks = sc->lt_period; 212 else 213 ticks = ((uint32_t)et->et_frequency * first) >> 32; 214 215 /* Reset timer */ 216 timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET); 217 timer0_write_4(sc, LPC_TIMER_TCR, 0); 218 219 /* Start timer */ 220 timer0_clear(sc); 221 timer0_write_4(sc, LPC_TIMER_MR0, ticks); 222 timer0_write_4(sc, LPC_TIMER_MCR, LPC_TIMER_MCR_MR0I | LPC_TIMER_MCR_MR0S); 223 timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); 224 return (0); 225} 226 227static int 228lpc_timer_stop(struct eventtimer *et) 229{ 230 struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv; 231 232 timer0_write_4(sc, LPC_TIMER_TCR, 0); 233 return (0); 234} 235 236static device_method_t lpc_timer_methods[] = { 237 DEVMETHOD(device_probe, lpc_timer_probe), 238 DEVMETHOD(device_attach, lpc_timer_attach), 239 { 0, 0 } 240}; 241 242static driver_t lpc_timer_driver = { 243 "timer", 244 lpc_timer_methods, 245 sizeof(struct lpc_timer_softc), 246}; 247 248static devclass_t lpc_timer_devclass; 249 250DRIVER_MODULE(timer, simplebus, lpc_timer_driver, lpc_timer_devclass, 0, 0); 251 252static int 253lpc_hardclock(void *arg) 254{ 255 struct lpc_timer_softc *sc = (struct lpc_timer_softc *)arg; 256 257 /* Reset pending interrupt */ 258 timer0_write_4(sc, LPC_TIMER_IR, 0xffffffff); 259 260 /* Start timer again */ 261 if (!sc->lt_oneshot) { 262 timer0_clear(sc); 263 timer0_write_4(sc, LPC_TIMER_MR0, sc->lt_period); 264 timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); 265 } 266 267 if (sc->lt_et.et_active) 268 sc->lt_et.et_event_cb(&sc->lt_et, sc->lt_et.et_arg); 269 270 return (FILTER_HANDLED); 271} 272 273static unsigned 274lpc_get_timecount(struct timecounter *tc) 275{ 276 return timer1_read_4(timer_softc, LPC_TIMER_TC); 277} 278 279void 280DELAY(int usec) 281{ 282 uint32_t counter; 283 uint32_t first, last; 284 int val = (lpc_timecounter.tc_frequency / 1000000 + 1) * usec; 285 286 /* Timer is not initialized yet */ 287 if (!lpc_timer_initialized) { 288 for (; usec > 0; usec--) 289 for (counter = 100; counter > 0; counter--) 290 ; 291 return; 292 } 293 294 first = lpc_get_timecount(&lpc_timecounter); 295 while (val > 0) { 296 last = lpc_get_timecount(&lpc_timecounter); 297 if (last < first) { 298 /* Timer rolled over */ 299 last = first; 300 } 301 302 val -= (last - first); 303 first = last; 304 } 305} 306