1/*- 2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/lpc/lpc_spi.c 331722 2018-03-29 02:50:57Z eadler $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bio.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/endian.h> 36#include <sys/kernel.h> 37#include <sys/kthread.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/mutex.h> 42#include <sys/queue.h> 43#include <sys/resource.h> 44#include <sys/rman.h> 45#include <sys/time.h> 46#include <sys/timetc.h> 47#include <sys/watchdog.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <machine/intr.h> 52 53#include <dev/spibus/spi.h> 54#include <dev/spibus/spibusvar.h> 55 56#include <dev/ofw/ofw_bus.h> 57#include <dev/ofw/ofw_bus_subr.h> 58 59#include <arm/lpc/lpcreg.h> 60#include <arm/lpc/lpcvar.h> 61 62#include "spibus_if.h" 63 64struct lpc_spi_softc 65{ 66 device_t ls_dev; 67 struct resource * ls_mem_res; 68 struct resource * ls_irq_res; 69 bus_space_tag_t ls_bst; 70 bus_space_handle_t ls_bsh; 71}; 72 73static int lpc_spi_probe(device_t); 74static int lpc_spi_attach(device_t); 75static int lpc_spi_detach(device_t); 76static int lpc_spi_transfer(device_t, device_t, struct spi_command *); 77 78#define lpc_spi_read_4(_sc, _reg) \ 79 bus_space_read_4(_sc->ls_bst, _sc->ls_bsh, _reg) 80#define lpc_spi_write_4(_sc, _reg, _val) \ 81 bus_space_write_4(_sc->ls_bst, _sc->ls_bsh, _reg, _val) 82 83static int 84lpc_spi_probe(device_t dev) 85{ 86 87 if (!ofw_bus_status_okay(dev)) 88 return (ENXIO); 89 90 if (!ofw_bus_is_compatible(dev, "lpc,spi")) 91 return (ENXIO); 92 93 device_set_desc(dev, "LPC32x0 PL022 SPI/SSP controller"); 94 return (BUS_PROBE_DEFAULT); 95} 96 97static int 98lpc_spi_attach(device_t dev) 99{ 100 struct lpc_spi_softc *sc = device_get_softc(dev); 101 int rid; 102 103 sc->ls_dev = dev; 104 105 rid = 0; 106 sc->ls_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 107 RF_ACTIVE); 108 if (!sc->ls_mem_res) { 109 device_printf(dev, "cannot allocate memory window\n"); 110 return (ENXIO); 111 } 112 113 sc->ls_bst = rman_get_bustag(sc->ls_mem_res); 114 sc->ls_bsh = rman_get_bushandle(sc->ls_mem_res); 115 116 rid = 0; 117 sc->ls_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 118 RF_ACTIVE); 119 if (!sc->ls_irq_res) { 120 device_printf(dev, "cannot allocate interrupt\n"); 121 return (ENXIO); 122 } 123 124 bus_space_write_4(sc->ls_bst, 0xd0028100, 0, (1<<12)|(1<<10)|(1<<9)|(1<<8)|(1<<6)|(1<<5)); 125 lpc_pwr_write(dev, LPC_CLKPWR_SSP_CTRL, LPC_CLKPWR_SSP_CTRL_SSP0EN); 126 lpc_spi_write_4(sc, LPC_SSP_CR0, LPC_SSP_CR0_DSS(8)); 127 lpc_spi_write_4(sc, LPC_SSP_CR1, LPC_SSP_CR1_SSE); 128 lpc_spi_write_4(sc, LPC_SSP_CPSR, 128); 129 130 device_add_child(dev, "spibus", 0); 131 return (bus_generic_attach(dev)); 132} 133 134static int 135lpc_spi_detach(device_t dev) 136{ 137 return (EBUSY); 138} 139 140static int 141lpc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 142{ 143 struct lpc_spi_softc *sc = device_get_softc(dev); 144 uint32_t cs; 145 uint8_t *in_buf, *out_buf; 146 int i; 147 148 spibus_get_cs(child, &cs); 149 150 cs &= ~SPIBUS_CS_HIGH; 151 152 /* Set CS active */ 153 lpc_gpio_set_state(child, cs, 0); 154 155 /* Wait for FIFO to be ready */ 156 while ((lpc_spi_read_4(sc, LPC_SSP_SR) & LPC_SSP_SR_TNF) == 0); 157 158 /* Command */ 159 in_buf = cmd->rx_cmd; 160 out_buf = cmd->tx_cmd; 161 for (i = 0; i < cmd->tx_cmd_sz; i++) { 162 lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); 163 in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); 164 } 165 166 /* Data */ 167 in_buf = cmd->rx_data; 168 out_buf = cmd->tx_data; 169 for (i = 0; i < cmd->tx_data_sz; i++) { 170 lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); 171 in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); 172 } 173 174 /* Set CS inactive */ 175 lpc_gpio_set_state(child, cs, 1); 176 177 return (0); 178} 179 180static device_method_t lpc_spi_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, lpc_spi_probe), 183 DEVMETHOD(device_attach, lpc_spi_attach), 184 DEVMETHOD(device_detach, lpc_spi_detach), 185 186 /* SPI interface */ 187 DEVMETHOD(spibus_transfer, lpc_spi_transfer), 188 189 { 0, 0 } 190}; 191 192static devclass_t lpc_spi_devclass; 193 194static driver_t lpc_spi_driver = { 195 "spi", 196 lpc_spi_methods, 197 sizeof(struct lpc_spi_softc), 198}; 199 200DRIVER_MODULE(lpcspi, simplebus, lpc_spi_driver, lpc_spi_devclass, 0, 0); 201