1280712Sian/*- 2280712Sian * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3280712Sian * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4280712Sian * All rights reserved. 5280712Sian * 6280712Sian * Redistribution and use in source and binary forms, with or without 7280712Sian * modification, are permitted provided that the following conditions 8280712Sian * are met: 9280712Sian * 1. Redistributions of source code must retain the above copyright 10280712Sian * notice, this list of conditions and the following disclaimer. 11280712Sian * 2. Redistributions in binary form must reproduce the above copyright 12280712Sian * notice, this list of conditions and the following disclaimer in the 13280712Sian * documentation and/or other materials provided with the distribution. 14280712Sian * 15280712Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16280712Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17280712Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18280712Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19280712Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20280712Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21280712Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22280712Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23280712Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24280712Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25280712Sian * SUCH DAMAGE. 26280712Sian * 27280712Sian * $FreeBSD$ 28280712Sian */ 29280712Sian 30295801Sskra#ifndef _MACHINE_PTE_V6_H_ 31295801Sskra#define _MACHINE_PTE_V6_H_ 32280712Sian 33280712Sian/* 34280712Sian * Domain Types for the Domain Access Control Register. 35280712Sian */ 36280712Sian#define DOMAIN_FAULT 0x00 /* no access */ 37280712Sian#define DOMAIN_CLIENT 0x01 /* client */ 38280712Sian#define DOMAIN_RESERVED 0x02 /* reserved */ 39280712Sian#define DOMAIN_MANAGER 0x03 /* manager */ 40280712Sian 41280712Sian/* 42280712Sian * TEX remap registers attributes 43280712Sian */ 44280712Sian#define PRRR_SO 0 /* Strongly ordered memory */ 45280712Sian#define PRRR_DEV 1 /* Device memory */ 46280712Sian#define PRRR_MEM 2 /* Normal memory */ 47280712Sian#define PRRR_DS0 (1 << 16) /* Shared bit for Device, S = 0 */ 48280712Sian#define PRRR_DS1 (1 << 17) /* Shared bit for Device, S = 1 */ 49280712Sian#define PRRR_NS0 (1 << 18) /* Shared bit for Normal, S = 0 */ 50280712Sian#define PRRR_NS1 (1 << 19) /* Shared bit for Normal, S = 1 */ 51280712Sian#define PRRR_NOS_SHIFT 24 /* base shif for Not Outer Shared bits */ 52280712Sian 53280712Sian#define NMRR_NC 0 /* Noncachable*/ 54280712Sian#define NMRR_WB_WA 1 /* Write Back, Write Allocate */ 55280712Sian#define NMRR_WT 2 /* Write Through, Non-Write Allocate */ 56280712Sian#define NMRR_WB 3 /* Write Back, Non-Write Allocate */ 57280712Sian 58280712Sian/* 59280712Sian * 60280712Sian * The ARM MMU is capable of mapping memory in the following chunks: 61280712Sian * 62280712Sian * 16M Supersections (L1 table) 63280712Sian * 64280712Sian * 1M Sections (L1 table) 65280712Sian * 66280712Sian * 64K Large Pages (L2 table) 67280712Sian * 68280712Sian * 4K Small Pages (L2 table) 69280712Sian * 70280712Sian * 71280712Sian * Coarse Tables can map Large and Small Pages. 72280712Sian * Coarse Tables are 1K in length. 73280712Sian * 74280712Sian * The Translation Table Base register holds the pointer to the 75280712Sian * L1 Table. The L1 Table is a 16K contiguous chunk of memory 76280712Sian * aligned to a 16K boundary. Each entry in the L1 Table maps 77280712Sian * 1M of virtual address space, either via a Section mapping or 78280712Sian * via an L2 Table. 79280712Sian * 80280712Sian */ 81280712Sian#define L1_TABLE_SIZE 0x4000 /* 16K */ 82280712Sian#define L1_ENTRIES 0x1000 /* 4K */ 83280712Sian#define L2_TABLE_SIZE 0x0400 /* 1K */ 84280712Sian#define L2_ENTRIES 0x0100 /* 256 */ 85280712Sian 86280712Sian/* ARMv6 super-sections. */ 87280712Sian#define L1_SUP_SIZE 0x01000000 /* 16M */ 88280712Sian#define L1_SUP_OFFSET (L1_SUP_SIZE - 1) 89280712Sian#define L1_SUP_FRAME (~L1_SUP_OFFSET) 90280712Sian#define L1_SUP_SHIFT 24 91280712Sian 92280712Sian#define L1_S_SIZE 0x00100000 /* 1M */ 93280712Sian#define L1_S_OFFSET (L1_S_SIZE - 1) 94280712Sian#define L1_S_FRAME (~L1_S_OFFSET) 95280712Sian#define L1_S_SHIFT 20 96280712Sian 97280712Sian#define L2_L_SIZE 0x00010000 /* 64K */ 98280712Sian#define L2_L_OFFSET (L2_L_SIZE - 1) 99280712Sian#define L2_L_FRAME (~L2_L_OFFSET) 100280712Sian#define L2_L_SHIFT 16 101280712Sian 102280712Sian#define L2_S_SIZE 0x00001000 /* 4K */ 103280712Sian#define L2_S_OFFSET (L2_S_SIZE - 1) 104280712Sian#define L2_S_FRAME (~L2_S_OFFSET) 105280712Sian#define L2_S_SHIFT 12 106280712Sian 107280712Sian/* 108280712Sian * ARM MMU L1 Descriptors 109280712Sian */ 110280712Sian#define L1_TYPE_INV 0x00 /* Invalid (fault) */ 111280712Sian#define L1_TYPE_C 0x01 /* Coarse L2 */ 112280712Sian#define L1_TYPE_S 0x02 /* Section */ 113280712Sian#define L1_TYPE_MASK 0x03 /* Mask of type bits */ 114280712Sian 115280712Sian/* L1 Section Descriptor */ 116280712Sian#define L1_S_B 0x00000004 /* bufferable Section */ 117280712Sian#define L1_S_C 0x00000008 /* cacheable Section */ 118280712Sian#define L1_S_NX 0x00000010 /* not executeable */ 119280712Sian#define L1_S_DOM(x) ((x) << 5) /* domain */ 120280712Sian#define L1_S_DOM_MASK L1_S_DOM(0xf) 121280712Sian#define L1_S_P 0x00000200 /* ECC enable for this section */ 122280712Sian#define L1_S_AP(x) ((x) << 10) /* access permissions */ 123280712Sian#define L1_S_AP0 0x00000400 /* access permissions bit 0 */ 124280712Sian#define L1_S_AP1 0x00000800 /* access permissions bit 1 */ 125280712Sian#define L1_S_TEX(x) ((x) << 12) /* type extension */ 126280712Sian#define L1_S_TEX0 0x00001000 /* type extension bit 0 */ 127280712Sian#define L1_S_TEX1 0x00002000 /* type extension bit 1 */ 128280712Sian#define L1_S_TEX2 0x00004000 /* type extension bit 2 */ 129280712Sian#define L1_S_AP2 0x00008000 /* access permissions bit 2 */ 130280712Sian#define L1_S_SHARED 0x00010000 /* shared */ 131280712Sian#define L1_S_NG 0x00020000 /* not global */ 132280712Sian#define L1_S_SUPERSEC 0x00040000 /* Section is a super-section. */ 133280712Sian#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 134280712Sian 135280712Sian/* L1 Coarse Descriptor */ 136280712Sian#define L1_C_DOM(x) ((x) << 5) /* domain */ 137280712Sian#define L1_C_DOM_MASK L1_C_DOM(0xf) 138280712Sian#define L1_C_P 0x00000200 /* ECC enable for this section */ 139280712Sian#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 140280712Sian 141280712Sian/* 142280712Sian * ARM MMU L2 Descriptors 143280712Sian */ 144280712Sian#define L2_TYPE_INV 0x00 /* Invalid (fault) */ 145280712Sian#define L2_TYPE_L 0x01 /* Large Page - 64k - not used yet*/ 146280712Sian#define L2_TYPE_S 0x02 /* Small Page - 4 */ 147280712Sian#define L2_TYPE_MASK 0x03 148280712Sian 149280712Sian#define L2_NX 0x00000001 /* Not executable */ 150280712Sian#define L2_B 0x00000004 /* Bufferable page */ 151280712Sian#define L2_C 0x00000008 /* Cacheable page */ 152280712Sian#define L2_AP(x) ((x) << 4) 153280712Sian#define L2_AP0 0x00000010 /* access permissions bit 0*/ 154280712Sian#define L2_AP1 0x00000020 /* access permissions bit 1*/ 155280712Sian#define L2_TEX(x) ((x) << 6) /* type extension */ 156280712Sian#define L2_TEX0 0x00000040 /* type extension bit 0 */ 157280712Sian#define L2_TEX1 0x00000080 /* type extension bit 1 */ 158280712Sian#define L2_TEX2 0x00000100 /* type extension bit 2 */ 159280712Sian#define L2_AP2 0x00000200 /* access permissions bit 2*/ 160280712Sian#define L2_SHARED 0x00000400 /* shared */ 161280712Sian#define L2_NG 0x00000800 /* not global */ 162280712Sian 163280712Sian/* 164280712Sian * TEX classes encoding 165280712Sian */ 166280712Sian#define TEX1_CLASS_0 ( 0) 167280712Sian#define TEX1_CLASS_1 ( L1_S_B) 168280712Sian#define TEX1_CLASS_2 ( L1_S_C ) 169280712Sian#define TEX1_CLASS_3 ( L1_S_C | L1_S_B) 170280712Sian#define TEX1_CLASS_4 (L1_S_TEX0 ) 171280712Sian#define TEX1_CLASS_5 (L1_S_TEX0 | L1_S_B) 172280712Sian#define TEX1_CLASS_6 (L1_S_TEX0 | L1_S_C ) /* Reserved for ARM11 */ 173280712Sian#define TEX1_CLASS_7 (L1_S_TEX0 | L1_S_C | L1_S_B) 174280712Sian 175280712Sian#define TEX2_CLASS_0 ( 0) 176280712Sian#define TEX2_CLASS_1 ( L2_B) 177280712Sian#define TEX2_CLASS_2 ( L2_C ) 178280712Sian#define TEX2_CLASS_3 ( L2_C | L2_B) 179280712Sian#define TEX2_CLASS_4 (L2_TEX0 ) 180280712Sian#define TEX2_CLASS_5 (L2_TEX0 | L2_B) 181280712Sian#define TEX2_CLASS_6 (L2_TEX0 | L2_C ) /* Reserved for ARM11 */ 182280712Sian#define TEX2_CLASS_7 (L2_TEX0 | L2_C | L2_B) 183280712Sian 184280712Sian/* L1 table definitions. */ 185280712Sian#define NB_IN_PT1 L1_TABLE_SIZE 186280712Sian#define NPTE1_IN_PT1 L1_ENTRIES 187280712Sian 188280712Sian/* L2 table definitions. */ 189280712Sian#define NB_IN_PT2 L2_TABLE_SIZE 190280712Sian#define NPTE2_IN_PT2 L2_ENTRIES 191280712Sian 192280712Sian/* 193280712Sian * Map memory attributes to TEX classes 194280712Sian */ 195280712Sian#define PTE2_ATTR_WB_WA TEX2_CLASS_0 196280712Sian#define PTE2_ATTR_NOCACHE TEX2_CLASS_1 197280712Sian#define PTE2_ATTR_DEVICE TEX2_CLASS_2 198280712Sian#define PTE2_ATTR_SO TEX2_CLASS_3 199291492Smmel#define PTE2_ATTR_WT TEX2_CLASS_4 200280712Sian/* 201280712Sian * Software defined bits for L1 descriptors 202280712Sian * - L1_AP0 is used as page accessed bit 203280712Sian * - L1_AP2 (RO / not RW) is used as page not modified bit 204280712Sian * - L1_TEX0 is used as software emulated RO bit 205280712Sian */ 206280712Sian#define PTE1_V L1_TYPE_S /* Valid bit */ 207280712Sian#define PTE1_A L1_S_AP0 /* Accessed - software emulated */ 208280712Sian#define PTE1_NM L1_S_AP2 /* not modified bit - software emulated 209280712Sian * used as real write enable bit */ 210280712Sian#define PTE1_M 0 /* Modified (dummy) */ 211280712Sian#define PTE1_S L1_S_SHARED /* Shared */ 212280712Sian#define PTE1_NG L1_S_NG /* Not global */ 213280712Sian#define PTE1_G 0 /* Global (dummy) */ 214280712Sian#define PTE1_NX L1_S_NX /* Not executable */ 215280712Sian#define PTE1_X 0 /* Executable (dummy) */ 216280712Sian#define PTE1_RO L1_S_TEX1 /* Read Only */ 217280712Sian#define PTE1_RW 0 /* Read-Write (dummy) */ 218280712Sian#define PTE1_U L1_S_AP1 /* User */ 219280712Sian#define PTE1_NU 0 /* Not user (kernel only) (dummy) */ 220280712Sian#define PTE1_W L1_S_TEX2 /* Wired */ 221280712Sian 222280712Sian#define PTE1_SHIFT L1_S_SHIFT 223280712Sian#define PTE1_SIZE L1_S_SIZE 224280712Sian#define PTE1_OFFSET L1_S_OFFSET 225280712Sian#define PTE1_FRAME L1_S_FRAME 226280712Sian 227280712Sian#define PTE1_ATTR_MASK (L1_S_TEX0 | L1_S_C | L1_S_B) 228280712Sian 229280712Sian#define PTE1_AP_KR (PTE1_RO | PTE1_NM) 230280712Sian#define PTE1_AP_KRW 0 231280712Sian#define PTE1_AP_KRUR (PTE1_RO | PTE1_NM | PTE1_U) 232280712Sian#define PTE1_AP_KRWURW PTE1_U 233280712Sian 234280712Sian/* 235280712Sian * PTE1 descriptors creation macros. 236280712Sian */ 237280712Sian#define PTE1_PA(pa) ((pa) & PTE1_FRAME) 238280712Sian#define PTE1_AP_COMMON (PTE1_V | PTE1_S) 239280712Sian 240280712Sian#define PTE1(pa, ap, attr) (PTE1_PA(pa) | (ap) | (attr) | PTE1_AP_COMMON) 241280712Sian 242280712Sian#define PTE1_KERN(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_G, attr) 243280712Sian#define PTE1_KERN_NG(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_NG, attr) 244280712Sian 245280712Sian#define PTE1_LINK(pa) (((pa) & L1_C_ADDR_MASK) | L1_TYPE_C) 246280712Sian 247280712Sian/* 248280712Sian * Software defined bits for L2 descriptors 249280712Sian * - L2_AP0 is used as page accessed bit 250280712Sian * - L2_AP2 (RO / not RW) is used as page not modified bit 251280712Sian * - L2_TEX0 is used as software emulated RO bit 252280712Sian */ 253280712Sian#define PTE2_V L2_TYPE_S /* Valid bit */ 254280712Sian#define PTE2_A L2_AP0 /* Accessed - software emulated */ 255280712Sian#define PTE2_NM L2_AP2 /* not modified bit - software emulated 256280712Sian * used as real write enable bit */ 257280712Sian#define PTE2_M 0 /* Modified (dummy) */ 258280712Sian#define PTE2_S L2_SHARED /* Shared */ 259280712Sian#define PTE2_NG L2_NG /* Not global */ 260280712Sian#define PTE2_G 0 /* Global (dummy) */ 261280712Sian#define PTE2_NX L2_NX /* Not executable */ 262280712Sian#define PTE2_X 0 /* Not executable (dummy) */ 263280712Sian#define PTE2_RO L2_TEX1 /* Read Only */ 264280712Sian#define PTE2_U L2_AP1 /* User */ 265280712Sian#define PTE2_NU 0 /* Not user (kernel only) (dummy) */ 266280712Sian#define PTE2_W L2_TEX2 /* Wired */ 267280712Sian 268280712Sian#define PTE2_SHIFT L2_S_SHIFT 269280712Sian#define PTE2_SIZE L2_S_SIZE 270280712Sian#define PTE2_OFFSET L2_S_OFFSET 271280712Sian#define PTE2_FRAME L2_S_FRAME 272280712Sian 273280712Sian#define PTE2_ATTR_MASK (L2_TEX0 | L2_C | L2_B) 274280712Sian 275280712Sian#define PTE2_AP_KR (PTE2_RO | PTE2_NM) 276280712Sian#define PTE2_AP_KRW 0 277280712Sian#define PTE2_AP_KRUR (PTE2_RO | PTE2_NM | PTE2_U) 278280712Sian#define PTE2_AP_KRWURW PTE2_U 279280712Sian 280280712Sian/* 281280712Sian * PTE2 descriptors creation macros. 282280712Sian */ 283280712Sian#define PTE2_PA(pa) ((pa) & PTE2_FRAME) 284280712Sian#define PTE2_AP_COMMON (PTE2_V | PTE2_S) 285280712Sian 286280712Sian#define PTE2(pa, ap, attr) (PTE2_PA(pa) | (ap) | (attr) | PTE2_AP_COMMON) 287280712Sian 288280712Sian#define PTE2_KERN(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_G, attr) 289280712Sian#define PTE2_KERN_NG(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_NG, attr) 290280712Sian 291295801Sskra#endif /* !_MACHINE_PTE_V6_H_ */ 292