pmap-v4.h revision 254532
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the Systems Programming Group of the University of Utah Computer 7 * Science Department and William Jolitz of UUNET Technologies Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Derived from hp300 version by Mike Hibler, this version by William 38 * Jolitz uses a recursive map [a pde points to the page directory] to 39 * map the page tables using the pagetables themselves. This is done to 40 * reduce the impact on kernel virtual memory for lots of sparse address 41 * space, and to reduce the cost of memory to each process. 42 * 43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46 * 47 * $FreeBSD: head/sys/arm/include/pmap.h 254532 2013-08-19 15:12:36Z raj $ 48 */ 49 50#ifndef _MACHINE_PMAP_H_ 51#define _MACHINE_PMAP_H_ 52 53#include <machine/pte.h> 54#include <machine/cpuconf.h> 55/* 56 * Pte related macros 57 */ 58#if ARM_ARCH_6 || ARM_ARCH_7A 59#ifdef SMP 60#define PTE_NOCACHE 2 61#else 62#define PTE_NOCACHE 1 63#endif 64#define PTE_CACHE 6 65#define PTE_DEVICE 2 66#define PTE_PAGETABLE 4 67#else 68#define PTE_NOCACHE 1 69#define PTE_CACHE 2 70#define PTE_PAGETABLE 3 71#endif 72 73enum mem_type { 74 STRONG_ORD = 0, 75 DEVICE_NOSHARE, 76 DEVICE_SHARE, 77 NRML_NOCACHE, 78 NRML_IWT_OWT, 79 NRML_IWB_OWB, 80 NRML_IWBA_OWBA 81}; 82 83#ifndef LOCORE 84 85#include <sys/queue.h> 86#include <sys/_cpuset.h> 87#include <sys/_lock.h> 88#include <sys/_mutex.h> 89 90#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 91#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 92 93#ifdef _KERNEL 94 95#define vtophys(va) pmap_kextract((vm_offset_t)(va)) 96 97#endif 98 99#define pmap_page_get_memattr(m) ((m)->md.pv_memattr) 100#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 101#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0) 102void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 103 104/* 105 * Pmap stuff 106 */ 107 108/* 109 * This structure is used to hold a virtual<->physical address 110 * association and is used mostly by bootstrap code 111 */ 112struct pv_addr { 113 SLIST_ENTRY(pv_addr) pv_list; 114 vm_offset_t pv_va; 115 vm_paddr_t pv_pa; 116}; 117 118struct pv_entry; 119struct pv_chunk; 120 121struct md_page { 122 int pvh_attrs; 123 vm_memattr_t pv_memattr; 124 vm_offset_t pv_kva; /* first kernel VA mapping */ 125 TAILQ_HEAD(,pv_entry) pv_list; 126}; 127 128struct l1_ttable; 129struct l2_dtable; 130 131 132/* 133 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 134 * A bucket size of 16 provides for 16MB of contiguous virtual address 135 * space per l2_dtable. Most processes will, therefore, require only two or 136 * three of these to map their whole working set. 137 */ 138#define L2_BUCKET_LOG2 4 139#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 140/* 141 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 142 * of l2_dtable structures required to track all possible page descriptors 143 * mappable by an L1 translation table is given by the following constants: 144 */ 145#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 146#define L2_SIZE (1 << L2_LOG2) 147 148struct pmap { 149 struct mtx pm_mtx; 150 u_int8_t pm_domain; 151 struct l1_ttable *pm_l1; 152 struct l2_dtable *pm_l2[L2_SIZE]; 153 cpuset_t pm_active; /* active on cpus */ 154 struct pmap_statistics pm_stats; /* pmap statictics */ 155#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 156 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ 157#else 158 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 159#endif 160}; 161 162typedef struct pmap *pmap_t; 163 164#ifdef _KERNEL 165extern struct pmap kernel_pmap_store; 166#define kernel_pmap (&kernel_pmap_store) 167#define pmap_kernel() kernel_pmap 168 169#define PMAP_ASSERT_LOCKED(pmap) \ 170 mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 171#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 172#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 173#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 174 NULL, MTX_DEF | MTX_DUPOK) 175#define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 176#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 177#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 178#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 179#endif 180 181 182/* 183 * For each vm_page_t, there is a list of all currently valid virtual 184 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 185 */ 186typedef struct pv_entry { 187 vm_offset_t pv_va; /* virtual address for mapping */ 188 TAILQ_ENTRY(pv_entry) pv_list; 189 int pv_flags; /* flags (wired, etc...) */ 190#if (ARM_MMU_V6 + ARM_MMU_V7) == 0 191 pmap_t pv_pmap; /* pmap where mapping lies */ 192 TAILQ_ENTRY(pv_entry) pv_plist; 193#endif 194} *pv_entry_t; 195 196/* 197 * pv_entries are allocated in chunks per-process. This avoids the 198 * need to track per-pmap assignments. 199 */ 200#define _NPCM 8 201#define _NPCPV 252 202 203struct pv_chunk { 204 pmap_t pc_pmap; 205 TAILQ_ENTRY(pv_chunk) pc_list; 206 uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */ 207 uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */ 208 TAILQ_ENTRY(pv_chunk) pc_lru; 209 struct pv_entry pc_pventry[_NPCPV]; 210}; 211 212#ifdef _KERNEL 213 214boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 215 216/* 217 * virtual address to page table entry and 218 * to physical address. Likewise for alternate address space. 219 * Note: these work recursively, thus vtopte of a pte will give 220 * the corresponding pde that in turn maps it. 221 */ 222 223/* 224 * The current top of kernel VM. 225 */ 226extern vm_offset_t pmap_curmaxkvaddr; 227 228struct pcb; 229 230void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 231/* Virtual address to page table entry */ 232static __inline pt_entry_t * 233vtopte(vm_offset_t va) 234{ 235 pd_entry_t *pdep; 236 pt_entry_t *ptep; 237 238 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 239 return (NULL); 240 return (ptep); 241} 242 243extern vm_paddr_t phys_avail[]; 244extern vm_offset_t virtual_avail; 245extern vm_offset_t virtual_end; 246 247void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt); 248int pmap_change_attr(vm_offset_t, vm_size_t, int); 249void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 250void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 251void *pmap_kenter_temp(vm_paddr_t pa, int i); 252void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 253vm_paddr_t pmap_kextract(vm_offset_t va); 254void pmap_kremove(vm_offset_t); 255void *pmap_mapdev(vm_offset_t, vm_size_t); 256void pmap_unmapdev(vm_offset_t, vm_size_t); 257vm_page_t pmap_use_pt(pmap_t, vm_offset_t); 258void pmap_debug(int); 259void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 260void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 261vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 262void 263pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 264 int cache); 265int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 266int pmap_dmap_iscurrent(pmap_t pmap); 267 268/* 269 * Definitions for MMU domains 270 */ 271#define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 272#define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 273 274/* 275 * The new pmap ensures that page-tables are always mapping Write-Thru. 276 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 277 * on every change. 278 * 279 * Unfortunately, not all CPUs have a write-through cache mode. So we 280 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 281 * and if there is the chance for PTE syncs to be needed, we define 282 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 283 * the code. 284 */ 285extern int pmap_needs_pte_sync; 286 287/* 288 * These macros define the various bit masks in the PTE. 289 * 290 * We use these macros since we use different bits on different processor 291 * models. 292 */ 293 294#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 295#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 296 L1_S_XSCALE_TEX(TEX_XSCALE_T)) 297 298#define L2_L_CACHE_MASK_generic (L2_B|L2_C) 299#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 300 L2_XSCALE_L_TEX(TEX_XSCALE_T)) 301 302#define L2_S_PROT_U_generic (L2_AP(AP_U)) 303#define L2_S_PROT_W_generic (L2_AP(AP_W)) 304#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 305 306#define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 307#define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 308#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 309 310#define L2_S_CACHE_MASK_generic (L2_B|L2_C) 311#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 312 L2_XSCALE_T_TEX(TEX_XSCALE_X)) 313 314#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 315#define L1_S_PROTO_xscale (L1_TYPE_S) 316 317#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 318#define L1_C_PROTO_xscale (L1_TYPE_C) 319 320#define L2_L_PROTO (L2_TYPE_L) 321 322#define L2_S_PROTO_generic (L2_TYPE_S) 323#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 324 325/* 326 * User-visible names for the ones that vary with MMU class. 327 */ 328#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 329#define L2_AP(x) (L2_AP0(x)) 330#else 331#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 332#endif 333 334#if ARM_NMMUS > 1 335/* More than one MMU class configured; use variables. */ 336#define L2_S_PROT_U pte_l2_s_prot_u 337#define L2_S_PROT_W pte_l2_s_prot_w 338#define L2_S_PROT_MASK pte_l2_s_prot_mask 339 340#define L1_S_CACHE_MASK pte_l1_s_cache_mask 341#define L2_L_CACHE_MASK pte_l2_l_cache_mask 342#define L2_S_CACHE_MASK pte_l2_s_cache_mask 343 344#define L1_S_PROTO pte_l1_s_proto 345#define L1_C_PROTO pte_l1_c_proto 346#define L2_S_PROTO pte_l2_s_proto 347 348#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 349#define L2_S_PROT_U L2_S_PROT_U_generic 350#define L2_S_PROT_W L2_S_PROT_W_generic 351#define L2_S_PROT_MASK L2_S_PROT_MASK_generic 352 353#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 354#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 355#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 356 357#define L1_S_PROTO L1_S_PROTO_generic 358#define L1_C_PROTO L1_C_PROTO_generic 359#define L2_S_PROTO L2_S_PROTO_generic 360 361#elif ARM_MMU_XSCALE == 1 362#define L2_S_PROT_U L2_S_PROT_U_xscale 363#define L2_S_PROT_W L2_S_PROT_W_xscale 364#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 365 366#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 367#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 368#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 369 370#define L1_S_PROTO L1_S_PROTO_xscale 371#define L1_C_PROTO L1_C_PROTO_xscale 372#define L2_S_PROTO L2_S_PROTO_xscale 373 374#elif (ARM_MMU_V6 + ARM_MMU_V7) != 0 375/* 376 * AP[2:1] access permissions model: 377 * 378 * AP[2](APX) - Write Disable 379 * AP[1] - User Enable 380 * AP[0] - Reference Flag 381 * 382 * AP[2] AP[1] Kernel User 383 * 0 0 R/W N 384 * 0 1 R/W R/W 385 * 1 0 R N 386 * 1 1 R R 387 * 388 */ 389#define L2_S_PROT_R (0) /* kernel read */ 390#define L2_S_PROT_U (L2_AP0(2)) /* user read */ 391#define L2_S_REF (L2_AP0(1)) /* reference flag */ 392 393#define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R|L2_APX) 394#define L2_S_EXECUTABLE(pte) (!(pte & L2_XN)) 395#define L2_S_WRITABLE(pte) (!(pte & L2_APX)) 396#define L2_S_REFERENCED(pte) (!!(pte & L2_S_REF)) 397 398#ifndef SMP 399#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C) 400#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C) 401#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C) 402#else 403#define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED) 404#define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED) 405#define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED) 406#endif /* SMP */ 407 408#define L1_S_PROTO (L1_TYPE_S) 409#define L1_C_PROTO (L1_TYPE_C) 410#define L2_S_PROTO (L2_TYPE_S) 411 412#ifndef SMP 413#define ARM_L1S_STRONG_ORD (0) 414#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 415#define ARM_L1S_DEVICE_SHARE (L1_S_B) 416#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)) 417#define ARM_L1S_NRML_IWT_OWT (L1_S_C) 418#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B) 419#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B) 420 421#define ARM_L2L_STRONG_ORD (0) 422#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 423#define ARM_L2L_DEVICE_SHARE (L2_B) 424#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)) 425#define ARM_L2L_NRML_IWT_OWT (L2_C) 426#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B) 427#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B) 428 429#define ARM_L2S_STRONG_ORD (0) 430#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 431#define ARM_L2S_DEVICE_SHARE (L2_B) 432#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)) 433#define ARM_L2S_NRML_IWT_OWT (L2_C) 434#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B) 435#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B) 436#else 437#define ARM_L1S_STRONG_ORD (0) 438#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 439#define ARM_L1S_DEVICE_SHARE (L1_S_B) 440#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED) 441#define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED) 442#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED) 443#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED) 444 445#define ARM_L2L_STRONG_ORD (0) 446#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 447#define ARM_L2L_DEVICE_SHARE (L2_B) 448#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED) 449#define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED) 450#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 451#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED) 452 453#define ARM_L2S_STRONG_ORD (0) 454#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 455#define ARM_L2S_DEVICE_SHARE (L2_B) 456#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED) 457#define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED) 458#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 459#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED) 460#endif /* SMP */ 461#endif /* ARM_NMMUS > 1 */ 462 463#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 464#define PMAP_NEEDS_PTE_SYNC 1 465#define PMAP_INCLUDE_PTE_SYNC 466#elif defined(CPU_XSCALE_81342) 467#define PMAP_NEEDS_PTE_SYNC 1 468#define PMAP_INCLUDE_PTE_SYNC 469#elif (ARM_MMU_SA1 == 0) 470#define PMAP_NEEDS_PTE_SYNC 0 471#endif 472 473/* 474 * These macros return various bits based on kernel/user and protection. 475 * Note that the compiler will usually fold these at compile time. 476 */ 477#if (ARM_MMU_V6 + ARM_MMU_V7) == 0 478 479#define L1_S_PROT_U (L1_S_AP(AP_U)) 480#define L1_S_PROT_W (L1_S_AP(AP_W)) 481#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 482#define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W) 483 484#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 485 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 486 487#define L2_L_PROT_U (L2_AP(AP_U)) 488#define L2_L_PROT_W (L2_AP(AP_W)) 489#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 490 491#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 492 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 493 494#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 495 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 496#else 497#define L1_S_PROT_U (L1_S_AP(AP_U)) 498#define L1_S_PROT_MASK (L1_S_APX|L1_S_AP(0x3)) 499#define L1_S_WRITABLE(pd) (!((pd) & L1_S_APX)) 500 501#define L1_S_PROT(ku, pr) (L1_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L1_S_PROT_U : 0) | \ 502 (((pr) & VM_PROT_WRITE) ? L1_S_APX : 0))) 503 504#define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3)) 505#define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 506 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 507 508#define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 509 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 510 511#endif 512 513/* 514 * Macros to test if a mapping is mappable with an L1 Section mapping 515 * or an L2 Large Page mapping. 516 */ 517#define L1_S_MAPPABLE_P(va, pa, size) \ 518 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 519 520#define L2_L_MAPPABLE_P(va, pa, size) \ 521 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 522 523/* 524 * Provide a fallback in case we were not able to determine it at 525 * compile-time. 526 */ 527#ifndef PMAP_NEEDS_PTE_SYNC 528#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 529#define PMAP_INCLUDE_PTE_SYNC 530#endif 531 532#define PTE_SYNC(pte) \ 533do { \ 534 if (PMAP_NEEDS_PTE_SYNC) { \ 535 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 536 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 537 } else \ 538 cpu_drain_writebuf(); \ 539} while (/*CONSTCOND*/0) 540 541#define PTE_SYNC_RANGE(pte, cnt) \ 542do { \ 543 if (PMAP_NEEDS_PTE_SYNC) { \ 544 cpu_dcache_wb_range((vm_offset_t)(pte), \ 545 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 546 cpu_l2cache_wb_range((vm_offset_t)(pte), \ 547 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 548 } else \ 549 cpu_drain_writebuf(); \ 550} while (/*CONSTCOND*/0) 551 552extern pt_entry_t pte_l1_s_cache_mode; 553extern pt_entry_t pte_l1_s_cache_mask; 554 555extern pt_entry_t pte_l2_l_cache_mode; 556extern pt_entry_t pte_l2_l_cache_mask; 557 558extern pt_entry_t pte_l2_s_cache_mode; 559extern pt_entry_t pte_l2_s_cache_mask; 560 561extern pt_entry_t pte_l1_s_cache_mode_pt; 562extern pt_entry_t pte_l2_l_cache_mode_pt; 563extern pt_entry_t pte_l2_s_cache_mode_pt; 564 565extern pt_entry_t pte_l2_s_prot_u; 566extern pt_entry_t pte_l2_s_prot_w; 567extern pt_entry_t pte_l2_s_prot_mask; 568 569extern pt_entry_t pte_l1_s_proto; 570extern pt_entry_t pte_l1_c_proto; 571extern pt_entry_t pte_l2_s_proto; 572 573extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 574extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 575 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 576extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 577 578#if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) 579void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 580void pmap_zero_page_generic(vm_paddr_t, int, int); 581 582void pmap_pte_init_generic(void); 583#if defined(CPU_ARM8) 584void pmap_pte_init_arm8(void); 585#endif 586#if defined(CPU_ARM9) 587void pmap_pte_init_arm9(void); 588#endif /* CPU_ARM9 */ 589#if defined(CPU_ARM10) 590void pmap_pte_init_arm10(void); 591#endif /* CPU_ARM10 */ 592#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 593void pmap_pte_init_mmu_v6(void); 594#endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */ 595#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 596 597#if /* ARM_MMU_SA1 == */1 598void pmap_pte_init_sa1(void); 599#endif /* ARM_MMU_SA1 == 1 */ 600 601#if ARM_MMU_XSCALE == 1 602void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 603void pmap_zero_page_xscale(vm_paddr_t, int, int); 604 605void pmap_pte_init_xscale(void); 606 607void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 608 609void pmap_use_minicache(vm_offset_t, vm_size_t); 610#endif /* ARM_MMU_XSCALE == 1 */ 611#if defined(CPU_XSCALE_81342) 612#define ARM_HAVE_SUPERSECTIONS 613#endif 614 615#define PTE_KERNEL 0 616#define PTE_USER 1 617#define l1pte_valid(pde) ((pde) != 0) 618#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 619#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 620#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 621 622#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 623#define l2pte_valid(pte) ((pte) != 0) 624#define l2pte_pa(pte) ((pte) & L2_S_FRAME) 625#define l2pte_minidata(pte) (((pte) & \ 626 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 627 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 628 629/* L1 and L2 page table macros */ 630#define pmap_pde_v(pde) l1pte_valid(*(pde)) 631#define pmap_pde_section(pde) l1pte_section_p(*(pde)) 632#define pmap_pde_page(pde) l1pte_page_p(*(pde)) 633#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 634 635#define pmap_pte_v(pte) l2pte_valid(*(pte)) 636#define pmap_pte_pa(pte) l2pte_pa(*(pte)) 637 638/* 639 * Flags that indicate attributes of pages or mappings of pages. 640 * 641 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 642 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 643 * pv_entry's for each page. They live in the same "namespace" so 644 * that we can clear multiple attributes at a time. 645 * 646 * Note the "non-cacheable" flag generally means the page has 647 * multiple mappings in a given address space. 648 */ 649#define PVF_MOD 0x01 /* page is modified */ 650#define PVF_REF 0x02 /* page is referenced */ 651#define PVF_WIRED 0x04 /* mapping is wired */ 652#define PVF_WRITE 0x08 /* mapping is writable */ 653#define PVF_EXEC 0x10 /* mapping is executable */ 654#define PVF_NC 0x20 /* mapping is non-cacheable */ 655#define PVF_MWC 0x40 /* mapping is used multiple times in userland */ 656#define PVF_UNMAN 0x80 /* mapping is unmanaged */ 657 658void vector_page_setprot(int); 659 660/* 661 * This structure is used by machine-dependent code to describe 662 * static mappings of devices, created at bootstrap time. 663 */ 664struct pmap_devmap { 665 vm_offset_t pd_va; /* virtual address */ 666 vm_paddr_t pd_pa; /* physical address */ 667 vm_size_t pd_size; /* size of region */ 668 vm_prot_t pd_prot; /* protection code */ 669 int pd_cache; /* cache attributes */ 670}; 671 672const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 673const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 674 675void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 676void pmap_devmap_register(const struct pmap_devmap *); 677 678#define SECTION_CACHE 0x1 679#define SECTION_PT 0x2 680void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 681#ifdef ARM_HAVE_SUPERSECTIONS 682void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 683#endif 684 685extern char *_tmppt; 686 687void pmap_postinit(void); 688 689#ifdef ARM_USE_SMALL_ALLOC 690void arm_add_smallalloc_pages(void *, void *, int, int); 691vm_offset_t arm_ptovirt(vm_paddr_t); 692void arm_init_smallalloc(void); 693struct arm_small_page { 694 void *addr; 695 TAILQ_ENTRY(arm_small_page) pg_list; 696}; 697 698#endif 699 700#define ARM_NOCACHE_KVA_SIZE 0x1000000 701extern vm_offset_t arm_nocache_startaddr; 702void *arm_remap_nocache(void *, vm_size_t); 703void arm_unmap_nocache(void *, vm_size_t); 704 705extern vm_paddr_t dump_avail[]; 706#endif /* _KERNEL */ 707 708#endif /* !LOCORE */ 709 710#endif /* !_MACHINE_PMAP_H_ */ 711