pmap-v4.h revision 171620
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the Systems Programming Group of the University of Utah Computer 7 * Science Department and William Jolitz of UUNET Technologies Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Derived from hp300 version by Mike Hibler, this version by William 38 * Jolitz uses a recursive map [a pde points to the page directory] to 39 * map the page tables using the pagetables themselves. This is done to 40 * reduce the impact on kernel virtual memory for lots of sparse address 41 * space, and to reduce the cost of memory to each process. 42 * 43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46 * 47 * $FreeBSD: head/sys/arm/include/pmap.h 171620 2007-07-27 14:45:04Z cognet $ 48 */ 49 50#ifndef _MACHINE_PMAP_H_ 51#define _MACHINE_PMAP_H_ 52 53#include <machine/pte.h> 54#include <machine/cpuconf.h> 55/* 56 * Pte related macros 57 */ 58#define PTE_NOCACHE 0 59#define PTE_CACHE 1 60#define PTE_PAGETABLE 2 61 62#ifndef LOCORE 63 64#include <sys/queue.h> 65#include <sys/_lock.h> 66#include <sys/_mutex.h> 67 68#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 69#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 70 71#ifdef _KERNEL 72 73#define vtophys(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va)) 74#define pmap_kextract(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va)) 75 76#endif 77 78#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 79/* 80 * Pmap stuff 81 */ 82 83/* 84 * This structure is used to hold a virtual<->physical address 85 * association and is used mostly by bootstrap code 86 */ 87struct pv_addr { 88 SLIST_ENTRY(pv_addr) pv_list; 89 vm_offset_t pv_va; 90 vm_paddr_t pv_pa; 91}; 92 93struct pv_entry; 94 95struct md_page { 96 int pvh_attrs; 97 u_int uro_mappings; 98 u_int urw_mappings; 99 union { 100 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 101 u_int i_mappings; 102 } k_u; 103#define kro_mappings k_u.s_mappings[0] 104#define krw_mappings k_u.s_mappings[1] 105#define k_mappings k_u.i_mappings 106 int pv_list_count; 107 TAILQ_HEAD(,pv_entry) pv_list; 108}; 109 110#define VM_MDPAGE_INIT(pg) \ 111do { \ 112 TAILQ_INIT(&pg->pv_list); \ 113 mtx_init(&(pg)->md_page.pvh_mtx, "MDPAGE Mutex", NULL, MTX_DEV);\ 114 (pg)->mdpage.pvh_attrs = 0; \ 115 (pg)->mdpage.uro_mappings = 0; \ 116 (pg)->mdpage.urw_mappings = 0; \ 117 (pg)->mdpage.k_mappings = 0; \ 118} while (/*CONSTCOND*/0) 119 120struct l1_ttable; 121struct l2_dtable; 122 123 124/* 125 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 126 * A bucket size of 16 provides for 16MB of contiguous virtual address 127 * space per l2_dtable. Most processes will, therefore, require only two or 128 * three of these to map their whole working set. 129 */ 130#define L2_BUCKET_LOG2 4 131#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 132/* 133 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 134 * of l2_dtable structures required to track all possible page descriptors 135 * mappable by an L1 translation table is given by the following constants: 136 */ 137#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 138#define L2_SIZE (1 << L2_LOG2) 139 140struct pmap { 141 struct mtx pm_mtx; 142 u_int8_t pm_domain; 143 struct l1_ttable *pm_l1; 144 struct l2_dtable *pm_l2[L2_SIZE]; 145 pd_entry_t *pm_pdir; /* KVA of page directory */ 146 int pm_count; /* reference count */ 147 int pm_active; /* active on cpus */ 148 struct pmap_statistics pm_stats; /* pmap statictics */ 149 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 150}; 151 152typedef struct pmap *pmap_t; 153 154#ifdef _KERNEL 155extern pmap_t kernel_pmap; 156#define pmap_kernel() kernel_pmap 157 158#define PMAP_ASSERT_LOCKED(pmap) \ 159 mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 160#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 161#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 162#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 163 NULL, MTX_DEF | MTX_DUPOK) 164#define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 165#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 166#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 167#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 168#endif 169 170 171/* 172 * For each vm_page_t, there is a list of all currently valid virtual 173 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 174 */ 175typedef struct pv_entry { 176 pmap_t pv_pmap; /* pmap where mapping lies */ 177 vm_offset_t pv_va; /* virtual address for mapping */ 178 TAILQ_ENTRY(pv_entry) pv_list; 179 TAILQ_ENTRY(pv_entry) pv_plist; 180 int pv_flags; /* flags (wired, etc...) */ 181} *pv_entry_t; 182 183#define PV_ENTRY_NULL ((pv_entry_t) 0) 184 185#ifdef _KERNEL 186 187boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 188 189/* 190 * virtual address to page table entry and 191 * to physical address. Likewise for alternate address space. 192 * Note: these work recursively, thus vtopte of a pte will give 193 * the corresponding pde that in turn maps it. 194 */ 195 196/* 197 * The current top of kernel VM. 198 */ 199extern vm_offset_t pmap_curmaxkvaddr; 200 201struct pcb; 202 203void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 204/* Virtual address to page table entry */ 205static __inline pt_entry_t * 206vtopte(vm_offset_t va) 207{ 208 pd_entry_t *pdep; 209 pt_entry_t *ptep; 210 211 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 212 return (NULL); 213 return (ptep); 214} 215 216extern vm_offset_t phys_avail[]; 217extern vm_offset_t virtual_avail; 218extern vm_offset_t virtual_end; 219 220void pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *); 221void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 222void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 223void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 224void pmap_kremove(vm_offset_t); 225void *pmap_mapdev(vm_offset_t, vm_size_t); 226void pmap_unmapdev(vm_offset_t, vm_size_t); 227vm_page_t pmap_use_pt(pmap_t, vm_offset_t); 228void pmap_debug(int); 229void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 230void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 231vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 232void 233pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 234 int cache); 235int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 236 237/* 238 * Definitions for MMU domains 239 */ 240#define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 241#define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 242 243/* 244 * The new pmap ensures that page-tables are always mapping Write-Thru. 245 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 246 * on every change. 247 * 248 * Unfortunately, not all CPUs have a write-through cache mode. So we 249 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 250 * and if there is the chance for PTE syncs to be needed, we define 251 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 252 * the code. 253 */ 254extern int pmap_needs_pte_sync; 255 256/* 257 * These macros define the various bit masks in the PTE. 258 * 259 * We use these macros since we use different bits on different processor 260 * models. 261 */ 262#define L1_S_PROT_U (L1_S_AP(AP_U)) 263#define L1_S_PROT_W (L1_S_AP(AP_W)) 264#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 265 266#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 267#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 268 L1_S_XSCALE_TEX(TEX_XSCALE_T)) 269 270#define L2_L_PROT_U (L2_AP(AP_U)) 271#define L2_L_PROT_W (L2_AP(AP_W)) 272#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 273 274#define L2_L_CACHE_MASK_generic (L2_B|L2_C) 275#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 276 L2_XSCALE_L_TEX(TEX_XSCALE_T)) 277 278#define L2_S_PROT_U_generic (L2_AP(AP_U)) 279#define L2_S_PROT_W_generic (L2_AP(AP_W)) 280#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 281 282#define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 283#define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 284#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 285 286#define L2_S_CACHE_MASK_generic (L2_B|L2_C) 287#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 288 L2_XSCALE_T_TEX(TEX_XSCALE_X)) 289 290#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 291#define L1_S_PROTO_xscale (L1_TYPE_S) 292 293#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 294#define L1_C_PROTO_xscale (L1_TYPE_C) 295 296#define L2_L_PROTO (L2_TYPE_L) 297 298#define L2_S_PROTO_generic (L2_TYPE_S) 299#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 300 301/* 302 * User-visible names for the ones that vary with MMU class. 303 */ 304 305#if ARM_NMMUS > 1 306/* More than one MMU class configured; use variables. */ 307#define L2_S_PROT_U pte_l2_s_prot_u 308#define L2_S_PROT_W pte_l2_s_prot_w 309#define L2_S_PROT_MASK pte_l2_s_prot_mask 310 311#define L1_S_CACHE_MASK pte_l1_s_cache_mask 312#define L2_L_CACHE_MASK pte_l2_l_cache_mask 313#define L2_S_CACHE_MASK pte_l2_s_cache_mask 314 315#define L1_S_PROTO pte_l1_s_proto 316#define L1_C_PROTO pte_l1_c_proto 317#define L2_S_PROTO pte_l2_s_proto 318 319#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 320#define L2_S_PROT_U L2_S_PROT_U_generic 321#define L2_S_PROT_W L2_S_PROT_W_generic 322#define L2_S_PROT_MASK L2_S_PROT_MASK_generic 323 324#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 325#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 326#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 327 328#define L1_S_PROTO L1_S_PROTO_generic 329#define L1_C_PROTO L1_C_PROTO_generic 330#define L2_S_PROTO L2_S_PROTO_generic 331 332#elif ARM_MMU_XSCALE == 1 333#define L2_S_PROT_U L2_S_PROT_U_xscale 334#define L2_S_PROT_W L2_S_PROT_W_xscale 335#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 336 337#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 338#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 339#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 340 341#define L1_S_PROTO L1_S_PROTO_xscale 342#define L1_C_PROTO L1_C_PROTO_xscale 343#define L2_S_PROTO L2_S_PROTO_xscale 344 345#endif /* ARM_NMMUS > 1 */ 346 347#ifdef SKYEYE_WORKAROUNDS 348#define PMAP_NEEDS_PTE_SYNC 1 349#define PMAP_INCLUDE_PTE_SYNC 350#else 351#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 352#define PMAP_NEEDS_PTE_SYNC 1 353#define PMAP_INCLUDE_PTE_SYNC 354#elif defined(CPU_XSCALE_81342) 355#define PMAP_NEEDS_PTE_SYNC 1 356#define PMAP_INCLUDE_PTE_SYNC 357#elif (ARM_MMU_SA1 == 0) 358#define PMAP_NEEDS_PTE_SYNC 0 359#endif 360#endif 361 362/* 363 * These macros return various bits based on kernel/user and protection. 364 * Note that the compiler will usually fold these at compile time. 365 */ 366#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 367 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 368 369#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 370 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 371 372#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 373 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 374 375/* 376 * Macros to test if a mapping is mappable with an L1 Section mapping 377 * or an L2 Large Page mapping. 378 */ 379#define L1_S_MAPPABLE_P(va, pa, size) \ 380 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 381 382#define L2_L_MAPPABLE_P(va, pa, size) \ 383 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 384 385/* 386 * Provide a fallback in case we were not able to determine it at 387 * compile-time. 388 */ 389#ifndef PMAP_NEEDS_PTE_SYNC 390#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 391#define PMAP_INCLUDE_PTE_SYNC 392#endif 393 394#define PTE_SYNC(pte) \ 395do { \ 396 if (PMAP_NEEDS_PTE_SYNC) { \ 397 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 398 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 399 }\ 400} while (/*CONSTCOND*/0) 401 402#define PTE_SYNC_RANGE(pte, cnt) \ 403do { \ 404 if (PMAP_NEEDS_PTE_SYNC) { \ 405 cpu_dcache_wb_range((vm_offset_t)(pte), \ 406 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 407 cpu_l2cache_wb_range((vm_offset_t)(pte), \ 408 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 409 } \ 410} while (/*CONSTCOND*/0) 411 412extern pt_entry_t pte_l1_s_cache_mode; 413extern pt_entry_t pte_l1_s_cache_mask; 414 415extern pt_entry_t pte_l2_l_cache_mode; 416extern pt_entry_t pte_l2_l_cache_mask; 417 418extern pt_entry_t pte_l2_s_cache_mode; 419extern pt_entry_t pte_l2_s_cache_mask; 420 421extern pt_entry_t pte_l1_s_cache_mode_pt; 422extern pt_entry_t pte_l2_l_cache_mode_pt; 423extern pt_entry_t pte_l2_s_cache_mode_pt; 424 425extern pt_entry_t pte_l2_s_prot_u; 426extern pt_entry_t pte_l2_s_prot_w; 427extern pt_entry_t pte_l2_s_prot_mask; 428 429extern pt_entry_t pte_l1_s_proto; 430extern pt_entry_t pte_l1_c_proto; 431extern pt_entry_t pte_l2_s_proto; 432 433extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 434extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 435 436#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) 437void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 438void pmap_zero_page_generic(vm_paddr_t, int, int); 439 440void pmap_pte_init_generic(void); 441#if defined(CPU_ARM8) 442void pmap_pte_init_arm8(void); 443#endif 444#if defined(CPU_ARM9) 445void pmap_pte_init_arm9(void); 446#endif /* CPU_ARM9 */ 447#if defined(CPU_ARM10) 448void pmap_pte_init_arm10(void); 449#endif /* CPU_ARM10 */ 450#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 451 452#if /* ARM_MMU_SA1 == */1 453void pmap_pte_init_sa1(void); 454#endif /* ARM_MMU_SA1 == 1 */ 455 456#if ARM_MMU_XSCALE == 1 457void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 458void pmap_zero_page_xscale(vm_paddr_t, int, int); 459 460void pmap_pte_init_xscale(void); 461 462void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 463 464void pmap_use_minicache(vm_offset_t, vm_size_t); 465#endif /* ARM_MMU_XSCALE == 1 */ 466#if defined(CPU_XSCALE_81342) 467#define ARM_HAVE_SUPERSECTIONS 468#endif 469 470#define PTE_KERNEL 0 471#define PTE_USER 1 472#define l1pte_valid(pde) ((pde) != 0) 473#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 474#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 475#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 476 477#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 478#define l2pte_valid(pte) ((pte) != 0) 479#define l2pte_pa(pte) ((pte) & L2_S_FRAME) 480#define l2pte_minidata(pte) (((pte) & \ 481 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 482 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 483 484/* L1 and L2 page table macros */ 485#define pmap_pde_v(pde) l1pte_valid(*(pde)) 486#define pmap_pde_section(pde) l1pte_section_p(*(pde)) 487#define pmap_pde_page(pde) l1pte_page_p(*(pde)) 488#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 489 490#define pmap_pte_v(pte) l2pte_valid(*(pte)) 491#define pmap_pte_pa(pte) l2pte_pa(*(pte)) 492 493/* 494 * Flags that indicate attributes of pages or mappings of pages. 495 * 496 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 497 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 498 * pv_entry's for each page. They live in the same "namespace" so 499 * that we can clear multiple attributes at a time. 500 * 501 * Note the "non-cacheable" flag generally means the page has 502 * multiple mappings in a given address space. 503 */ 504#define PVF_MOD 0x01 /* page is modified */ 505#define PVF_REF 0x02 /* page is referenced */ 506#define PVF_WIRED 0x04 /* mapping is wired */ 507#define PVF_WRITE 0x08 /* mapping is writable */ 508#define PVF_EXEC 0x10 /* mapping is executable */ 509#define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 510#define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 511#define PVF_NC (PVF_UNC|PVF_KNC) 512 513void vector_page_setprot(int); 514 515void pmap_update(pmap_t); 516 517/* 518 * This structure is used by machine-dependent code to describe 519 * static mappings of devices, created at bootstrap time. 520 */ 521struct pmap_devmap { 522 vm_offset_t pd_va; /* virtual address */ 523 vm_paddr_t pd_pa; /* physical address */ 524 vm_size_t pd_size; /* size of region */ 525 vm_prot_t pd_prot; /* protection code */ 526 int pd_cache; /* cache attributes */ 527}; 528 529const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 530const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 531 532void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 533void pmap_devmap_register(const struct pmap_devmap *); 534 535#define SECTION_CACHE 0x1 536#define SECTION_PT 0x2 537void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 538#ifdef ARM_HAVE_SUPERSECTIONS 539void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 540#endif 541 542extern char *_tmppt; 543 544void pmap_postinit(void); 545 546#ifdef ARM_USE_SMALL_ALLOC 547void arm_add_smallalloc_pages(void *, void *, int, int); 548vm_offset_t arm_ptovirt(vm_paddr_t); 549void arm_init_smallalloc(void); 550struct arm_small_page { 551 void *addr; 552 TAILQ_ENTRY(arm_small_page) pg_list; 553}; 554 555#endif 556 557#define ARM_NOCACHE_KVA_SIZE 0x1000000 558extern vm_offset_t arm_nocache_startaddr; 559void *arm_remap_nocache(void *, vm_size_t); 560void arm_unmap_nocache(void *, vm_size_t); 561 562extern vm_paddr_t dump_avail[]; 563#endif /* _KERNEL */ 564 565#endif /* !LOCORE */ 566 567#endif /* !_MACHINE_PMAP_H_ */ 568