pmap-v4.h revision 142570
1139735Simp/*- 2129198Scognet * Copyright (c) 1991 Regents of the University of California. 3129198Scognet * All rights reserved. 4129198Scognet * 5129198Scognet * This code is derived from software contributed to Berkeley by 6129198Scognet * the Systems Programming Group of the University of Utah Computer 7129198Scognet * Science Department and William Jolitz of UUNET Technologies Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed by the University of 20129198Scognet * California, Berkeley and its contributors. 21129198Scognet * 4. Neither the name of the University nor the names of its contributors 22129198Scognet * may be used to endorse or promote products derived from this software 23129198Scognet * without specific prior written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27129198Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28129198Scognet * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29129198Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30129198Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31129198Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35129198Scognet * SUCH DAMAGE. 36129198Scognet * 37129198Scognet * Derived from hp300 version by Mike Hibler, this version by William 38129198Scognet * Jolitz uses a recursive map [a pde points to the page directory] to 39129198Scognet * map the page tables using the pagetables themselves. This is done to 40129198Scognet * reduce the impact on kernel virtual memory for lots of sparse address 41129198Scognet * space, and to reduce the cost of memory to each process. 42129198Scognet * 43129198Scognet * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44129198Scognet * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45129198Scognet * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46129198Scognet * 47129198Scognet * $FreeBSD: head/sys/arm/include/pmap.h 142570 2005-02-26 18:59:01Z cognet $ 48129198Scognet */ 49129198Scognet 50129198Scognet#ifndef _MACHINE_PMAP_H_ 51129198Scognet#define _MACHINE_PMAP_H_ 52129198Scognet 53129198Scognet#include <machine/pte.h> 54129198Scognet 55129198Scognet/* 56129198Scognet * Pte related macros 57129198Scognet */ 58129198Scognet#define PTE_NOCACHE 0 59129198Scognet#define PTE_CACHE 1 60137362Scognet#define PTE_PAGETABLE 2 61129198Scognet 62129198Scognet#ifndef LOCORE 63129198Scognet 64129198Scognet#include <sys/queue.h> 65129198Scognet 66129198Scognet#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 67129198Scognet#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 68129198Scognet 69129198Scognet#ifdef _KERNEL 70129198Scognet 71135641Scognet#define vtophys(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va)) 72135641Scognet#define pmap_kextract(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va)) 73129198Scognet 74129198Scognet#endif 75129198Scognet 76135641Scognet#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 77129198Scognet/* 78137362Scognet * Pmap stuff 79129198Scognet */ 80129198Scognet 81129198Scognet/* 82129198Scognet * This structure is used to hold a virtual<->physical address 83129198Scognet * association and is used mostly by bootstrap code 84129198Scognet */ 85129198Scognetstruct pv_addr { 86129198Scognet SLIST_ENTRY(pv_addr) pv_list; 87129198Scognet vm_offset_t pv_va; 88129198Scognet vm_paddr_t pv_pa; 89129198Scognet}; 90129198Scognet 91129198Scognetstruct pv_entry; 92129198Scognet 93129198Scognetstruct md_page { 94129198Scognet int pvh_attrs; 95129198Scognet u_int uro_mappings; 96129198Scognet u_int urw_mappings; 97129198Scognet union { 98129198Scognet u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 99129198Scognet u_int i_mappings; 100129198Scognet } k_u; 101129198Scognet#define kro_mappings k_u.s_mappings[0] 102129198Scognet#define krw_mappings k_u.s_mappings[1] 103129198Scognet#define k_mappings k_u.i_mappings 104129198Scognet int pv_list_count; 105129198Scognet TAILQ_HEAD(,pv_entry) pv_list; 106129198Scognet}; 107129198Scognet 108129198Scognet#define VM_MDPAGE_INIT(pg) \ 109129198Scognetdo { \ 110129198Scognet TAILQ_INIT(&pg->pv_list); \ 111129198Scognet mtx_init(&(pg)->md_page.pvh_mtx, "MDPAGE Mutex", NULL, MTX_DEV);\ 112129198Scognet (pg)->mdpage.pvh_attrs = 0; \ 113129198Scognet (pg)->mdpage.uro_mappings = 0; \ 114129198Scognet (pg)->mdpage.urw_mappings = 0; \ 115129198Scognet (pg)->mdpage.k_mappings = 0; \ 116129198Scognet} while (/*CONSTCOND*/0) 117129198Scognet 118129198Scognetstruct l1_ttable; 119129198Scognetstruct l2_dtable; 120129198Scognet 121129198Scognet 122129198Scognet/* 123129198Scognet * The number of L2 descriptor tables which can be tracked by an l2_dtable. 124129198Scognet * A bucket size of 16 provides for 16MB of contiguous virtual address 125129198Scognet * space per l2_dtable. Most processes will, therefore, require only two or 126129198Scognet * three of these to map their whole working set. 127129198Scognet */ 128129198Scognet#define L2_BUCKET_LOG2 4 129129198Scognet#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 130129198Scognet/* 131129198Scognet * Given the above "L2-descriptors-per-l2_dtable" constant, the number 132129198Scognet * of l2_dtable structures required to track all possible page descriptors 133129198Scognet * mappable by an L1 translation table is given by the following constants: 134129198Scognet */ 135129198Scognet#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 136129198Scognet#define L2_SIZE (1 << L2_LOG2) 137129198Scognet 138129198Scognetstruct pmap { 139129198Scognet u_int8_t pm_domain; 140129198Scognet struct l1_ttable *pm_l1; 141129198Scognet struct l2_dtable *pm_l2[L2_SIZE]; 142129198Scognet pd_entry_t *pm_pdir; /* KVA of page directory */ 143129198Scognet int pm_count; /* reference count */ 144129198Scognet int pm_active; /* active on cpus */ 145129198Scognet struct pmap_statistics pm_stats; /* pmap statictics */ 146129198Scognet LIST_ENTRY(pmap) pm_list; /* List of all pmaps */ 147129198Scognet}; 148129198Scognet 149129198Scognettypedef struct pmap *pmap_t; 150129198Scognet 151129198Scognet#ifdef _KERNEL 152129198Scognetextern pmap_t kernel_pmap; 153129198Scognet#define pmap_kernel() kernel_pmap 154137362Scognet 155129198Scognet#endif 156129198Scognet 157135641Scognet 158129198Scognet/* 159129198Scognet * For each vm_page_t, there is a list of all currently valid virtual 160129198Scognet * mappings of that page. An entry is a pv_entry_t, the list is pv_table. 161129198Scognet */ 162129198Scognettypedef struct pv_entry { 163138413Scognet pmap_t pv_pmap; /* pmap where mapping lies */ 164138413Scognet vm_offset_t pv_va; /* virtual address for mapping */ 165138413Scognet TAILQ_ENTRY(pv_entry) pv_list; 166129198Scognet int pv_flags; /* flags (wired, etc...) */ 167129198Scognet} *pv_entry_t; 168129198Scognet 169129198Scognet#define PV_ENTRY_NULL ((pv_entry_t) 0) 170129198Scognet 171129198Scognet#ifdef _KERNEL 172129198Scognet 173129198Scognetboolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 174129198Scognet 175129198Scognet/* 176129198Scognet * virtual address to page table entry and 177129198Scognet * to physical address. Likewise for alternate address space. 178129198Scognet * Note: these work recursively, thus vtopte of a pte will give 179129198Scognet * the corresponding pde that in turn maps it. 180129198Scognet */ 181129198Scognet 182135641Scognet/* 183135641Scognet * The current top of kernel VM. 184135641Scognet */ 185135641Scognetextern vm_offset_t pmap_curmaxkvaddr; 186135641Scognet 187132056Scognetstruct pcb; 188132056Scognet 189129198Scognetvoid pmap_set_pcb_pagedir(pmap_t, struct pcb *); 190129198Scognet/* Virtual address to page table entry */ 191129198Scognetstatic __inline pt_entry_t * 192129198Scognetvtopte(vm_offset_t va) 193129198Scognet{ 194129198Scognet pd_entry_t *pdep; 195129198Scognet pt_entry_t *ptep; 196129198Scognet 197129198Scognet if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 198129198Scognet return (NULL); 199129198Scognet return (ptep); 200129198Scognet} 201129198Scognet 202129198Scognetextern vm_offset_t avail_end; 203129198Scognetextern vm_offset_t clean_eva; 204129198Scognetextern vm_offset_t clean_sva; 205129198Scognetextern vm_offset_t phys_avail[]; 206129198Scognetextern vm_offset_t virtual_avail; 207129198Scognetextern vm_offset_t virtual_end; 208129198Scognet 209129198Scognetvoid pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *); 210129198Scognetvoid pmap_kenter(vm_offset_t va, vm_paddr_t pa); 211142570Scognetvoid pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 212129198Scognetvoid pmap_kremove(vm_offset_t); 213129198Scognetvoid *pmap_mapdev(vm_offset_t, vm_size_t); 214129198Scognetvoid pmap_unmapdev(vm_offset_t, vm_size_t); 215129198Scognetvm_page_t pmap_use_pt(pmap_t, vm_offset_t); 216129198Scognetvoid pmap_debug(int); 217129198Scognetvoid pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 218129198Scognetvoid pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 219129198Scognetvm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 220129198Scognetvoid 221129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 222129198Scognet int cache); 223129198Scognetint pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 224129198Scognet 225129198Scognet/* 226129198Scognet * Definitions for MMU domains 227129198Scognet */ 228129198Scognet#define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 229129198Scognet#define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 230129198Scognet 231129198Scognet/* 232129198Scognet * The new pmap ensures that page-tables are always mapping Write-Thru. 233129198Scognet * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 234129198Scognet * on every change. 235129198Scognet * 236129198Scognet * Unfortunately, not all CPUs have a write-through cache mode. So we 237129198Scognet * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 238129198Scognet * and if there is the chance for PTE syncs to be needed, we define 239129198Scognet * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 240129198Scognet * the code. 241129198Scognet */ 242129198Scognetextern int pmap_needs_pte_sync; 243129198Scognet 244129198Scognet/* 245129198Scognet * These macros define the various bit masks in the PTE. 246129198Scognet * 247129198Scognet * We use these macros since we use different bits on different processor 248129198Scognet * models. 249129198Scognet */ 250129198Scognet#define L1_S_PROT_U (L1_S_AP(AP_U)) 251129198Scognet#define L1_S_PROT_W (L1_S_AP(AP_W)) 252129198Scognet#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 253129198Scognet 254129198Scognet#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 255129198Scognet#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 256129198Scognet 257129198Scognet#define L2_L_PROT_U (L2_AP(AP_U)) 258129198Scognet#define L2_L_PROT_W (L2_AP(AP_W)) 259129198Scognet#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 260129198Scognet 261129198Scognet#define L2_L_CACHE_MASK_generic (L2_B|L2_C) 262129198Scognet#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 263129198Scognet 264129198Scognet#define L2_S_PROT_U_generic (L2_AP(AP_U)) 265129198Scognet#define L2_S_PROT_W_generic (L2_AP(AP_W)) 266129198Scognet#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 267129198Scognet 268129198Scognet#define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 269129198Scognet#define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 270129198Scognet#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 271129198Scognet 272129198Scognet#define L2_S_CACHE_MASK_generic (L2_B|L2_C) 273129198Scognet#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 274129198Scognet 275129198Scognet#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 276129198Scognet#define L1_S_PROTO_xscale (L1_TYPE_S) 277129198Scognet 278129198Scognet#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 279129198Scognet#define L1_C_PROTO_xscale (L1_TYPE_C) 280129198Scognet 281129198Scognet#define L2_L_PROTO (L2_TYPE_L) 282129198Scognet 283129198Scognet#define L2_S_PROTO_generic (L2_TYPE_S) 284129198Scognet#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 285129198Scognet 286129198Scognet/* 287129198Scognet * User-visible names for the ones that vary with MMU class. 288129198Scognet */ 289129198Scognet 290129198Scognet#if ARM_NMMUS > 1 291129198Scognet/* More than one MMU class configured; use variables. */ 292129198Scognet#define L2_S_PROT_U pte_l2_s_prot_u 293129198Scognet#define L2_S_PROT_W pte_l2_s_prot_w 294129198Scognet#define L2_S_PROT_MASK pte_l2_s_prot_mask 295129198Scognet 296129198Scognet#define L1_S_CACHE_MASK pte_l1_s_cache_mask 297129198Scognet#define L2_L_CACHE_MASK pte_l2_l_cache_mask 298129198Scognet#define L2_S_CACHE_MASK pte_l2_s_cache_mask 299129198Scognet 300129198Scognet#define L1_S_PROTO pte_l1_s_proto 301129198Scognet#define L1_C_PROTO pte_l1_c_proto 302129198Scognet#define L2_S_PROTO pte_l2_s_proto 303129198Scognet 304129198Scognet#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 305129198Scognet#define L2_S_PROT_U L2_S_PROT_U_generic 306129198Scognet#define L2_S_PROT_W L2_S_PROT_W_generic 307129198Scognet#define L2_S_PROT_MASK L2_S_PROT_MASK_generic 308129198Scognet 309129198Scognet#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 310129198Scognet#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 311129198Scognet#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 312129198Scognet 313129198Scognet#define L1_S_PROTO L1_S_PROTO_generic 314129198Scognet#define L1_C_PROTO L1_C_PROTO_generic 315129198Scognet#define L2_S_PROTO L2_S_PROTO_generic 316129198Scognet 317129198Scognet#elif ARM_MMU_XSCALE == 1 318129198Scognet#define L2_S_PROT_U L2_S_PROT_U_xscale 319129198Scognet#define L2_S_PROT_W L2_S_PROT_W_xscale 320129198Scognet#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 321129198Scognet 322129198Scognet#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 323129198Scognet#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 324129198Scognet#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 325129198Scognet 326129198Scognet#define L1_S_PROTO L1_S_PROTO_xscale 327129198Scognet#define L1_C_PROTO L1_C_PROTO_xscale 328129198Scognet#define L2_S_PROTO L2_S_PROTO_xscale 329129198Scognet 330129198Scognet#endif /* ARM_NMMUS > 1 */ 331129198Scognet 332129198Scognet#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 333129198Scognet#define PMAP_NEEDS_PTE_SYNC 1 334129198Scognet#define PMAP_INCLUDE_PTE_SYNC 335129198Scognet#elif (ARM_MMU_SA1 == 0) 336129198Scognet#define PMAP_NEEDS_PTE_SYNC 0 337129198Scognet#endif 338129198Scognet 339129198Scognet/* 340129198Scognet * These macros return various bits based on kernel/user and protection. 341129198Scognet * Note that the compiler will usually fold these at compile time. 342129198Scognet */ 343129198Scognet#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 344129198Scognet (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 345129198Scognet 346129198Scognet#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 347129198Scognet (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 348129198Scognet 349129198Scognet#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 350129198Scognet (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 351129198Scognet 352129198Scognet/* 353129198Scognet * Macros to test if a mapping is mappable with an L1 Section mapping 354129198Scognet * or an L2 Large Page mapping. 355129198Scognet */ 356129198Scognet#define L1_S_MAPPABLE_P(va, pa, size) \ 357129198Scognet ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 358129198Scognet 359129198Scognet#define L2_L_MAPPABLE_P(va, pa, size) \ 360129198Scognet ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 361129198Scognet 362129198Scognet/* 363129198Scognet * Provide a fallback in case we were not able to determine it at 364129198Scognet * compile-time. 365129198Scognet */ 366129198Scognet#ifndef PMAP_NEEDS_PTE_SYNC 367129198Scognet#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 368129198Scognet#define PMAP_INCLUDE_PTE_SYNC 369129198Scognet#endif 370129198Scognet 371129198Scognet#define PTE_SYNC(pte) \ 372129198Scognetdo { \ 373129198Scognet if (PMAP_NEEDS_PTE_SYNC) \ 374129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 375129198Scognet} while (/*CONSTCOND*/0) 376129198Scognet 377129198Scognet#define PTE_SYNC_RANGE(pte, cnt) \ 378129198Scognetdo { \ 379129198Scognet if (PMAP_NEEDS_PTE_SYNC) { \ 380129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), \ 381129198Scognet (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 382129198Scognet } \ 383129198Scognet} while (/*CONSTCOND*/0) 384129198Scognet 385129198Scognetextern pt_entry_t pte_l1_s_cache_mode; 386129198Scognetextern pt_entry_t pte_l1_s_cache_mask; 387129198Scognet 388129198Scognetextern pt_entry_t pte_l2_l_cache_mode; 389129198Scognetextern pt_entry_t pte_l2_l_cache_mask; 390129198Scognet 391129198Scognetextern pt_entry_t pte_l2_s_cache_mode; 392129198Scognetextern pt_entry_t pte_l2_s_cache_mask; 393129198Scognet 394129198Scognetextern pt_entry_t pte_l1_s_cache_mode_pt; 395129198Scognetextern pt_entry_t pte_l2_l_cache_mode_pt; 396129198Scognetextern pt_entry_t pte_l2_s_cache_mode_pt; 397129198Scognet 398129198Scognetextern pt_entry_t pte_l2_s_prot_u; 399129198Scognetextern pt_entry_t pte_l2_s_prot_w; 400129198Scognetextern pt_entry_t pte_l2_s_prot_mask; 401129198Scognet 402129198Scognetextern pt_entry_t pte_l1_s_proto; 403129198Scognetextern pt_entry_t pte_l1_c_proto; 404129198Scognetextern pt_entry_t pte_l2_s_proto; 405129198Scognet 406129198Scognetextern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 407129198Scognetextern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 408129198Scognet 409129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 410129198Scognetvoid pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 411129198Scognetvoid pmap_zero_page_generic(vm_paddr_t, int, int); 412129198Scognet 413129198Scognetvoid pmap_pte_init_generic(void); 414129198Scognet#if defined(CPU_ARM8) 415129198Scognetvoid pmap_pte_init_arm8(void); 416129198Scognet#endif 417129198Scognet#if defined(CPU_ARM9) 418129198Scognetvoid pmap_pte_init_arm9(void); 419129198Scognet#endif /* CPU_ARM9 */ 420129198Scognet#if defined(CPU_ARM10) 421129198Scognetvoid pmap_pte_init_arm10(void); 422129198Scognet#endif /* CPU_ARM10 */ 423129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 424129198Scognet 425129198Scognet#if /* ARM_MMU_SA1 == */1 426129198Scognetvoid pmap_pte_init_sa1(void); 427129198Scognet#endif /* ARM_MMU_SA1 == 1 */ 428129198Scognet 429129198Scognet#if ARM_MMU_XSCALE == 1 430129198Scognetvoid pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 431129198Scognetvoid pmap_zero_page_xscale(vm_paddr_t, int, int); 432129198Scognet 433129198Scognetvoid pmap_pte_init_xscale(void); 434129198Scognet 435129198Scognetvoid xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 436129198Scognet 437135641Scognetvoid pmap_use_minicache(vm_offset_t, vm_size_t); 438129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 439129198Scognet#define PTE_KERNEL 0 440129198Scognet#define PTE_USER 1 441129198Scognet#define l1pte_valid(pde) ((pde) != 0) 442129198Scognet#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 443129198Scognet#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 444129198Scognet#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 445129198Scognet 446129198Scognet#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 447129198Scognet#define l2pte_valid(pte) ((pte) != 0) 448129198Scognet#define l2pte_pa(pte) ((pte) & L2_S_FRAME) 449129198Scognet#define l2pte_minidata(pte) (((pte) & \ 450129198Scognet (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 451129198Scognet == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 452129198Scognet 453129198Scognet/* L1 and L2 page table macros */ 454129198Scognet#define pmap_pde_v(pde) l1pte_valid(*(pde)) 455129198Scognet#define pmap_pde_section(pde) l1pte_section_p(*(pde)) 456129198Scognet#define pmap_pde_page(pde) l1pte_page_p(*(pde)) 457129198Scognet#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 458129198Scognet 459129198Scognet#define pmap_pte_v(pte) l2pte_valid(*(pte)) 460129198Scognet#define pmap_pte_pa(pte) l2pte_pa(*(pte)) 461129198Scognet 462129198Scognet/* 463129198Scognet * Flags that indicate attributes of pages or mappings of pages. 464129198Scognet * 465129198Scognet * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 466129198Scognet * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 467129198Scognet * pv_entry's for each page. They live in the same "namespace" so 468129198Scognet * that we can clear multiple attributes at a time. 469129198Scognet * 470129198Scognet * Note the "non-cacheable" flag generally means the page has 471129198Scognet * multiple mappings in a given address space. 472129198Scognet */ 473129198Scognet#define PVF_MOD 0x01 /* page is modified */ 474129198Scognet#define PVF_REF 0x02 /* page is referenced */ 475129198Scognet#define PVF_WIRED 0x04 /* mapping is wired */ 476129198Scognet#define PVF_WRITE 0x08 /* mapping is writable */ 477129198Scognet#define PVF_EXEC 0x10 /* mapping is executable */ 478129198Scognet#define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 479129198Scognet#define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 480129198Scognet#define PVF_NC (PVF_UNC|PVF_KNC) 481129198Scognet 482129198Scognetvoid vector_page_setprot(int); 483135641Scognet 484135641Scognetvoid pmap_update(pmap_t); 485135641Scognet 486129198Scognet/* 487135641Scognet * This structure is used by machine-dependent code to describe 488135641Scognet * static mappings of devices, created at bootstrap time. 489129198Scognet */ 490135641Scognetstruct pmap_devmap { 491135641Scognet vm_offset_t pd_va; /* virtual address */ 492135641Scognet vm_paddr_t pd_pa; /* physical address */ 493135641Scognet vm_size_t pd_size; /* size of region */ 494135641Scognet vm_prot_t pd_prot; /* protection code */ 495135641Scognet int pd_cache; /* cache attributes */ 496135641Scognet}; 497129198Scognet 498135641Scognetconst struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 499135641Scognetconst struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 500129198Scognet 501135641Scognetvoid pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 502135641Scognetvoid pmap_devmap_register(const struct pmap_devmap *); 503137362Scognet 504137362Scognetextern char *_tmppt; 505137362Scognet 506129198Scognet#endif /* _KERNEL */ 507129198Scognet 508129198Scognet#endif /* !LOCORE */ 509129198Scognet 510129198Scognet#endif /* !_MACHINE_PMAP_H_ */ 511