1139735Simp/*- 2129198Scognet * Copyright (c) 1991 Regents of the University of California. 3129198Scognet * All rights reserved. 4129198Scognet * 5129198Scognet * This code is derived from software contributed to Berkeley by 6129198Scognet * the Systems Programming Group of the University of Utah Computer 7129198Scognet * Science Department and William Jolitz of UUNET Technologies Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed by the University of 20129198Scognet * California, Berkeley and its contributors. 21129198Scognet * 4. Neither the name of the University nor the names of its contributors 22129198Scognet * may be used to endorse or promote products derived from this software 23129198Scognet * without specific prior written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27129198Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28129198Scognet * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29129198Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30129198Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31129198Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35129198Scognet * SUCH DAMAGE. 36129198Scognet * 37129198Scognet * Derived from hp300 version by Mike Hibler, this version by William 38129198Scognet * Jolitz uses a recursive map [a pde points to the page directory] to 39129198Scognet * map the page tables using the pagetables themselves. This is done to 40129198Scognet * reduce the impact on kernel virtual memory for lots of sparse address 41129198Scognet * space, and to reduce the cost of memory to each process. 42129198Scognet * 43129198Scognet * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44129198Scognet * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45129198Scognet * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46129198Scognet * 47129198Scognet * $FreeBSD: stable/11/sys/arm/include/pmap-v4.h 314530 2017-03-02 01:18:46Z ian $ 48129198Scognet */ 49295036Smmel 50295798Sskra#ifndef _MACHINE_PMAP_V4_H_ 51295798Sskra#define _MACHINE_PMAP_V4_H_ 52129198Scognet 53295801Sskra#include <machine/pte-v4.h> 54314530Sian 55129198Scognet/* 56314530Sian * Define the MMU types we support based on the cpu types. While the code has 57314530Sian * some theoretical support for multiple MMU types in a single kernel, there are 58314530Sian * no actual working configurations that use that feature. 59314530Sian */ 60314530Sian#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_FA526)) 61314530Sian#define ARM_MMU_GENERIC 1 62314530Sian#else 63314530Sian#define ARM_MMU_GENERIC 0 64314530Sian#endif 65314530Sian 66314530Sian#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 67314530Sian defined(CPU_XSCALE_81342)) 68314530Sian#define ARM_MMU_XSCALE 1 69314530Sian#else 70314530Sian#define ARM_MMU_XSCALE 0 71314530Sian#endif 72314530Sian 73314530Sian#define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_XSCALE) 74314530Sian#if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 75314530Sian#error ARM_NMMUS is 0 76314530Sian#endif 77314530Sian 78314530Sian/* 79129198Scognet * Pte related macros 80129198Scognet */ 81239268Sgonzo#define PTE_NOCACHE 1 82239268Sgonzo#define PTE_CACHE 2 83257672Sian#define PTE_DEVICE PTE_NOCACHE 84239268Sgonzo#define PTE_PAGETABLE 3 85236992Simp 86239268Sgonzoenum mem_type { 87239268Sgonzo STRONG_ORD = 0, 88239268Sgonzo DEVICE_NOSHARE, 89239268Sgonzo DEVICE_SHARE, 90239268Sgonzo NRML_NOCACHE, 91239268Sgonzo NRML_IWT_OWT, 92239268Sgonzo NRML_IWB_OWB, 93239268Sgonzo NRML_IWBA_OWBA 94239268Sgonzo}; 95239268Sgonzo 96129198Scognet#ifndef LOCORE 97129198Scognet 98129198Scognet#include <sys/queue.h> 99222813Sattilio#include <sys/_cpuset.h> 100159325Salc#include <sys/_lock.h> 101159325Salc#include <sys/_mutex.h> 102129198Scognet 103129198Scognet#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 104129198Scognet#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 105129198Scognet 106244414Scognet#define pmap_page_get_memattr(m) ((m)->md.pv_memattr) 107135641Scognet#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 108195649Salc 109129198Scognet/* 110137362Scognet * Pmap stuff 111129198Scognet */ 112129198Scognet 113129198Scognet/* 114129198Scognet * This structure is used to hold a virtual<->physical address 115129198Scognet * association and is used mostly by bootstrap code 116129198Scognet */ 117129198Scognetstruct pv_addr { 118129198Scognet SLIST_ENTRY(pv_addr) pv_list; 119129198Scognet vm_offset_t pv_va; 120129198Scognet vm_paddr_t pv_pa; 121129198Scognet}; 122129198Scognet 123129198Scognetstruct pv_entry; 124250634Sgberstruct pv_chunk; 125129198Scognet 126129198Scognetstruct md_page { 127129198Scognet int pvh_attrs; 128244414Scognet vm_memattr_t pv_memattr; 129194459Sthompsa vm_offset_t pv_kva; /* first kernel VA mapping */ 130129198Scognet TAILQ_HEAD(,pv_entry) pv_list; 131129198Scognet}; 132129198Scognet 133129198Scognetstruct l1_ttable; 134129198Scognetstruct l2_dtable; 135129198Scognet 136129198Scognet 137129198Scognet/* 138129198Scognet * The number of L2 descriptor tables which can be tracked by an l2_dtable. 139129198Scognet * A bucket size of 16 provides for 16MB of contiguous virtual address 140129198Scognet * space per l2_dtable. Most processes will, therefore, require only two or 141129198Scognet * three of these to map their whole working set. 142129198Scognet */ 143129198Scognet#define L2_BUCKET_LOG2 4 144129198Scognet#define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 145129198Scognet/* 146129198Scognet * Given the above "L2-descriptors-per-l2_dtable" constant, the number 147129198Scognet * of l2_dtable structures required to track all possible page descriptors 148129198Scognet * mappable by an L1 translation table is given by the following constants: 149129198Scognet */ 150129198Scognet#define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 151129198Scognet#define L2_SIZE (1 << L2_LOG2) 152129198Scognet 153129198Scognetstruct pmap { 154159325Salc struct mtx pm_mtx; 155129198Scognet u_int8_t pm_domain; 156129198Scognet struct l1_ttable *pm_l1; 157129198Scognet struct l2_dtable *pm_l2[L2_SIZE]; 158222813Sattilio cpuset_t pm_active; /* active on cpus */ 159129198Scognet struct pmap_statistics pm_stats; /* pmap statictics */ 160144760Scognet TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 161129198Scognet}; 162129198Scognet 163129198Scognettypedef struct pmap *pmap_t; 164129198Scognet 165129198Scognet#ifdef _KERNEL 166191873Salcextern struct pmap kernel_pmap_store; 167191873Salc#define kernel_pmap (&kernel_pmap_store) 168137362Scognet 169159325Salc#define PMAP_ASSERT_LOCKED(pmap) \ 170159325Salc mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 171159325Salc#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 172159325Salc#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 173159325Salc#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 174159325Salc NULL, MTX_DEF | MTX_DUPOK) 175159325Salc#define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 176159325Salc#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 177159325Salc#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 178159325Salc#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 179129198Scognet#endif 180129198Scognet 181129198Scognet/* 182129198Scognet * For each vm_page_t, there is a list of all currently valid virtual 183164250Sru * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 184129198Scognet */ 185129198Scognettypedef struct pv_entry { 186138413Scognet vm_offset_t pv_va; /* virtual address for mapping */ 187138413Scognet TAILQ_ENTRY(pv_entry) pv_list; 188250634Sgber int pv_flags; /* flags (wired, etc...) */ 189250634Sgber pmap_t pv_pmap; /* pmap where mapping lies */ 190144760Scognet TAILQ_ENTRY(pv_entry) pv_plist; 191129198Scognet} *pv_entry_t; 192129198Scognet 193250634Sgber/* 194250634Sgber * pv_entries are allocated in chunks per-process. This avoids the 195250634Sgber * need to track per-pmap assignments. 196250634Sgber */ 197250634Sgber#define _NPCM 8 198250634Sgber#define _NPCPV 252 199250634Sgber 200250634Sgberstruct pv_chunk { 201250634Sgber pmap_t pc_pmap; 202250634Sgber TAILQ_ENTRY(pv_chunk) pc_list; 203250634Sgber uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */ 204250634Sgber uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */ 205250634Sgber TAILQ_ENTRY(pv_chunk) pc_lru; 206250634Sgber struct pv_entry pc_pventry[_NPCPV]; 207250634Sgber}; 208250634Sgber 209129198Scognet#ifdef _KERNEL 210129198Scognet 211129198Scognetboolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 212129198Scognet 213129198Scognet/* 214129198Scognet * virtual address to page table entry and 215129198Scognet * to physical address. Likewise for alternate address space. 216129198Scognet * Note: these work recursively, thus vtopte of a pte will give 217129198Scognet * the corresponding pde that in turn maps it. 218129198Scognet */ 219129198Scognet 220135641Scognet/* 221135641Scognet * The current top of kernel VM. 222135641Scognet */ 223135641Scognetextern vm_offset_t pmap_curmaxkvaddr; 224135641Scognet 225129198Scognet/* Virtual address to page table entry */ 226129198Scognetstatic __inline pt_entry_t * 227129198Scognetvtopte(vm_offset_t va) 228129198Scognet{ 229129198Scognet pd_entry_t *pdep; 230129198Scognet pt_entry_t *ptep; 231129198Scognet 232295042Sskra if (pmap_get_pde_pte(kernel_pmap, va, &pdep, &ptep) == FALSE) 233129198Scognet return (NULL); 234129198Scognet return (ptep); 235129198Scognet} 236129198Scognet 237247046Salcvoid pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt); 238239268Sgonzoint pmap_change_attr(vm_offset_t, vm_size_t, int); 239129198Scognetvoid pmap_kenter(vm_offset_t va, vm_paddr_t pa); 240156191Scognetvoid pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 241142570Scognetvoid pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 242294722Sskravm_paddr_t pmap_dump_kextract(vm_offset_t, pt2_entry_t *); 243129198Scognetvoid pmap_kremove(vm_offset_t); 244129198Scognetvm_page_t pmap_use_pt(pmap_t, vm_offset_t); 245129198Scognetvoid pmap_debug(int); 246129198Scognetvoid pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 247129198Scognetvoid pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 248129198Scognetvm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 249129198Scognetvoid 250129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 251129198Scognet int cache); 252129198Scognetint pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 253129198Scognet 254129198Scognet/* 255129198Scognet * Definitions for MMU domains 256129198Scognet */ 257169756Scognet#define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 258169756Scognet#define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 259129198Scognet 260129198Scognet/* 261129198Scognet * The new pmap ensures that page-tables are always mapping Write-Thru. 262129198Scognet * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 263129198Scognet * on every change. 264129198Scognet * 265129198Scognet * Unfortunately, not all CPUs have a write-through cache mode. So we 266129198Scognet * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 267129198Scognet * and if there is the chance for PTE syncs to be needed, we define 268129198Scognet * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 269129198Scognet * the code. 270129198Scognet */ 271129198Scognetextern int pmap_needs_pte_sync; 272129198Scognet 273129198Scognet/* 274129198Scognet * These macros define the various bit masks in the PTE. 275129198Scognet * 276129198Scognet * We use these macros since we use different bits on different processor 277129198Scognet * models. 278129198Scognet */ 279129198Scognet 280129198Scognet#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 281171620Scognet#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 282171620Scognet L1_S_XSCALE_TEX(TEX_XSCALE_T)) 283129198Scognet 284129198Scognet#define L2_L_CACHE_MASK_generic (L2_B|L2_C) 285171620Scognet#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 286171620Scognet L2_XSCALE_L_TEX(TEX_XSCALE_T)) 287129198Scognet 288129198Scognet#define L2_S_PROT_U_generic (L2_AP(AP_U)) 289129198Scognet#define L2_S_PROT_W_generic (L2_AP(AP_W)) 290129198Scognet#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 291129198Scognet 292129198Scognet#define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 293129198Scognet#define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 294129198Scognet#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 295129198Scognet 296129198Scognet#define L2_S_CACHE_MASK_generic (L2_B|L2_C) 297171620Scognet#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 298171620Scognet L2_XSCALE_T_TEX(TEX_XSCALE_X)) 299129198Scognet 300129198Scognet#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 301129198Scognet#define L1_S_PROTO_xscale (L1_TYPE_S) 302129198Scognet 303129198Scognet#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 304129198Scognet#define L1_C_PROTO_xscale (L1_TYPE_C) 305129198Scognet 306129198Scognet#define L2_L_PROTO (L2_TYPE_L) 307129198Scognet 308129198Scognet#define L2_S_PROTO_generic (L2_TYPE_S) 309129198Scognet#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 310129198Scognet 311129198Scognet/* 312129198Scognet * User-visible names for the ones that vary with MMU class. 313129198Scognet */ 314239268Sgonzo#define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 315129198Scognet 316295129Sskra#if ARM_NMMUS > 1 317263676Sandrew/* More than one MMU class configured; use variables. */ 318263676Sandrew#define L2_S_PROT_U pte_l2_s_prot_u 319263676Sandrew#define L2_S_PROT_W pte_l2_s_prot_w 320263676Sandrew#define L2_S_PROT_MASK pte_l2_s_prot_mask 321263676Sandrew 322263676Sandrew#define L1_S_CACHE_MASK pte_l1_s_cache_mask 323263676Sandrew#define L2_L_CACHE_MASK pte_l2_l_cache_mask 324263676Sandrew#define L2_S_CACHE_MASK pte_l2_s_cache_mask 325263676Sandrew 326263676Sandrew#define L1_S_PROTO pte_l1_s_proto 327263676Sandrew#define L1_C_PROTO pte_l1_c_proto 328263676Sandrew#define L2_S_PROTO pte_l2_s_proto 329263676Sandrew 330263676Sandrew#elif ARM_MMU_GENERIC != 0 331263676Sandrew#define L2_S_PROT_U L2_S_PROT_U_generic 332263676Sandrew#define L2_S_PROT_W L2_S_PROT_W_generic 333263676Sandrew#define L2_S_PROT_MASK L2_S_PROT_MASK_generic 334263676Sandrew 335263676Sandrew#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 336263676Sandrew#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 337263676Sandrew#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 338263676Sandrew 339263676Sandrew#define L1_S_PROTO L1_S_PROTO_generic 340263676Sandrew#define L1_C_PROTO L1_C_PROTO_generic 341263676Sandrew#define L2_S_PROTO L2_S_PROTO_generic 342263676Sandrew 343263676Sandrew#elif ARM_MMU_XSCALE == 1 344263676Sandrew#define L2_S_PROT_U L2_S_PROT_U_xscale 345263676Sandrew#define L2_S_PROT_W L2_S_PROT_W_xscale 346263676Sandrew#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 347263676Sandrew 348263676Sandrew#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 349263676Sandrew#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 350263676Sandrew#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 351263676Sandrew 352263676Sandrew#define L1_S_PROTO L1_S_PROTO_xscale 353263676Sandrew#define L1_C_PROTO L1_C_PROTO_xscale 354263676Sandrew#define L2_S_PROTO L2_S_PROTO_xscale 355263676Sandrew 356129198Scognet#endif /* ARM_NMMUS > 1 */ 357129198Scognet 358295129Sskra#if defined(CPU_XSCALE_81342) 359171620Scognet#define PMAP_NEEDS_PTE_SYNC 1 360171620Scognet#define PMAP_INCLUDE_PTE_SYNC 361262958Sian#else 362129198Scognet#define PMAP_NEEDS_PTE_SYNC 0 363129198Scognet#endif 364129198Scognet 365129198Scognet/* 366129198Scognet * These macros return various bits based on kernel/user and protection. 367129198Scognet * Note that the compiler will usually fold these at compile time. 368129198Scognet */ 369239268Sgonzo#define L1_S_PROT_U (L1_S_AP(AP_U)) 370239268Sgonzo#define L1_S_PROT_W (L1_S_AP(AP_W)) 371239268Sgonzo#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 372239268Sgonzo#define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W) 373239268Sgonzo 374129198Scognet#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 375129198Scognet (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 376129198Scognet 377239268Sgonzo#define L2_L_PROT_U (L2_AP(AP_U)) 378239268Sgonzo#define L2_L_PROT_W (L2_AP(AP_W)) 379239268Sgonzo#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 380239268Sgonzo 381129198Scognet#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 382129198Scognet (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 383129198Scognet 384129198Scognet#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 385129198Scognet (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 386129198Scognet 387129198Scognet/* 388129198Scognet * Macros to test if a mapping is mappable with an L1 Section mapping 389129198Scognet * or an L2 Large Page mapping. 390129198Scognet */ 391129198Scognet#define L1_S_MAPPABLE_P(va, pa, size) \ 392129198Scognet ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 393129198Scognet 394129198Scognet#define L2_L_MAPPABLE_P(va, pa, size) \ 395129198Scognet ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 396129198Scognet 397129198Scognet/* 398129198Scognet * Provide a fallback in case we were not able to determine it at 399129198Scognet * compile-time. 400129198Scognet */ 401129198Scognet#ifndef PMAP_NEEDS_PTE_SYNC 402129198Scognet#define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 403129198Scognet#define PMAP_INCLUDE_PTE_SYNC 404129198Scognet#endif 405129198Scognet 406256707Scognet#ifdef ARM_L2_PIPT 407256707Scognet#define _sync_l2(pte, size) cpu_l2cache_wb_range(vtophys(pte), size) 408256707Scognet#else 409256708Scognet#define _sync_l2(pte, size) cpu_l2cache_wb_range(pte, size) 410256707Scognet#endif 411256707Scognet 412129198Scognet#define PTE_SYNC(pte) \ 413129198Scognetdo { \ 414171620Scognet if (PMAP_NEEDS_PTE_SYNC) { \ 415129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 416256707Scognet cpu_drain_writebuf(); \ 417256707Scognet _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\ 418228530Sraj } else \ 419228530Sraj cpu_drain_writebuf(); \ 420129198Scognet} while (/*CONSTCOND*/0) 421129198Scognet 422129198Scognet#define PTE_SYNC_RANGE(pte, cnt) \ 423129198Scognetdo { \ 424129198Scognet if (PMAP_NEEDS_PTE_SYNC) { \ 425129198Scognet cpu_dcache_wb_range((vm_offset_t)(pte), \ 426129198Scognet (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 427256707Scognet cpu_drain_writebuf(); \ 428256707Scognet _sync_l2((vm_offset_t)(pte), \ 429171620Scognet (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 430228530Sraj } else \ 431228530Sraj cpu_drain_writebuf(); \ 432129198Scognet} while (/*CONSTCOND*/0) 433129198Scognet 434129198Scognetextern pt_entry_t pte_l1_s_cache_mode; 435129198Scognetextern pt_entry_t pte_l1_s_cache_mask; 436129198Scognet 437129198Scognetextern pt_entry_t pte_l2_l_cache_mode; 438129198Scognetextern pt_entry_t pte_l2_l_cache_mask; 439129198Scognet 440129198Scognetextern pt_entry_t pte_l2_s_cache_mode; 441129198Scognetextern pt_entry_t pte_l2_s_cache_mask; 442129198Scognet 443129198Scognetextern pt_entry_t pte_l1_s_cache_mode_pt; 444129198Scognetextern pt_entry_t pte_l2_l_cache_mode_pt; 445129198Scognetextern pt_entry_t pte_l2_s_cache_mode_pt; 446129198Scognet 447129198Scognetextern pt_entry_t pte_l2_s_prot_u; 448129198Scognetextern pt_entry_t pte_l2_s_prot_w; 449129198Scognetextern pt_entry_t pte_l2_s_prot_mask; 450236992Simp 451129198Scognetextern pt_entry_t pte_l1_s_proto; 452129198Scognetextern pt_entry_t pte_l1_c_proto; 453129198Scognetextern pt_entry_t pte_l2_s_proto; 454129198Scognet 455129198Scognetextern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 456248280Skibextern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 457248280Skib vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 458129198Scognetextern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 459129198Scognet 460295129Sskra#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_81342) 461129198Scognetvoid pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 462129198Scognetvoid pmap_zero_page_generic(vm_paddr_t, int, int); 463129198Scognet 464129198Scognetvoid pmap_pte_init_generic(void); 465295129Sskra#endif /* ARM_MMU_GENERIC != 0 */ 466129198Scognet 467129198Scognet#if ARM_MMU_XSCALE == 1 468129198Scognetvoid pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 469129198Scognetvoid pmap_zero_page_xscale(vm_paddr_t, int, int); 470129198Scognet 471129198Scognetvoid pmap_pte_init_xscale(void); 472129198Scognet 473129198Scognetvoid xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 474129198Scognet 475135641Scognetvoid pmap_use_minicache(vm_offset_t, vm_size_t); 476129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 477171620Scognet#if defined(CPU_XSCALE_81342) 478171620Scognet#define ARM_HAVE_SUPERSECTIONS 479171620Scognet#endif 480171620Scognet 481129198Scognet#define PTE_KERNEL 0 482129198Scognet#define PTE_USER 1 483129198Scognet#define l1pte_valid(pde) ((pde) != 0) 484129198Scognet#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 485129198Scognet#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 486129198Scognet#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 487129198Scognet 488295752Sskra#define l2pte_index(v) (((v) & L1_S_OFFSET) >> L2_S_SHIFT) 489129198Scognet#define l2pte_valid(pte) ((pte) != 0) 490129198Scognet#define l2pte_pa(pte) ((pte) & L2_S_FRAME) 491129198Scognet#define l2pte_minidata(pte) (((pte) & \ 492129198Scognet (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 493129198Scognet == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 494129198Scognet 495129198Scognet/* L1 and L2 page table macros */ 496129198Scognet#define pmap_pde_v(pde) l1pte_valid(*(pde)) 497129198Scognet#define pmap_pde_section(pde) l1pte_section_p(*(pde)) 498129198Scognet#define pmap_pde_page(pde) l1pte_page_p(*(pde)) 499129198Scognet#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 500129198Scognet 501129198Scognet#define pmap_pte_v(pte) l2pte_valid(*(pte)) 502129198Scognet#define pmap_pte_pa(pte) l2pte_pa(*(pte)) 503129198Scognet 504129198Scognet/* 505129198Scognet * Flags that indicate attributes of pages or mappings of pages. 506129198Scognet * 507129198Scognet * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 508129198Scognet * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 509129198Scognet * pv_entry's for each page. They live in the same "namespace" so 510129198Scognet * that we can clear multiple attributes at a time. 511129198Scognet * 512129198Scognet * Note the "non-cacheable" flag generally means the page has 513129198Scognet * multiple mappings in a given address space. 514129198Scognet */ 515129198Scognet#define PVF_MOD 0x01 /* page is modified */ 516129198Scognet#define PVF_REF 0x02 /* page is referenced */ 517129198Scognet#define PVF_WIRED 0x04 /* mapping is wired */ 518129198Scognet#define PVF_WRITE 0x08 /* mapping is writable */ 519129198Scognet#define PVF_EXEC 0x10 /* mapping is executable */ 520175840Scognet#define PVF_NC 0x20 /* mapping is non-cacheable */ 521175840Scognet#define PVF_MWC 0x40 /* mapping is used multiple times in userland */ 522194459Sthompsa#define PVF_UNMAN 0x80 /* mapping is unmanaged */ 523129198Scognet 524129198Scognetvoid vector_page_setprot(int); 525135641Scognet 526147114Scognet#define SECTION_CACHE 0x1 527147114Scognet#define SECTION_PT 0x2 528147114Scognetvoid pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 529171620Scognet#ifdef ARM_HAVE_SUPERSECTIONS 530170582Scognetvoid pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 531171620Scognet#endif 532147114Scognet 533152128Scognetvoid pmap_postinit(void); 534152128Scognet 535129198Scognet#endif /* _KERNEL */ 536129198Scognet 537129198Scognet#endif /* !LOCORE */ 538129198Scognet 539295798Sskra#endif /* !_MACHINE_PMAP_V4_H_ */ 540