cpufunc.h revision 201468
1129198Scognet/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1997 Mark Brinicombe. 5129198Scognet * Copyright (c) 1997 Causality Limited 6129198Scognet * All rights reserved. 7129198Scognet * 8129198Scognet * Redistribution and use in source and binary forms, with or without 9129198Scognet * modification, are permitted provided that the following conditions 10129198Scognet * are met: 11129198Scognet * 1. Redistributions of source code must retain the above copyright 12129198Scognet * notice, this list of conditions and the following disclaimer. 13129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 14129198Scognet * notice, this list of conditions and the following disclaimer in the 15129198Scognet * documentation and/or other materials provided with the distribution. 16129198Scognet * 3. All advertising materials mentioning features or use of this software 17129198Scognet * must display the following acknowledgement: 18129198Scognet * This product includes software developed by Causality Limited. 19129198Scognet * 4. The name of Causality Limited may not be used to endorse or promote 20129198Scognet * products derived from this software without specific prior written 21129198Scognet * permission. 22129198Scognet * 23129198Scognet * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24129198Scognet * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25129198Scognet * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26129198Scognet * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33129198Scognet * SUCH DAMAGE. 34129198Scognet * 35129198Scognet * RiscBSD kernel project 36129198Scognet * 37129198Scognet * cpufunc.h 38129198Scognet * 39129198Scognet * Prototypes for cpu, mmu and tlb related functions. 40129198Scognet * 41129198Scognet * $FreeBSD: head/sys/arm/include/cpufunc.h 201468 2010-01-04 03:35:45Z rpaulo $ 42129198Scognet */ 43129198Scognet 44129198Scognet#ifndef _MACHINE_CPUFUNC_H_ 45129198Scognet#define _MACHINE_CPUFUNC_H_ 46129198Scognet 47129198Scognet#ifdef _KERNEL 48129198Scognet 49129198Scognet#include <sys/types.h> 50129198Scognet#include <machine/cpuconf.h> 51132055Scognet#include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52129198Scognet 53132055Scognetstatic __inline void 54132055Scognetbreakpoint(void) 55132055Scognet{ 56137940Scognet __asm(".word 0xe7ffffff"); 57132055Scognet} 58132471Scognet 59129198Scognetstruct cpu_functions { 60129198Scognet 61129198Scognet /* CPU functions */ 62129198Scognet 63129198Scognet u_int (*cf_id) (void); 64129198Scognet void (*cf_cpwait) (void); 65129198Scognet 66129198Scognet /* MMU functions */ 67129198Scognet 68129198Scognet u_int (*cf_control) (u_int bic, u_int eor); 69129198Scognet void (*cf_domains) (u_int domains); 70129198Scognet void (*cf_setttb) (u_int ttb); 71129198Scognet u_int (*cf_faultstatus) (void); 72129198Scognet u_int (*cf_faultaddress) (void); 73129198Scognet 74129198Scognet /* TLB functions */ 75129198Scognet 76129198Scognet void (*cf_tlb_flushID) (void); 77129198Scognet void (*cf_tlb_flushID_SE) (u_int va); 78129198Scognet void (*cf_tlb_flushI) (void); 79129198Scognet void (*cf_tlb_flushI_SE) (u_int va); 80129198Scognet void (*cf_tlb_flushD) (void); 81129198Scognet void (*cf_tlb_flushD_SE) (u_int va); 82129198Scognet 83129198Scognet /* 84129198Scognet * Cache operations: 85129198Scognet * 86129198Scognet * We define the following primitives: 87129198Scognet * 88129198Scognet * icache_sync_all Synchronize I-cache 89129198Scognet * icache_sync_range Synchronize I-cache range 90129198Scognet * 91129198Scognet * dcache_wbinv_all Write-back and Invalidate D-cache 92129198Scognet * dcache_wbinv_range Write-back and Invalidate D-cache range 93129198Scognet * dcache_inv_range Invalidate D-cache range 94129198Scognet * dcache_wb_range Write-back D-cache range 95129198Scognet * 96129198Scognet * idcache_wbinv_all Write-back and Invalidate D-cache, 97129198Scognet * Invalidate I-cache 98129198Scognet * idcache_wbinv_range Write-back and Invalidate D-cache, 99129198Scognet * Invalidate I-cache range 100129198Scognet * 101129198Scognet * Note that the ARM term for "write-back" is "clean". We use 102129198Scognet * the term "write-back" since it's a more common way to describe 103129198Scognet * the operation. 104129198Scognet * 105129198Scognet * There are some rules that must be followed: 106129198Scognet * 107129198Scognet * I-cache Synch (all or range): 108129198Scognet * The goal is to synchronize the instruction stream, 109129198Scognet * so you may beed to write-back dirty D-cache blocks 110129198Scognet * first. If a range is requested, and you can't 111129198Scognet * synchronize just a range, you have to hit the whole 112129198Scognet * thing. 113129198Scognet * 114129198Scognet * D-cache Write-Back and Invalidate range: 115129198Scognet * If you can't WB-Inv a range, you must WB-Inv the 116129198Scognet * entire D-cache. 117129198Scognet * 118129198Scognet * D-cache Invalidate: 119129198Scognet * If you can't Inv the D-cache, you must Write-Back 120129198Scognet * and Invalidate. Code that uses this operation 121129198Scognet * MUST NOT assume that the D-cache will not be written 122129198Scognet * back to memory. 123129198Scognet * 124129198Scognet * D-cache Write-Back: 125129198Scognet * If you can't Write-back without doing an Inv, 126129198Scognet * that's fine. Then treat this as a WB-Inv. 127129198Scognet * Skipping the invalidate is merely an optimization. 128129198Scognet * 129129198Scognet * All operations: 130129198Scognet * Valid virtual addresses must be passed to each 131129198Scognet * cache operation. 132129198Scognet */ 133129198Scognet void (*cf_icache_sync_all) (void); 134129198Scognet void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 135129198Scognet 136129198Scognet void (*cf_dcache_wbinv_all) (void); 137129198Scognet void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 138129198Scognet void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 139129198Scognet void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 140129198Scognet 141129198Scognet void (*cf_idcache_wbinv_all) (void); 142129198Scognet void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 143171618Scognet void (*cf_l2cache_wbinv_all) (void); 144171618Scognet void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 145171618Scognet void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 146171618Scognet void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 147129198Scognet 148129198Scognet /* Other functions */ 149129198Scognet 150129198Scognet void (*cf_flush_prefetchbuf) (void); 151129198Scognet void (*cf_drain_writebuf) (void); 152129198Scognet void (*cf_flush_brnchtgt_C) (void); 153129198Scognet void (*cf_flush_brnchtgt_E) (u_int va); 154129198Scognet 155129198Scognet void (*cf_sleep) (int mode); 156129198Scognet 157129198Scognet /* Soft functions */ 158129198Scognet 159129198Scognet int (*cf_dataabt_fixup) (void *arg); 160129198Scognet int (*cf_prefetchabt_fixup) (void *arg); 161129198Scognet 162129198Scognet void (*cf_context_switch) (void); 163129198Scognet 164129198Scognet void (*cf_setup) (char *string); 165129198Scognet}; 166129198Scognet 167129198Scognetextern struct cpu_functions cpufuncs; 168129198Scognetextern u_int cputype; 169129198Scognet 170129198Scognet#define cpu_id() cpufuncs.cf_id() 171129198Scognet#define cpu_cpwait() cpufuncs.cf_cpwait() 172129198Scognet 173129198Scognet#define cpu_control(c, e) cpufuncs.cf_control(c, e) 174129198Scognet#define cpu_domains(d) cpufuncs.cf_domains(d) 175129198Scognet#define cpu_setttb(t) cpufuncs.cf_setttb(t) 176129198Scognet#define cpu_faultstatus() cpufuncs.cf_faultstatus() 177129198Scognet#define cpu_faultaddress() cpufuncs.cf_faultaddress() 178129198Scognet 179129198Scognet#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 180129198Scognet#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 181129198Scognet#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 182129198Scognet#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 183129198Scognet#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 184129198Scognet#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 185129198Scognet 186129198Scognet#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 187129198Scognet#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 188129198Scognet 189129198Scognet#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 190129198Scognet#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 191129198Scognet#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 192129198Scognet#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 193129198Scognet 194129198Scognet#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 195129198Scognet#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 196171618Scognet#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 197171618Scognet#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 198171618Scognet#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 199171618Scognet#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 200129198Scognet 201129198Scognet#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 202129198Scognet#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 203129198Scognet#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 204129198Scognet#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 205129198Scognet 206129198Scognet#define cpu_sleep(m) cpufuncs.cf_sleep(m) 207129198Scognet 208129198Scognet#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 209129198Scognet#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 210129198Scognet#define ABORT_FIXUP_OK 0 /* fixup succeeded */ 211129198Scognet#define ABORT_FIXUP_FAILED 1 /* fixup failed */ 212129198Scognet#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 213129198Scognet 214129198Scognet#define cpu_setup(a) cpufuncs.cf_setup(a) 215129198Scognet 216129198Scognetint set_cpufuncs (void); 217129198Scognet#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 218129198Scognet#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 219129198Scognet 220129198Scognetvoid cpufunc_nullop (void); 221129198Scognetint cpufunc_null_fixup (void *); 222129198Scognetint early_abort_fixup (void *); 223129198Scognetint late_abort_fixup (void *); 224129198Scognetu_int cpufunc_id (void); 225129198Scognetu_int cpufunc_control (u_int clear, u_int bic); 226129198Scognetvoid cpufunc_domains (u_int domains); 227129198Scognetu_int cpufunc_faultstatus (void); 228129198Scognetu_int cpufunc_faultaddress (void); 229129198Scognet 230129198Scognet#ifdef CPU_ARM3 231129198Scognetu_int arm3_control (u_int clear, u_int bic); 232129198Scognetvoid arm3_cache_flush (void); 233129198Scognet#endif /* CPU_ARM3 */ 234129198Scognet 235129198Scognet#if defined(CPU_ARM6) || defined(CPU_ARM7) 236129198Scognetvoid arm67_setttb (u_int ttb); 237129198Scognetvoid arm67_tlb_flush (void); 238129198Scognetvoid arm67_tlb_purge (u_int va); 239129198Scognetvoid arm67_cache_flush (void); 240129198Scognetvoid arm67_context_switch (void); 241129198Scognet#endif /* CPU_ARM6 || CPU_ARM7 */ 242129198Scognet 243129198Scognet#ifdef CPU_ARM6 244129198Scognetvoid arm6_setup (char *string); 245129198Scognet#endif /* CPU_ARM6 */ 246129198Scognet 247129198Scognet#ifdef CPU_ARM7 248129198Scognetvoid arm7_setup (char *string); 249129198Scognet#endif /* CPU_ARM7 */ 250129198Scognet 251129198Scognet#ifdef CPU_ARM7TDMI 252129198Scognetint arm7_dataabt_fixup (void *arg); 253129198Scognetvoid arm7tdmi_setup (char *string); 254129198Scognetvoid arm7tdmi_setttb (u_int ttb); 255129198Scognetvoid arm7tdmi_tlb_flushID (void); 256129198Scognetvoid arm7tdmi_tlb_flushID_SE (u_int va); 257129198Scognetvoid arm7tdmi_cache_flushID (void); 258129198Scognetvoid arm7tdmi_context_switch (void); 259129198Scognet#endif /* CPU_ARM7TDMI */ 260129198Scognet 261129198Scognet#ifdef CPU_ARM8 262129198Scognetvoid arm8_setttb (u_int ttb); 263129198Scognetvoid arm8_tlb_flushID (void); 264129198Scognetvoid arm8_tlb_flushID_SE (u_int va); 265129198Scognetvoid arm8_cache_flushID (void); 266129198Scognetvoid arm8_cache_flushID_E (u_int entry); 267129198Scognetvoid arm8_cache_cleanID (void); 268129198Scognetvoid arm8_cache_cleanID_E (u_int entry); 269129198Scognetvoid arm8_cache_purgeID (void); 270129198Scognetvoid arm8_cache_purgeID_E (u_int entry); 271129198Scognet 272129198Scognetvoid arm8_cache_syncI (void); 273129198Scognetvoid arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 274129198Scognetvoid arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 275129198Scognetvoid arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 276129198Scognetvoid arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 277129198Scognetvoid arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 278129198Scognet 279129198Scognetvoid arm8_context_switch (void); 280129198Scognet 281129198Scognetvoid arm8_setup (char *string); 282129198Scognet 283129198Scognetu_int arm8_clock_config (u_int, u_int); 284129198Scognet#endif 285129198Scognet 286201468Srpaulo 287201468Srpaulo#ifdef CPU_FA526 288201468Srpaulovoid fa526_setup (char *arg); 289201468Srpaulovoid fa526_setttb (u_int ttb); 290201468Srpaulovoid fa526_context_switch (void); 291201468Srpaulovoid fa526_cpu_sleep (int); 292201468Srpaulovoid fa526_tlb_flushI_SE (u_int); 293201468Srpaulovoid fa526_tlb_flushID_SE (u_int); 294201468Srpaulovoid fa526_flush_prefetchbuf (void); 295201468Srpaulovoid fa526_flush_brnchtgt_E (u_int); 296201468Srpaulo 297201468Srpaulovoid fa526_icache_sync_all (void); 298201468Srpaulovoid fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 299201468Srpaulovoid fa526_dcache_wbinv_all (void); 300201468Srpaulovoid fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 301201468Srpaulovoid fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 302201468Srpaulovoid fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 303201468Srpaulovoid fa526_idcache_wbinv_all(void); 304201468Srpaulovoid fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 305201468Srpaulo#endif 306201468Srpaulo 307201468Srpaulo 308129198Scognet#ifdef CPU_SA110 309129198Scognetvoid sa110_setup (char *string); 310129198Scognetvoid sa110_context_switch (void); 311129198Scognet#endif /* CPU_SA110 */ 312129198Scognet 313129198Scognet#if defined(CPU_SA1100) || defined(CPU_SA1110) 314129198Scognetvoid sa11x0_drain_readbuf (void); 315129198Scognet 316129198Scognetvoid sa11x0_context_switch (void); 317129198Scognetvoid sa11x0_cpu_sleep (int mode); 318129198Scognet 319129198Scognetvoid sa11x0_setup (char *string); 320129198Scognet#endif 321129198Scognet 322129198Scognet#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 323129198Scognetvoid sa1_setttb (u_int ttb); 324129198Scognet 325129198Scognetvoid sa1_tlb_flushID_SE (u_int va); 326129198Scognet 327129198Scognetvoid sa1_cache_flushID (void); 328129198Scognetvoid sa1_cache_flushI (void); 329129198Scognetvoid sa1_cache_flushD (void); 330129198Scognetvoid sa1_cache_flushD_SE (u_int entry); 331129198Scognet 332129198Scognetvoid sa1_cache_cleanID (void); 333129198Scognetvoid sa1_cache_cleanD (void); 334129198Scognetvoid sa1_cache_cleanD_E (u_int entry); 335129198Scognet 336129198Scognetvoid sa1_cache_purgeID (void); 337129198Scognetvoid sa1_cache_purgeID_E (u_int entry); 338129198Scognetvoid sa1_cache_purgeD (void); 339129198Scognetvoid sa1_cache_purgeD_E (u_int entry); 340129198Scognet 341129198Scognetvoid sa1_cache_syncI (void); 342129198Scognetvoid sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 343129198Scognetvoid sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 344129198Scognetvoid sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 345129198Scognetvoid sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 346129198Scognetvoid sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 347129198Scognet 348129198Scognet#endif 349129198Scognet 350129198Scognet#ifdef CPU_ARM9 351129198Scognetvoid arm9_setttb (u_int); 352129198Scognet 353129198Scognetvoid arm9_tlb_flushID_SE (u_int va); 354129198Scognet 355167752Skevlovoid arm9_icache_sync_all (void); 356167752Skevlovoid arm9_icache_sync_range (vm_offset_t, vm_size_t); 357129198Scognet 358167752Skevlovoid arm9_dcache_wbinv_all (void); 359167752Skevlovoid arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 360167752Skevlovoid arm9_dcache_inv_range (vm_offset_t, vm_size_t); 361167752Skevlovoid arm9_dcache_wb_range (vm_offset_t, vm_size_t); 362129198Scognet 363167752Skevlovoid arm9_idcache_wbinv_all (void); 364167752Skevlovoid arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 365129198Scognet 366129198Scognetvoid arm9_context_switch (void); 367129198Scognet 368129198Scognetvoid arm9_setup (char *string); 369146948Scognet 370146948Scognetextern unsigned arm9_dcache_sets_max; 371146948Scognetextern unsigned arm9_dcache_sets_inc; 372146948Scognetextern unsigned arm9_dcache_index_max; 373146948Scognetextern unsigned arm9_dcache_index_inc; 374129198Scognet#endif 375129198Scognet 376172738Simp#if defined(CPU_ARM9E) || defined(CPU_ARM10) 377129198Scognetvoid arm10_setttb (u_int); 378129198Scognet 379129198Scognetvoid arm10_tlb_flushID_SE (u_int); 380129198Scognetvoid arm10_tlb_flushI_SE (u_int); 381129198Scognet 382129198Scognetvoid arm10_icache_sync_all (void); 383129198Scognetvoid arm10_icache_sync_range (vm_offset_t, vm_size_t); 384129198Scognet 385129198Scognetvoid arm10_dcache_wbinv_all (void); 386129198Scognetvoid arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 387129198Scognetvoid arm10_dcache_inv_range (vm_offset_t, vm_size_t); 388129198Scognetvoid arm10_dcache_wb_range (vm_offset_t, vm_size_t); 389129198Scognet 390129198Scognetvoid arm10_idcache_wbinv_all (void); 391129198Scognetvoid arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 392129198Scognet 393129198Scognetvoid arm10_context_switch (void); 394129198Scognet 395129198Scognetvoid arm10_setup (char *string); 396129198Scognet 397129198Scognetextern unsigned arm10_dcache_sets_max; 398129198Scognetextern unsigned arm10_dcache_sets_inc; 399129198Scognetextern unsigned arm10_dcache_index_max; 400129198Scognetextern unsigned arm10_dcache_index_inc; 401183835Sraj 402186933Sraju_int sheeva_control_ext (u_int, u_int); 403186933Srajvoid sheeva_setttb (u_int); 404186933Srajvoid sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 405186933Srajvoid sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 406186933Srajvoid sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 407186933Srajvoid sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 408183835Sraj 409186933Srajvoid sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 410186933Srajvoid sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 411186933Srajvoid sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 412186933Srajvoid sheeva_l2cache_wbinv_all (void); 413129198Scognet#endif 414129198Scognet 415172738Simp#ifdef CPU_ARM11 416172738Simpvoid arm11_setttb (u_int); 417172738Simp 418172738Simpvoid arm11_tlb_flushID_SE (u_int); 419172738Simpvoid arm11_tlb_flushI_SE (u_int); 420172738Simp 421172738Simpvoid arm11_context_switch (void); 422172738Simp 423172738Simpvoid arm11_setup (char *string); 424172738Simpvoid arm11_tlb_flushID (void); 425172738Simpvoid arm11_tlb_flushI (void); 426172738Simpvoid arm11_tlb_flushD (void); 427172738Simpvoid arm11_tlb_flushD_SE (u_int va); 428172738Simp 429172738Simpvoid arm11_drain_writebuf (void); 430172738Simp#endif 431172738Simp 432172738Simp#if defined(CPU_ARM9E) || defined (CPU_ARM10) 433172738Simpvoid armv5_ec_setttb(u_int); 434172738Simp 435172738Simpvoid armv5_ec_icache_sync_all(void); 436172738Simpvoid armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 437172738Simp 438172738Simpvoid armv5_ec_dcache_wbinv_all(void); 439172738Simpvoid armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 440172738Simpvoid armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 441172738Simpvoid armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 442172738Simp 443172738Simpvoid armv5_ec_idcache_wbinv_all(void); 444172738Simpvoid armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 445172738Simp#endif 446172738Simp 447172738Simp#if defined (CPU_ARM10) || defined (CPU_ARM11) 448172738Simpvoid armv5_setttb(u_int); 449172738Simp 450172738Simpvoid armv5_icache_sync_all(void); 451172738Simpvoid armv5_icache_sync_range(vm_offset_t, vm_size_t); 452172738Simp 453172738Simpvoid armv5_dcache_wbinv_all(void); 454172738Simpvoid armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); 455172738Simpvoid armv5_dcache_inv_range(vm_offset_t, vm_size_t); 456172738Simpvoid armv5_dcache_wb_range(vm_offset_t, vm_size_t); 457172738Simp 458172738Simpvoid armv5_idcache_wbinv_all(void); 459172738Simpvoid armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); 460172738Simp 461172738Simpextern unsigned armv5_dcache_sets_max; 462172738Simpextern unsigned armv5_dcache_sets_inc; 463172738Simpextern unsigned armv5_dcache_index_max; 464172738Simpextern unsigned armv5_dcache_index_inc; 465172738Simp#endif 466172738Simp 467172738Simp#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 468172738Simp defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 469161592Scognet defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 470201468Srpaulo defined(CPU_FA526) || \ 471161592Scognet defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 472164080Scognet defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 473161592Scognet 474129198Scognetvoid armv4_tlb_flushID (void); 475129198Scognetvoid armv4_tlb_flushI (void); 476129198Scognetvoid armv4_tlb_flushD (void); 477129198Scognetvoid armv4_tlb_flushD_SE (u_int va); 478129198Scognet 479129198Scognetvoid armv4_drain_writebuf (void); 480129198Scognet#endif 481129198Scognet 482129198Scognet#if defined(CPU_IXP12X0) 483129198Scognetvoid ixp12x0_drain_readbuf (void); 484129198Scognetvoid ixp12x0_context_switch (void); 485129198Scognetvoid ixp12x0_setup (char *string); 486129198Scognet#endif 487129198Scognet 488161592Scognet#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 489161592Scognet defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 490164080Scognet defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 491129198Scognetvoid xscale_cpwait (void); 492129198Scognet 493129198Scognetvoid xscale_cpu_sleep (int mode); 494129198Scognet 495129198Scognetu_int xscale_control (u_int clear, u_int bic); 496129198Scognet 497129198Scognetvoid xscale_setttb (u_int ttb); 498129198Scognet 499129198Scognetvoid xscale_tlb_flushID_SE (u_int va); 500129198Scognet 501129198Scognetvoid xscale_cache_flushID (void); 502129198Scognetvoid xscale_cache_flushI (void); 503129198Scognetvoid xscale_cache_flushD (void); 504129198Scognetvoid xscale_cache_flushD_SE (u_int entry); 505129198Scognet 506129198Scognetvoid xscale_cache_cleanID (void); 507129198Scognetvoid xscale_cache_cleanD (void); 508129198Scognetvoid xscale_cache_cleanD_E (u_int entry); 509129198Scognet 510129198Scognetvoid xscale_cache_clean_minidata (void); 511129198Scognet 512129198Scognetvoid xscale_cache_purgeID (void); 513129198Scognetvoid xscale_cache_purgeID_E (u_int entry); 514129198Scognetvoid xscale_cache_purgeD (void); 515129198Scognetvoid xscale_cache_purgeD_E (u_int entry); 516129198Scognet 517129198Scognetvoid xscale_cache_syncI (void); 518129198Scognetvoid xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 519129198Scognetvoid xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 520129198Scognetvoid xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 521129198Scognetvoid xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 522129198Scognetvoid xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 523129198Scognetvoid xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 524129198Scognet 525129198Scognetvoid xscale_context_switch (void); 526129198Scognet 527129198Scognetvoid xscale_setup (char *string); 528161592Scognet#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 529161592Scognet CPU_XSCALE_80219 */ 530129198Scognet 531164080Scognet#ifdef CPU_XSCALE_81342 532164080Scognet 533171618Scognetvoid xscalec3_l2cache_purge (void); 534171618Scognetvoid xscalec3_cache_purgeID (void); 535171618Scognetvoid xscalec3_cache_purgeD (void); 536164080Scognetvoid xscalec3_cache_cleanID (void); 537164080Scognetvoid xscalec3_cache_cleanD (void); 538171618Scognetvoid xscalec3_cache_syncI (void); 539164080Scognet 540171618Scognetvoid xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 541171618Scognetvoid xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 542171618Scognetvoid xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 543164080Scognetvoid xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 544171618Scognetvoid xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 545164080Scognet 546171618Scognetvoid xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 547171618Scognetvoid xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 548171618Scognetvoid xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 549164080Scognet 550171618Scognet 551164080Scognetvoid xscalec3_setttb (u_int ttb); 552164080Scognetvoid xscalec3_context_switch (void); 553164080Scognet 554164080Scognet#endif /* CPU_XSCALE_81342 */ 555164080Scognet 556129198Scognet#define tlb_flush cpu_tlb_flushID 557129198Scognet#define setttb cpu_setttb 558129198Scognet#define drain_writebuf cpu_drain_writebuf 559129198Scognet 560129198Scognet/* 561129198Scognet * Macros for manipulating CPU interrupts 562129198Scognet */ 563129198Scognetstatic __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 564129198Scognet 565129198Scognetstatic __inline u_int32_t 566129198Scognet__set_cpsr_c(u_int bic, u_int eor) 567129198Scognet{ 568129198Scognet u_int32_t tmp, ret; 569129198Scognet 570129198Scognet __asm __volatile( 571129198Scognet "mrs %0, cpsr\n" /* Get the CPSR */ 572129198Scognet "bic %1, %0, %2\n" /* Clear bits */ 573129198Scognet "eor %1, %1, %3\n" /* XOR bits */ 574129198Scognet "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 575129198Scognet : "=&r" (ret), "=&r" (tmp) 576137226Scognet : "r" (bic), "r" (eor) : "memory"); 577129198Scognet 578129198Scognet return ret; 579129198Scognet} 580129198Scognet 581129198Scognet#define disable_interrupts(mask) \ 582129198Scognet (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 583129198Scognet (mask) & (I32_bit | F32_bit))) 584129198Scognet 585129198Scognet#define enable_interrupts(mask) \ 586159145Scognet (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 587129198Scognet 588129198Scognet#define restore_interrupts(old_cpsr) \ 589129198Scognet (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 590129198Scognet 591137226Scognet#define intr_disable() \ 592137226Scognet disable_interrupts(I32_bit | F32_bit) 593137226Scognet#define intr_restore(s) \ 594137226Scognet restore_interrupts(s) 595129198Scognet/* Functions to manipulate the CPSR. */ 596129198Scognetu_int SetCPSR(u_int bic, u_int eor); 597129198Scognetu_int GetCPSR(void); 598129198Scognet 599129198Scognet/* 600129198Scognet * Functions to manipulate cpu r13 601129198Scognet * (in arm/arm32/setstack.S) 602129198Scognet */ 603129198Scognet 604167752Skevlovoid set_stackptr (u_int mode, u_int address); 605167752Skevlou_int get_stackptr (u_int mode); 606129198Scognet 607129198Scognet/* 608129198Scognet * Miscellany 609129198Scognet */ 610129198Scognet 611167752Skevloint get_pc_str_offset (void); 612129198Scognet 613129198Scognet/* 614129198Scognet * CPU functions from locore.S 615129198Scognet */ 616129198Scognet 617167752Skevlovoid cpu_reset (void) __attribute__((__noreturn__)); 618129198Scognet 619129198Scognet/* 620129198Scognet * Cache info variables. 621129198Scognet */ 622129198Scognet 623129198Scognet/* PRIMARY CACHE VARIABLES */ 624129198Scognetextern int arm_picache_size; 625129198Scognetextern int arm_picache_line_size; 626129198Scognetextern int arm_picache_ways; 627129198Scognet 628129198Scognetextern int arm_pdcache_size; /* and unified */ 629129198Scognetextern int arm_pdcache_line_size; 630129198Scognetextern int arm_pdcache_ways; 631129198Scognet 632129198Scognetextern int arm_pcache_type; 633129198Scognetextern int arm_pcache_unified; 634129198Scognet 635129198Scognetextern int arm_dcache_align; 636129198Scognetextern int arm_dcache_align_mask; 637129198Scognet 638129198Scognet#endif /* _KERNEL */ 639129198Scognet#endif /* _MACHINE_CPUFUNC_H_ */ 640129198Scognet 641129198Scognet/* End of cpufunc.h */ 642