cpufunc.h revision 129198
1/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3/* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD: head/sys/arm/include/cpufunc.h 129198 2004-05-14 11:46:45Z cognet $ 42 */ 43 44#ifndef _MACHINE_CPUFUNC_H_ 45#define _MACHINE_CPUFUNC_H_ 46 47#ifdef _KERNEL 48 49#include <sys/types.h> 50#include <machine/cpuconf.h> 51 52void disable_intr(void); 53void enable_intr(void); 54 55static __inline register_t 56intr_disable(void) 57{ 58 int s = 0, tmp; 59 60 __asm __volatile("mrs %0, cpsr; \ 61 orr %1, %0, %2;\ 62 msr cpsr_all, %1;" 63 : "=r" (s), "=r" (tmp) 64 : "I" (I32_bit) 65 : "cc"); 66 return (s); 67} 68 69static __inline void 70intr_restore(int s) 71{ 72 __asm __volatile("msr cpsr_all, %0 " 73 : /* no output */ 74 : "r" (s) 75 : "cc"); 76} 77struct cpu_functions { 78 79 /* CPU functions */ 80 81 u_int (*cf_id) (void); 82 void (*cf_cpwait) (void); 83 84 /* MMU functions */ 85 86 u_int (*cf_control) (u_int bic, u_int eor); 87 void (*cf_domains) (u_int domains); 88 void (*cf_setttb) (u_int ttb); 89 u_int (*cf_faultstatus) (void); 90 u_int (*cf_faultaddress) (void); 91 92 /* TLB functions */ 93 94 void (*cf_tlb_flushID) (void); 95 void (*cf_tlb_flushID_SE) (u_int va); 96 void (*cf_tlb_flushI) (void); 97 void (*cf_tlb_flushI_SE) (u_int va); 98 void (*cf_tlb_flushD) (void); 99 void (*cf_tlb_flushD_SE) (u_int va); 100 101 /* 102 * Cache operations: 103 * 104 * We define the following primitives: 105 * 106 * icache_sync_all Synchronize I-cache 107 * icache_sync_range Synchronize I-cache range 108 * 109 * dcache_wbinv_all Write-back and Invalidate D-cache 110 * dcache_wbinv_range Write-back and Invalidate D-cache range 111 * dcache_inv_range Invalidate D-cache range 112 * dcache_wb_range Write-back D-cache range 113 * 114 * idcache_wbinv_all Write-back and Invalidate D-cache, 115 * Invalidate I-cache 116 * idcache_wbinv_range Write-back and Invalidate D-cache, 117 * Invalidate I-cache range 118 * 119 * Note that the ARM term for "write-back" is "clean". We use 120 * the term "write-back" since it's a more common way to describe 121 * the operation. 122 * 123 * There are some rules that must be followed: 124 * 125 * I-cache Synch (all or range): 126 * The goal is to synchronize the instruction stream, 127 * so you may beed to write-back dirty D-cache blocks 128 * first. If a range is requested, and you can't 129 * synchronize just a range, you have to hit the whole 130 * thing. 131 * 132 * D-cache Write-Back and Invalidate range: 133 * If you can't WB-Inv a range, you must WB-Inv the 134 * entire D-cache. 135 * 136 * D-cache Invalidate: 137 * If you can't Inv the D-cache, you must Write-Back 138 * and Invalidate. Code that uses this operation 139 * MUST NOT assume that the D-cache will not be written 140 * back to memory. 141 * 142 * D-cache Write-Back: 143 * If you can't Write-back without doing an Inv, 144 * that's fine. Then treat this as a WB-Inv. 145 * Skipping the invalidate is merely an optimization. 146 * 147 * All operations: 148 * Valid virtual addresses must be passed to each 149 * cache operation. 150 */ 151 void (*cf_icache_sync_all) (void); 152 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 153 154 void (*cf_dcache_wbinv_all) (void); 155 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 156 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 157 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 158 159 void (*cf_idcache_wbinv_all) (void); 160 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 161 162 /* Other functions */ 163 164 void (*cf_flush_prefetchbuf) (void); 165 void (*cf_drain_writebuf) (void); 166 void (*cf_flush_brnchtgt_C) (void); 167 void (*cf_flush_brnchtgt_E) (u_int va); 168 169 void (*cf_sleep) (int mode); 170 171 /* Soft functions */ 172 173 int (*cf_dataabt_fixup) (void *arg); 174 int (*cf_prefetchabt_fixup) (void *arg); 175 176 void (*cf_context_switch) (void); 177 178 void (*cf_setup) (char *string); 179}; 180 181extern struct cpu_functions cpufuncs; 182extern u_int cputype; 183 184#define cpu_id() cpufuncs.cf_id() 185#define cpu_cpwait() cpufuncs.cf_cpwait() 186 187#define cpu_control(c, e) cpufuncs.cf_control(c, e) 188#define cpu_domains(d) cpufuncs.cf_domains(d) 189#define cpu_setttb(t) cpufuncs.cf_setttb(t) 190#define cpu_faultstatus() cpufuncs.cf_faultstatus() 191#define cpu_faultaddress() cpufuncs.cf_faultaddress() 192 193#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 194#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 195#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 196#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 197#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 198#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 199 200#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 201#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 202 203#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 204#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 205#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 206#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 207 208#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 209#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 210 211#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 212#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 213#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 214#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 215 216#define cpu_sleep(m) cpufuncs.cf_sleep(m) 217 218#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 219#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 220#define ABORT_FIXUP_OK 0 /* fixup succeeded */ 221#define ABORT_FIXUP_FAILED 1 /* fixup failed */ 222#define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 223 224#define cpu_setup(a) cpufuncs.cf_setup(a) 225 226int set_cpufuncs (void); 227#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 228#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 229 230void cpufunc_nullop (void); 231int cpufunc_null_fixup (void *); 232int early_abort_fixup (void *); 233int late_abort_fixup (void *); 234u_int cpufunc_id (void); 235u_int cpufunc_control (u_int clear, u_int bic); 236void cpufunc_domains (u_int domains); 237u_int cpufunc_faultstatus (void); 238u_int cpufunc_faultaddress (void); 239 240#ifdef CPU_ARM3 241u_int arm3_control (u_int clear, u_int bic); 242void arm3_cache_flush (void); 243#endif /* CPU_ARM3 */ 244 245#if defined(CPU_ARM6) || defined(CPU_ARM7) 246void arm67_setttb (u_int ttb); 247void arm67_tlb_flush (void); 248void arm67_tlb_purge (u_int va); 249void arm67_cache_flush (void); 250void arm67_context_switch (void); 251#endif /* CPU_ARM6 || CPU_ARM7 */ 252 253#ifdef CPU_ARM6 254void arm6_setup (char *string); 255#endif /* CPU_ARM6 */ 256 257#ifdef CPU_ARM7 258void arm7_setup (char *string); 259#endif /* CPU_ARM7 */ 260 261#ifdef CPU_ARM7TDMI 262int arm7_dataabt_fixup (void *arg); 263void arm7tdmi_setup (char *string); 264void arm7tdmi_setttb (u_int ttb); 265void arm7tdmi_tlb_flushID (void); 266void arm7tdmi_tlb_flushID_SE (u_int va); 267void arm7tdmi_cache_flushID (void); 268void arm7tdmi_context_switch (void); 269#endif /* CPU_ARM7TDMI */ 270 271#ifdef CPU_ARM8 272void arm8_setttb (u_int ttb); 273void arm8_tlb_flushID (void); 274void arm8_tlb_flushID_SE (u_int va); 275void arm8_cache_flushID (void); 276void arm8_cache_flushID_E (u_int entry); 277void arm8_cache_cleanID (void); 278void arm8_cache_cleanID_E (u_int entry); 279void arm8_cache_purgeID (void); 280void arm8_cache_purgeID_E (u_int entry); 281 282void arm8_cache_syncI (void); 283void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 284void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 285void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 286void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 287void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 288 289void arm8_context_switch (void); 290 291void arm8_setup (char *string); 292 293u_int arm8_clock_config (u_int, u_int); 294#endif 295 296#ifdef CPU_SA110 297void sa110_setup (char *string); 298void sa110_context_switch (void); 299#endif /* CPU_SA110 */ 300 301#if defined(CPU_SA1100) || defined(CPU_SA1110) 302void sa11x0_drain_readbuf (void); 303 304void sa11x0_context_switch (void); 305void sa11x0_cpu_sleep (int mode); 306 307void sa11x0_setup (char *string); 308#endif 309 310#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 311void sa1_setttb (u_int ttb); 312 313void sa1_tlb_flushID_SE (u_int va); 314 315void sa1_cache_flushID (void); 316void sa1_cache_flushI (void); 317void sa1_cache_flushD (void); 318void sa1_cache_flushD_SE (u_int entry); 319 320void sa1_cache_cleanID (void); 321void sa1_cache_cleanD (void); 322void sa1_cache_cleanD_E (u_int entry); 323 324void sa1_cache_purgeID (void); 325void sa1_cache_purgeID_E (u_int entry); 326void sa1_cache_purgeD (void); 327void sa1_cache_purgeD_E (u_int entry); 328 329void sa1_cache_syncI (void); 330void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 331void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 332void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 333void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 334void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 335 336#endif 337 338#ifdef CPU_ARM9 339void arm9_setttb (u_int); 340 341void arm9_tlb_flushID_SE (u_int va); 342 343void arm9_cache_flushID (void); 344void arm9_cache_flushID_SE (u_int); 345void arm9_cache_flushI (void); 346void arm9_cache_flushI_SE (u_int); 347void arm9_cache_flushD (void); 348void arm9_cache_flushD_SE (u_int); 349 350void arm9_cache_cleanID (void); 351 352void arm9_cache_syncI (void); 353void arm9_cache_flushID_rng (vm_offset_t, vm_size_t); 354void arm9_cache_flushD_rng (vm_offset_t, vm_size_t); 355void arm9_cache_syncI_rng (vm_offset_t, vm_size_t); 356 357void arm9_context_switch (void); 358 359void arm9_setup (char *string); 360#endif 361 362#ifdef CPU_ARM10 363void arm10_setttb (u_int); 364 365void arm10_tlb_flushID_SE (u_int); 366void arm10_tlb_flushI_SE (u_int); 367 368void arm10_icache_sync_all (void); 369void arm10_icache_sync_range (vm_offset_t, vm_size_t); 370 371void arm10_dcache_wbinv_all (void); 372void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 373void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 374void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 375 376void arm10_idcache_wbinv_all (void); 377void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 378 379void arm10_context_switch (void); 380 381void arm10_setup (char *string); 382 383extern unsigned arm10_dcache_sets_max; 384extern unsigned arm10_dcache_sets_inc; 385extern unsigned arm10_dcache_index_max; 386extern unsigned arm10_dcache_index_inc; 387#endif 388 389#if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \ 390 defined(CPU_SA1100) || defined(CPU_SA1110) || \ 391 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 392 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 393 394void armv4_tlb_flushID (void); 395void armv4_tlb_flushI (void); 396void armv4_tlb_flushD (void); 397void armv4_tlb_flushD_SE (u_int va); 398 399void armv4_drain_writebuf (void); 400#endif 401 402#if defined(CPU_IXP12X0) 403void ixp12x0_drain_readbuf (void); 404void ixp12x0_context_switch (void); 405void ixp12x0_setup (char *string); 406#endif 407 408#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 409 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 410void xscale_cpwait (void); 411 412void xscale_cpu_sleep (int mode); 413 414u_int xscale_control (u_int clear, u_int bic); 415 416void xscale_setttb (u_int ttb); 417 418void xscale_tlb_flushID_SE (u_int va); 419 420void xscale_cache_flushID (void); 421void xscale_cache_flushI (void); 422void xscale_cache_flushD (void); 423void xscale_cache_flushD_SE (u_int entry); 424 425void xscale_cache_cleanID (void); 426void xscale_cache_cleanD (void); 427void xscale_cache_cleanD_E (u_int entry); 428 429void xscale_cache_clean_minidata (void); 430 431void xscale_cache_purgeID (void); 432void xscale_cache_purgeID_E (u_int entry); 433void xscale_cache_purgeD (void); 434void xscale_cache_purgeD_E (u_int entry); 435 436void xscale_cache_syncI (void); 437void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 438void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 439void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 440void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 441void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 442void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 443 444void xscale_context_switch (void); 445 446void xscale_setup (char *string); 447#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 448 449#define tlb_flush cpu_tlb_flushID 450#define setttb cpu_setttb 451#define drain_writebuf cpu_drain_writebuf 452 453/* 454 * Macros for manipulating CPU interrupts 455 */ 456static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 457 458static __inline u_int32_t 459__set_cpsr_c(u_int bic, u_int eor) 460{ 461 u_int32_t tmp, ret; 462 463 __asm __volatile( 464 "mrs %0, cpsr\n" /* Get the CPSR */ 465 "bic %1, %0, %2\n" /* Clear bits */ 466 "eor %1, %1, %3\n" /* XOR bits */ 467 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 468 : "=&r" (ret), "=&r" (tmp) 469 : "r" (bic), "r" (eor)); 470 471 return ret; 472} 473 474#define disable_interrupts(mask) \ 475 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 476 (mask) & (I32_bit | F32_bit))) 477 478#define enable_interrupts(mask) \ 479 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 480 481#define restore_interrupts(old_cpsr) \ 482 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 483 484/* Functions to manipulate the CPSR. */ 485u_int SetCPSR(u_int bic, u_int eor); 486u_int GetCPSR(void); 487 488/* 489 * Functions to manipulate cpu r13 490 * (in arm/arm32/setstack.S) 491 */ 492 493void set_stackptr __P((u_int mode, u_int address)); 494u_int get_stackptr __P((u_int mode)); 495 496/* 497 * Miscellany 498 */ 499 500int get_pc_str_offset __P((void)); 501 502/* 503 * CPU functions from locore.S 504 */ 505 506void cpu_reset __P((void)) __attribute__((__noreturn__)); 507 508/* 509 * Cache info variables. 510 */ 511 512/* PRIMARY CACHE VARIABLES */ 513extern int arm_picache_size; 514extern int arm_picache_line_size; 515extern int arm_picache_ways; 516 517extern int arm_pdcache_size; /* and unified */ 518extern int arm_pdcache_line_size; 519extern int arm_pdcache_ways; 520 521extern int arm_pcache_type; 522extern int arm_pcache_unified; 523 524extern int arm_dcache_align; 525extern int arm_dcache_align_mask; 526 527#endif /* _KERNEL */ 528#endif /* _MACHINE_CPUFUNC_H_ */ 529 530/* End of cpufunc.h */ 531