1129198Scognet/* $NetBSD: cpu.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */ 2129198Scognet/* $FreeBSD: stable/11/sys/arm/include/cpu.h 340270 2018-11-08 22:42:55Z jhb $ */ 3129198Scognet 4129198Scognet#ifndef MACHINE_CPU_H 5129198Scognet#define MACHINE_CPU_H 6129198Scognet 7129198Scognet#include <machine/armreg.h> 8257200Sian#include <machine/frame.h> 9129198Scognet 10236524Simpvoid cpu_halt(void); 11236524Simpvoid swi_vm(void *); 12129198Scognet 13253750Savg#ifdef _KERNEL 14276808Sian#if __ARM_ARCH >= 6 15276808Sian#include <machine/cpu-v6.h> 16295315Smmel#else 17295315Smmel#include <machine/cpu-v4.h> 18290614Sbz#endif /* __ARM_ARCH >= 6 */ 19290614Sbz 20129198Scognetstatic __inline uint64_t 21129198Scognetget_cyclecount(void) 22129198Scognet{ 23276803Sian#if __ARM_ARCH >= 6 24290614Sbz#if (__ARM_ARCH > 6) && defined(DEV_PMU) 25290614Sbz if (pmu_attched) { 26290614Sbz u_int cpu; 27290614Sbz uint64_t h, h2; 28290614Sbz uint32_t l, r; 29290614Sbz 30290614Sbz cpu = PCPU_GET(cpuid); 31290614Sbz h = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]); 32290614Sbz l = cp15_pmccntr_get(); 33290614Sbz /* In case interrupts are disabled we need to check for overflow. */ 34290614Sbz r = cp15_pmovsr_get(); 35290614Sbz if (r & PMU_OVSR_C) { 36290614Sbz atomic_add_32(&ccnt_hi[cpu], 1); 37290614Sbz /* Clear the event. */ 38290614Sbz cp15_pmovsr_set(PMU_OVSR_C); 39290614Sbz } 40290614Sbz /* Make sure there was no wrap-around while we read the lo half. */ 41290614Sbz h2 = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]); 42290614Sbz if (h != h2) 43290614Sbz l = cp15_pmccntr_get(); 44290614Sbz return (h2 << 32 | l); 45290614Sbz } else 46290614Sbz#endif 47290614Sbz return cp15_pmccntr_get(); 48266083Smarkm#else /* No performance counters, so use binuptime(9). This is slooooow */ 49137223Scognet struct bintime bt; 50137223Scognet 51137223Scognet binuptime(&bt); 52219653Sjkim return ((uint64_t)bt.sec << 56 | bt.frac >> 8); 53266083Smarkm#endif 54129198Scognet} 55253750Savg#endif 56129198Scognet 57129198Scognet#define TRAPF_USERMODE(frame) ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) 58129198Scognet 59129198Scognet#define TRAPF_PC(tfp) ((tfp)->tf_pc) 60129198Scognet 61236524Simp#define cpu_getstack(td) ((td)->td_frame->tf_usr_sp) 62236524Simp#define cpu_setstack(td, sp) ((td)->td_frame->tf_usr_sp = (sp)) 63133084Smux#define cpu_spinwait() /* nothing */ 64340270Sjhb#define cpu_lock_delay() DELAY(1) 65129198Scognet 66129198Scognet#define ARM_NVEC 8 67129198Scognet#define ARM_VEC_ALL 0xffffffff 68129198Scognet 69129198Scognetextern vm_offset_t vector_page; 70129198Scognet 71261663Sandrew/* 72261663Sandrew * Params passed into initarm. If you change the size of this you will 73261663Sandrew * need to update locore.S to allocate more memory on the stack before 74261663Sandrew * it calls initarm. 75261663Sandrew */ 76236524Simpstruct arm_boot_params { 77236524Simp register_t abp_size; /* Size of this structure */ 78236524Simp register_t abp_r0; /* r0 from the boot loader */ 79236524Simp register_t abp_r1; /* r1 from the boot loader */ 80236524Simp register_t abp_r2; /* r2 from the boot loader */ 81236524Simp register_t abp_r3; /* r3 from the boot loader */ 82261562Sandrew vm_offset_t abp_physaddr; /* The kernel physical address */ 83261663Sandrew vm_offset_t abp_pagetable; /* The early page table */ 84236524Simp}; 85236524Simp 86141094Snjlvoid arm_vector_init(vm_offset_t, int); 87141094Snjlvoid fork_trampoline(void); 88141094Snjlvoid identify_arm_cpu(void); 89236524Simpvoid *initarm(struct arm_boot_params *); 90129198Scognet 91129198Scognetextern char btext[]; 92129198Scognetextern char etext[]; 93236524Simpint badaddr_read(void *, size_t, void *); 94129198Scognet#endif /* !MACHINE_CPU_H */ 95