1/*-
2 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de>
3 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx6_mp.c 307344 2016-10-15 08:27:54Z mmel $");
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/kernel.h>
33#include <sys/lock.h>
34#include <sys/mutex.h>
35#include <sys/smp.h>
36
37#include <vm/vm.h>
38#include <vm/pmap.h>
39
40#include <machine/cpu.h>
41#include <machine/smp.h>
42#include <machine/fdt.h>
43#include <machine/intr.h>
44
45#define	SCU_PHYSBASE			0x00a00000
46#define	SCU_SIZE			0x00001000
47
48#define	SCU_CONTROL_REG			0x00
49#define	  SCU_CONTROL_ENABLE		  (1 << 0)
50#define	SCU_CONFIG_REG			0x04
51#define	  SCU_CONFIG_REG_NCPU_MASK	  0x03
52#define	SCU_CPUPOWER_REG		0x08
53#define	SCU_INV_TAGS_REG		0x0c
54#define	SCU_DIAG_CONTROL		0x30
55#define	  SCU_DIAG_DISABLE_MIGBIT	  (1 << 0)
56#define	SCU_FILTER_START_REG		0x40
57#define	SCU_FILTER_END_REG		0x44
58#define	SCU_SECURE_ACCESS_REG		0x50
59#define	SCU_NONSECURE_ACCESS_REG	0x54
60
61#define	SRC_PHYSBASE			0x020d8000
62#define SRC_SIZE			0x4000
63#define	SRC_CONTROL_REG			0x00
64#define	SRC_CONTROL_C1ENA_SHIFT		  22	/* Bit for Core 1 enable */
65#define	SRC_CONTROL_C1RST_SHIFT		  14	/* Bit for Core 1 reset */
66#define	SRC_GPR0_C1FUNC			0x20	/* Register for Core 1 entry func */
67#define	SRC_GPR1_C1ARG			0x24	/* Register for Core 1 entry arg */
68
69void
70platform_mp_setmaxid(void)
71{
72	bus_space_handle_t scu;
73	int hwcpu, ncpu;
74	uint32_t val;
75
76	/* If we've already set the global vars don't bother to do it again. */
77	if (mp_ncpus != 0)
78		return;
79
80	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
81		panic("Couldn't map the SCU\n");
82	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG);
83	hwcpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1;
84	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
85
86	ncpu = hwcpu;
87	TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
88	if (ncpu < 1 || ncpu > hwcpu)
89		ncpu = hwcpu;
90
91	mp_ncpus = ncpu;
92	mp_maxid = ncpu - 1;
93}
94
95void
96platform_mp_start_ap(void)
97{
98	bus_space_handle_t scu;
99	bus_space_handle_t src;
100
101	uint32_t val;
102	int i;
103
104	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
105		panic("Couldn't map the SCU\n");
106	if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
107		panic("Couldn't map the system reset controller (SRC)\n");
108
109	/*
110	 * Invalidate SCU cache tags.  The 0x0000ffff constant invalidates all
111	 * ways on all cores 0-3.  Per the ARM docs, it's harmless to write to
112	 * the bits for cores that are not present.
113	 */
114	bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
115
116	/*
117	 * Erratum ARM/MP: 764369 (problems with cache maintenance).
118	 * Setting the "disable-migratory bit" in the undocumented SCU
119	 * Diagnostic Control Register helps work around the problem.
120	 */
121	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
122	bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
123	    val | SCU_DIAG_DISABLE_MIGBIT);
124
125	/*
126	 * Enable the SCU, then clean the cache on this core.  After these two
127	 * operations the cache tag ram in the SCU is coherent with the contents
128	 * of the cache on this core.  The other cores aren't running yet so
129	 * their caches can't contain valid data yet, but we've initialized
130	 * their SCU tag ram above, so they will be coherent from startup.
131	 */
132	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
133	bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
134	    val | SCU_CONTROL_ENABLE);
135	dcache_wbinv_poc_all();
136
137	/*
138	 * For each AP core, set the entry point address and argument registers,
139	 * and set the core-enable and core-reset bits in the control register.
140	 */
141	val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
142	for (i=1; i < mp_ncpus; i++) {
143		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
144		    pmap_kextract((vm_offset_t)mpentry));
145		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG  + 8*i, 0);
146
147		val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
148		    ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
149
150	}
151	bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val);
152
153	dsb();
154	sev();
155
156	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
157	bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
158}
159