1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Oleksandr Rybalko 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx51_ipuv3_fbd.c 314503 2017-03-01 18:53:05Z ian $"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bio.h> 37#include <sys/bus.h> 38#include <sys/conf.h> 39#include <sys/endian.h> 40#include <sys/kernel.h> 41#include <sys/kthread.h> 42#include <sys/lock.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/mutex.h> 46#include <sys/queue.h> 47#include <sys/resource.h> 48#include <sys/rman.h> 49#include <sys/time.h> 50#include <sys/timetc.h> 51#include <sys/fbio.h> 52#include <sys/consio.h> 53#include <sys/eventhandler.h> 54 55#include <sys/kdb.h> 56 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <machine/frame.h> 60#include <machine/intr.h> 61 62#include <dev/fdt/fdt_common.h> 63#include <dev/ofw/ofw_bus.h> 64#include <dev/ofw/ofw_bus_subr.h> 65 66#include <dev/vt/vt.h> 67#include <dev/vt/colors/vt_termcolors.h> 68 69#include <arm/freescale/imx/imx51_ccmvar.h> 70 71#include <arm/freescale/imx/imx51_ipuv3reg.h> 72 73#include "fb_if.h" 74 75#define IMX51_IPU_HSP_CLOCK 665000000 76 77struct ipu3sc_softc { 78 device_t dev; 79 device_t sc_fbd; /* fbd child */ 80 struct fb_info sc_info; 81 82 bus_space_tag_t iot; 83 bus_space_handle_t ioh; 84 bus_space_handle_t cm_ioh; 85 bus_space_handle_t dp_ioh; 86 bus_space_handle_t di0_ioh; 87 bus_space_handle_t di1_ioh; 88 bus_space_handle_t dctmpl_ioh; 89 bus_space_handle_t dc_ioh; 90 bus_space_handle_t dmfc_ioh; 91 bus_space_handle_t idmac_ioh; 92 bus_space_handle_t cpmem_ioh; 93}; 94 95static struct ipu3sc_softc *ipu3sc_softc; 96 97#define IPUV3_READ(ipuv3, module, reg) \ 98 bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) 99#define IPUV3_WRITE(ipuv3, module, reg, val) \ 100 bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) 101 102#define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40) 103#define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20) 104#define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000) 105#define IMX_IPU_DP0 0 106#define IMX_IPU_DP1 1 107#define CPMEM_CHANNEL(_dp, _ch, _w) \ 108 (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \ 109 CPMEM_WORD_OFFSET(_w)) 110#define CPMEM_OFFSET(_dp, _ch, _w, _o) \ 111 (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o)) 112 113static int ipu3_fb_probe(device_t); 114static int ipu3_fb_attach(device_t); 115 116static void 117ipu3_fb_init(struct ipu3sc_softc *sc) 118{ 119 uint64_t w0sh96; 120 uint32_t w1sh96; 121 122 /* FW W0[137:125] - 96 = [41:29] */ 123 /* FH W0[149:138] - 96 = [53:42] */ 124 w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16)); 125 w0sh96 <<= 32; 126 w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12)); 127 128 sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1; 129 sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1; 130 131 /* SLY W1[115:102] - 96 = [19:6] */ 132 w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12)); 133 sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1; 134 135 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 136 sc->sc_info.fb_stride); 137 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 138 139 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 140 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 141 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 142 143 /* DP1 + config_ch_23 + word_2 */ 144 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0), 145 (((uint32_t)sc->sc_info.fb_pbase >> 3) | 146 (((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff); 147 148 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4), 149 (((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff); 150 151 /* XXX: fetch or set it from/to IPU. */ 152 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride / 153 sc->sc_info.fb_width * 8; 154} 155 156/* Use own color map, because of different RGB offset. */ 157static int 158ipu3_fb_init_cmap(uint32_t *cmap, int bytespp) 159{ 160 161 switch (bytespp) { 162 case 8: 163 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 164 0x7, 5, 0x7, 2, 0x3, 0)); 165 case 15: 166 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 167 0x1f, 10, 0x1f, 5, 0x1f, 0)); 168 case 16: 169 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 170 0x1f, 11, 0x3f, 5, 0x1f, 0)); 171 case 24: 172 case 32: /* Ignore alpha. */ 173 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 174 0xff, 0, 0xff, 8, 0xff, 16)); 175 default: 176 return (1); 177 } 178} 179 180static int 181ipu3_fb_probe(device_t dev) 182{ 183 184 if (!ofw_bus_status_okay(dev)) 185 return (ENXIO); 186 187 if (!ofw_bus_is_compatible(dev, "fsl,ipu3")) 188 return (ENXIO); 189 190 device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)"); 191 192 return (BUS_PROBE_DEFAULT); 193} 194 195static int 196ipu3_fb_attach(device_t dev) 197{ 198 struct ipu3sc_softc *sc = device_get_softc(dev); 199 bus_space_tag_t iot; 200 bus_space_handle_t ioh; 201 phandle_t node; 202 pcell_t reg; 203 int err; 204 uintptr_t base; 205 206 ipu3sc_softc = sc; 207 208 if (bootverbose) 209 device_printf(dev, "clock gate status is %d\n", 210 imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); 211 212 sc->dev = dev; 213 214 sc = device_get_softc(dev); 215 sc->iot = iot = fdtbus_bs_tag; 216 217 /* 218 * Retrieve the device address based on the start address in the 219 * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register 220 * address, so we just subtract IPU_CM_BASE to get the offset at which 221 * the IPU device was memory mapped. 222 * On i.MX53, the offset is 0. 223 */ 224 node = ofw_bus_get_node(dev); 225 if ((OF_getencprop(node, "reg", ®, sizeof(reg))) <= 0) 226 base = 0; 227 else 228 base = reg - IPU_CM_BASE(0); 229 /* map controller registers */ 230 err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); 231 if (err) 232 goto fail_retarn_cm; 233 sc->cm_ioh = ioh; 234 235 /* map Display Multi FIFO Controller registers */ 236 err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh); 237 if (err) 238 goto fail_retarn_dmfc; 239 sc->dmfc_ioh = ioh; 240 241 /* map Display Interface 0 registers */ 242 err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh); 243 if (err) 244 goto fail_retarn_di0; 245 sc->di0_ioh = ioh; 246 247 /* map Display Interface 1 registers */ 248 err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh); 249 if (err) 250 goto fail_retarn_di1; 251 sc->di1_ioh = ioh; 252 253 /* map Display Processor registers */ 254 err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh); 255 if (err) 256 goto fail_retarn_dp; 257 sc->dp_ioh = ioh; 258 259 /* map Display Controller registers */ 260 err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh); 261 if (err) 262 goto fail_retarn_dc; 263 sc->dc_ioh = ioh; 264 265 /* map Image DMA Controller registers */ 266 err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0, 267 &ioh); 268 if (err) 269 goto fail_retarn_idmac; 270 sc->idmac_ioh = ioh; 271 272 /* map CPMEM registers */ 273 err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0, 274 &ioh); 275 if (err) 276 goto fail_retarn_cpmem; 277 sc->cpmem_ioh = ioh; 278 279 /* map DCTEMPL registers */ 280 err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0, 281 &ioh); 282 if (err) 283 goto fail_retarn_dctmpl; 284 sc->dctmpl_ioh = ioh; 285 286#ifdef notyet 287 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, 288 ipuv3intr, sc); 289 if (sc->ih == NULL) { 290 device_printf(sc->dev, 291 "unable to establish interrupt at irq %d\n", 292 IMX51_INT_IPUV3); 293 return (ENXIO); 294 } 295#endif 296 297 /* 298 * We have to wait until interrupts are enabled. 299 * Mailbox relies on it to get data from VideoCore 300 */ 301 ipu3_fb_init(sc); 302 303 sc->sc_info.fb_name = device_get_nameunit(dev); 304 305 ipu3_fb_init_cmap(sc->sc_info.fb_cmap, sc->sc_info.fb_depth); 306 sc->sc_info.fb_cmsize = 16; 307 308 /* Ask newbus to attach framebuffer device to me. */ 309 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 310 if (sc->sc_fbd == NULL) 311 device_printf(dev, "Can't attach fbd device\n"); 312 313 return (bus_generic_attach(dev)); 314 315fail_retarn_dctmpl: 316 bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); 317fail_retarn_cpmem: 318 bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); 319fail_retarn_idmac: 320 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); 321fail_retarn_dp: 322 bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); 323fail_retarn_dc: 324 bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE); 325fail_retarn_di1: 326 bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); 327fail_retarn_di0: 328 bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); 329fail_retarn_dmfc: 330 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); 331fail_retarn_cm: 332 device_printf(sc->dev, 333 "failed to map registers (errno=%d)\n", err); 334 return (err); 335} 336 337static struct fb_info * 338ipu3_fb_getinfo(device_t dev) 339{ 340 struct ipu3sc_softc *sc = device_get_softc(dev); 341 342 return (&sc->sc_info); 343} 344 345static device_method_t ipu3_fb_methods[] = { 346 /* Device interface */ 347 DEVMETHOD(device_probe, ipu3_fb_probe), 348 DEVMETHOD(device_attach, ipu3_fb_attach), 349 350 /* Framebuffer service methods */ 351 DEVMETHOD(fb_getinfo, ipu3_fb_getinfo), 352 { 0, 0 } 353}; 354 355static devclass_t ipu3_fb_devclass; 356 357static driver_t ipu3_fb_driver = { 358 "fb", 359 ipu3_fb_methods, 360 sizeof(struct ipu3sc_softc), 361}; 362 363DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0); 364