1/*-
2 * Copyright (c) 2009 Yohanes Nugroho <yohanes@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#ifndef	_IFECEVAR_H
30#define	_IFECEVAR_H
31
32#define	ECE_MAX_TX_BUFFERS	128
33#define	ECE_MAX_RX_BUFFERS	128
34#define	MAX_FRAGMENT		32
35
36typedef struct {
37	/* 1st 32Bits */
38	uint32_t		data_ptr;
39	/* 2nd	32Bits*/
40	uint32_t		length:16;
41
42	uint32_t		tco:1; /*tcp checksum offload*/
43	uint32_t		uco:1; /*udp checksum offload*/
44	uint32_t		ico:1; /*ip checksum offload*/
45	/* force_route_port_map*/
46	uint32_t		pmap:3;
47	/* force_route */
48	uint32_t		fr:1;
49	/* force_priority_value */
50	uint32_t		pri:3;
51	/* force_priority */
52	uint32_t		fp:1;
53	/*interrupt_bit*/
54	uint32_t		interrupt:1;
55	/*last_seg*/
56	uint32_t		ls:1;
57	/*first_seg*/
58	uint32_t		fs:1;
59	/* end_bit */
60	uint32_t		eor:1;
61	/* c_bit */
62	uint32_t		cown:1;
63	/* 3rd 32Bits*/
64	/*vid_index*/
65	uint32_t		vid:3;
66	/*insert_vid_tag*/
67	uint32_t		insv:1;
68	/*pppoe_section_index*/
69	uint32_t		sid:3;
70	/*insert_pppoe_section*/
71	uint32_t		inss:1;
72	uint32_t		unused:24;
73	/* 4th 32Bits*/
74	uint32_t		unused2;
75
76} eth_tx_desc_t;
77
78typedef struct{
79	uint32_t		data_ptr;
80	uint32_t		length:16;
81	uint32_t		l4f:1;
82	uint32_t		ipf:1;
83	uint32_t		prot:2;
84	uint32_t		hr:6;
85	uint32_t		sp:2;
86	uint32_t		ls:1;
87	uint32_t		fs:1;
88	uint32_t		eor:1;
89	uint32_t		cown:1;
90	uint32_t		unused;
91	uint32_t		unused2;
92} eth_rx_desc_t;
93
94
95struct rx_desc_info {
96	struct mbuf*buff;
97	bus_dmamap_t dmamap;
98	eth_rx_desc_t *desc;
99};
100
101struct tx_desc_info {
102	struct mbuf*buff;
103	bus_dmamap_t dmamap;
104	eth_tx_desc_t *desc;
105};
106
107
108struct ece_softc
109{
110	struct ifnet *ifp;		/* ifnet pointer */
111	struct mtx sc_mtx;		/* global mutex */
112	struct mtx sc_mtx_tx;		/* tx mutex */
113	struct mtx sc_mtx_rx;		/* rx mutex */
114	struct mtx sc_mtx_cleanup;	/* rx mutex */
115
116	bus_dma_tag_t	sc_parent_tag;	/* parent bus DMA tag */
117
118	device_t dev;			/* Myself */
119	device_t miibus;		/* My child miibus */
120	void *intrhand;			/* Interrupt handle */
121	void *intrhand_qf;		/* queue full */
122	void *intrhand_tx;		/* tx complete */
123	void *intrhand_status;		/* error status */
124
125	struct resource *irq_res_tx;	/* transmit */
126	struct resource *irq_res_rec;	/* receive */
127	struct resource *irq_res_qf;	/* queue full */
128	struct resource *irq_res_status; /* status */
129
130	struct resource	*mem_res;	/* Memory resource */
131
132	struct callout tick_ch;		/* Tick callout */
133
134	struct taskqueue *sc_tq;
135	struct task	sc_intr_task;
136	struct task	sc_cleanup_task;
137	struct task	sc_tx_task;
138
139	bus_dmamap_t	dmamap_ring_tx;
140	bus_dmamap_t	dmamap_ring_rx;
141	bus_dmamap_t	rx_sparemap;
142
143	/*dma tag for ring*/
144	bus_dma_tag_t	dmatag_ring_tx;
145	bus_dma_tag_t	dmatag_ring_rx;
146
147	/*dma tag for data*/
148	bus_dma_tag_t	dmatag_data_tx;
149	bus_dma_tag_t	dmatag_data_rx;
150
151	/*the ring*/
152	eth_tx_desc_t*	desc_tx;
153	eth_rx_desc_t*	desc_rx;
154
155	/*ring physical address*/
156	bus_addr_t	ring_paddr_tx;
157	bus_addr_t	ring_paddr_rx;
158
159	/*index of last received descriptor*/
160	uint32_t last_rx;
161	struct rx_desc_info rx_desc[ECE_MAX_RX_BUFFERS];
162
163	/* tx producer index */
164	uint32_t tx_prod;
165	/* tx consumer index */
166	uint32_t tx_cons;
167	/* tx ring index*/
168	uint32_t desc_curr_tx;
169
170	struct tx_desc_info tx_desc[ECE_MAX_TX_BUFFERS];
171};
172
173
174struct arl_table_entry_t {
175	uint32_t cmd_complete: 1;
176	uint32_t table_end: 1;
177	uint32_t search_match: 1;
178	uint32_t filter:1; /*if set, packet will be dropped */
179	uint32_t vlan_mac:1; /*indicates that this is the gateway mac address*/
180	uint32_t vlan_gid:3; /*vlan id*/
181	uint32_t age_field:3;
182	uint32_t port_map:3;
183	 /*48 bit mac address*/
184	uint8_t mac_addr[6];
185	uint8_t pad[2];
186};
187
188struct mac_list{
189	char mac_addr[6];
190	struct mac_list *next;
191};
192
193#endif
194