swtch-v4.S revision 248361
1129198Scognet/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37139735Simp/*- 38129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 39129198Scognet * Copyright (c) 1994 Brini. 40129198Scognet * All rights reserved. 41129198Scognet * 42129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 43129198Scognet * 44129198Scognet * Redistribution and use in source and binary forms, with or without 45129198Scognet * modification, are permitted provided that the following conditions 46129198Scognet * are met: 47129198Scognet * 1. Redistributions of source code must retain the above copyright 48129198Scognet * notice, this list of conditions and the following disclaimer. 49129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 50129198Scognet * notice, this list of conditions and the following disclaimer in the 51129198Scognet * documentation and/or other materials provided with the distribution. 52129198Scognet * 3. All advertising materials mentioning features or use of this software 53129198Scognet * must display the following acknowledgement: 54129198Scognet * This product includes software developed by Brini. 55129198Scognet * 4. The name of the company nor the name of the author may be used to 56129198Scognet * endorse or promote products derived from this software without specific 57129198Scognet * prior written permission. 58129198Scognet * 59129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69129198Scognet * SUCH DAMAGE. 70129198Scognet * 71129198Scognet * RiscBSD kernel project 72129198Scognet * 73129198Scognet * cpuswitch.S 74129198Scognet * 75129198Scognet * cpu switching functions 76129198Scognet * 77129198Scognet * Created : 15/10/94 78129198Scognet * 79129198Scognet */ 80129198Scognet 81137274Scognet#include "assym.s" 82245477Scognet#include "opt_sched.h" 83137274Scognet 84129198Scognet#include <machine/asm.h> 85129198Scognet#include <machine/asmacros.h> 86129198Scognet#include <machine/armreg.h> 87129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/swtch.S 248361 2013-03-16 02:48:49Z andrew $"); 88129198Scognet 89129198Scognet#define DOMAIN_CLIENT 0x01 90129198Scognet 91239268Sgonzo#ifdef _ARM_ARCH_6 92239268Sgonzo#define GET_PCPU(tmp) \ 93239268Sgonzo mrc p15, 0, tmp, c13, c0, 4; 94239268Sgonzo#else 95239268Sgonzo.Lcurpcpu: 96239268Sgonzo .word _C_LABEL(__pcpu) 97129198Scognet 98239268Sgonzo#define GET_PCPU(tmp) \ 99239268Sgonzo ldr tmp, .Lcurpcpu 100239268Sgonzo#endif 101129198Scognet 102129198Scognet.Lcpufuncs: 103129198Scognet .word _C_LABEL(cpufuncs) 104171780Scognet.Lblocked_lock: 105171780Scognet .word _C_LABEL(blocked_lock) 106239268Sgonzo 107135655ScognetENTRY(cpu_throw) 108135655Scognet mov r5, r1 109129198Scognet 110135655Scognet /* 111239268Sgonzo * r0 = oldtd 112137274Scognet * r5 = newtd 113135655Scognet */ 114129198Scognet 115239268Sgonzo GET_PCPU(r7) 116239268Sgonzo 117239268Sgonzo#ifdef ARM_VFP_SUPPORT 118239268Sgonzo /* 119239268Sgonzo * vfp_discard will clear pcpu->pc_vfpcthread, and modify 120239268Sgonzo * and modify the control as needed. 121239268Sgonzo */ 122239268Sgonzo ldr r4, [r7, #(PC_VFPCTHREAD)] /* this thread using vfp? */ 123239268Sgonzo cmp r0, r4 124239268Sgonzo bne 3f 125239268Sgonzo bl _C_LABEL(vfp_discard) /* yes, shut down vfp */ 126239268Sgonzo3: 127239268Sgonzo#endif /* ARM_VFP_SUPPORT */ 128239268Sgonzo 129137274Scognet ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */ 130239268Sgonzo 131135655Scognet /* Switch to lwp0 context */ 132135655Scognet 133135655Scognet ldr r9, .Lcpufuncs 134239268Sgonzo#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) 135135655Scognet mov lr, pc 136135655Scognet ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] 137239268Sgonzo#endif 138135655Scognet ldr r0, [r7, #(PCB_PL1VEC)] 139135655Scognet ldr r1, [r7, #(PCB_DACR)] 140135655Scognet /* 141135655Scognet * r0 = Pointer to L1 slot for vector_page (or NULL) 142135655Scognet * r1 = lwp0's DACR 143135655Scognet * r5 = lwp0 144135655Scognet * r6 = exit func 145135655Scognet * r7 = lwp0's PCB 146135655Scognet * r9 = cpufuncs 147135655Scognet */ 148135655Scognet 149135655Scognet /* 150135655Scognet * Ensure the vector table is accessible by fixing up lwp0's L1 151135655Scognet */ 152135655Scognet cmp r0, #0 /* No need to fixup vector table? */ 153135655Scognet ldrne r3, [r0] /* But if yes, fetch current value */ 154135655Scognet ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */ 155135655Scognet mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 156135655Scognet cmpne r3, r2 /* Stuffing the same value? */ 157135655Scognet strne r2, [r0] /* Store if not. */ 158135655Scognet 159135655Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 160135655Scognet /* 161135655Scognet * Need to sync the cache to make sure that last store is 162135655Scognet * visible to the MMU. 163135655Scognet */ 164135655Scognet movne r1, #4 165135655Scognet movne lr, pc 166135655Scognet ldrne pc, [r9, #CF_DCACHE_WB_RANGE] 167135655Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 168135655Scognet 169135655Scognet /* 170135655Scognet * Note: We don't do the same optimisation as cpu_switch() with 171135655Scognet * respect to avoiding flushing the TLB if we're switching to 172135655Scognet * the same L1 since this process' VM space may be about to go 173135655Scognet * away, so we don't want *any* turds left in the TLB. 174135655Scognet */ 175135655Scognet 176135655Scognet /* Switch the memory to the new process */ 177135655Scognet ldr r0, [r7, #(PCB_PAGEDIR)] 178135655Scognet mov lr, pc 179135655Scognet ldr pc, [r9, #CF_CONTEXT_SWITCH] 180135655Scognet 181135655Scognet /* Restore all the save registers */ 182172614Scognet#ifndef _ARM_ARCH_5E 183135655Scognet add r1, r7, #PCB_R8 184135655Scognet ldmia r1, {r8-r13} 185135655Scognet#else 186135655Scognet ldr r8, [r7, #(PCB_R8)] 187135655Scognet ldr r9, [r7, #(PCB_R9)] 188135655Scognet ldr r10, [r7, #(PCB_R10)] 189135655Scognet ldr r11, [r7, #(PCB_R11)] 190135655Scognet ldr r12, [r7, #(PCB_R12)] 191135655Scognet ldr r13, [r7, #(PCB_SP)] 192135655Scognet#endif 193135655Scognet 194138751Scognet /* We have a new curthread now so make a note it */ 195239268Sgonzo GET_CURTHREAD_PTR(r6) 196138751Scognet str r5, [r6] 197135655Scognet 198142570Scognet /* Set the new tp */ 199142955Scognet ldr r6, [r5, #(TD_MD + MD_TP)] 200239268Sgonzo#ifdef ARM_TP_ADDRESS 201188540Scognet ldr r4, =ARM_TP_ADDRESS 202188540Scognet str r6, [r4] 203188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_START)] 204188540Scognet str r6, [r4, #4] /* ARM_RAS_START */ 205188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_END)] 206188581Scognet str r6, [r4, #8] /* ARM_RAS_END */ 207239268Sgonzo#else 208239268Sgonzo mcr p15, 0, r6, c13, c0, 3 209239268Sgonzo#endif 210138751Scognet /* Hook in a new pcb */ 211239268Sgonzo GET_PCPU(r6) 212239268Sgonzo str r7, [r6, #PC_CURPCB] 213138751Scognet 214247864Sandrew add sp, sp, #4; 215138856Scognet ldmfd sp!, {r4-r7, pc} 216248361SandrewEND(cpu_throw) 217138751Scognet 218129198ScognetENTRY(cpu_switch) 219129198Scognet stmfd sp!, {r4-r7, lr} 220247864Sandrew sub sp, sp, #4; 221171780Scognet mov r6, r2 /* Save the mutex */ 222129198Scognet 223135655Scognet.Lswitch_resume: 224137274Scognet /* rem: r0 = old lwp */ 225129198Scognet /* rem: interrupts are disabled */ 226129198Scognet 227129198Scognet /* Process is now on a processor. */ 228135655Scognet /* We have a new curthread now so make a note it */ 229239268Sgonzo GET_CURTHREAD_PTR(r7) 230137274Scognet str r1, [r7] 231129198Scognet 232129198Scognet /* Hook in a new pcb */ 233239268Sgonzo GET_PCPU(r7) 234137274Scognet ldr r2, [r1, #TD_PCB] 235239268Sgonzo str r2, [r7, #PC_CURPCB] 236129198Scognet 237137274Scognet /* rem: r1 = new process */ 238129198Scognet /* rem: interrupts are enabled */ 239129198Scognet 240129198Scognet /* Stage two : Save old context */ 241129198Scognet 242171780Scognet /* Get the user structure for the old thread. */ 243137274Scognet ldr r2, [r0, #(TD_PCB)] 244171780Scognet mov r4, r0 /* Save the old thread. */ 245129198Scognet 246171780Scognet /* Save all the registers in the old thread's pcb */ 247172614Scognet#ifndef _ARM_ARCH_5E 248137274Scognet add r7, r2, #(PCB_R8) 249129198Scognet stmia r7, {r8-r13} 250129198Scognet#else 251137274Scognet strd r8, [r2, #(PCB_R8)] 252137274Scognet strd r10, [r2, #(PCB_R10)] 253137274Scognet strd r12, [r2, #(PCB_R12)] 254129198Scognet#endif 255181144Scognet str pc, [r2, #(PCB_PC)] 256236991Simp 257129198Scognet /* 258129198Scognet * NOTE: We can now use r8-r13 until it is time to restore 259129198Scognet * them for the new process. 260129198Scognet */ 261239268Sgonzo#ifdef ARM_TP_ADDRESS 262142570Scognet /* Store the old tp */ 263175982Sraj ldr r3, =ARM_TP_ADDRESS 264188540Scognet ldr r9, [r3] 265142570Scognet str r9, [r0, #(TD_MD + MD_TP)] 266188540Scognet ldr r9, [r3, #4] 267188540Scognet str r9, [r0, #(TD_MD + MD_RAS_START)] 268188540Scognet ldr r9, [r3, #8] 269188540Scognet str r9, [r0, #(TD_MD + MD_RAS_END)] 270129198Scognet 271142570Scognet /* Set the new tp */ 272142570Scognet ldr r9, [r1, #(TD_MD + MD_TP)] 273188540Scognet str r9, [r3] 274188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_START)] 275188540Scognet str r9, [r3, #4] 276188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_END)] 277188540Scognet str r9, [r3, #8] 278239268Sgonzo#else 279239268Sgonzo /* Store the old tp */ 280239268Sgonzo mrc p15, 0, r9, c13, c0, 3 281239268Sgonzo str r9, [r0, #(TD_MD + MD_TP)] 282129198Scognet 283239268Sgonzo /* Set the new tp */ 284239268Sgonzo ldr r9, [r1, #(TD_MD + MD_TP)] 285239268Sgonzo mcr p15, 0, r9, c13, c0, 3 286239268Sgonzo#endif 287239268Sgonzo 288129198Scognet /* Get the user structure for the new process in r9 */ 289137274Scognet ldr r9, [r1, #(TD_PCB)] 290129198Scognet 291138751Scognet mrs r3, cpsr 292129198Scognet /* 293236991Simp * We can do that, since 294138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 295129198Scognet */ 296138751Scognet orr r8, r3, #(PSR_UND32_MODE) 297138751Scognet msr cpsr_c, r8 298129198Scognet 299138751Scognet str sp, [r2, #(PCB_UND_SP)] 300129198Scognet 301129198Scognet msr cpsr_c, r3 /* Restore the old mode */ 302239268Sgonzo /* rem: r2 = old PCB */ 303129198Scognet /* rem: r9 = new PCB */ 304129198Scognet /* rem: interrupts are enabled */ 305129198Scognet 306239268Sgonzo#ifdef ARM_VFP_SUPPORT 307239268Sgonzo /* 308239268Sgonzo * vfp_store will clear pcpu->pc_vfpcthread, save 309239268Sgonzo * registers and state, and modify the control as needed. 310239268Sgonzo * a future exception will bounce the backup settings in the fp unit. 311239268Sgonzo * XXX vfp_store can't change r4 312239268Sgonzo */ 313239268Sgonzo GET_PCPU(r7) 314239268Sgonzo ldr r8, [r7, #(PC_VFPCTHREAD)] 315239268Sgonzo cmp r4, r8 /* old thread used vfp? */ 316239268Sgonzo bne 1f /* no, don't save */ 317239268Sgonzo cmp r1, r4 /* same thread ? */ 318239268Sgonzo beq 1f /* yes, skip vfp store */ 319239268Sgonzo#ifdef SMP 320239268Sgonzo ldr r8, [r7, #(PC_CPU)] /* last used on this cpu? */ 321239268Sgonzo ldr r3, [r2, #(PCB_VFPCPU)] 322239268Sgonzo cmp r8, r3 /* last cpu to use these registers? */ 323239268Sgonzo bne 1f /* no. these values are stale */ 324239268Sgonzo#endif 325239268Sgonzo add r0, r2, #(PCB_VFPSTATE) 326239268Sgonzo bl _C_LABEL(vfp_store) 327239268Sgonzo1: 328239268Sgonzo#endif /* ARM_VFP_SUPPORT */ 329129198Scognet 330239268Sgonzo /* r1 now free! */ 331239268Sgonzo 332129198Scognet /* Third phase : restore saved context */ 333129198Scognet 334239268Sgonzo /* rem: r2 = old PCB */ 335129198Scognet /* rem: r9 = new PCB */ 336129198Scognet /* rem: interrupts are enabled */ 337129198Scognet 338138414Scognet ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */ 339138414Scognet mov r2, #DOMAIN_CLIENT 340138414Scognet cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */ 341138414Scognet beq .Lcs_context_switched /* Yup. Don't flush cache */ 342138414Scognet mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */ 343129198Scognet /* 344129198Scognet * Get the new L1 table pointer into r11. If we're switching to 345129198Scognet * an LWP with the same address space as the outgoing one, we can 346129198Scognet * skip the cache purge and the TTB load. 347129198Scognet * 348129198Scognet * To avoid data dep stalls that would happen anyway, we try 349129198Scognet * and get some useful work done in the mean time. 350129198Scognet */ 351138414Scognet mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */ 352129198Scognet ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */ 353129198Scognet 354129198Scognet 355129198Scognet teq r10, r11 /* Same L1? */ 356137274Scognet cmpeq r0, r5 /* Same DACR? */ 357129198Scognet beq .Lcs_context_switched /* yes! */ 358129198Scognet 359239268Sgonzo#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B) 360129198Scognet /* 361129198Scognet * Definately need to flush the cache. 362129198Scognet */ 363129198Scognet 364129198Scognet ldr r1, .Lcpufuncs 365129198Scognet mov lr, pc 366129198Scognet ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 367239268Sgonzo#endif 368129198Scognet.Lcs_cache_purge_skipped: 369171780Scognet /* rem: r6 = lock */ 370129198Scognet /* rem: r9 = new PCB */ 371129198Scognet /* rem: r10 = old L1 */ 372129198Scognet /* rem: r11 = new L1 */ 373129198Scognet 374129198Scognet mov r2, #0x00000000 375129198Scognet ldr r7, [r9, #(PCB_PL1VEC)] 376129198Scognet 377129198Scognet /* 378129198Scognet * Ensure the vector table is accessible by fixing up the L1 379129198Scognet */ 380129198Scognet cmp r7, #0 /* No need to fixup vector table? */ 381129198Scognet ldrne r2, [r7] /* But if yes, fetch current value */ 382129198Scognet ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ 383137274Scognet mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */ 384129198Scognet cmpne r2, r0 /* Stuffing the same value? */ 385135655Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 386129198Scognet strne r0, [r7] /* Nope, update it */ 387129198Scognet#else 388129198Scognet beq .Lcs_same_vector 389129198Scognet str r0, [r7] /* Otherwise, update it */ 390129198Scognet 391129198Scognet /* 392129198Scognet * Need to sync the cache to make sure that last store is 393129198Scognet * visible to the MMU. 394129198Scognet */ 395129198Scognet ldr r2, .Lcpufuncs 396129198Scognet mov r0, r7 397129198Scognet mov r1, #4 398129198Scognet mov lr, pc 399129198Scognet ldr pc, [r2, #CF_DCACHE_WB_RANGE] 400129198Scognet 401129198Scognet.Lcs_same_vector: 402129198Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 403129198Scognet 404129198Scognet cmp r10, r11 /* Switching to the same L1? */ 405129198Scognet ldr r10, .Lcpufuncs 406129198Scognet beq .Lcs_same_l1 /* Yup. */ 407129198Scognet /* 408129198Scognet * Do a full context switch, including full TLB flush. 409129198Scognet */ 410129198Scognet mov r0, r11 411129198Scognet mov lr, pc 412129198Scognet ldr pc, [r10, #CF_CONTEXT_SWITCH] 413129198Scognet 414129198Scognet b .Lcs_context_switched 415129198Scognet 416129198Scognet /* 417129198Scognet * We're switching to a different process in the same L1. 418129198Scognet * In this situation, we only need to flush the TLB for the 419129198Scognet * vector_page mapping, and even then only if r7 is non-NULL. 420129198Scognet */ 421129198Scognet.Lcs_same_l1: 422129198Scognet cmp r7, #0 423129198Scognet movne r0, #0 /* We *know* vector_page's VA is 0x0 */ 424129198Scognet movne lr, pc 425129198Scognet ldrne pc, [r10, #CF_TLB_FLUSHID_SE] 426138751Scognet /* 427236991Simp * We can do that, since 428138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 429138751Scognet */ 430129198Scognet 431129198Scognet.Lcs_context_switched: 432129198Scognet 433171780Scognet /* Release the old thread */ 434171780Scognet str r6, [r4, #TD_LOCK] 435245477Scognet#if defined(SCHED_ULE) && defined(SMP) 436171780Scognet ldr r6, .Lblocked_lock 437239268Sgonzo GET_CURTHREAD_PTR(r3) 438171780Scognet 439171780Scognet1: 440171780Scognet ldr r4, [r3, #TD_LOCK] 441171780Scognet cmp r4, r6 442171780Scognet beq 1b 443245477Scognet#endif 444171780Scognet 445129198Scognet /* XXXSCW: Safe to re-enable FIQs here */ 446129198Scognet 447129198Scognet /* rem: r9 = new PCB */ 448129198Scognet 449138751Scognet mrs r3, cpsr 450129198Scognet /* 451236991Simp * We can do that, since 452138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 453129198Scognet */ 454138751Scognet orr r2, r3, #(PSR_UND32_MODE) 455138751Scognet msr cpsr_c, r2 456129198Scognet 457129198Scognet ldr sp, [r9, #(PCB_UND_SP)] 458129198Scognet 459129198Scognet msr cpsr_c, r3 /* Restore the old mode */ 460129198Scognet /* Restore all the save registers */ 461172614Scognet#ifndef _ARM_ARCH_5E 462129198Scognet add r7, r9, #PCB_R8 463129198Scognet ldmia r7, {r8-r13} 464129198Scognet sub r7, r7, #PCB_R8 /* restore PCB pointer */ 465129198Scognet#else 466129198Scognet mov r7, r9 467129198Scognet ldr r8, [r7, #(PCB_R8)] 468129198Scognet ldr r9, [r7, #(PCB_R9)] 469129198Scognet ldr r10, [r7, #(PCB_R10)] 470129198Scognet ldr r11, [r7, #(PCB_R11)] 471129198Scognet ldr r12, [r7, #(PCB_R12)] 472129198Scognet ldr r13, [r7, #(PCB_SP)] 473129198Scognet#endif 474129198Scognet 475171780Scognet /* rem: r6 = lock */ 476129198Scognet /* rem: r7 = new pcb */ 477129198Scognet 478129198Scognet#ifdef ARMFPE 479129198Scognet add r0, r7, #(USER_SIZE) & 0x00ff 480236991Simp add r0, r0, #(USER_SIZE) & 0xff00 481129198Scognet bl _C_LABEL(arm_fpe_core_changecontext) 482129198Scognet#endif 483129198Scognet 484129198Scognet /* rem: r5 = new lwp's proc */ 485171780Scognet /* rem: r6 = lock */ 486129198Scognet /* rem: r7 = new PCB */ 487129198Scognet 488129198Scognet.Lswitch_return: 489129198Scognet 490129198Scognet /* 491129198Scognet * Pull the registers that got pushed when either savectx() or 492129198Scognet * cpu_switch() was called and return. 493129198Scognet */ 494247864Sandrew add sp, sp, #4; 495129198Scognet ldmfd sp!, {r4-r7, pc} 496129198Scognet#ifdef DIAGNOSTIC 497129198Scognet.Lswitch_bogons: 498129198Scognet adr r0, .Lswitch_panic_str 499129198Scognet bl _C_LABEL(panic) 500129198Scognet1: nop 501129198Scognet b 1b 502129198Scognet 503129198Scognet.Lswitch_panic_str: 504129198Scognet .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n" 505129198Scognet#endif 506248361SandrewEND(cpu_switch) 507248361Sandrew 508129198ScognetENTRY(savectx) 509150856Scognet stmfd sp!, {r4-r7, lr} 510247864Sandrew sub sp, sp, #4 511150856Scognet /* 512150856Scognet * r0 = pcb 513150856Scognet */ 514150856Scognet /* Store all the registers in the process's pcb */ 515150856Scognet add r2, r0, #(PCB_R8) 516150856Scognet stmia r2, {r8-r13} 517239268Sgonzo#ifdef ARM_VFP_SUPPORT 518239268Sgonzo /* 519239268Sgonzo * vfp_store will clear pcpu->pc_vfpcthread, save 520239268Sgonzo * registers and state, and modify the control as needed. 521239268Sgonzo * a future exception will bounce the backup settings in the fp unit. 522239268Sgonzo */ 523239268Sgonzo GET_PCPU(r7) 524239268Sgonzo ldr r4, [r7, #(PC_VFPCTHREAD)] /* vfp thread */ 525239268Sgonzo ldr r2, [r7, #(PC_CURTHREAD)] /* current thread */ 526239268Sgonzo cmp r4, r2 527239268Sgonzo bne 1f 528239268Sgonzo#ifdef SMP 529239268Sgonzo ldr r2, [r7, #(PC_CPU)] /* last used on this cpu? */ 530239268Sgonzo ldr r3, [r0, #(PCB_VFPCPU)] 531239268Sgonzo cmp r2, r3 532239268Sgonzo bne 1f /* no. these values are stale */ 533239268Sgonzo#endif 534239268Sgonzo add r0, r0, #(PCB_VFPSTATE) 535239268Sgonzo bl _C_LABEL(vfp_store) 536239268Sgonzo1: 537239268Sgonzo#endif /* ARM_VFP_SUPPORT */ 538247864Sandrew add sp, sp, #4; 539150856Scognet ldmfd sp!, {r4-r7, pc} 540248361SandrewEND(savectx) 541150856Scognet 542129198ScognetENTRY(fork_trampoline) 543129198Scognet mov r1, r5 544129198Scognet mov r2, sp 545129198Scognet mov r0, r4 546137976Scognet mov fp, #0 547129198Scognet bl _C_LABEL(fork_exit) 548135655Scognet /* Kill irq"s */ 549135655Scognet mrs r0, cpsr 550157616Scognet orr r0, r0, #(I32_bit|F32_bit) 551135655Scognet msr cpsr_c, r0 552146596Scognet DO_AST 553129198Scognet PULLFRAME 554129198Scognet 555129198Scognet movs pc, lr /* Exit */ 556129198Scognet 557135655ScognetAST_LOCALS 558248361SandrewEND(fork_trampoline) 559248361Sandrew 560