pmap-v4.c revision 146647
1/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2/*- 3 * Copyright 2004 Olivier Houchard. 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/*- 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65/*- 66 * Copyright (c) 1999 The NetBSD Foundation, Inc. 67 * All rights reserved. 68 * 69 * This code is derived from software contributed to The NetBSD Foundation 70 * by Charles M. Hannum. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 3. All advertising materials mentioning features or use of this software 81 * must display the following acknowledgement: 82 * This product includes software developed by the NetBSD 83 * Foundation, Inc. and its contributors. 84 * 4. Neither the name of The NetBSD Foundation nor the names of its 85 * contributors may be used to endorse or promote products derived 86 * from this software without specific prior written permission. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98 * POSSIBILITY OF SUCH DAMAGE. 99 */ 100 101/*- 102 * Copyright (c) 1994-1998 Mark Brinicombe. 103 * Copyright (c) 1994 Brini. 104 * All rights reserved. 105 * 106 * This code is derived from software written for Brini by Mark Brinicombe 107 * 108 * Redistribution and use in source and binary forms, with or without 109 * modification, are permitted provided that the following conditions 110 * are met: 111 * 1. Redistributions of source code must retain the above copyright 112 * notice, this list of conditions and the following disclaimer. 113 * 2. Redistributions in binary form must reproduce the above copyright 114 * notice, this list of conditions and the following disclaimer in the 115 * documentation and/or other materials provided with the distribution. 116 * 3. All advertising materials mentioning features or use of this software 117 * must display the following acknowledgement: 118 * This product includes software developed by Mark Brinicombe. 119 * 4. The name of the author may not be used to endorse or promote products 120 * derived from this software without specific prior written permission. 121 * 122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 131 * 132 * RiscBSD kernel project 133 * 134 * pmap.c 135 * 136 * Machine dependant vm stuff 137 * 138 * Created : 20/09/94 139 */ 140 141/* 142 * Special compilation symbols 143 * PMAP_DEBUG - Build in pmap_debug_level code 144 */ 145/* Include header files */ 146 147#include "opt_vm.h" 148 149#include <sys/cdefs.h> 150__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 146647 2005-05-26 15:01:13Z cognet $"); 151#include <sys/param.h> 152#include <sys/systm.h> 153#include <sys/kernel.h> 154#include <sys/proc.h> 155#include <sys/malloc.h> 156#include <sys/msgbuf.h> 157#include <sys/vmmeter.h> 158#include <sys/mman.h> 159#include <sys/smp.h> 160#include <sys/sx.h> 161#include <sys/sched.h> 162 163#include <vm/vm.h> 164#include <vm/uma.h> 165#include <vm/pmap.h> 166#include <vm/vm_kern.h> 167#include <vm/vm_object.h> 168#include <vm/vm_map.h> 169#include <vm/vm_page.h> 170#include <vm/vm_pageout.h> 171#include <vm/vm_extern.h> 172#include <sys/lock.h> 173#include <sys/mutex.h> 174#include <machine/md_var.h> 175#include <machine/vmparam.h> 176#include <machine/cpu.h> 177#include <machine/cpufunc.h> 178#include <machine/pcb.h> 179 180#ifdef PMAP_DEBUG 181#define PDEBUG(_lev_,_stat_) \ 182 if (pmap_debug_level >= (_lev_)) \ 183 ((_stat_)) 184#define dprintf printf 185 186int pmap_debug_level = 0; 187#define PMAP_INLINE 188#else /* PMAP_DEBUG */ 189#define PDEBUG(_lev_,_stat_) /* Nothing */ 190#define dprintf(x, arg...) 191#define PMAP_INLINE __inline 192#endif /* PMAP_DEBUG */ 193 194extern struct pv_addr systempage; 195/* 196 * Internal function prototypes 197 */ 198static void pmap_free_pv_entry (pv_entry_t); 199static pv_entry_t pmap_get_pv_entry(void); 200 201static void pmap_vac_me_harder(struct vm_page *, pmap_t, 202 vm_offset_t); 203static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, 204 vm_offset_t); 205static void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t); 206static void pmap_alloc_l1(pmap_t); 207static void pmap_free_l1(pmap_t); 208static void pmap_use_l1(pmap_t); 209 210static int pmap_clearbit(struct vm_page *, u_int); 211 212static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 213static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 214static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 215static vm_offset_t kernel_pt_lookup(vm_paddr_t); 216 217static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 218 219vm_offset_t avail_end; /* PA of last available physical page */ 220vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 221vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 222vm_offset_t pmap_curmaxkvaddr; 223 224extern void *end; 225vm_offset_t kernel_vm_end = 0; 226 227struct pmap kernel_pmap_store; 228pmap_t kernel_pmap; 229 230static pt_entry_t *csrc_pte, *cdst_pte; 231static vm_offset_t csrcp, cdstp; 232static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 233/* 234 * These routines are called when the CPU type is identified to set up 235 * the PTE prototypes, cache modes, etc. 236 * 237 * The variables are always here, just in case LKMs need to reference 238 * them (though, they shouldn't). 239 */ 240 241pt_entry_t pte_l1_s_cache_mode; 242pt_entry_t pte_l1_s_cache_mode_pt; 243pt_entry_t pte_l1_s_cache_mask; 244 245pt_entry_t pte_l2_l_cache_mode; 246pt_entry_t pte_l2_l_cache_mode_pt; 247pt_entry_t pte_l2_l_cache_mask; 248 249pt_entry_t pte_l2_s_cache_mode; 250pt_entry_t pte_l2_s_cache_mode_pt; 251pt_entry_t pte_l2_s_cache_mask; 252 253pt_entry_t pte_l2_s_prot_u; 254pt_entry_t pte_l2_s_prot_w; 255pt_entry_t pte_l2_s_prot_mask; 256 257pt_entry_t pte_l1_s_proto; 258pt_entry_t pte_l1_c_proto; 259pt_entry_t pte_l2_s_proto; 260 261void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 262void (*pmap_zero_page_func)(vm_paddr_t, int, int); 263/* 264 * Which pmap is currently 'live' in the cache 265 * 266 * XXXSCW: Fix for SMP ... 267 */ 268union pmap_cache_state *pmap_cache_state; 269 270LIST_HEAD(pmaplist, pmap); 271struct pmaplist allpmaps; 272 273static boolean_t pmap_initialized = FALSE; /* Has pmap_init completed? */ 274 275/* static pt_entry_t *msgbufmap;*/ 276struct msgbuf *msgbufp = 0; 277 278extern void bcopy_page(vm_offset_t, vm_offset_t); 279extern void bzero_page(vm_offset_t); 280 281char *_tmppt; 282 283/* 284 * Metadata for L1 translation tables. 285 */ 286struct l1_ttable { 287 /* Entry on the L1 Table list */ 288 SLIST_ENTRY(l1_ttable) l1_link; 289 290 /* Entry on the L1 Least Recently Used list */ 291 TAILQ_ENTRY(l1_ttable) l1_lru; 292 293 /* Track how many domains are allocated from this L1 */ 294 volatile u_int l1_domain_use_count; 295 296 /* 297 * A free-list of domain numbers for this L1. 298 * We avoid using ffs() and a bitmap to track domains since ffs() 299 * is slow on ARM. 300 */ 301 u_int8_t l1_domain_first; 302 u_int8_t l1_domain_free[PMAP_DOMAINS]; 303 304 /* Physical address of this L1 page table */ 305 vm_paddr_t l1_physaddr; 306 307 /* KVA of this L1 page table */ 308 pd_entry_t *l1_kva; 309}; 310 311/* 312 * Convert a virtual address into its L1 table index. That is, the 313 * index used to locate the L2 descriptor table pointer in an L1 table. 314 * This is basically used to index l1->l1_kva[]. 315 * 316 * Each L2 descriptor table represents 1MB of VA space. 317 */ 318#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 319 320/* 321 * L1 Page Tables are tracked using a Least Recently Used list. 322 * - New L1s are allocated from the HEAD. 323 * - Freed L1s are added to the TAIl. 324 * - Recently accessed L1s (where an 'access' is some change to one of 325 * the userland pmaps which owns this L1) are moved to the TAIL. 326 */ 327static TAILQ_HEAD(, l1_ttable) l1_lru_list; 328/* 329 * A list of all L1 tables 330 */ 331static SLIST_HEAD(, l1_ttable) l1_list; 332static struct mtx l1_lru_lock; 333 334/* 335 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 336 * 337 * This is normally 16MB worth L2 page descriptors for any given pmap. 338 * Reference counts are maintained for L2 descriptors so they can be 339 * freed when empty. 340 */ 341struct l2_dtable { 342 /* The number of L2 page descriptors allocated to this l2_dtable */ 343 u_int l2_occupancy; 344 345 /* List of L2 page descriptors */ 346 struct l2_bucket { 347 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 348 vm_paddr_t l2b_phys; /* Physical address of same */ 349 u_short l2b_l1idx; /* This L2 table's L1 index */ 350 u_short l2b_occupancy; /* How many active descriptors */ 351 } l2_bucket[L2_BUCKET_SIZE]; 352}; 353 354/* pmap_kenter_internal flags */ 355#define KENTER_CACHE 0x1 356#define KENTER_USER 0x2 357 358/* 359 * Given an L1 table index, calculate the corresponding l2_dtable index 360 * and bucket index within the l2_dtable. 361 */ 362#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 363 (L2_SIZE - 1)) 364#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 365 366/* 367 * Given a virtual address, this macro returns the 368 * virtual address required to drop into the next L2 bucket. 369 */ 370#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 371 372/* 373 * L2 allocation. 374 */ 375#define pmap_alloc_l2_dtable() \ 376 (void*)uma_zalloc(l2table_zone, M_NOWAIT) 377#define pmap_free_l2_dtable(l2) \ 378 uma_zfree(l2table_zone, l2) 379 380/* 381 * We try to map the page tables write-through, if possible. However, not 382 * all CPUs have a write-through cache mode, so on those we have to sync 383 * the cache when we frob page tables. 384 * 385 * We try to evaluate this at compile time, if possible. However, it's 386 * not always possible to do that, hence this run-time var. 387 */ 388int pmap_needs_pte_sync; 389 390/* 391 * Macro to determine if a mapping might be resident in the 392 * instruction cache and/or TLB 393 */ 394#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 395 396/* 397 * Macro to determine if a mapping might be resident in the 398 * data cache and/or TLB 399 */ 400#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 401 402/* 403 * Data for the pv entry allocation mechanism 404 */ 405#define MINPV 2048 406 407#ifndef PMAP_SHPGPERPROC 408#define PMAP_SHPGPERPROC 200 409#endif 410 411#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 412 curproc->p_vmspace->vm_map.pmap == (pm)) 413static uma_zone_t pvzone; 414static uma_zone_t l2zone; 415static uma_zone_t l2table_zone; 416static vm_offset_t pmap_kernel_l2dtable_kva; 417static vm_offset_t pmap_kernel_l2ptp_kva; 418static vm_paddr_t pmap_kernel_l2ptp_phys; 419static struct vm_object pvzone_obj; 420static struct vm_object l2zone_obj; 421static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 422int pmap_pagedaemon_waken = 0; 423 424void pmap_deactivate(struct thread *); 425 426void 427pmap_deactivate(struct thread *td) 428{ 429} 430/* 431 * This list exists for the benefit of pmap_map_chunk(). It keeps track 432 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 433 * find them as necessary. 434 * 435 * Note that the data on this list MUST remain valid after initarm() returns, 436 * as pmap_bootstrap() uses it to contruct L2 table metadata. 437 */ 438SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 439 440static void 441pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 442{ 443 int i; 444 445 l1->l1_kva = l1pt; 446 l1->l1_domain_use_count = 0; 447 l1->l1_domain_first = 0; 448 449 for (i = 0; i < PMAP_DOMAINS; i++) 450 l1->l1_domain_free[i] = i + 1; 451 452 /* 453 * Copy the kernel's L1 entries to each new L1. 454 */ 455 if (pmap_initialized) 456 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 457 458 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 459 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 460 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 461 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 462} 463 464static vm_offset_t 465kernel_pt_lookup(vm_paddr_t pa) 466{ 467 struct pv_addr *pv; 468 469 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 470#ifndef ARM32_NEW_VM_LAYOUT 471 if (pv->pv_pa == (pa & ~PAGE_MASK)) { 472 return (pv->pv_va | (pa & PAGE_MASK)); 473 } 474#else 475 if (pv->pv_pa == pa) 476 return (pv->pv_va); 477#endif 478 } 479 return (0); 480} 481 482#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 483void 484pmap_pte_init_generic(void) 485{ 486 487 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 488 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 489 490 pte_l2_l_cache_mode = L2_B|L2_C; 491 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 492 493 pte_l2_s_cache_mode = L2_B|L2_C; 494 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 495 496 /* 497 * If we have a write-through cache, set B and C. If 498 * we have a write-back cache, then we assume setting 499 * only C will make those pages write-through. 500 */ 501 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 502 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 503 pte_l2_l_cache_mode_pt = L2_B|L2_C; 504 pte_l2_s_cache_mode_pt = L2_B|L2_C; 505 } else { 506 pte_l1_s_cache_mode_pt = L1_S_C; 507 pte_l2_l_cache_mode_pt = L2_C; 508 pte_l2_s_cache_mode_pt = L2_C; 509 } 510 511 pte_l2_s_prot_u = L2_S_PROT_U_generic; 512 pte_l2_s_prot_w = L2_S_PROT_W_generic; 513 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 514 515 pte_l1_s_proto = L1_S_PROTO_generic; 516 pte_l1_c_proto = L1_C_PROTO_generic; 517 pte_l2_s_proto = L2_S_PROTO_generic; 518 519 pmap_copy_page_func = pmap_copy_page_generic; 520 pmap_zero_page_func = pmap_zero_page_generic; 521} 522 523#if defined(CPU_ARM8) 524void 525pmap_pte_init_arm8(void) 526{ 527 528 /* 529 * ARM8 is compatible with generic, but we need to use 530 * the page tables uncached. 531 */ 532 pmap_pte_init_generic(); 533 534 pte_l1_s_cache_mode_pt = 0; 535 pte_l2_l_cache_mode_pt = 0; 536 pte_l2_s_cache_mode_pt = 0; 537} 538#endif /* CPU_ARM8 */ 539 540#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 541void 542pmap_pte_init_arm9(void) 543{ 544 545 /* 546 * ARM9 is compatible with generic, but we want to use 547 * write-through caching for now. 548 */ 549 pmap_pte_init_generic(); 550 551 pte_l1_s_cache_mode = L1_S_C; 552 pte_l2_l_cache_mode = L2_C; 553 pte_l2_s_cache_mode = L2_C; 554 555 pte_l1_s_cache_mode_pt = L1_S_C; 556 pte_l2_l_cache_mode_pt = L2_C; 557 pte_l2_s_cache_mode_pt = L2_C; 558} 559#endif /* CPU_ARM9 */ 560#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 561 562#if defined(CPU_ARM10) 563void 564pmap_pte_init_arm10(void) 565{ 566 567 /* 568 * ARM10 is compatible with generic, but we want to use 569 * write-through caching for now. 570 */ 571 pmap_pte_init_generic(); 572 573 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 574 pte_l2_l_cache_mode = L2_B | L2_C; 575 pte_l2_s_cache_mode = L2_B | L2_C; 576 577 pte_l1_s_cache_mode_pt = L1_S_C; 578 pte_l2_l_cache_mode_pt = L2_C; 579 pte_l2_s_cache_mode_pt = L2_C; 580 581} 582#endif /* CPU_ARM10 */ 583 584#if ARM_MMU_SA1 == 1 585void 586pmap_pte_init_sa1(void) 587{ 588 589 /* 590 * The StrongARM SA-1 cache does not have a write-through 591 * mode. So, do the generic initialization, then reset 592 * the page table cache mode to B=1,C=1, and note that 593 * the PTEs need to be sync'd. 594 */ 595 pmap_pte_init_generic(); 596 597 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 598 pte_l2_l_cache_mode_pt = L2_B|L2_C; 599 pte_l2_s_cache_mode_pt = L2_B|L2_C; 600 601 pmap_needs_pte_sync = 1; 602} 603#endif /* ARM_MMU_SA1 == 1*/ 604 605#if ARM_MMU_XSCALE == 1 606#if (ARM_NMMUS > 1) 607static u_int xscale_use_minidata; 608#endif 609 610void 611pmap_pte_init_xscale(void) 612{ 613 uint32_t auxctl; 614 int write_through = 0; 615 616 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 617 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 618 619 pte_l2_l_cache_mode = L2_B|L2_C; 620 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 621 622 pte_l2_s_cache_mode = L2_B|L2_C; 623 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 624 625 pte_l1_s_cache_mode_pt = L1_S_C; 626 pte_l2_l_cache_mode_pt = L2_C; 627 pte_l2_s_cache_mode_pt = L2_C; 628#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 629 /* 630 * The XScale core has an enhanced mode where writes that 631 * miss the cache cause a cache line to be allocated. This 632 * is significantly faster than the traditional, write-through 633 * behavior of this case. 634 */ 635 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 636 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 637 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 638#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 639#ifdef XSCALE_CACHE_WRITE_THROUGH 640 /* 641 * Some versions of the XScale core have various bugs in 642 * their cache units, the work-around for which is to run 643 * the cache in write-through mode. Unfortunately, this 644 * has a major (negative) impact on performance. So, we 645 * go ahead and run fast-and-loose, in the hopes that we 646 * don't line up the planets in a way that will trip the 647 * bugs. 648 * 649 * However, we give you the option to be slow-but-correct. 650 */ 651 write_through = 1; 652#elif defined(XSCALE_CACHE_WRITE_BACK) 653 /* force write back cache mode */ 654 write_through = 0; 655#elif defined(CPU_XSCALE_PXA2X0) 656 /* 657 * Intel PXA2[15]0 processors are known to have a bug in 658 * write-back cache on revision 4 and earlier (stepping 659 * A[01] and B[012]). Fixed for C0 and later. 660 */ 661 { 662 uint32_t id, type; 663 664 id = cpufunc_id(); 665 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 666 667 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 668 if ((id & CPU_ID_REVISION_MASK) < 5) { 669 /* write through for stepping A0-1 and B0-2 */ 670 write_through = 1; 671 } 672 } 673 } 674#endif /* XSCALE_CACHE_WRITE_THROUGH */ 675 676 if (write_through) { 677 pte_l1_s_cache_mode = L1_S_C; 678 pte_l2_l_cache_mode = L2_C; 679 pte_l2_s_cache_mode = L2_C; 680 } 681 682#if (ARM_NMMUS > 1) 683 xscale_use_minidata = 1; 684#endif 685 686 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 687 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 688 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 689 690 pte_l1_s_proto = L1_S_PROTO_xscale; 691 pte_l1_c_proto = L1_C_PROTO_xscale; 692 pte_l2_s_proto = L2_S_PROTO_xscale; 693 694 pmap_copy_page_func = pmap_copy_page_xscale; 695 pmap_zero_page_func = pmap_zero_page_xscale; 696 697 /* 698 * Disable ECC protection of page table access, for now. 699 */ 700 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 701 auxctl &= ~XSCALE_AUXCTL_P; 702 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 703} 704 705/* 706 * xscale_setup_minidata: 707 * 708 * Set up the mini-data cache clean area. We require the 709 * caller to allocate the right amount of physically and 710 * virtually contiguous space. 711 */ 712extern vm_offset_t xscale_minidata_clean_addr; 713extern vm_size_t xscale_minidata_clean_size; /* already initialized */ 714void 715xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 716{ 717 pd_entry_t *pde = (pd_entry_t *) l1pt; 718 pt_entry_t *pte; 719 vm_size_t size; 720 uint32_t auxctl; 721 722 xscale_minidata_clean_addr = va; 723 724 /* Round it to page size. */ 725 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 726 727 for (; size != 0; 728 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 729#ifndef ARM32_NEW_VM_LAYOUT 730 pte = (pt_entry_t *) 731 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 732#else 733 pte = (pt_entry_t *) kernel_pt_lookup( 734 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 735#endif 736 if (pte == NULL) 737 panic("xscale_setup_minidata: can't find L2 table for " 738 "VA 0x%08x", (u_int32_t) va); 739#ifndef ARM32_NEW_VM_LAYOUT 740 pte[(va >> PAGE_SHIFT) & 0x3ff] = 741#else 742 pte[l2pte_index(va)] = 743#endif 744 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 745 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 746 } 747 748 /* 749 * Configure the mini-data cache for write-back with 750 * read/write-allocate. 751 * 752 * NOTE: In order to reconfigure the mini-data cache, we must 753 * make sure it contains no valid data! In order to do that, 754 * we must issue a global data cache invalidate command! 755 * 756 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 757 * THIS IS VERY IMPORTANT! 758 */ 759 760 /* Invalidate data and mini-data. */ 761 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 762 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 763 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 764 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 765} 766#endif 767 768/* 769 * Allocate an L1 translation table for the specified pmap. 770 * This is called at pmap creation time. 771 */ 772static void 773pmap_alloc_l1(pmap_t pm) 774{ 775 struct l1_ttable *l1; 776 u_int8_t domain; 777 778 /* 779 * Remove the L1 at the head of the LRU list 780 */ 781 mtx_lock(&l1_lru_lock); 782 l1 = TAILQ_FIRST(&l1_lru_list); 783 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 784 785 /* 786 * Pick the first available domain number, and update 787 * the link to the next number. 788 */ 789 domain = l1->l1_domain_first; 790 l1->l1_domain_first = l1->l1_domain_free[domain]; 791 792 /* 793 * If there are still free domain numbers in this L1, 794 * put it back on the TAIL of the LRU list. 795 */ 796 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 797 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 798 799 mtx_unlock(&l1_lru_lock); 800 801 /* 802 * Fix up the relevant bits in the pmap structure 803 */ 804 pm->pm_l1 = l1; 805 pm->pm_domain = domain; 806} 807 808/* 809 * Free an L1 translation table. 810 * This is called at pmap destruction time. 811 */ 812static void 813pmap_free_l1(pmap_t pm) 814{ 815 struct l1_ttable *l1 = pm->pm_l1; 816 817 mtx_lock(&l1_lru_lock); 818 819 /* 820 * If this L1 is currently on the LRU list, remove it. 821 */ 822 if (l1->l1_domain_use_count < PMAP_DOMAINS) 823 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 824 825 /* 826 * Free up the domain number which was allocated to the pmap 827 */ 828 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 829 l1->l1_domain_first = pm->pm_domain; 830 l1->l1_domain_use_count--; 831 832 /* 833 * The L1 now must have at least 1 free domain, so add 834 * it back to the LRU list. If the use count is zero, 835 * put it at the head of the list, otherwise it goes 836 * to the tail. 837 */ 838 if (l1->l1_domain_use_count == 0) { 839 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 840 } else 841 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 842 843 mtx_unlock(&l1_lru_lock); 844} 845 846static PMAP_INLINE void 847pmap_use_l1(pmap_t pm) 848{ 849 struct l1_ttable *l1; 850 851 /* 852 * Do nothing if we're in interrupt context. 853 * Access to an L1 by the kernel pmap must not affect 854 * the LRU list. 855 */ 856 if (pm == pmap_kernel()) 857 return; 858 859 l1 = pm->pm_l1; 860 861 /* 862 * If the L1 is not currently on the LRU list, just return 863 */ 864 if (l1->l1_domain_use_count == PMAP_DOMAINS) 865 return; 866 867 mtx_lock(&l1_lru_lock); 868 869 /* 870 * Check the use count again, now that we've acquired the lock 871 */ 872 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 873 mtx_unlock(&l1_lru_lock); 874 return; 875 } 876 877 /* 878 * Move the L1 to the back of the LRU list 879 */ 880 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 881 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 882 883 mtx_unlock(&l1_lru_lock); 884} 885 886 887/* 888 * Returns a pointer to the L2 bucket associated with the specified pmap 889 * and VA, or NULL if no L2 bucket exists for the address. 890 */ 891static PMAP_INLINE struct l2_bucket * 892pmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 893{ 894 struct l2_dtable *l2; 895 struct l2_bucket *l2b; 896 u_short l1idx; 897 898 l1idx = L1_IDX(va); 899 900 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 901 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 902 return (NULL); 903 904 return (l2b); 905} 906 907/* 908 * Returns a pointer to the L2 bucket associated with the specified pmap 909 * and VA. 910 * 911 * If no L2 bucket exists, perform the necessary allocations to put an L2 912 * bucket/page table in place. 913 * 914 * Note that if a new L2 bucket/page was allocated, the caller *must* 915 * increment the bucket occupancy counter appropriately *before* 916 * releasing the pmap's lock to ensure no other thread or cpu deallocates 917 * the bucket/page in the meantime. 918 */ 919static struct l2_bucket * 920pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 921{ 922 struct l2_dtable *l2; 923 struct l2_bucket *l2b; 924 u_short l1idx; 925 926 l1idx = L1_IDX(va); 927 928 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 929 /* 930 * No mapping at this address, as there is 931 * no entry in the L1 table. 932 * Need to allocate a new l2_dtable. 933 */ 934 if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 935 return (NULL); 936 } 937 bzero(l2, sizeof(*l2)); 938 /* 939 * Link it into the parent pmap 940 */ 941 pm->pm_l2[L2_IDX(l1idx)] = l2; 942 } 943 944 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 945 946 /* 947 * Fetch pointer to the L2 page table associated with the address. 948 */ 949 if (l2b->l2b_kva == NULL) { 950 pt_entry_t *ptep; 951 952 /* 953 * No L2 page table has been allocated. Chances are, this 954 * is because we just allocated the l2_dtable, above. 955 */ 956 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT); 957 l2b->l2b_phys = vtophys(ptep); 958 if (ptep == NULL) { 959 /* 960 * Oops, no more L2 page tables available at this 961 * time. We may need to deallocate the l2_dtable 962 * if we allocated a new one above. 963 */ 964 if (l2->l2_occupancy == 0) { 965 pm->pm_l2[L2_IDX(l1idx)] = NULL; 966 pmap_free_l2_dtable(l2); 967 } 968 return (NULL); 969 } 970 971 l2->l2_occupancy++; 972 l2b->l2b_kva = ptep; 973 l2b->l2b_l1idx = l1idx; 974 } 975 976 return (l2b); 977} 978 979static PMAP_INLINE void 980#ifndef PMAP_INCLUDE_PTE_SYNC 981pmap_free_l2_ptp(pt_entry_t *l2) 982#else 983pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 984#endif 985{ 986#ifdef PMAP_INCLUDE_PTE_SYNC 987 /* 988 * Note: With a write-back cache, we may need to sync this 989 * L2 table before re-using it. 990 * This is because it may have belonged to a non-current 991 * pmap, in which case the cache syncs would have been 992 * skipped when the pages were being unmapped. If the 993 * L2 table were then to be immediately re-allocated to 994 * the *current* pmap, it may well contain stale mappings 995 * which have not yet been cleared by a cache write-back 996 * and so would still be visible to the mmu. 997 */ 998 if (need_sync) 999 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1000#endif 1001 uma_zfree(l2zone, l2); 1002} 1003/* 1004 * One or more mappings in the specified L2 descriptor table have just been 1005 * invalidated. 1006 * 1007 * Garbage collect the metadata and descriptor table itself if necessary. 1008 * 1009 * The pmap lock must be acquired when this is called (not necessary 1010 * for the kernel pmap). 1011 */ 1012static void 1013pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1014{ 1015 struct l2_dtable *l2; 1016 pd_entry_t *pl1pd, l1pd; 1017 pt_entry_t *ptep; 1018 u_short l1idx; 1019 1020 1021 /* 1022 * Update the bucket's reference count according to how many 1023 * PTEs the caller has just invalidated. 1024 */ 1025 l2b->l2b_occupancy -= count; 1026 1027 /* 1028 * Note: 1029 * 1030 * Level 2 page tables allocated to the kernel pmap are never freed 1031 * as that would require checking all Level 1 page tables and 1032 * removing any references to the Level 2 page table. See also the 1033 * comment elsewhere about never freeing bootstrap L2 descriptors. 1034 * 1035 * We make do with just invalidating the mapping in the L2 table. 1036 * 1037 * This isn't really a big deal in practice and, in fact, leads 1038 * to a performance win over time as we don't need to continually 1039 * alloc/free. 1040 */ 1041 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1042 return; 1043 1044 /* 1045 * There are no more valid mappings in this level 2 page table. 1046 * Go ahead and NULL-out the pointer in the bucket, then 1047 * free the page table. 1048 */ 1049 l1idx = l2b->l2b_l1idx; 1050 ptep = l2b->l2b_kva; 1051 l2b->l2b_kva = NULL; 1052 1053 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1054 1055 /* 1056 * If the L1 slot matches the pmap's domain 1057 * number, then invalidate it. 1058 */ 1059 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1060 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1061 *pl1pd = 0; 1062 PTE_SYNC(pl1pd); 1063 } 1064 1065 /* 1066 * Release the L2 descriptor table back to the pool cache. 1067 */ 1068#ifndef PMAP_INCLUDE_PTE_SYNC 1069 pmap_free_l2_ptp(ptep); 1070#else 1071 pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1072#endif 1073 1074 /* 1075 * Update the reference count in the associated l2_dtable 1076 */ 1077 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1078 if (--l2->l2_occupancy > 0) 1079 return; 1080 1081 /* 1082 * There are no more valid mappings in any of the Level 1 1083 * slots managed by this l2_dtable. Go ahead and NULL-out 1084 * the pointer in the parent pmap and free the l2_dtable. 1085 */ 1086 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1087 pmap_free_l2_dtable(l2); 1088} 1089 1090/* 1091 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1092 * structures. 1093 */ 1094static int 1095pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1096{ 1097#ifndef PMAP_INCLUDE_PTE_SYNC 1098 struct l2_bucket *l2b; 1099 pt_entry_t *ptep, pte; 1100 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1101 1102 /* 1103 * The mappings for these page tables were initially made using 1104 * pmap_kenter() by the pool subsystem. Therefore, the cache- 1105 * mode will not be right for page table mappings. To avoid 1106 * polluting the pmap_kenter() code with a special case for 1107 * page tables, we simply fix up the cache-mode here if it's not 1108 * correct. 1109 */ 1110 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1111 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1112 pte = *ptep; 1113 1114 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1115 /* 1116 * Page tables must have the cache-mode set to Write-Thru. 1117 */ 1118 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1119 PTE_SYNC(ptep); 1120 cpu_tlb_flushD_SE(va); 1121 cpu_cpwait(); 1122 } 1123 1124#endif 1125 memset(mem, 0, L2_TABLE_SIZE_REAL); 1126 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1127 return (0); 1128} 1129 1130/* 1131 * A bunch of routines to conditionally flush the caches/TLB depending 1132 * on whether the specified pmap actually needs to be flushed at any 1133 * given time. 1134 */ 1135static PMAP_INLINE void 1136pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1137{ 1138 1139 if (pmap_is_current(pm)) 1140 cpu_tlb_flushID_SE(va); 1141} 1142 1143static PMAP_INLINE void 1144pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1145{ 1146 1147 if (pmap_is_current(pm)) 1148 cpu_tlb_flushD_SE(va); 1149} 1150 1151static PMAP_INLINE void 1152pmap_tlb_flushID(pmap_t pm) 1153{ 1154 1155 if (pmap_is_current(pm)) 1156 cpu_tlb_flushID(); 1157} 1158static PMAP_INLINE void 1159pmap_tlb_flushD(pmap_t pm) 1160{ 1161 1162 if (pmap_is_current(pm)) 1163 cpu_tlb_flushD(); 1164} 1165 1166static PMAP_INLINE void 1167pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1168{ 1169 1170 if (pmap_is_current(pm)) 1171 cpu_idcache_wbinv_range(va, len); 1172} 1173 1174static PMAP_INLINE void 1175pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, 1176 boolean_t do_inv, boolean_t rd_only) 1177{ 1178 1179 if (pmap_is_current(pm)) { 1180 if (do_inv) { 1181 if (rd_only) 1182 cpu_dcache_inv_range(va, len); 1183 else 1184 cpu_dcache_wbinv_range(va, len); 1185 } else 1186 if (!rd_only) 1187 cpu_dcache_wb_range(va, len); 1188 } 1189} 1190 1191static PMAP_INLINE void 1192pmap_idcache_wbinv_all(pmap_t pm) 1193{ 1194 1195 if (pmap_is_current(pm)) 1196 cpu_idcache_wbinv_all(); 1197} 1198 1199static PMAP_INLINE void 1200pmap_dcache_wbinv_all(pmap_t pm) 1201{ 1202 1203 if (pmap_is_current(pm)) 1204 cpu_dcache_wbinv_all(); 1205} 1206 1207/* 1208 * this routine defines the region(s) of memory that should 1209 * not be tested for the modified bit. 1210 */ 1211static PMAP_INLINE int 1212pmap_track_modified(vm_offset_t va) 1213{ 1214 if ((va < kmi.clean_sva) || (va >= kmi.clean_eva)) 1215 return 1; 1216 else 1217 return 0; 1218} 1219/* 1220 * PTE_SYNC_CURRENT: 1221 * 1222 * Make sure the pte is written out to RAM. 1223 * We need to do this for one of two cases: 1224 * - We're dealing with the kernel pmap 1225 * - There is no pmap active in the cache/tlb. 1226 * - The specified pmap is 'active' in the cache/tlb. 1227 */ 1228#ifdef PMAP_INCLUDE_PTE_SYNC 1229#define PTE_SYNC_CURRENT(pm, ptep) \ 1230do { \ 1231 if (PMAP_NEEDS_PTE_SYNC && \ 1232 pmap_is_current(pm)) \ 1233 PTE_SYNC(ptep); \ 1234} while (/*CONSTCOND*/0) 1235#else 1236#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1237#endif 1238 1239/* 1240 * Since we have a virtually indexed cache, we may need to inhibit caching if 1241 * there is more than one mapping and at least one of them is writable. 1242 * Since we purge the cache on every context switch, we only need to check for 1243 * other mappings within the same pmap, or kernel_pmap. 1244 * This function is also called when a page is unmapped, to possibly reenable 1245 * caching on any remaining mappings. 1246 * 1247 * The code implements the following logic, where: 1248 * 1249 * KW = # of kernel read/write pages 1250 * KR = # of kernel read only pages 1251 * UW = # of user read/write pages 1252 * UR = # of user read only pages 1253 * 1254 * KC = kernel mapping is cacheable 1255 * UC = user mapping is cacheable 1256 * 1257 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1258 * +--------------------------------------------- 1259 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1260 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1261 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1262 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1263 */ 1264 1265static const int pmap_vac_flags[4][4] = { 1266 {-1, 0, 0, PVF_KNC}, 1267 {0, 0, PVF_NC, PVF_NC}, 1268 {0, PVF_NC, PVF_NC, PVF_NC}, 1269 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1270}; 1271 1272static PMAP_INLINE int 1273pmap_get_vac_flags(const struct vm_page *pg) 1274{ 1275 int kidx, uidx; 1276 1277 kidx = 0; 1278 if (pg->md.kro_mappings || pg->md.krw_mappings > 1) 1279 kidx |= 1; 1280 if (pg->md.krw_mappings) 1281 kidx |= 2; 1282 1283 uidx = 0; 1284 if (pg->md.uro_mappings || pg->md.urw_mappings > 1) 1285 uidx |= 1; 1286 if (pg->md.urw_mappings) 1287 uidx |= 2; 1288 1289 return (pmap_vac_flags[uidx][kidx]); 1290} 1291 1292static __inline void 1293pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1294{ 1295 int nattr; 1296 1297 nattr = pmap_get_vac_flags(pg); 1298 1299 if (nattr < 0) { 1300 pg->md.pvh_attrs &= ~PVF_NC; 1301 return; 1302 } 1303 1304 if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) { 1305 return; 1306 } 1307 1308 if (pm == pmap_kernel()) 1309 pmap_vac_me_kpmap(pg, pm, va); 1310 else 1311 pmap_vac_me_user(pg, pm, va); 1312 1313 pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr; 1314} 1315 1316static void 1317pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1318{ 1319 u_int u_cacheable, u_entries; 1320 struct pv_entry *pv; 1321 pmap_t last_pmap = pm; 1322 1323 /* 1324 * Pass one, see if there are both kernel and user pmaps for 1325 * this page. Calculate whether there are user-writable or 1326 * kernel-writable pages. 1327 */ 1328 u_cacheable = 0; 1329 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1330 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1331 u_cacheable++; 1332 } 1333 1334 u_entries = pg->md.urw_mappings + pg->md.uro_mappings; 1335 1336 /* 1337 * We know we have just been updating a kernel entry, so if 1338 * all user pages are already cacheable, then there is nothing 1339 * further to do. 1340 */ 1341 if (pg->md.k_mappings == 0 && u_cacheable == u_entries) 1342 return; 1343 1344 if (u_entries) { 1345 /* 1346 * Scan over the list again, for each entry, if it 1347 * might not be set correctly, call pmap_vac_me_user 1348 * to recalculate the settings. 1349 */ 1350 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1351 /* 1352 * We know kernel mappings will get set 1353 * correctly in other calls. We also know 1354 * that if the pmap is the same as last_pmap 1355 * then we've just handled this entry. 1356 */ 1357 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1358 continue; 1359 1360 /* 1361 * If there are kernel entries and this page 1362 * is writable but non-cacheable, then we can 1363 * skip this entry also. 1364 */ 1365 if (pg->md.k_mappings && 1366 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1367 (PVF_NC | PVF_WRITE)) 1368 continue; 1369 1370 /* 1371 * Similarly if there are no kernel-writable 1372 * entries and the page is already 1373 * read-only/cacheable. 1374 */ 1375 if (pg->md.krw_mappings == 0 && 1376 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1377 continue; 1378 1379 /* 1380 * For some of the remaining cases, we know 1381 * that we must recalculate, but for others we 1382 * can't tell if they are correct or not, so 1383 * we recalculate anyway. 1384 */ 1385 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1386 } 1387 1388 if (pg->md.k_mappings == 0) 1389 return; 1390 } 1391 1392 pmap_vac_me_user(pg, pm, va); 1393} 1394 1395static void 1396pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1397{ 1398 pmap_t kpmap = pmap_kernel(); 1399 struct pv_entry *pv, *npv; 1400 struct l2_bucket *l2b; 1401 pt_entry_t *ptep, pte; 1402 u_int entries = 0; 1403 u_int writable = 0; 1404 u_int cacheable_entries = 0; 1405 u_int kern_cacheable = 0; 1406 u_int other_writable = 0; 1407 1408 /* 1409 * Count mappings and writable mappings in this pmap. 1410 * Include kernel mappings as part of our own. 1411 * Keep a pointer to the first one. 1412 */ 1413 npv = TAILQ_FIRST(&pg->md.pv_list); 1414 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1415 /* Count mappings in the same pmap */ 1416 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1417 if (entries++ == 0) 1418 npv = pv; 1419 1420 /* Cacheable mappings */ 1421 if ((pv->pv_flags & PVF_NC) == 0) { 1422 cacheable_entries++; 1423 if (kpmap == pv->pv_pmap) 1424 kern_cacheable++; 1425 } 1426 1427 /* Writable mappings */ 1428 if (pv->pv_flags & PVF_WRITE) 1429 ++writable; 1430 } else 1431 if (pv->pv_flags & PVF_WRITE) 1432 other_writable = 1; 1433 } 1434 1435 /* 1436 * Enable or disable caching as necessary. 1437 * Note: the first entry might be part of the kernel pmap, 1438 * so we can't assume this is indicative of the state of the 1439 * other (maybe non-kpmap) entries. 1440 */ 1441 if ((entries > 1 && writable) || 1442 (entries > 0 && pm == kpmap && other_writable)) { 1443 if (cacheable_entries == 0) 1444 return; 1445 1446 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1447 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1448 (pv->pv_flags & PVF_NC)) 1449 continue; 1450 1451 pv->pv_flags |= PVF_NC; 1452 1453 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1454 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1455 pte = *ptep & ~L2_S_CACHE_MASK; 1456 1457 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1458 l2pte_valid(pte)) { 1459 if (PV_BEEN_EXECD(pv->pv_flags)) { 1460 pmap_idcache_wbinv_range(pv->pv_pmap, 1461 pv->pv_va, PAGE_SIZE); 1462 pmap_tlb_flushID_SE(pv->pv_pmap, 1463 pv->pv_va); 1464 } else 1465 if (PV_BEEN_REFD(pv->pv_flags)) { 1466 pmap_dcache_wb_range(pv->pv_pmap, 1467 pv->pv_va, PAGE_SIZE, TRUE, 1468 (pv->pv_flags & PVF_WRITE) == 0); 1469 pmap_tlb_flushD_SE(pv->pv_pmap, 1470 pv->pv_va); 1471 } 1472 } 1473 1474 *ptep = pte; 1475 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1476 } 1477 cpu_cpwait(); 1478 } else 1479 if (entries > cacheable_entries) { 1480 /* 1481 * Turn cacheing back on for some pages. If it is a kernel 1482 * page, only do so if there are no other writable pages. 1483 */ 1484 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1485 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1486 (kpmap != pv->pv_pmap || other_writable))) 1487 continue; 1488 1489 pv->pv_flags &= ~PVF_NC; 1490 1491 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1492 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1493 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1494 1495 if (l2pte_valid(pte)) { 1496 if (PV_BEEN_EXECD(pv->pv_flags)) { 1497 pmap_tlb_flushID_SE(pv->pv_pmap, 1498 pv->pv_va); 1499 } else 1500 if (PV_BEEN_REFD(pv->pv_flags)) { 1501 pmap_tlb_flushD_SE(pv->pv_pmap, 1502 pv->pv_va); 1503 } 1504 } 1505 1506 *ptep = pte; 1507 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1508 } 1509 } 1510} 1511 1512/* 1513 * Modify pte bits for all ptes corresponding to the given physical address. 1514 * We use `maskbits' rather than `clearbits' because we're always passing 1515 * constants and the latter would require an extra inversion at run-time. 1516 */ 1517static int 1518pmap_clearbit(struct vm_page *pg, u_int maskbits) 1519{ 1520 struct l2_bucket *l2b; 1521 struct pv_entry *pv; 1522 pt_entry_t *ptep, npte, opte; 1523 pmap_t pm; 1524 vm_offset_t va; 1525 u_int oflags; 1526 int count = 0; 1527#if 0 1528 PMAP_HEAD_TO_MAP_LOCK(); 1529 simple_lock(&pg->mdpage.pvh_slock); 1530#endif 1531 1532 /* 1533 * Clear saved attributes (modify, reference) 1534 */ 1535 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1536 1537 if (TAILQ_EMPTY(&pg->md.pv_list)) { 1538#if 0 1539 simple_unlock(&pg->mdpage.pvh_slock); 1540 PMAP_HEAD_TO_MAP_UNLOCK(); 1541#endif 1542 return (0); 1543 } 1544 1545 /* 1546 * Loop over all current mappings setting/clearing as appropos 1547 */ 1548 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1549 va = pv->pv_va; 1550 pm = pv->pv_pmap; 1551 oflags = pv->pv_flags; 1552 pv->pv_flags &= ~maskbits; 1553 1554#if 0 1555 pmap_acquire_pmap_lock(pm); 1556#endif 1557 1558 l2b = pmap_get_l2_bucket(pm, va); 1559 1560 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1561 npte = opte = *ptep; 1562 1563 if (maskbits & (PVF_WRITE|PVF_MOD) && 1564 !pmap_track_modified(pv->pv_va)) { 1565 if ((pv->pv_flags & PVF_NC)) { 1566 /* 1567 * Entry is not cacheable: 1568 * 1569 * Don't turn caching on again if this is a 1570 * modified emulation. This would be 1571 * inconsitent with the settings created by 1572 * pmap_vac_me_harder(). Otherwise, it's safe 1573 * to re-enable cacheing. 1574 * 1575 * There's no need to call pmap_vac_me_harder() 1576 * here: all pages are losing their write 1577 * permission. 1578 */ 1579 if (maskbits & PVF_WRITE) { 1580 npte |= pte_l2_s_cache_mode; 1581 pv->pv_flags &= ~PVF_NC; 1582 } 1583 } else 1584 if (opte & L2_S_PROT_W) { 1585 vm_page_dirty(pg); 1586 /* 1587 * Entry is writable/cacheable: check if pmap 1588 * is current if it is flush it, otherwise it 1589 * won't be in the cache 1590 */ 1591 if (PV_BEEN_EXECD(oflags)) 1592 pmap_idcache_wbinv_range(pm, pv->pv_va, 1593 PAGE_SIZE); 1594 else 1595 if (PV_BEEN_REFD(oflags)) 1596 pmap_dcache_wb_range(pm, pv->pv_va, 1597 PAGE_SIZE, 1598 (maskbits & PVF_REF) ? TRUE : FALSE, 1599 FALSE); 1600 } 1601 1602 /* make the pte read only */ 1603 npte &= ~L2_S_PROT_W; 1604 1605 if (maskbits & PVF_WRITE) { 1606 /* 1607 * Keep alias accounting up to date 1608 */ 1609 if (pv->pv_pmap == pmap_kernel()) { 1610 if (oflags & PVF_WRITE) { 1611 pg->md.krw_mappings--; 1612 pg->md.kro_mappings++; 1613 } 1614 } else 1615 if (oflags & PVF_WRITE) { 1616 pg->md.urw_mappings--; 1617 pg->md.uro_mappings++; 1618 } 1619 } 1620 } 1621 1622 if (maskbits & PVF_REF && !pmap_track_modified(pv->pv_va)) { 1623 if ((pv->pv_flags & PVF_NC) == 0 && 1624 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1625 /* 1626 * Check npte here; we may have already 1627 * done the wbinv above, and the validity 1628 * of the PTE is the same for opte and 1629 * npte. 1630 */ 1631 if (npte & L2_S_PROT_W) { 1632 if (PV_BEEN_EXECD(oflags)) 1633 pmap_idcache_wbinv_range(pm, 1634 pv->pv_va, PAGE_SIZE); 1635 else 1636 if (PV_BEEN_REFD(oflags)) 1637 pmap_dcache_wb_range(pm, 1638 pv->pv_va, PAGE_SIZE, 1639 TRUE, FALSE); 1640 } else 1641 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1642 /* XXXJRT need idcache_inv_range */ 1643 if (PV_BEEN_EXECD(oflags)) 1644 pmap_idcache_wbinv_range(pm, 1645 pv->pv_va, PAGE_SIZE); 1646 else 1647 if (PV_BEEN_REFD(oflags)) 1648 pmap_dcache_wb_range(pm, 1649 pv->pv_va, PAGE_SIZE, 1650 TRUE, TRUE); 1651 } 1652 } 1653 1654 /* 1655 * Make the PTE invalid so that we will take a 1656 * page fault the next time the mapping is 1657 * referenced. 1658 */ 1659 npte &= ~L2_TYPE_MASK; 1660 npte |= L2_TYPE_INV; 1661 } 1662 1663 if (npte != opte) { 1664 count++; 1665 *ptep = npte; 1666 PTE_SYNC(ptep); 1667 /* Flush the TLB entry if a current pmap. */ 1668 if (PV_BEEN_EXECD(oflags)) 1669 pmap_tlb_flushID_SE(pm, pv->pv_va); 1670 else 1671 if (PV_BEEN_REFD(oflags)) 1672 pmap_tlb_flushD_SE(pm, pv->pv_va); 1673 } 1674 1675#if 0 1676 pmap_release_pmap_lock(pm); 1677#endif 1678 1679 } 1680 1681#if 0 1682 simple_unlock(&pg->mdpage.pvh_slock); 1683 PMAP_HEAD_TO_MAP_UNLOCK(); 1684#endif 1685 if (maskbits & PVF_WRITE) 1686 vm_page_flag_clear(pg, PG_WRITEABLE); 1687 return (count); 1688} 1689 1690/* 1691 * main pv_entry manipulation functions: 1692 * pmap_enter_pv: enter a mapping onto a vm_page list 1693 * pmap_remove_pv: remove a mappiing from a vm_page list 1694 * 1695 * NOTE: pmap_enter_pv expects to lock the pvh itself 1696 * pmap_remove_pv expects te caller to lock the pvh before calling 1697 */ 1698 1699/* 1700 * pmap_enter_pv: enter a mapping onto a vm_page lst 1701 * 1702 * => caller should hold the proper lock on pmap_main_lock 1703 * => caller should have pmap locked 1704 * => we will gain the lock on the vm_page and allocate the new pv_entry 1705 * => caller should adjust ptp's wire_count before calling 1706 * => caller should not adjust pmap's wire_count 1707 */ 1708static void 1709pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1710 vm_offset_t va, u_int flags) 1711{ 1712 1713 1714 pve->pv_pmap = pm; 1715 pve->pv_va = va; 1716 pve->pv_flags = flags; 1717 1718#if 0 1719 mtx_lock(&pg->md.pvh_mtx); 1720#endif 1721 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1722 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1723 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1724 if (pm == pmap_kernel()) { 1725 if (flags & PVF_WRITE) 1726 pg->md.krw_mappings++; 1727 else 1728 pg->md.kro_mappings++; 1729 } 1730 if (flags & PVF_WRITE) 1731 pg->md.urw_mappings++; 1732 else 1733 pg->md.uro_mappings++; 1734 pg->md.pv_list_count++; 1735#if 0 1736 mtx_unlock(&pg->md.pvh_mtx); 1737#endif 1738 if (pve->pv_flags & PVF_WIRED) 1739 ++pm->pm_stats.wired_count; 1740 vm_page_flag_set(pg, PG_REFERENCED); 1741} 1742 1743/* 1744 * 1745 * pmap_find_pv: Find a pv entry 1746 * 1747 * => caller should hold lock on vm_page 1748 */ 1749static PMAP_INLINE struct pv_entry * 1750pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1751{ 1752 struct pv_entry *pv; 1753 1754 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1755 if (pm == pv->pv_pmap && va == pv->pv_va) 1756 break; 1757 return (pv); 1758} 1759 1760/* 1761 * vector_page_setprot: 1762 * 1763 * Manipulate the protection of the vector page. 1764 */ 1765void 1766vector_page_setprot(int prot) 1767{ 1768 struct l2_bucket *l2b; 1769 pt_entry_t *ptep; 1770 1771 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1772 1773 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1774 1775 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1776 PTE_SYNC(ptep); 1777 cpu_tlb_flushD_SE(vector_page); 1778 cpu_cpwait(); 1779} 1780 1781/* 1782 * pmap_remove_pv: try to remove a mapping from a pv_list 1783 * 1784 * => caller should hold proper lock on pmap_main_lock 1785 * => pmap should be locked 1786 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1787 * => caller should adjust ptp's wire_count and free PTP if needed 1788 * => caller should NOT adjust pmap's wire_count 1789 * => we return the removed pve 1790 */ 1791 1792static void 1793pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1794{ 1795 1796 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1797 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1798 if (pve->pv_flags & PVF_WIRED) 1799 --pm->pm_stats.wired_count; 1800 pg->md.pv_list_count--; 1801 if (pg->md.pvh_attrs & PVF_MOD) 1802 vm_page_dirty(pg); 1803 if (pm == pmap_kernel()) { 1804 if (pve->pv_flags & PVF_WRITE) 1805 pg->md.krw_mappings--; 1806 else 1807 pg->md.kro_mappings--; 1808 } else 1809 if (pve->pv_flags & PVF_WRITE) 1810 pg->md.urw_mappings--; 1811 else 1812 pg->md.uro_mappings--; 1813 if (TAILQ_FIRST(&pg->md.pv_list) == NULL || 1814 (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) { 1815 pg->md.pvh_attrs &= ~PVF_MOD; 1816 if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1817 pg->md.pvh_attrs &= ~PVF_REF; 1818 vm_page_flag_clear(pg, PG_WRITEABLE); 1819 } 1820 if (TAILQ_FIRST(&pg->md.pv_list)) 1821 vm_page_flag_set(pg, PG_REFERENCED); 1822 if (pve->pv_flags & PVF_WRITE) 1823 pmap_vac_me_harder(pg, pm, 0); 1824} 1825 1826static struct pv_entry * 1827pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1828{ 1829 struct pv_entry *pve; 1830 1831 pve = TAILQ_FIRST(&pg->md.pv_list); 1832 1833 while (pve) { 1834 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1835 pmap_nuke_pv(pg, pm, pve); 1836 break; 1837 } 1838 pve = TAILQ_NEXT(pve, pv_list); 1839 } 1840 1841 return(pve); /* return removed pve */ 1842} 1843/* 1844 * 1845 * pmap_modify_pv: Update pv flags 1846 * 1847 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1848 * => caller should NOT adjust pmap's wire_count 1849 * => caller must call pmap_vac_me_harder() if writable status of a page 1850 * may have changed. 1851 * => we return the old flags 1852 * 1853 * Modify a physical-virtual mapping in the pv table 1854 */ 1855static u_int 1856pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1857 u_int clr_mask, u_int set_mask) 1858{ 1859 struct pv_entry *npv; 1860 u_int flags, oflags; 1861 1862 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1863 return (0); 1864 1865 /* 1866 * There is at least one VA mapping this page. 1867 */ 1868 1869 if (clr_mask & (PVF_REF | PVF_MOD)) 1870 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1871 1872 oflags = npv->pv_flags; 1873 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1874 1875 if ((flags ^ oflags) & PVF_WIRED) { 1876 if (flags & PVF_WIRED) 1877 ++pm->pm_stats.wired_count; 1878 else 1879 --pm->pm_stats.wired_count; 1880 } 1881 1882 if ((flags ^ oflags) & PVF_WRITE) { 1883 if (pm == pmap_kernel()) { 1884 if (flags & PVF_WRITE) { 1885 pg->md.krw_mappings++; 1886 pg->md.kro_mappings--; 1887 } else { 1888 pg->md.kro_mappings++; 1889 pg->md.krw_mappings--; 1890 } 1891 } else 1892 if (flags & PVF_WRITE) { 1893 pg->md.urw_mappings++; 1894 pg->md.uro_mappings--; 1895 } else { 1896 pg->md.uro_mappings++; 1897 pg->md.urw_mappings--; 1898 } 1899 if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) { 1900 pg->md.pvh_attrs &= ~PVF_MOD; 1901 vm_page_flag_clear(pg, PG_WRITEABLE); 1902 } 1903 pmap_vac_me_harder(pg, pm, 0); 1904 } 1905 1906 return (oflags); 1907} 1908 1909/* Function to set the debug level of the pmap code */ 1910#ifdef PMAP_DEBUG 1911void 1912pmap_debug(int level) 1913{ 1914 pmap_debug_level = level; 1915 dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1916} 1917#endif /* PMAP_DEBUG */ 1918 1919void 1920pmap_pinit0(struct pmap *pmap) 1921{ 1922 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1923 1924 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1925 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1926 bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1927} 1928 1929 1930/* 1931 * Initialize the pmap module. 1932 * Called by vm_init, to initialize any structures that the pmap 1933 * system needs to map virtual memory. 1934 * pmap_init has been enhanced to support in a fairly consistant 1935 * way, discontiguous physical memory. 1936 */ 1937void 1938pmap_init(void) 1939{ 1940 int i; 1941 1942 PDEBUG(1, printf("pmap_init: phys_start = %08x\n")); 1943 /* 1944 * Allocate memory for random pmap data structures. Includes the 1945 * pv_head_table. 1946 */ 1947 for(i = 0; i < vm_page_array_size; i++) { 1948 vm_page_t m; 1949 1950 m = &vm_page_array[i]; 1951 TAILQ_INIT(&m->md.pv_list); 1952 m->md.pv_list_count = 0; 1953 } 1954 1955 /* 1956 * init the pv free list 1957 */ 1958 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1959 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1960 uma_prealloc(pvzone, MINPV); 1961 /* 1962 * Now it is safe to enable pv_table recording. 1963 */ 1964 pmap_initialized = TRUE; 1965 PDEBUG(1, printf("pmap_init: done!\n")); 1966} 1967 1968int 1969pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1970{ 1971 struct l2_dtable *l2; 1972 struct l2_bucket *l2b; 1973 pd_entry_t *pl1pd, l1pd; 1974 pt_entry_t *ptep, pte; 1975 vm_paddr_t pa; 1976 u_int l1idx; 1977 int rv = 0; 1978 1979#if 0 1980 PMAP_MAP_TO_HEAD_LOCK(); 1981 pmap_acquire_pmap_lock(pm); 1982#endif 1983 l1idx = L1_IDX(va); 1984 1985 /* 1986 * If there is no l2_dtable for this address, then the process 1987 * has no business accessing it. 1988 * 1989 * Note: This will catch userland processes trying to access 1990 * kernel addresses. 1991 */ 1992 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1993 if (l2 == NULL) 1994 goto out; 1995 1996 /* 1997 * Likewise if there is no L2 descriptor table 1998 */ 1999 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2000 if (l2b->l2b_kva == NULL) 2001 goto out; 2002 2003 /* 2004 * Check the PTE itself. 2005 */ 2006 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2007 pte = *ptep; 2008 if (pte == 0) 2009 goto out; 2010 2011 /* 2012 * Catch a userland access to the vector page mapped at 0x0 2013 */ 2014 if (user && (pte & L2_S_PROT_U) == 0) 2015 goto out; 2016 2017 pa = l2pte_pa(pte); 2018 2019 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2020 /* 2021 * This looks like a good candidate for "page modified" 2022 * emulation... 2023 */ 2024 struct pv_entry *pv; 2025 struct vm_page *pg; 2026 2027 /* Extract the physical address of the page */ 2028 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 2029 goto out; 2030 } 2031 /* Get the current flags for this page. */ 2032 2033 pv = pmap_find_pv(pg, pm, va); 2034 if (pv == NULL) { 2035 goto out; 2036 } 2037 2038 /* 2039 * Do the flags say this page is writable? If not then it 2040 * is a genuine write fault. If yes then the write fault is 2041 * our fault as we did not reflect the write access in the 2042 * PTE. Now we know a write has occurred we can correct this 2043 * and also set the modified bit 2044 */ 2045 if ((pv->pv_flags & PVF_WRITE) == 0) { 2046 goto out; 2047 } 2048 2049 if (pmap_track_modified(pv->pv_va)) { 2050 pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 2051 vm_page_dirty(pg); 2052 } 2053 pv->pv_flags |= PVF_REF | PVF_MOD; 2054 2055 /* 2056 * Re-enable write permissions for the page. No need to call 2057 * pmap_vac_me_harder(), since this is just a 2058 * modified-emulation fault, and the PVF_WRITE bit isn't 2059 * changing. We've already set the cacheable bits based on 2060 * the assumption that we can write to this page. 2061 */ 2062 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W | 2063 pte_l2_s_cache_mask; 2064 PTE_SYNC(ptep); 2065 rv = 1; 2066 } else 2067 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2068 /* 2069 * This looks like a good candidate for "page referenced" 2070 * emulation. 2071 */ 2072 struct pv_entry *pv; 2073 struct vm_page *pg; 2074 2075 /* Extract the physical address of the page */ 2076 vm_page_lock_queues(); 2077 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 2078 vm_page_unlock_queues(); 2079 goto out; 2080 } 2081 /* Get the current flags for this page. */ 2082 2083 pv = pmap_find_pv(pg, pm, va); 2084 if (pv == NULL) { 2085 vm_page_unlock_queues(); 2086 goto out; 2087 } 2088 2089 pg->md.pvh_attrs |= PVF_REF; 2090 pv->pv_flags |= PVF_REF; 2091 2092 2093 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2094 PTE_SYNC(ptep); 2095 rv = 1; 2096 vm_page_unlock_queues(); 2097 } 2098 2099 /* 2100 * We know there is a valid mapping here, so simply 2101 * fix up the L1 if necessary. 2102 */ 2103 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2104 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2105 if (*pl1pd != l1pd) { 2106 *pl1pd = l1pd; 2107 PTE_SYNC(pl1pd); 2108 rv = 1; 2109 } 2110 2111#ifdef CPU_SA110 2112 /* 2113 * There are bugs in the rev K SA110. This is a check for one 2114 * of them. 2115 */ 2116 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2117 curcpu()->ci_arm_cpurev < 3) { 2118 /* Always current pmap */ 2119 if (l2pte_valid(pte)) { 2120 extern int kernel_debug; 2121 if (kernel_debug & 1) { 2122 struct proc *p = curlwp->l_proc; 2123 printf("prefetch_abort: page is already " 2124 "mapped - pte=%p *pte=%08x\n", ptep, pte); 2125 printf("prefetch_abort: pc=%08lx proc=%p " 2126 "process=%s\n", va, p, p->p_comm); 2127 printf("prefetch_abort: far=%08x fs=%x\n", 2128 cpu_faultaddress(), cpu_faultstatus()); 2129 } 2130#ifdef DDB 2131 if (kernel_debug & 2) 2132 Debugger(); 2133#endif 2134 rv = 1; 2135 } 2136 } 2137#endif /* CPU_SA110 */ 2138 2139#ifdef DEBUG 2140 /* 2141 * If 'rv == 0' at this point, it generally indicates that there is a 2142 * stale TLB entry for the faulting address. This happens when two or 2143 * more processes are sharing an L1. Since we don't flush the TLB on 2144 * a context switch between such processes, we can take domain faults 2145 * for mappings which exist at the same VA in both processes. EVEN IF 2146 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2147 * example. 2148 * 2149 * This is extremely likely to happen if pmap_enter() updated the L1 2150 * entry for a recently entered mapping. In this case, the TLB is 2151 * flushed for the new mapping, but there may still be TLB entries for 2152 * other mappings belonging to other processes in the 1MB range 2153 * covered by the L1 entry. 2154 * 2155 * Since 'rv == 0', we know that the L1 already contains the correct 2156 * value, so the fault must be due to a stale TLB entry. 2157 * 2158 * Since we always need to flush the TLB anyway in the case where we 2159 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2160 * stale TLB entries dynamically. 2161 * 2162 * However, the above condition can ONLY happen if the current L1 is 2163 * being shared. If it happens when the L1 is unshared, it indicates 2164 * that other parts of the pmap are not doing their job WRT managing 2165 * the TLB. 2166 */ 2167 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2168 extern int last_fault_code; 2169 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2170 pm, va, ftype); 2171 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2172 l2, l2b, ptep, pl1pd); 2173 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2174 pte, l1pd, last_fault_code); 2175#ifdef DDB 2176 Debugger(); 2177#endif 2178 } 2179#endif 2180 2181 cpu_tlb_flushID_SE(va); 2182 cpu_cpwait(); 2183 2184 rv = 1; 2185 2186out: 2187#if 0 2188 pmap_release_pmap_lock(pm); 2189 PMAP_MAP_TO_HEAD_UNLOCK(); 2190#endif 2191 return (rv); 2192} 2193 2194/* 2195 * Initialize the address space (zone) for the pv_entries. Set a 2196 * high water mark so that the system can recover from excessive 2197 * numbers of pv entries. 2198 */ 2199void 2200pmap_init2() 2201{ 2202 int shpgperproc = PMAP_SHPGPERPROC; 2203 struct l2_bucket *l2b; 2204 struct l1_ttable *l1; 2205 pd_entry_t *pl1pt; 2206 pt_entry_t *ptep, pte; 2207 vm_offset_t va, eva; 2208 u_int loop, needed; 2209 2210 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 2211 2212 pv_entry_max = shpgperproc * maxproc + vm_page_array_size; 2213 pv_entry_high_water = 9 * (pv_entry_max / 10); 2214 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 2215 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 2216 uma_prealloc(l2zone, 4096); 2217 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 2218 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 2219 UMA_ZONE_VM | UMA_ZONE_NOFREE); 2220 uma_prealloc(l2table_zone, 1024); 2221 2222 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 2223 uma_zone_set_obj(l2zone, &l2zone_obj, pv_entry_max); 2224 2225 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2226 needed -= 1; 2227 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2228 2229 for (loop = 0; loop < needed; loop++, l1++) { 2230 /* Allocate a L1 page table */ 2231 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2232 0xffffffff, L1_TABLE_SIZE, 0); 2233 2234 if (va == 0) 2235 panic("Cannot allocate L1 KVM"); 2236 2237 eva = va + L1_TABLE_SIZE; 2238 pl1pt = (pd_entry_t *)va; 2239 2240 while (va < eva) { 2241 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2242 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2243 pte = *ptep; 2244 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2245 *ptep = pte; 2246 PTE_SYNC(ptep); 2247 cpu_tlb_flushD_SE(va); 2248 2249 va += PAGE_SIZE; 2250 } 2251 pmap_init_l1(l1, pl1pt); 2252 } 2253 2254 2255#ifdef DEBUG 2256 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2257 needed); 2258#endif 2259} 2260 2261/* 2262 * This is used to stuff certain critical values into the PCB where they 2263 * can be accessed quickly from cpu_switch() et al. 2264 */ 2265void 2266pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2267{ 2268 struct l2_bucket *l2b; 2269 2270 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2271 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2272 (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2273 2274 if (vector_page < KERNBASE) { 2275 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2276 l2b = pmap_get_l2_bucket(pm, vector_page); 2277 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2278 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2279 } else 2280 pcb->pcb_pl1vec = NULL; 2281} 2282 2283void 2284pmap_activate(struct thread *td) 2285{ 2286 pmap_t pm; 2287 struct pcb *pcb; 2288 int s; 2289 2290 pm = vmspace_pmap(td->td_proc->p_vmspace); 2291 pcb = td->td_pcb; 2292 2293 critical_enter(); 2294 pmap_set_pcb_pagedir(pm, pcb); 2295 2296 if (td == curthread) { 2297 u_int cur_dacr, cur_ttb; 2298 2299 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2300 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2301 2302 cur_ttb &= ~(L1_TABLE_SIZE - 1); 2303 2304 if (cur_ttb == (u_int)pcb->pcb_pagedir && 2305 cur_dacr == pcb->pcb_dacr) { 2306 /* 2307 * No need to switch address spaces. 2308 */ 2309 critical_exit(); 2310 return; 2311 } 2312 2313 2314 /* 2315 * We MUST, I repeat, MUST fix up the L1 entry corresponding 2316 * to 'vector_page' in the incoming L1 table before switching 2317 * to it otherwise subsequent interrupts/exceptions (including 2318 * domain faults!) will jump into hyperspace. 2319 */ 2320 if (pcb->pcb_pl1vec) { 2321 2322 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2323 /* 2324 * Don't need to PTE_SYNC() at this point since 2325 * cpu_setttb() is about to flush both the cache 2326 * and the TLB. 2327 */ 2328 } 2329 2330 cpu_domains(pcb->pcb_dacr); 2331 cpu_setttb(pcb->pcb_pagedir); 2332 2333 splx(s); 2334 } 2335 critical_exit(); 2336} 2337 2338static int 2339pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2340{ 2341 pd_entry_t *pdep, pde; 2342 pt_entry_t *ptep, pte; 2343 vm_offset_t pa; 2344 int rv = 0; 2345 2346 /* 2347 * Make sure the descriptor itself has the correct cache mode 2348 */ 2349 pdep = &kl1[L1_IDX(va)]; 2350 pde = *pdep; 2351 2352 if (l1pte_section_p(pde)) { 2353 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2354 *pdep = (pde & ~L1_S_CACHE_MASK) | 2355 pte_l1_s_cache_mode_pt; 2356 PTE_SYNC(pdep); 2357 cpu_dcache_wbinv_range((vm_offset_t)pdep, 2358 sizeof(*pdep)); 2359 rv = 1; 2360 } 2361 } else { 2362 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2363 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2364 if (ptep == NULL) 2365 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2366 2367 ptep = &ptep[l2pte_index(va)]; 2368 pte = *ptep; 2369 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2370 *ptep = (pte & ~L2_S_CACHE_MASK) | 2371 pte_l2_s_cache_mode_pt; 2372 PTE_SYNC(ptep); 2373 cpu_dcache_wbinv_range((vm_offset_t)ptep, 2374 sizeof(*ptep)); 2375 rv = 1; 2376 } 2377 } 2378 2379 return (rv); 2380} 2381 2382static void 2383pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2384 pt_entry_t **ptep) 2385{ 2386 vm_offset_t va = *availp; 2387 struct l2_bucket *l2b; 2388 2389 if (ptep) { 2390 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2391 if (l2b == NULL) 2392 panic("pmap_alloc_specials: no l2b for 0x%x", va); 2393 2394 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2395 } 2396 2397 *vap = va; 2398 *availp = va + (PAGE_SIZE * pages); 2399} 2400 2401/* 2402 * Bootstrap the system enough to run with virtual memory. 2403 * 2404 * On the arm this is called after mapping has already been enabled 2405 * and just syncs the pmap module with what has already been done. 2406 * [We can't call it easily with mapping off since the kernel is not 2407 * mapped with PA == VA, hence we would have to relocate every address 2408 * from the linked base (virtual) address "KERNBASE" to the actual 2409 * (physical) address starting relative to 0] 2410 */ 2411#define PMAP_STATIC_L2_SIZE 16 2412void 2413pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2414{ 2415 static struct l1_ttable static_l1; 2416 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2417 struct l1_ttable *l1 = &static_l1; 2418 struct l2_dtable *l2; 2419 struct l2_bucket *l2b; 2420 pd_entry_t pde; 2421 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2422 pt_entry_t *ptep; 2423 vm_paddr_t pa; 2424 vm_offset_t va; 2425 vm_size_t size; 2426 int l1idx, l2idx, l2next = 0; 2427 2428 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n", 2429 firstaddr, loadaddr)); 2430 2431 virtual_avail = firstaddr; 2432 kernel_pmap = &kernel_pmap_store; 2433 kernel_pmap->pm_l1 = l1; 2434 2435 /* 2436 * Scan the L1 translation table created by initarm() and create 2437 * the required metadata for all valid mappings found in it. 2438 */ 2439 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2440 pde = kernel_l1pt[l1idx]; 2441 2442 /* 2443 * We're only interested in Coarse mappings. 2444 * pmap_extract() can deal with section mappings without 2445 * recourse to checking L2 metadata. 2446 */ 2447 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2448 continue; 2449 2450 /* 2451 * Lookup the KVA of this L2 descriptor table 2452 */ 2453 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2454 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2455 2456 if (ptep == NULL) { 2457 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2458 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2459 } 2460 2461 /* 2462 * Fetch the associated L2 metadata structure. 2463 * Allocate a new one if necessary. 2464 */ 2465 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2466 if (l2next == PMAP_STATIC_L2_SIZE) 2467 panic("pmap_bootstrap: out of static L2s"); 2468 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2469 &static_l2[l2next++]; 2470 } 2471 2472 /* 2473 * One more L1 slot tracked... 2474 */ 2475 l2->l2_occupancy++; 2476 2477 /* 2478 * Fill in the details of the L2 descriptor in the 2479 * appropriate bucket. 2480 */ 2481 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2482 l2b->l2b_kva = ptep; 2483 l2b->l2b_phys = pa; 2484 l2b->l2b_l1idx = l1idx; 2485 2486 /* 2487 * Establish an initial occupancy count for this descriptor 2488 */ 2489 for (l2idx = 0; 2490 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2491 l2idx++) { 2492 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2493 l2b->l2b_occupancy++; 2494 } 2495 } 2496 2497 /* 2498 * Make sure the descriptor itself has the correct cache mode. 2499 * If not, fix it, but whine about the problem. Port-meisters 2500 * should consider this a clue to fix up their initarm() 2501 * function. :) 2502 */ 2503 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2504 printf("pmap_bootstrap: WARNING! wrong cache mode for " 2505 "L2 pte @ %p\n", ptep); 2506 } 2507 } 2508 2509 2510 /* 2511 * Ensure the primary (kernel) L1 has the correct cache mode for 2512 * a page table. Bitch if it is not correctly set. 2513 */ 2514 for (va = (vm_offset_t)kernel_l1pt; 2515 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2516 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2517 printf("pmap_bootstrap: WARNING! wrong cache mode for " 2518 "primary L1 @ 0x%x\n", va); 2519 } 2520 2521 cpu_dcache_wbinv_all(); 2522 cpu_tlb_flushID(); 2523 cpu_cpwait(); 2524 2525 kernel_pmap->pm_active = -1; 2526 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2527 LIST_INIT(&allpmaps); 2528 TAILQ_INIT(&kernel_pmap->pm_pvlist); 2529 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 2530 2531 /* 2532 * Reserve some special page table entries/VA space for temporary 2533 * mapping of pages. 2534 */ 2535#define SYSMAP(c, p, v, n) \ 2536 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2537 2538 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2539 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2540 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2541 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2542 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2543 pmap_alloc_specials(&virtual_avail, 2544 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2545 &pmap_kernel_l2ptp_kva, NULL); 2546 2547 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2548 pmap_alloc_specials(&virtual_avail, 2549 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2550 &pmap_kernel_l2dtable_kva, NULL); 2551 2552 pmap_alloc_specials(&virtual_avail, 2553 1, (vm_offset_t*)&_tmppt, NULL); 2554 SLIST_INIT(&l1_list); 2555 TAILQ_INIT(&l1_lru_list); 2556 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2557 pmap_init_l1(l1, kernel_l1pt); 2558 cpu_dcache_wbinv_all(); 2559 2560 virtual_avail = round_page(virtual_avail); 2561 virtual_end = lastaddr; 2562 kernel_vm_end = pmap_curmaxkvaddr; 2563} 2564 2565/*************************************************** 2566 * Pmap allocation/deallocation routines. 2567 ***************************************************/ 2568 2569/* 2570 * Release any resources held by the given physical map. 2571 * Called when a pmap initialized by pmap_pinit is being released. 2572 * Should only be called if the map contains no valid mappings. 2573 */ 2574void 2575pmap_release(pmap_t pmap) 2576{ 2577 struct pcb *pcb; 2578 2579 pmap_idcache_wbinv_all(pmap); 2580 pmap_tlb_flushID(pmap); 2581 cpu_cpwait(); 2582 LIST_REMOVE(pmap, pm_list); 2583 if (vector_page < KERNBASE) { 2584 struct pcb *curpcb = PCPU_GET(curpcb); 2585 pcb = thread0.td_pcb; 2586 if (pmap_is_current(pmap)) { 2587 /* 2588 * Frob the L1 entry corresponding to the vector 2589 * page so that it contains the kernel pmap's domain 2590 * number. This will ensure pmap_remove() does not 2591 * pull the current vector page out from under us. 2592 */ 2593 critical_enter(); 2594 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2595 cpu_domains(pcb->pcb_dacr); 2596 cpu_setttb(pcb->pcb_pagedir); 2597 critical_exit(); 2598 } 2599 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2600 /* 2601 * Make sure cpu_switch(), et al, DTRT. This is safe to do 2602 * since this process has no remaining mappings of its own. 2603 */ 2604 curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2605 curpcb->pcb_l1vec = pcb->pcb_l1vec; 2606 curpcb->pcb_dacr = pcb->pcb_dacr; 2607 curpcb->pcb_pagedir = pcb->pcb_pagedir; 2608 2609 } 2610 pmap_free_l1(pmap); 2611 2612 dprintf("pmap_release()\n"); 2613} 2614 2615 2616 2617/* 2618 * Helper function for pmap_grow_l2_bucket() 2619 */ 2620static __inline int 2621pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2622{ 2623 struct l2_bucket *l2b; 2624 pt_entry_t *ptep; 2625 vm_paddr_t pa; 2626 struct vm_page *pg; 2627 2628 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_ZERO | 2629 VM_ALLOC_WIRED); 2630 if (pg == NULL) 2631 return (1); 2632 pa = VM_PAGE_TO_PHYS(pg); 2633 2634 if (pap) 2635 *pap = pa; 2636 2637 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2638 2639 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2640 *ptep = L2_S_PROTO | pa | cache_mode | 2641 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2642 PTE_SYNC(ptep); 2643 return (0); 2644} 2645 2646/* 2647 * This is the same as pmap_alloc_l2_bucket(), except that it is only 2648 * used by pmap_growkernel(). 2649 */ 2650static __inline struct l2_bucket * 2651pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2652{ 2653 struct l2_dtable *l2; 2654 struct l2_bucket *l2b; 2655 struct l1_ttable *l1; 2656 pd_entry_t *pl1pd; 2657 u_short l1idx; 2658 vm_offset_t nva; 2659 2660 l1idx = L1_IDX(va); 2661 2662 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2663 /* 2664 * No mapping at this address, as there is 2665 * no entry in the L1 table. 2666 * Need to allocate a new l2_dtable. 2667 */ 2668 nva = pmap_kernel_l2dtable_kva; 2669 if ((nva & PAGE_MASK) == 0) { 2670 /* 2671 * Need to allocate a backing page 2672 */ 2673 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2674 return (NULL); 2675 } 2676 2677 l2 = (struct l2_dtable *)nva; 2678 nva += sizeof(struct l2_dtable); 2679 2680 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2681 PAGE_MASK)) { 2682 /* 2683 * The new l2_dtable straddles a page boundary. 2684 * Map in another page to cover it. 2685 */ 2686 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2687 return (NULL); 2688 } 2689 2690 pmap_kernel_l2dtable_kva = nva; 2691 2692 /* 2693 * Link it into the parent pmap 2694 */ 2695 pm->pm_l2[L2_IDX(l1idx)] = l2; 2696 } 2697 2698 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2699 2700 /* 2701 * Fetch pointer to the L2 page table associated with the address. 2702 */ 2703 if (l2b->l2b_kva == NULL) { 2704 pt_entry_t *ptep; 2705 2706 /* 2707 * No L2 page table has been allocated. Chances are, this 2708 * is because we just allocated the l2_dtable, above. 2709 */ 2710 nva = pmap_kernel_l2ptp_kva; 2711 ptep = (pt_entry_t *)nva; 2712 if ((nva & PAGE_MASK) == 0) { 2713 /* 2714 * Need to allocate a backing page 2715 */ 2716 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2717 &pmap_kernel_l2ptp_phys)) 2718 return (NULL); 2719 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2720 } 2721 2722 l2->l2_occupancy++; 2723 l2b->l2b_kva = ptep; 2724 l2b->l2b_l1idx = l1idx; 2725 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2726 2727 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2728 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2729 } 2730 2731 /* Distribute new L1 entry to all other L1s */ 2732 SLIST_FOREACH(l1, &l1_list, l1_link) { 2733 pl1pd = &l1->l1_kva[L1_IDX(va)]; 2734 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2735 L1_C_PROTO; 2736 PTE_SYNC(pl1pd); 2737 } 2738 2739 return (l2b); 2740} 2741 2742 2743/* 2744 * grow the number of kernel page table entries, if needed 2745 */ 2746void 2747pmap_growkernel(vm_offset_t addr) 2748{ 2749 pmap_t kpm = pmap_kernel(); 2750 int s; 2751 2752 if (addr <= pmap_curmaxkvaddr) 2753 return; /* we are OK */ 2754 2755 /* 2756 * whoops! we need to add kernel PTPs 2757 */ 2758 2759 s = splhigh(); /* to be safe */ 2760 2761 /* Map 1MB at a time */ 2762 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2763 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2764 2765 /* 2766 * flush out the cache, expensive but growkernel will happen so 2767 * rarely 2768 */ 2769 cpu_dcache_wbinv_all(); 2770 cpu_tlb_flushD(); 2771 cpu_cpwait(); 2772 kernel_vm_end = pmap_curmaxkvaddr; 2773 2774} 2775 2776 2777/* 2778 * pmap_page_protect: 2779 * 2780 * Lower the permission for all mappings to a given page. 2781 */ 2782void 2783pmap_page_protect(vm_page_t m, vm_prot_t prot) 2784{ 2785 switch(prot) { 2786 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2787 case VM_PROT_READ|VM_PROT_WRITE: 2788 return; 2789 2790 case VM_PROT_READ: 2791 case VM_PROT_READ|VM_PROT_EXECUTE: 2792 pmap_clearbit(m, PVF_WRITE); 2793 break; 2794 2795 default: 2796 pmap_remove_all(m); 2797 break; 2798 } 2799 2800} 2801 2802 2803/* 2804 * Remove all pages from specified address space 2805 * this aids process exit speeds. Also, this code 2806 * is special cased for current process only, but 2807 * can have the more generic (and slightly slower) 2808 * mode enabled. This is much faster than pmap_remove 2809 * in the case of running down an entire address space. 2810 */ 2811void 2812pmap_remove_pages(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2813{ 2814 struct pv_entry *pv, *npv; 2815 struct l2_bucket *l2b = NULL; 2816 vm_page_t m; 2817 pt_entry_t *pt; 2818 2819 vm_page_lock_queues(); 2820 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2821 if (pv->pv_va >= eva || pv->pv_va < sva) { 2822 npv = TAILQ_NEXT(pv, pv_plist); 2823 continue; 2824 } 2825 if (pv->pv_flags & PVF_WIRED) { 2826 /* The page is wired, cannot remove it now. */ 2827 npv = TAILQ_NEXT(pv, pv_plist); 2828 continue; 2829 } 2830 pmap->pm_stats.resident_count--; 2831 l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2832 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2833 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2834 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2835 *pt = 0; 2836 PTE_SYNC(pt); 2837 npv = TAILQ_NEXT(pv, pv_plist); 2838 pmap_nuke_pv(m, pmap, pv); 2839 pmap_free_pv_entry(pv); 2840 } 2841 vm_page_unlock_queues(); 2842 cpu_idcache_wbinv_all(); 2843 cpu_tlb_flushID(); 2844 cpu_cpwait(); 2845} 2846 2847 2848/*************************************************** 2849 * Low level mapping routines..... 2850 ***************************************************/ 2851 2852/* 2853 * add a wired page to the kva 2854 * note that in order for the mapping to take effect -- you 2855 * should do a invltlb after doing the pmap_kenter... 2856 */ 2857static PMAP_INLINE void 2858pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2859{ 2860 struct l2_bucket *l2b; 2861 pt_entry_t *pte; 2862 pt_entry_t opte; 2863 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2864 (uint32_t) va, (uint32_t) pa)); 2865 2866 2867 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2868 if (l2b == NULL) 2869 l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2870 KASSERT(l2b != NULL, ("No L2 Bucket")); 2871 pte = &l2b->l2b_kva[l2pte_index(va)]; 2872 opte = *pte; 2873 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2874 (uint32_t) pte, opte, *pte)); 2875 if (l2pte_valid(opte)) { 2876 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2877 cpu_tlb_flushD_SE(va); 2878 cpu_cpwait(); 2879 } else { 2880 if (opte == 0) 2881 l2b->l2b_occupancy++; 2882 } 2883 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2884 VM_PROT_READ | VM_PROT_WRITE); 2885 if (flags & KENTER_CACHE) 2886 *pte |= pte_l2_s_cache_mode; 2887 if (flags & KENTER_USER) 2888 *pte |= L2_S_PROT_U; 2889 PTE_SYNC(pte); 2890} 2891 2892void 2893pmap_kenter(vm_offset_t va, vm_paddr_t pa) 2894{ 2895 pmap_kenter_internal(va, pa, KENTER_CACHE); 2896} 2897 2898void 2899pmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2900{ 2901 2902 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2903 /* 2904 * Call pmap_fault_fixup now, to make sure we'll have no exception 2905 * at the first use of the new address, or bad things will happen, 2906 * as we use one of these addresses in the exception handlers. 2907 */ 2908 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2909} 2910 2911/* 2912 * remove a page rom the kernel pagetables 2913 */ 2914PMAP_INLINE void 2915pmap_kremove(vm_offset_t va) 2916{ 2917 struct l2_bucket *l2b; 2918 pt_entry_t *pte, opte; 2919 2920 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2921 if (!l2b) 2922 return; 2923 KASSERT(l2b != NULL, ("No L2 Bucket")); 2924 pte = &l2b->l2b_kva[l2pte_index(va)]; 2925 opte = *pte; 2926 if (l2pte_valid(opte)) { 2927 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2928 cpu_tlb_flushD_SE(va); 2929 cpu_cpwait(); 2930 *pte = 0; 2931 } 2932} 2933 2934 2935/* 2936 * Used to map a range of physical addresses into kernel 2937 * virtual address space. 2938 * 2939 * The value passed in '*virt' is a suggested virtual address for 2940 * the mapping. Architectures which can support a direct-mapped 2941 * physical to virtual region can return the appropriate address 2942 * within that region, leaving '*virt' unchanged. Other 2943 * architectures should map the pages starting at '*virt' and 2944 * update '*virt' with the first usable address after the mapped 2945 * region. 2946 */ 2947vm_offset_t 2948pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2949{ 2950 vm_offset_t sva = *virt; 2951 vm_offset_t va = sva; 2952 2953 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2954 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2955 prot)); 2956 2957 while (start < end) { 2958 pmap_kenter(va, start); 2959 va += PAGE_SIZE; 2960 start += PAGE_SIZE; 2961 } 2962 *virt = va; 2963 return (sva); 2964} 2965 2966static void 2967pmap_wb_page(vm_page_t m, boolean_t do_inv) 2968{ 2969 struct pv_entry *pv; 2970 2971 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2972 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, do_inv, 2973 (pv->pv_flags & PVF_WRITE) == 0); 2974} 2975 2976/* 2977 * Add a list of wired pages to the kva 2978 * this routine is only used for temporary 2979 * kernel mappings that do not need to have 2980 * page modification or references recorded. 2981 * Note that old mappings are simply written 2982 * over. The page *must* be wired. 2983 */ 2984void 2985pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2986{ 2987 int i; 2988 2989 for (i = 0; i < count; i++) { 2990 pmap_wb_page(m[i], TRUE); 2991 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2992 KENTER_CACHE); 2993 va += PAGE_SIZE; 2994 } 2995} 2996 2997 2998/* 2999 * this routine jerks page mappings from the 3000 * kernel -- it is meant only for temporary mappings. 3001 */ 3002void 3003pmap_qremove(vm_offset_t va, int count) 3004{ 3005 vm_paddr_t pa; 3006 int i; 3007 3008 for (i = 0; i < count; i++) { 3009 pa = vtophys(va); 3010 if (pa) { 3011 pmap_wb_page(PHYS_TO_VM_PAGE(pa), TRUE); 3012 pmap_kremove(va); 3013 } 3014 va += PAGE_SIZE; 3015 } 3016} 3017 3018 3019/* 3020 * pmap_object_init_pt preloads the ptes for a given object 3021 * into the specified pmap. This eliminates the blast of soft 3022 * faults on process startup and immediately after an mmap. 3023 */ 3024void 3025pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3026 vm_pindex_t pindex, vm_size_t size) 3027{ 3028 printf("pmap_object_init_pt()\n"); 3029} 3030 3031 3032/* 3033 * pmap_is_prefaultable: 3034 * 3035 * Return whether or not the specified virtual address is elgible 3036 * for prefault. 3037 */ 3038boolean_t 3039pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3040{ 3041 pd_entry_t *pde; 3042 pt_entry_t *pte; 3043 3044 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3045 return (FALSE); 3046 if (*pte == 0) 3047 return (TRUE); 3048 return (FALSE); 3049} 3050 3051/* 3052 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3053 * Returns TRUE if the mapping exists, else FALSE. 3054 * 3055 * NOTE: This function is only used by a couple of arm-specific modules. 3056 * It is not safe to take any pmap locks here, since we could be right 3057 * in the middle of debugging the pmap anyway... 3058 * 3059 * It is possible for this routine to return FALSE even though a valid 3060 * mapping does exist. This is because we don't lock, so the metadata 3061 * state may be inconsistent. 3062 * 3063 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3064 * a "section" mapping. 3065 */ 3066boolean_t 3067pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3068{ 3069 struct l2_dtable *l2; 3070 pd_entry_t *pl1pd, l1pd; 3071 pt_entry_t *ptep; 3072 u_short l1idx; 3073 3074 if (pm->pm_l1 == NULL) 3075 return (FALSE); 3076 3077 l1idx = L1_IDX(va); 3078 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3079 l1pd = *pl1pd; 3080 3081 if (l1pte_section_p(l1pd)) { 3082 *ptp = NULL; 3083 return (TRUE); 3084 } 3085 3086 if (pm->pm_l2 == NULL) 3087 return (FALSE); 3088 3089 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3090 3091 if (l2 == NULL || 3092 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3093 return (FALSE); 3094 } 3095 3096 *ptp = &ptep[l2pte_index(va)]; 3097 return (TRUE); 3098} 3099 3100/* 3101 * Routine: pmap_remove_all 3102 * Function: 3103 * Removes this physical page from 3104 * all physical maps in which it resides. 3105 * Reflects back modify bits to the pager. 3106 * 3107 * Notes: 3108 * Original versions of this routine were very 3109 * inefficient because they iteratively called 3110 * pmap_remove (slow...) 3111 */ 3112void 3113pmap_remove_all(vm_page_t m) 3114{ 3115 pv_entry_t pv; 3116 pt_entry_t *ptep, pte; 3117 struct l2_bucket *l2b; 3118 boolean_t flush = FALSE; 3119 pmap_t curpm; 3120 int flags = 0; 3121 3122#if defined(PMAP_DEBUG) 3123 /* 3124 * XXX this makes pmap_page_protect(NONE) illegal for non-managed 3125 * pages! 3126 */ 3127 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) { 3128 panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m)); 3129 } 3130#endif 3131 3132 if (TAILQ_EMPTY(&m->md.pv_list)) 3133 return; 3134 curpm = vmspace_pmap(curproc->p_vmspace); 3135 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3136 if (flush == FALSE && (pv->pv_pmap == curpm || 3137 pv->pv_pmap == pmap_kernel())) 3138 flush = TRUE; 3139 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3140 KASSERT(l2b != NULL, ("No l2 bucket")); 3141 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3142 pte = *ptep; 3143 *ptep = 0; 3144 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3145 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3146 if (pv->pv_flags & PVF_WIRED) 3147 pv->pv_pmap->pm_stats.wired_count--; 3148 pv->pv_pmap->pm_stats.resident_count--; 3149 flags |= pv->pv_flags; 3150 pmap_nuke_pv(m, pv->pv_pmap, pv); 3151 pmap_free_pv_entry(pv); 3152 } 3153 3154 if (flush) { 3155 if (PV_BEEN_EXECD(flags)) 3156 pmap_tlb_flushID(curpm); 3157 else 3158 pmap_tlb_flushD(curpm); 3159 } 3160} 3161 3162 3163/* 3164 * Set the physical protection on the 3165 * specified range of this map as requested. 3166 */ 3167void 3168pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3169{ 3170 struct l2_bucket *l2b; 3171 pt_entry_t *ptep, pte; 3172 vm_offset_t next_bucket; 3173 u_int flags; 3174 int flush; 3175 3176 if ((prot & VM_PROT_READ) == 0) { 3177 mtx_lock(&Giant); 3178 pmap_remove(pm, sva, eva); 3179 mtx_unlock(&Giant); 3180 return; 3181 } 3182 3183 if (prot & VM_PROT_WRITE) { 3184 /* 3185 * If this is a read->write transition, just ignore it and let 3186 * vm_fault() take care of it later. 3187 */ 3188 return; 3189 } 3190 3191 mtx_lock(&Giant); 3192 3193 /* 3194 * OK, at this point, we know we're doing write-protect operation. 3195 * If the pmap is active, write-back the range. 3196 */ 3197 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3198 3199 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3200 flags = 0; 3201 3202 vm_page_lock_queues(); 3203 while (sva < eva) { 3204 next_bucket = L2_NEXT_BUCKET(sva); 3205 if (next_bucket > eva) 3206 next_bucket = eva; 3207 3208 l2b = pmap_get_l2_bucket(pm, sva); 3209 if (l2b == NULL) { 3210 sva = next_bucket; 3211 continue; 3212 } 3213 3214 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3215 3216 while (sva < next_bucket) { 3217 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3218 struct vm_page *pg; 3219 u_int f; 3220 3221 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3222 pte &= ~L2_S_PROT_W; 3223 *ptep = pte; 3224 PTE_SYNC(ptep); 3225 3226 if (pg != NULL) { 3227 f = pmap_modify_pv(pg, pm, sva, 3228 PVF_WRITE, 0); 3229 pmap_vac_me_harder(pg, pm, sva); 3230 if (pmap_track_modified(sva)) 3231 vm_page_dirty(pg); 3232 } else 3233 f = PVF_REF | PVF_EXEC; 3234 3235 if (flush >= 0) { 3236 flush++; 3237 flags |= f; 3238 } else 3239 if (PV_BEEN_EXECD(f)) 3240 pmap_tlb_flushID_SE(pm, sva); 3241 else 3242 if (PV_BEEN_REFD(f)) 3243 pmap_tlb_flushD_SE(pm, sva); 3244 } 3245 3246 sva += PAGE_SIZE; 3247 ptep++; 3248 } 3249 } 3250 3251 3252 if (flush) { 3253 if (PV_BEEN_EXECD(flags)) 3254 pmap_tlb_flushID(pm); 3255 else 3256 if (PV_BEEN_REFD(flags)) 3257 pmap_tlb_flushD(pm); 3258 } 3259 vm_page_unlock_queues(); 3260 3261 mtx_unlock(&Giant); 3262} 3263 3264 3265/* 3266 * Insert the given physical page (p) at 3267 * the specified virtual address (v) in the 3268 * target physical map with the protection requested. 3269 * 3270 * If specified, the page will be wired down, meaning 3271 * that the related pte can not be reclaimed. 3272 * 3273 * NB: This is the only routine which MAY NOT lazy-evaluate 3274 * or lose information. That is, this routine must actually 3275 * insert this page into the given map NOW. 3276 */ 3277 3278void 3279pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3280 boolean_t wired) 3281{ 3282 struct l2_bucket *l2b = NULL; 3283 struct vm_page *opg; 3284 struct pv_entry *pve = NULL; 3285 pt_entry_t *ptep, npte, opte; 3286 u_int nflags; 3287 u_int oflags; 3288 vm_paddr_t pa; 3289 3290 vm_page_lock_queues(); 3291 if (va == vector_page) { 3292 pa = systempage.pv_pa; 3293 m = NULL; 3294 } else 3295 pa = VM_PAGE_TO_PHYS(m); 3296 nflags = 0; 3297 if (prot & VM_PROT_WRITE) 3298 nflags |= PVF_WRITE; 3299 if (prot & VM_PROT_EXECUTE) 3300 nflags |= PVF_EXEC; 3301 if (wired) 3302 nflags |= PVF_WIRED; 3303 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3304 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3305 3306 if (pmap == pmap_kernel()) { 3307 l2b = pmap_get_l2_bucket(pmap, va); 3308 if (l2b == NULL) 3309 l2b = pmap_grow_l2_bucket(pmap, va); 3310 } else 3311 l2b = pmap_alloc_l2_bucket(pmap, va); 3312 KASSERT(l2b != NULL, 3313 ("pmap_enter: failed to allocate l2 bucket")); 3314 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3315 3316 opte = *ptep; 3317 npte = pa; 3318 oflags = 0; 3319 if (opte) { 3320 /* 3321 * There is already a mapping at this address. 3322 * If the physical address is different, lookup the 3323 * vm_page. 3324 */ 3325 if (l2pte_pa(opte) != pa) 3326 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3327 else 3328 opg = m; 3329 } else 3330 opg = NULL; 3331 3332 if ((prot & (VM_PROT_ALL)) || 3333 (!m || m->md.pvh_attrs & PVF_REF)) { 3334 /* 3335 * - The access type indicates that we don't need 3336 * to do referenced emulation. 3337 * OR 3338 * - The physical page has already been referenced 3339 * so no need to re-do referenced emulation here. 3340 */ 3341 npte |= L2_S_PROTO; 3342 3343 nflags |= PVF_REF; 3344 3345 if (m && ((prot & VM_PROT_WRITE) != 0 || 3346 (m->md.pvh_attrs & PVF_MOD))) { 3347 /* 3348 * This is a writable mapping, and the 3349 * page's mod state indicates it has 3350 * already been modified. Make it 3351 * writable from the outset. 3352 */ 3353 nflags |= PVF_MOD; 3354 if (!(m->md.pvh_attrs & PVF_MOD) && 3355 pmap_track_modified(va)) 3356 vm_page_dirty(m); 3357 } 3358 if (m && opte) 3359 vm_page_flag_set(m, PG_REFERENCED); 3360 } else { 3361 /* 3362 * Need to do page referenced emulation. 3363 */ 3364 npte |= L2_TYPE_INV; 3365 } 3366 3367 if (prot & VM_PROT_WRITE) 3368 npte |= L2_S_PROT_W; 3369 npte |= pte_l2_s_cache_mode; 3370 if (m && m == opg) { 3371 /* 3372 * We're changing the attrs of an existing mapping. 3373 */ 3374#if 0 3375 simple_lock(&pg->mdpage.pvh_slock); 3376#endif 3377 oflags = pmap_modify_pv(m, pmap, va, 3378 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3379 PVF_MOD | PVF_REF, nflags); 3380#if 0 3381 simple_unlock(&pg->mdpage.pvh_slock); 3382#endif 3383 3384 /* 3385 * We may need to flush the cache if we're 3386 * doing rw-ro... 3387 */ 3388 if (pmap_is_current(pmap) && 3389 (oflags & PVF_NC) == 0 && 3390 (opte & L2_S_PROT_W) != 0 && 3391 (prot & VM_PROT_WRITE) == 0) 3392 cpu_dcache_wb_range(va, PAGE_SIZE); 3393 } else { 3394 /* 3395 * New mapping, or changing the backing page 3396 * of an existing mapping. 3397 */ 3398 if (opg) { 3399 /* 3400 * Replacing an existing mapping with a new one. 3401 * It is part of our managed memory so we 3402 * must remove it from the PV list 3403 */ 3404#if 0 3405 simple_lock(&opg->mdpage.pvh_slock); 3406#endif 3407 pve = pmap_remove_pv(opg, pmap, va); 3408 if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) && pve) 3409 pmap_free_pv_entry(pve); 3410 else if (!pve) 3411 pve = pmap_get_pv_entry(); 3412 KASSERT(pve != NULL, ("No pv")); 3413#if 0 3414 simple_unlock(&opg->mdpage.pvh_slock); 3415#endif 3416 oflags = pve->pv_flags; 3417 3418 /* 3419 * If the old mapping was valid (ref/mod 3420 * emulation creates 'invalid' mappings 3421 * initially) then make sure to frob 3422 * the cache. 3423 */ 3424 if ((oflags & PVF_NC) == 0 && 3425 l2pte_valid(opte)) { 3426 if (PV_BEEN_EXECD(oflags)) { 3427 pmap_idcache_wbinv_range(pmap, va, 3428 PAGE_SIZE); 3429 } else 3430 if (PV_BEEN_REFD(oflags)) { 3431 pmap_dcache_wb_range(pmap, va, 3432 PAGE_SIZE, TRUE, 3433 (oflags & PVF_WRITE) == 0); 3434 } 3435 } 3436 } else if (m) 3437 if ((pve = pmap_get_pv_entry()) == NULL) { 3438 panic("pmap_enter: no pv entries"); 3439 } 3440 if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3441 pmap_enter_pv(m, pve, pmap, va, nflags); 3442 } 3443 /* 3444 * Make sure userland mappings get the right permissions 3445 */ 3446 if (pmap != pmap_kernel() && va != vector_page) { 3447 npte |= L2_S_PROT_U; 3448 } 3449 3450 /* 3451 * Keep the stats up to date 3452 */ 3453 if (opte == 0) { 3454 l2b->l2b_occupancy++; 3455 pmap->pm_stats.resident_count++; 3456 } 3457 3458 3459 /* 3460 * If this is just a wiring change, the two PTEs will be 3461 * identical, so there's no need to update the page table. 3462 */ 3463 if (npte != opte) { 3464 boolean_t is_cached = pmap_is_current(pmap); 3465 3466 *ptep = npte; 3467 if (is_cached) { 3468 /* 3469 * We only need to frob the cache/tlb if this pmap 3470 * is current 3471 */ 3472 PTE_SYNC(ptep); 3473 if (L1_IDX(va) != L1_IDX(vector_page) && 3474 l2pte_valid(npte)) { 3475 /* 3476 * This mapping is likely to be accessed as 3477 * soon as we return to userland. Fix up the 3478 * L1 entry to avoid taking another 3479 * page/domain fault. 3480 */ 3481 pd_entry_t *pl1pd, l1pd; 3482 3483 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3484 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3485 L1_C_PROTO; 3486 if (*pl1pd != l1pd) { 3487 *pl1pd = l1pd; 3488 PTE_SYNC(pl1pd); 3489 } 3490 } 3491 } 3492 3493 if (PV_BEEN_EXECD(oflags)) 3494 pmap_tlb_flushID_SE(pmap, va); 3495 else if (PV_BEEN_REFD(oflags)) 3496 pmap_tlb_flushD_SE(pmap, va); 3497 3498 3499 pmap_vac_me_harder(m, pmap, va); 3500 } 3501 vm_page_unlock_queues(); 3502} 3503 3504/* 3505 * this code makes some *MAJOR* assumptions: 3506 * 1. Current pmap & pmap exists. 3507 * 2. Not wired. 3508 * 3. Read access. 3509 * 4. No page table pages. 3510 * 6. Page IS managed. 3511 * but is *MUCH* faster than pmap_enter... 3512 */ 3513 3514vm_page_t 3515pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t mpte) 3516{ 3517 3518 vm_page_busy(m); 3519 vm_page_unlock_queues(); 3520 VM_OBJECT_UNLOCK(m->object); 3521 mtx_lock(&Giant); 3522 pmap_enter(pmap, va, m, VM_PROT_READ|VM_PROT_EXECUTE, FALSE); 3523 pmap_idcache_wbinv_all(pmap); 3524 mtx_unlock(&Giant); 3525 VM_OBJECT_LOCK(m->object); 3526 vm_page_lock_queues(); 3527 vm_page_wakeup(m); 3528 return (NULL); 3529} 3530 3531/* 3532 * Routine: pmap_change_wiring 3533 * Function: Change the wiring attribute for a map/virtual-address 3534 * pair. 3535 * In/out conditions: 3536 * The mapping must already exist in the pmap. 3537 */ 3538void 3539pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3540{ 3541 struct l2_bucket *l2b; 3542 pt_entry_t *ptep, pte; 3543 vm_page_t pg; 3544 3545 l2b = pmap_get_l2_bucket(pmap, va); 3546 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3547 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3548 pte = *ptep; 3549 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3550 if (pg) 3551 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired); 3552} 3553 3554 3555/* 3556 * Copy the range specified by src_addr/len 3557 * from the source map to the range dst_addr/len 3558 * in the destination map. 3559 * 3560 * This routine is only advisory and need not do anything. 3561 */ 3562void 3563pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3564 vm_size_t len, vm_offset_t src_addr) 3565{ 3566} 3567 3568 3569/* 3570 * Routine: pmap_extract 3571 * Function: 3572 * Extract the physical page address associated 3573 * with the given map/virtual_address pair. 3574 */ 3575vm_paddr_t 3576pmap_extract(pmap_t pm, vm_offset_t va) 3577{ 3578 struct l2_dtable *l2; 3579 pd_entry_t *pl1pd, l1pd; 3580 pt_entry_t *ptep, pte; 3581 vm_paddr_t pa; 3582 u_int l1idx; 3583 l1idx = L1_IDX(va); 3584 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3585 l1pd = *pl1pd; 3586 3587 if (l1pte_section_p(l1pd)) { 3588 /* 3589 * These should only happen for pmap_kernel() 3590 */ 3591 KASSERT(pm == pmap_kernel(), ("huh")); 3592 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3593 } else { 3594 /* 3595 * Note that we can't rely on the validity of the L1 3596 * descriptor as an indication that a mapping exists. 3597 * We have to look it up in the L2 dtable. 3598 */ 3599 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3600 3601 if (l2 == NULL || 3602 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3603 return (0); 3604 } 3605 3606 ptep = &ptep[l2pte_index(va)]; 3607 pte = *ptep; 3608 3609 if (pte == 0) 3610 return (0); 3611 3612 switch (pte & L2_TYPE_MASK) { 3613 case L2_TYPE_L: 3614 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3615 break; 3616 3617 default: 3618 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3619 break; 3620 } 3621 } 3622 3623 return (pa); 3624} 3625 3626/* 3627 * Atomically extract and hold the physical page with the given 3628 * pmap and virtual address pair if that mapping permits the given 3629 * protection. 3630 * 3631 */ 3632vm_page_t 3633pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3634{ 3635 struct l2_dtable *l2; 3636 pd_entry_t *pl1pd, l1pd; 3637 pt_entry_t *ptep, pte; 3638 vm_paddr_t pa; 3639 vm_page_t m = NULL; 3640 u_int l1idx; 3641 l1idx = L1_IDX(va); 3642 pl1pd = &pmap->pm_l1->l1_kva[l1idx]; 3643 l1pd = *pl1pd; 3644 3645 vm_page_lock_queues(); 3646 if (l1pte_section_p(l1pd)) { 3647 /* 3648 * These should only happen for pmap_kernel() 3649 */ 3650 KASSERT(pmap == pmap_kernel(), ("huh")); 3651 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3652 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3653 m = PHYS_TO_VM_PAGE(pa); 3654 vm_page_hold(m); 3655 } 3656 3657 } else { 3658 /* 3659 * Note that we can't rely on the validity of the L1 3660 * descriptor as an indication that a mapping exists. 3661 * We have to look it up in the L2 dtable. 3662 */ 3663 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3664 3665 if (l2 == NULL || 3666 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3667 return (NULL); 3668 } 3669 3670 ptep = &ptep[l2pte_index(va)]; 3671 pte = *ptep; 3672 3673 if (pte == 0) 3674 return (NULL); 3675 3676 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3677 switch (pte & L2_TYPE_MASK) { 3678 case L2_TYPE_L: 3679 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3680 break; 3681 3682 default: 3683 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3684 break; 3685 } 3686 m = PHYS_TO_VM_PAGE(pa); 3687 vm_page_hold(m); 3688 } 3689 } 3690 3691 vm_page_unlock_queues(); 3692 return (m); 3693} 3694 3695/* 3696 * Initialize a preallocated and zeroed pmap structure, 3697 * such as one in a vmspace structure. 3698 */ 3699 3700void 3701pmap_pinit(pmap_t pmap) 3702{ 3703 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3704 3705 pmap_alloc_l1(pmap); 3706 bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3707 3708 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 3709 pmap->pm_count = 1; 3710 pmap->pm_active = 0; 3711 3712 TAILQ_INIT(&pmap->pm_pvlist); 3713 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3714 pmap->pm_stats.resident_count = 1; 3715 if (vector_page < KERNBASE) { 3716 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3717 VM_PROT_READ, 1); 3718 } 3719} 3720 3721 3722/*************************************************** 3723 * page management routines. 3724 ***************************************************/ 3725 3726 3727static void 3728pmap_free_pv_entry(pv_entry_t pv) 3729{ 3730 pv_entry_count--; 3731 uma_zfree(pvzone, pv); 3732} 3733 3734 3735/* 3736 * get a new pv_entry, allocating a block from the system 3737 * when needed. 3738 * the memory allocation is performed bypassing the malloc code 3739 * because of the possibility of allocations at interrupt time. 3740 */ 3741static pv_entry_t 3742pmap_get_pv_entry(void) 3743{ 3744 pv_entry_t ret_value; 3745 3746 pv_entry_count++; 3747 if (pv_entry_high_water && 3748 (pv_entry_count > pv_entry_high_water) && 3749 (pmap_pagedaemon_waken == 0)) { 3750 pmap_pagedaemon_waken = 1; 3751 wakeup (&vm_pages_needed); 3752 } 3753 ret_value = uma_zalloc(pvzone, M_NOWAIT); 3754 return ret_value; 3755} 3756 3757 3758/* 3759 * Remove the given range of addresses from the specified map. 3760 * 3761 * It is assumed that the start and end are properly 3762 * rounded to the page size. 3763 */ 3764#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3765void 3766pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3767{ 3768 struct l2_bucket *l2b; 3769 vm_offset_t next_bucket; 3770 pt_entry_t *ptep; 3771 u_int cleanlist_idx, total, cnt; 3772 struct { 3773 vm_offset_t va; 3774 pt_entry_t *pte; 3775 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3776 u_int mappings, is_exec, is_refd; 3777 int flushall = 0; 3778 3779 3780 /* 3781 * we lock in the pmap => pv_head direction 3782 */ 3783#if 0 3784 PMAP_MAP_TO_HEAD_LOCK(); 3785 pmap_acquire_pmap_lock(pm); 3786#endif 3787 3788 vm_page_lock_queues(); 3789 if (!pmap_is_current(pm)) { 3790 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3791 } else 3792 cleanlist_idx = 0; 3793 3794 total = 0; 3795 while (sva < eva) { 3796 /* 3797 * Do one L2 bucket's worth at a time. 3798 */ 3799 next_bucket = L2_NEXT_BUCKET(sva); 3800 if (next_bucket > eva) 3801 next_bucket = eva; 3802 3803 l2b = pmap_get_l2_bucket(pm, sva); 3804 if (l2b == NULL) { 3805 sva = next_bucket; 3806 continue; 3807 } 3808 3809 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3810 mappings = 0; 3811 3812 while (sva < next_bucket) { 3813 struct vm_page *pg; 3814 pt_entry_t pte; 3815 vm_paddr_t pa; 3816 3817 pte = *ptep; 3818 3819 if (pte == 0) { 3820 /* 3821 * Nothing here, move along 3822 */ 3823 sva += PAGE_SIZE; 3824 ptep++; 3825 continue; 3826 } 3827 3828 pm->pm_stats.resident_count--; 3829 pa = l2pte_pa(pte); 3830 is_exec = 0; 3831 is_refd = 1; 3832 3833 /* 3834 * Update flags. In a number of circumstances, 3835 * we could cluster a lot of these and do a 3836 * number of sequential pages in one go. 3837 */ 3838 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3839 struct pv_entry *pve; 3840#if 0 3841 simple_lock(&pg->mdpage.pvh_slock); 3842#endif 3843 pve = pmap_remove_pv(pg, pm, sva); 3844 if (pve) { 3845#if 0 3846 simple_unlock(&pg->mdpage.pvh_slock); 3847#endif 3848 is_exec = 3849 PV_BEEN_EXECD(pve->pv_flags); 3850 is_refd = 3851 PV_BEEN_REFD(pve->pv_flags); 3852 pmap_free_pv_entry(pve); 3853 } 3854 } 3855 3856 if (!l2pte_valid(pte)) { 3857 *ptep = 0; 3858 PTE_SYNC_CURRENT(pm, ptep); 3859 sva += PAGE_SIZE; 3860 ptep++; 3861 mappings++; 3862 continue; 3863 } 3864 3865 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3866 /* Add to the clean list. */ 3867 cleanlist[cleanlist_idx].pte = ptep; 3868 cleanlist[cleanlist_idx].va = 3869 sva | (is_exec & 1); 3870 cleanlist_idx++; 3871 } else 3872 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3873 /* Nuke everything if needed. */ 3874 pmap_idcache_wbinv_all(pm); 3875 pmap_tlb_flushID(pm); 3876 3877 /* 3878 * Roll back the previous PTE list, 3879 * and zero out the current PTE. 3880 */ 3881 for (cnt = 0; 3882 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3883 *cleanlist[cnt].pte = 0; 3884 } 3885 *ptep = 0; 3886 PTE_SYNC(ptep); 3887 cleanlist_idx++; 3888 flushall = 1; 3889 } else { 3890 *ptep = 0; 3891 PTE_SYNC(ptep); 3892 if (is_exec) 3893 pmap_tlb_flushID_SE(pm, sva); 3894 else 3895 if (is_refd) 3896 pmap_tlb_flushD_SE(pm, sva); 3897 } 3898 3899 sva += PAGE_SIZE; 3900 ptep++; 3901 mappings++; 3902 } 3903 3904 /* 3905 * Deal with any left overs 3906 */ 3907 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3908 total += cleanlist_idx; 3909 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3910 vm_offset_t clva = 3911 cleanlist[cnt].va & ~1; 3912 if (cleanlist[cnt].va & 1) { 3913 pmap_idcache_wbinv_range(pm, 3914 clva, PAGE_SIZE); 3915 pmap_tlb_flushID_SE(pm, clva); 3916 } else { 3917 pmap_dcache_wb_range(pm, 3918 clva, PAGE_SIZE, TRUE, 3919 FALSE); 3920 pmap_tlb_flushD_SE(pm, clva); 3921 } 3922 *cleanlist[cnt].pte = 0; 3923 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 3924 } 3925 3926 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3927 cleanlist_idx = 0; 3928 else { 3929 /* 3930 * We are removing so much entries it's just 3931 * easier to flush the whole cache. 3932 */ 3933 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3934 pmap_idcache_wbinv_all(pm); 3935 flushall = 1; 3936 } 3937 } 3938 3939 pmap_free_l2_bucket(pm, l2b, mappings); 3940 } 3941 3942 vm_page_unlock_queues(); 3943 if (flushall) 3944 cpu_tlb_flushID(); 3945#if 0 3946 pmap_release_pmap_lock(pm); 3947 PMAP_MAP_TO_HEAD_UNLOCK(); 3948#endif 3949} 3950 3951 3952 3953 3954/* 3955 * pmap_zero_page() 3956 * 3957 * Zero a given physical page by mapping it at a page hook point. 3958 * In doing the zero page op, the page we zero is mapped cachable, as with 3959 * StrongARM accesses to non-cached pages are non-burst making writing 3960 * _any_ bulk data very slow. 3961 */ 3962#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3963void 3964pmap_zero_page_generic(vm_paddr_t phys, int off, int size) 3965{ 3966#ifdef DEBUG 3967 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3968 3969 if (pg->md.pvh_list != NULL) 3970 panic("pmap_zero_page: page has mappings"); 3971#endif 3972 3973 3974 /* 3975 * Hook in the page, zero it, and purge the cache for that 3976 * zeroed page. Invalidate the TLB as needed. 3977 */ 3978 *cdst_pte = L2_S_PROTO | phys | 3979 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3980 PTE_SYNC(cdst_pte); 3981 cpu_tlb_flushD_SE(cdstp); 3982 cpu_cpwait(); 3983 if (off || size != PAGE_SIZE) 3984 bzero((void *)(cdstp + off), size); 3985 else 3986 bzero_page(cdstp); 3987 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3988} 3989#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3990 3991#if ARM_MMU_XSCALE == 1 3992void 3993pmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 3994{ 3995 /* 3996 * Hook in the page, zero it, and purge the cache for that 3997 * zeroed page. Invalidate the TLB as needed. 3998 */ 3999 *cdst_pte = L2_S_PROTO | phys | 4000 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4001 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4002 PTE_SYNC(cdst_pte); 4003 cpu_tlb_flushD_SE(cdstp); 4004 cpu_cpwait(); 4005 if (off || size != PAGE_SIZE) 4006 bzero((void *)(cdstp + off), size); 4007 else 4008 bzero_page(cdstp); 4009 xscale_cache_clean_minidata(); 4010} 4011 4012/* 4013 * Change the PTEs for the specified kernel mappings such that they 4014 * will use the mini data cache instead of the main data cache. 4015 */ 4016void 4017pmap_use_minicache(vm_offset_t va, vm_size_t size) 4018{ 4019 struct l2_bucket *l2b; 4020 pt_entry_t *ptep, *sptep, pte; 4021 vm_offset_t next_bucket, eva; 4022 4023#if (ARM_NMMUS > 1) 4024 if (xscale_use_minidata == 0) 4025 return; 4026#endif 4027 4028 eva = va + size; 4029 4030 while (va < eva) { 4031 next_bucket = L2_NEXT_BUCKET(va); 4032 if (next_bucket > eva) 4033 next_bucket = eva; 4034 4035 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4036 4037 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4038 4039 while (va < next_bucket) { 4040 pte = *ptep; 4041 if (!l2pte_minidata(pte)) { 4042 cpu_dcache_wbinv_range(va, PAGE_SIZE); 4043 cpu_tlb_flushD_SE(va); 4044 *ptep = pte & ~L2_B; 4045 } 4046 ptep++; 4047 va += PAGE_SIZE; 4048 } 4049 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4050 } 4051 cpu_cpwait(); 4052} 4053#endif /* ARM_MMU_XSCALE == 1 */ 4054 4055/* 4056 * pmap_zero_page zeros the specified hardware page by mapping 4057 * the page into KVM and using bzero to clear its contents. 4058 */ 4059void 4060pmap_zero_page(vm_page_t m) 4061{ 4062 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4063} 4064 4065 4066/* 4067 * pmap_zero_page_area zeros the specified hardware page by mapping 4068 * the page into KVM and using bzero to clear its contents. 4069 * 4070 * off and size may not cover an area beyond a single hardware page. 4071 */ 4072void 4073pmap_zero_page_area(vm_page_t m, int off, int size) 4074{ 4075 4076 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4077} 4078 4079 4080/* 4081 * pmap_zero_page_idle zeros the specified hardware page by mapping 4082 * the page into KVM and using bzero to clear its contents. This 4083 * is intended to be called from the vm_pagezero process only and 4084 * outside of Giant. 4085 */ 4086void 4087pmap_zero_page_idle(vm_page_t m) 4088{ 4089 4090 pmap_zero_page(m); 4091} 4092 4093/* 4094 * pmap_clean_page() 4095 * 4096 * This is a local function used to work out the best strategy to clean 4097 * a single page referenced by its entry in the PV table. It's used by 4098 * pmap_copy_page, pmap_zero page and maybe some others later on. 4099 * 4100 * Its policy is effectively: 4101 * o If there are no mappings, we don't bother doing anything with the cache. 4102 * o If there is one mapping, we clean just that page. 4103 * o If there are multiple mappings, we clean the entire cache. 4104 * 4105 * So that some functions can be further optimised, it returns 0 if it didn't 4106 * clean the entire cache, or 1 if it did. 4107 * 4108 * XXX One bug in this routine is that if the pv_entry has a single page 4109 * mapped at 0x00000000 a whole cache clean will be performed rather than 4110 * just the 1 page. Since this should not occur in everyday use and if it does 4111 * it will just result in not the most efficient clean for the page. 4112 */ 4113static int 4114pmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4115{ 4116 pmap_t pm, pm_to_clean = NULL; 4117 struct pv_entry *npv; 4118 u_int cache_needs_cleaning = 0; 4119 u_int flags = 0; 4120 vm_offset_t page_to_clean = 0; 4121 4122 if (pv == NULL) { 4123 /* nothing mapped in so nothing to flush */ 4124 return (0); 4125 } 4126 4127 /* 4128 * Since we flush the cache each time we change to a different 4129 * user vmspace, we only need to flush the page if it is in the 4130 * current pmap. 4131 */ 4132 if (curthread) 4133 pm = vmspace_pmap(curproc->p_vmspace); 4134 else 4135 pm = pmap_kernel(); 4136 4137 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4138 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4139 flags |= npv->pv_flags; 4140 /* 4141 * The page is mapped non-cacheable in 4142 * this map. No need to flush the cache. 4143 */ 4144 if (npv->pv_flags & PVF_NC) { 4145#ifdef DIAGNOSTIC 4146 if (cache_needs_cleaning) 4147 panic("pmap_clean_page: " 4148 "cache inconsistency"); 4149#endif 4150 break; 4151 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4152 continue; 4153 if (cache_needs_cleaning) { 4154 page_to_clean = 0; 4155 break; 4156 } else { 4157 page_to_clean = npv->pv_va; 4158 pm_to_clean = npv->pv_pmap; 4159 } 4160 cache_needs_cleaning = 1; 4161 } 4162 } 4163 if (page_to_clean) { 4164 if (PV_BEEN_EXECD(flags)) 4165 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4166 PAGE_SIZE); 4167 else 4168 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4169 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4170 } else if (cache_needs_cleaning) { 4171 if (PV_BEEN_EXECD(flags)) 4172 pmap_idcache_wbinv_all(pm); 4173 else 4174 pmap_dcache_wbinv_all(pm); 4175 return (1); 4176 } 4177 return (0); 4178} 4179 4180/* 4181 * pmap_copy_page copies the specified (machine independent) 4182 * page by mapping the page into virtual memory and using 4183 * bcopy to copy the page, one machine dependent page at a 4184 * time. 4185 */ 4186 4187/* 4188 * pmap_copy_page() 4189 * 4190 * Copy one physical page into another, by mapping the pages into 4191 * hook points. The same comment regarding cachability as in 4192 * pmap_zero_page also applies here. 4193 */ 4194#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4195void 4196pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4197{ 4198 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4199#ifdef DEBUG 4200 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4201 4202 if (dst_pg->md.pvh_list != NULL) 4203 panic("pmap_copy_page: dst page has mappings"); 4204#endif 4205 4206 4207 /* 4208 * Clean the source page. Hold the source page's lock for 4209 * the duration of the copy so that no other mappings can 4210 * be created while we have a potentially aliased mapping. 4211 */ 4212#if 0 4213 mtx_lock(&src_pg->md.pvh_mtx); 4214#endif 4215 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4216 4217 /* 4218 * Map the pages into the page hook points, copy them, and purge 4219 * the cache for the appropriate page. Invalidate the TLB 4220 * as required. 4221 */ 4222 *csrc_pte = L2_S_PROTO | src | 4223 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4224 PTE_SYNC(csrc_pte); 4225 *cdst_pte = L2_S_PROTO | dst | 4226 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4227 PTE_SYNC(cdst_pte); 4228 cpu_tlb_flushD_SE(csrcp); 4229 cpu_tlb_flushD_SE(cdstp); 4230 cpu_cpwait(); 4231 bcopy_page(csrcp, cdstp); 4232 cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4233#if 0 4234 mtx_lock(&src_pg->md.pvh_mtx); 4235#endif 4236 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4237} 4238#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4239 4240#if ARM_MMU_XSCALE == 1 4241void 4242pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4243{ 4244 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4245#ifdef DEBUG 4246 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4247 4248 if (dst_pg->md.pvh_list != NULL) 4249 panic("pmap_copy_page: dst page has mappings"); 4250#endif 4251 4252 4253 /* 4254 * Clean the source page. Hold the source page's lock for 4255 * the duration of the copy so that no other mappings can 4256 * be created while we have a potentially aliased mapping. 4257 */ 4258 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4259 4260 /* 4261 * Map the pages into the page hook points, copy them, and purge 4262 * the cache for the appropriate page. Invalidate the TLB 4263 * as required. 4264 */ 4265 *csrc_pte = L2_S_PROTO | src | 4266 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4267 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4268 PTE_SYNC(csrc_pte); 4269 *cdst_pte = L2_S_PROTO | dst | 4270 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4271 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4272 PTE_SYNC(cdst_pte); 4273 cpu_tlb_flushD_SE(csrcp); 4274 cpu_tlb_flushD_SE(cdstp); 4275 cpu_cpwait(); 4276 bcopy_page(csrcp, cdstp); 4277 xscale_cache_clean_minidata(); 4278} 4279#endif /* ARM_MMU_XSCALE == 1 */ 4280 4281void 4282pmap_copy_page(vm_page_t src, vm_page_t dst) 4283{ 4284 cpu_dcache_wbinv_all(); 4285 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4286} 4287 4288 4289 4290 4291/* 4292 * this routine returns true if a physical page resides 4293 * in the given pmap. 4294 */ 4295boolean_t 4296pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4297{ 4298 pv_entry_t pv; 4299 int loops = 0; 4300 int s; 4301 4302 if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 4303 return (FALSE); 4304 4305 s = splvm(); 4306 4307 /* 4308 * Not found, check current mappings returning immediately 4309 */ 4310 for (pv = TAILQ_FIRST(&m->md.pv_list); 4311 pv; 4312 pv = TAILQ_NEXT(pv, pv_list)) { 4313 if (pv->pv_pmap == pmap) { 4314 splx(s); 4315 return (TRUE); 4316 } 4317 loops++; 4318 if (loops >= 16) 4319 break; 4320 } 4321 splx(s); 4322 return (FALSE); 4323} 4324 4325 4326/* 4327 * pmap_ts_referenced: 4328 * 4329 * Return the count of reference bits for a page, clearing all of them. 4330 */ 4331int 4332pmap_ts_referenced(vm_page_t m) 4333{ 4334 return (pmap_clearbit(m, PVF_REF)); 4335} 4336 4337 4338boolean_t 4339pmap_is_modified(vm_page_t m) 4340{ 4341 4342 if (m->md.pvh_attrs & PVF_MOD) 4343 return (TRUE); 4344 4345 return(FALSE); 4346} 4347 4348 4349/* 4350 * Clear the modify bits on the specified physical page. 4351 */ 4352void 4353pmap_clear_modify(vm_page_t m) 4354{ 4355 4356 if (m->md.pvh_attrs & PVF_MOD) 4357 pmap_clearbit(m, PVF_MOD); 4358} 4359 4360 4361/* 4362 * pmap_clear_reference: 4363 * 4364 * Clear the reference bit on the specified physical page. 4365 */ 4366void 4367pmap_clear_reference(vm_page_t m) 4368{ 4369 4370 if (m->md.pvh_attrs & PVF_REF) 4371 pmap_clearbit(m, PVF_REF); 4372} 4373 4374 4375/* 4376 * perform the pmap work for mincore 4377 */ 4378int 4379pmap_mincore(pmap_t pmap, vm_offset_t addr) 4380{ 4381 printf("pmap_mincore()\n"); 4382 4383 return (0); 4384} 4385 4386 4387vm_offset_t 4388pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 4389{ 4390 4391 return(addr); 4392} 4393 4394 4395/* 4396 * Map a set of physical memory pages into the kernel virtual 4397 * address space. Return a pointer to where it is mapped. This 4398 * routine is intended to be used for mapping device memory, 4399 * NOT real memory. 4400 */ 4401void * 4402pmap_mapdev(vm_offset_t pa, vm_size_t size) 4403{ 4404 vm_offset_t va, tmpva, offset; 4405 4406 offset = pa & PAGE_MASK; 4407 size = roundup(size, PAGE_SIZE); 4408 4409 GIANT_REQUIRED; 4410 4411 va = kmem_alloc_nofault(kernel_map, size); 4412 if (!va) 4413 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4414 for (tmpva = va; size > 0;) { 4415 pmap_kenter_internal(tmpva, pa, 0); 4416 size -= PAGE_SIZE; 4417 tmpva += PAGE_SIZE; 4418 pa += PAGE_SIZE; 4419 } 4420 4421 return ((void *)(va)); 4422} 4423 4424#define BOOTSTRAP_DEBUG 4425 4426/* 4427 * pmap_map_section: 4428 * 4429 * Create a single section mapping. 4430 */ 4431void 4432pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4433 int prot, int cache) 4434{ 4435 pd_entry_t *pde = (pd_entry_t *) l1pt; 4436 pd_entry_t fl; 4437 4438 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4439 4440 switch (cache) { 4441 case PTE_NOCACHE: 4442 default: 4443 fl = 0; 4444 break; 4445 4446 case PTE_CACHE: 4447 fl = pte_l1_s_cache_mode; 4448 break; 4449 4450 case PTE_PAGETABLE: 4451 fl = pte_l1_s_cache_mode_pt; 4452 break; 4453 } 4454 4455 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4456 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4457 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4458 4459} 4460 4461/* 4462 * pmap_link_l2pt: 4463 * 4464 * Link the L2 page table specified by "pa" into the L1 4465 * page table at the slot for "va". 4466 */ 4467void 4468pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4469{ 4470 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4471 u_int slot = va >> L1_S_SHIFT; 4472 4473#ifndef ARM32_NEW_VM_LAYOUT 4474 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0, ("blah")); 4475 KASSERT((l2pv->pv_pa & PAGE_MASK) == 0, ("ouin")); 4476#endif 4477 4478 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4479 4480 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4481#ifdef ARM32_NEW_VM_LAYOUT 4482 PTE_SYNC(&pde[slot]); 4483#else 4484 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4485 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4486 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4487 PTE_SYNC_RANGE(&pde[slot + 0], 4); 4488#endif 4489 4490 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4491 4492 4493} 4494 4495/* 4496 * pmap_map_entry 4497 * 4498 * Create a single page mapping. 4499 */ 4500void 4501pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4502 int cache) 4503{ 4504 pd_entry_t *pde = (pd_entry_t *) l1pt; 4505 pt_entry_t fl; 4506 pt_entry_t *pte; 4507 4508 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4509 4510 switch (cache) { 4511 case PTE_NOCACHE: 4512 default: 4513 fl = 0; 4514 break; 4515 4516 case PTE_CACHE: 4517 fl = pte_l2_s_cache_mode; 4518 break; 4519 4520 case PTE_PAGETABLE: 4521 fl = pte_l2_s_cache_mode_pt; 4522 break; 4523 } 4524 4525 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4526 panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4527 4528#ifndef ARM32_NEW_VM_LAYOUT 4529 pte = (pt_entry_t *) 4530 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4531#else 4532 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4533#endif 4534 4535 if (pte == NULL) 4536 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4537 4538#ifndef ARM32_NEW_VM_LAYOUT 4539 pte[(va >> PAGE_SHIFT) & 0x3ff] = 4540 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4541 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]); 4542#else 4543 pte[l2pte_index(va)] = 4544 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4545 PTE_SYNC(&pte[l2pte_index(va)]); 4546#endif 4547} 4548 4549/* 4550 * pmap_map_chunk: 4551 * 4552 * Map a chunk of memory using the most efficient mappings 4553 * possible (section. large page, small page) into the 4554 * provided L1 and L2 tables at the specified virtual address. 4555 */ 4556vm_size_t 4557pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4558 vm_size_t size, int prot, int cache) 4559{ 4560 pd_entry_t *pde = (pd_entry_t *) l1pt; 4561 pt_entry_t *pte, f1, f2s, f2l; 4562 vm_size_t resid; 4563 int i; 4564 4565 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4566 4567 if (l1pt == 0) 4568 panic("pmap_map_chunk: no L1 table provided"); 4569 4570#ifdef VERBOSE_INIT_ARM 4571 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4572 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4573#endif 4574 4575 switch (cache) { 4576 case PTE_NOCACHE: 4577 default: 4578 f1 = 0; 4579 f2l = 0; 4580 f2s = 0; 4581 break; 4582 4583 case PTE_CACHE: 4584 f1 = pte_l1_s_cache_mode; 4585 f2l = pte_l2_l_cache_mode; 4586 f2s = pte_l2_s_cache_mode; 4587 break; 4588 4589 case PTE_PAGETABLE: 4590 f1 = pte_l1_s_cache_mode_pt; 4591 f2l = pte_l2_l_cache_mode_pt; 4592 f2s = pte_l2_s_cache_mode_pt; 4593 break; 4594 } 4595 4596 size = resid; 4597 4598 while (resid > 0) { 4599 /* See if we can use a section mapping. */ 4600 if (L1_S_MAPPABLE_P(va, pa, resid)) { 4601#ifdef VERBOSE_INIT_ARM 4602 printf("S"); 4603#endif 4604 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4605 L1_S_PROT(PTE_KERNEL, prot) | f1 | 4606 L1_S_DOM(PMAP_DOMAIN_KERNEL); 4607 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4608 va += L1_S_SIZE; 4609 pa += L1_S_SIZE; 4610 resid -= L1_S_SIZE; 4611 continue; 4612 } 4613 4614 /* 4615 * Ok, we're going to use an L2 table. Make sure 4616 * one is actually in the corresponding L1 slot 4617 * for the current VA. 4618 */ 4619 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4620 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4621 4622#ifndef ARM32_NEW_VM_LAYOUT 4623 pte = (pt_entry_t *) 4624 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4625#else 4626 pte = (pt_entry_t *) kernel_pt_lookup( 4627 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4628#endif 4629 if (pte == NULL) 4630 panic("pmap_map_chunk: can't find L2 table for VA" 4631 "0x%08x", va); 4632 /* See if we can use a L2 large page mapping. */ 4633 if (L2_L_MAPPABLE_P(va, pa, resid)) { 4634#ifdef VERBOSE_INIT_ARM 4635 printf("L"); 4636#endif 4637 for (i = 0; i < 16; i++) { 4638#ifndef ARM32_NEW_VM_LAYOUT 4639 pte[((va >> PAGE_SHIFT) & 0x3f0) + i] = 4640 L2_L_PROTO | pa | 4641 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4642 PTE_SYNC(&pte[((va >> PAGE_SHIFT) & 0x3f0) + i]); 4643#else 4644 pte[l2pte_index(va) + i] = 4645 L2_L_PROTO | pa | 4646 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4647 PTE_SYNC(&pte[l2pte_index(va) + i]); 4648#endif 4649 } 4650 va += L2_L_SIZE; 4651 pa += L2_L_SIZE; 4652 resid -= L2_L_SIZE; 4653 continue; 4654 } 4655 4656 /* Use a small page mapping. */ 4657#ifdef VERBOSE_INIT_ARM 4658 printf("P"); 4659#endif 4660#ifndef ARM32_NEW_VM_LAYOUT 4661 pte[(va >> PAGE_SHIFT) & 0x3ff] = 4662 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4663 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]); 4664#else 4665 pte[l2pte_index(va)] = 4666 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4667 PTE_SYNC(&pte[l2pte_index(va)]); 4668#endif 4669 va += PAGE_SIZE; 4670 pa += PAGE_SIZE; 4671 resid -= PAGE_SIZE; 4672 } 4673#ifdef VERBOSE_INIT_ARM 4674 printf("\n"); 4675#endif 4676 return (size); 4677 4678} 4679 4680/********************** Static device map routines ***************************/ 4681 4682static const struct pmap_devmap *pmap_devmap_table; 4683 4684/* 4685 * Register the devmap table. This is provided in case early console 4686 * initialization needs to register mappings created by bootstrap code 4687 * before pmap_devmap_bootstrap() is called. 4688 */ 4689void 4690pmap_devmap_register(const struct pmap_devmap *table) 4691{ 4692 4693 pmap_devmap_table = table; 4694} 4695 4696/* 4697 * Map all of the static regions in the devmap table, and remember 4698 * the devmap table so other parts of the kernel can look up entries 4699 * later. 4700 */ 4701void 4702pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4703{ 4704 int i; 4705 4706 pmap_devmap_table = table; 4707 4708 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4709#ifdef VERBOSE_INIT_ARM 4710 printf("devmap: %08lx -> %08lx @ %08lx\n", 4711 pmap_devmap_table[i].pd_pa, 4712 pmap_devmap_table[i].pd_pa + 4713 pmap_devmap_table[i].pd_size - 1, 4714 pmap_devmap_table[i].pd_va); 4715#endif 4716 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4717 pmap_devmap_table[i].pd_pa, 4718 pmap_devmap_table[i].pd_size, 4719 pmap_devmap_table[i].pd_prot, 4720 pmap_devmap_table[i].pd_cache); 4721 } 4722} 4723 4724const struct pmap_devmap * 4725pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4726{ 4727 int i; 4728 4729 if (pmap_devmap_table == NULL) 4730 return (NULL); 4731 4732 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4733 if (pa >= pmap_devmap_table[i].pd_pa && 4734 pa + size <= pmap_devmap_table[i].pd_pa + 4735 pmap_devmap_table[i].pd_size) 4736 return (&pmap_devmap_table[i]); 4737 } 4738 4739 return (NULL); 4740} 4741 4742const struct pmap_devmap * 4743pmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4744{ 4745 int i; 4746 4747 if (pmap_devmap_table == NULL) 4748 return (NULL); 4749 4750 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4751 if (va >= pmap_devmap_table[i].pd_va && 4752 va + size <= pmap_devmap_table[i].pd_va + 4753 pmap_devmap_table[i].pd_size) 4754 return (&pmap_devmap_table[i]); 4755 } 4756 4757 return (NULL); 4758} 4759 4760