pmap-v4.c revision 239268
1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 81129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 82129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 83129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 84129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 85129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 86129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 87129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 88129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 89129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 90129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 91129198Scognet * POSSIBILITY OF SUCH DAMAGE. 92129198Scognet */ 93129198Scognet 94139735Simp/*- 95129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 96129198Scognet * Copyright (c) 1994 Brini. 97129198Scognet * All rights reserved. 98139735Simp * 99129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 100129198Scognet * 101129198Scognet * Redistribution and use in source and binary forms, with or without 102129198Scognet * modification, are permitted provided that the following conditions 103129198Scognet * are met: 104129198Scognet * 1. Redistributions of source code must retain the above copyright 105129198Scognet * notice, this list of conditions and the following disclaimer. 106129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 107129198Scognet * notice, this list of conditions and the following disclaimer in the 108129198Scognet * documentation and/or other materials provided with the distribution. 109129198Scognet * 3. All advertising materials mentioning features or use of this software 110129198Scognet * must display the following acknowledgement: 111129198Scognet * This product includes software developed by Mark Brinicombe. 112129198Scognet * 4. The name of the author may not be used to endorse or promote products 113129198Scognet * derived from this software without specific prior written permission. 114129198Scognet * 115129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 116129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 117129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 118129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 119129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 120129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 121129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 122129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 123129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 124129198Scognet * 125129198Scognet * RiscBSD kernel project 126129198Scognet * 127129198Scognet * pmap.c 128129198Scognet * 129129198Scognet * Machine dependant vm stuff 130129198Scognet * 131129198Scognet * Created : 20/09/94 132129198Scognet */ 133129198Scognet 134129198Scognet/* 135129198Scognet * Special compilation symbols 136129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 137129198Scognet */ 138129198Scognet/* Include header files */ 139135641Scognet 140137552Scognet#include "opt_vm.h" 141137552Scognet 142129198Scognet#include <sys/cdefs.h> 143129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 239268 2012-08-15 03:03:03Z gonzo $"); 144129198Scognet#include <sys/param.h> 145129198Scognet#include <sys/systm.h> 146129198Scognet#include <sys/kernel.h> 147183838Sraj#include <sys/ktr.h> 148129198Scognet#include <sys/proc.h> 149129198Scognet#include <sys/malloc.h> 150129198Scognet#include <sys/msgbuf.h> 151129198Scognet#include <sys/vmmeter.h> 152129198Scognet#include <sys/mman.h> 153129198Scognet#include <sys/smp.h> 154129198Scognet#include <sys/sched.h> 155129198Scognet 156129198Scognet#include <vm/vm.h> 157239065Skib#include <vm/vm_param.h> 158129198Scognet#include <vm/uma.h> 159129198Scognet#include <vm/pmap.h> 160129198Scognet#include <vm/vm_kern.h> 161129198Scognet#include <vm/vm_object.h> 162129198Scognet#include <vm/vm_map.h> 163129198Scognet#include <vm/vm_page.h> 164129198Scognet#include <vm/vm_pageout.h> 165129198Scognet#include <vm/vm_extern.h> 166129198Scognet#include <sys/lock.h> 167129198Scognet#include <sys/mutex.h> 168129198Scognet#include <machine/md_var.h> 169129198Scognet#include <machine/cpu.h> 170129198Scognet#include <machine/cpufunc.h> 171129198Scognet#include <machine/pcb.h> 172129198Scognet 173129198Scognet#ifdef PMAP_DEBUG 174129198Scognet#define PDEBUG(_lev_,_stat_) \ 175129198Scognet if (pmap_debug_level >= (_lev_)) \ 176129198Scognet ((_stat_)) 177129198Scognet#define dprintf printf 178129198Scognet 179129198Scognetint pmap_debug_level = 0; 180236991Simp#define PMAP_INLINE 181129198Scognet#else /* PMAP_DEBUG */ 182129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 183129198Scognet#define dprintf(x, arg...) 184135641Scognet#define PMAP_INLINE __inline 185129198Scognet#endif /* PMAP_DEBUG */ 186129198Scognet 187129198Scognetextern struct pv_addr systempage; 188225988Smarcel 189225988Smarcelextern int last_fault_code; 190225988Smarcel 191129198Scognet/* 192129198Scognet * Internal function prototypes 193129198Scognet */ 194135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 195129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 196129198Scognet 197159127Salcstatic void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 198160260Scognet vm_prot_t, boolean_t, int); 199194459Sthompsastatic void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t); 200129198Scognetstatic void pmap_alloc_l1(pmap_t); 201129198Scognetstatic void pmap_free_l1(pmap_t); 202129198Scognet 203135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 204129198Scognet 205129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 206129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 207129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 208129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 209129198Scognet 210129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 211129198Scognet 212129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 213129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 214135641Scognetvm_offset_t pmap_curmaxkvaddr; 215150865Scognetvm_paddr_t kernel_l1pa; 216129198Scognet 217129198Scognetextern void *end; 218129198Scognetvm_offset_t kernel_vm_end = 0; 219129198Scognet 220129198Scognetstruct pmap kernel_pmap_store; 221129198Scognet 222129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 223129198Scognetstatic vm_offset_t csrcp, cdstp; 224159088Scognetstatic struct mtx cmtx; 225159088Scognet 226129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 227129198Scognet/* 228129198Scognet * These routines are called when the CPU type is identified to set up 229129198Scognet * the PTE prototypes, cache modes, etc. 230129198Scognet * 231129198Scognet * The variables are always here, just in case LKMs need to reference 232129198Scognet * them (though, they shouldn't). 233129198Scognet */ 234129198Scognet 235129198Scognetpt_entry_t pte_l1_s_cache_mode; 236129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 237129198Scognetpt_entry_t pte_l1_s_cache_mask; 238129198Scognet 239129198Scognetpt_entry_t pte_l2_l_cache_mode; 240129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 241129198Scognetpt_entry_t pte_l2_l_cache_mask; 242129198Scognet 243129198Scognetpt_entry_t pte_l2_s_cache_mode; 244129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 245129198Scognetpt_entry_t pte_l2_s_cache_mask; 246129198Scognet 247129198Scognetpt_entry_t pte_l2_s_prot_u; 248129198Scognetpt_entry_t pte_l2_s_prot_w; 249129198Scognetpt_entry_t pte_l2_s_prot_mask; 250129198Scognet 251129198Scognetpt_entry_t pte_l1_s_proto; 252129198Scognetpt_entry_t pte_l1_c_proto; 253129198Scognetpt_entry_t pte_l2_s_proto; 254129198Scognet 255129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 256129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 257129198Scognet/* 258129198Scognet * Which pmap is currently 'live' in the cache 259129198Scognet * 260129198Scognet * XXXSCW: Fix for SMP ... 261129198Scognet */ 262129198Scognetunion pmap_cache_state *pmap_cache_state; 263129198Scognet 264129198Scognetstruct msgbuf *msgbufp = 0; 265129198Scognet 266184728Sraj/* 267184728Sraj * Crashdump maps. 268184728Sraj */ 269184728Srajstatic caddr_t crashdumpmap; 270184728Sraj 271129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 272129198Scognetextern void bzero_page(vm_offset_t); 273137362Scognet 274164079Scognetextern vm_offset_t alloc_firstaddr; 275164079Scognet 276137362Scognetchar *_tmppt; 277137362Scognet 278129198Scognet/* 279129198Scognet * Metadata for L1 translation tables. 280129198Scognet */ 281129198Scognetstruct l1_ttable { 282129198Scognet /* Entry on the L1 Table list */ 283129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 284129198Scognet 285129198Scognet /* Entry on the L1 Least Recently Used list */ 286129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 287129198Scognet 288129198Scognet /* Track how many domains are allocated from this L1 */ 289129198Scognet volatile u_int l1_domain_use_count; 290129198Scognet 291129198Scognet /* 292129198Scognet * A free-list of domain numbers for this L1. 293129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 294129198Scognet * is slow on ARM. 295129198Scognet */ 296129198Scognet u_int8_t l1_domain_first; 297129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 298129198Scognet 299129198Scognet /* Physical address of this L1 page table */ 300129198Scognet vm_paddr_t l1_physaddr; 301129198Scognet 302129198Scognet /* KVA of this L1 page table */ 303129198Scognet pd_entry_t *l1_kva; 304129198Scognet}; 305129198Scognet 306129198Scognet/* 307129198Scognet * Convert a virtual address into its L1 table index. That is, the 308129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 309129198Scognet * This is basically used to index l1->l1_kva[]. 310129198Scognet * 311129198Scognet * Each L2 descriptor table represents 1MB of VA space. 312129198Scognet */ 313129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 314129198Scognet 315129198Scognet/* 316129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 317129198Scognet * - New L1s are allocated from the HEAD. 318129198Scognet * - Freed L1s are added to the TAIl. 319129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 320129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 321129198Scognet */ 322129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 323135641Scognet/* 324135641Scognet * A list of all L1 tables 325135641Scognet */ 326135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 327129198Scognetstatic struct mtx l1_lru_lock; 328129198Scognet 329129198Scognet/* 330129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 331129198Scognet * 332129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 333129198Scognet * Reference counts are maintained for L2 descriptors so they can be 334129198Scognet * freed when empty. 335129198Scognet */ 336129198Scognetstruct l2_dtable { 337129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 338129198Scognet u_int l2_occupancy; 339129198Scognet 340129198Scognet /* List of L2 page descriptors */ 341129198Scognet struct l2_bucket { 342129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 343129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 344129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 345129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 346129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 347129198Scognet}; 348129198Scognet 349135641Scognet/* pmap_kenter_internal flags */ 350135641Scognet#define KENTER_CACHE 0x1 351142570Scognet#define KENTER_USER 0x2 352135641Scognet 353129198Scognet/* 354129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 355129198Scognet * and bucket index within the l2_dtable. 356129198Scognet */ 357129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 358129198Scognet (L2_SIZE - 1)) 359129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 360129198Scognet 361129198Scognet/* 362129198Scognet * Given a virtual address, this macro returns the 363129198Scognet * virtual address required to drop into the next L2 bucket. 364129198Scognet */ 365129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 366129198Scognet 367129198Scognet/* 368129198Scognet * L2 allocation. 369129198Scognet */ 370129198Scognet#define pmap_alloc_l2_dtable() \ 371160260Scognet (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE) 372129198Scognet#define pmap_free_l2_dtable(l2) \ 373129198Scognet uma_zfree(l2table_zone, l2) 374129198Scognet 375129198Scognet/* 376129198Scognet * We try to map the page tables write-through, if possible. However, not 377129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 378129198Scognet * the cache when we frob page tables. 379129198Scognet * 380129198Scognet * We try to evaluate this at compile time, if possible. However, it's 381129198Scognet * not always possible to do that, hence this run-time var. 382129198Scognet */ 383129198Scognetint pmap_needs_pte_sync; 384129198Scognet 385129198Scognet/* 386129198Scognet * Macro to determine if a mapping might be resident in the 387129198Scognet * instruction cache and/or TLB 388129198Scognet */ 389129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 390129198Scognet 391129198Scognet/* 392129198Scognet * Macro to determine if a mapping might be resident in the 393129198Scognet * data cache and/or TLB 394129198Scognet */ 395129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 396129198Scognet 397129198Scognet#ifndef PMAP_SHPGPERPROC 398129198Scognet#define PMAP_SHPGPERPROC 200 399129198Scognet#endif 400129198Scognet 401135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 402135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 403194459Sthompsastatic uma_zone_t pvzone = NULL; 404147114Scognetuma_zone_t l2zone; 405129198Scognetstatic uma_zone_t l2table_zone; 406135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 407135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 408135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 409129198Scognetstatic struct vm_object pvzone_obj; 410129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 411129198Scognet 412129198Scognet/* 413129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 414129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 415129198Scognet * find them as necessary. 416129198Scognet * 417129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 418129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 419129198Scognet */ 420129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 421129198Scognet 422129198Scognetstatic void 423129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 424129198Scognet{ 425129198Scognet int i; 426129198Scognet 427129198Scognet l1->l1_kva = l1pt; 428129198Scognet l1->l1_domain_use_count = 0; 429174181Scognet l1->l1_domain_first = 0; 430129198Scognet 431129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 432174181Scognet l1->l1_domain_free[i] = i + 1; 433129198Scognet 434129198Scognet /* 435129198Scognet * Copy the kernel's L1 entries to each new L1. 436129198Scognet */ 437147249Scognet if (l1pt != pmap_kernel()->pm_l1->l1_kva) 438129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 439129198Scognet 440129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 441129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 442135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 443129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 444129198Scognet} 445129198Scognet 446129198Scognetstatic vm_offset_t 447129198Scognetkernel_pt_lookup(vm_paddr_t pa) 448129198Scognet{ 449129198Scognet struct pv_addr *pv; 450129198Scognet 451129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 452129198Scognet if (pv->pv_pa == pa) 453129198Scognet return (pv->pv_va); 454129198Scognet } 455129198Scognet return (0); 456129198Scognet} 457129198Scognet 458129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 459129198Scognetvoid 460129198Scognetpmap_pte_init_generic(void) 461129198Scognet{ 462129198Scognet 463129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 464129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 465129198Scognet 466129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 467129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 468129198Scognet 469129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 470129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 471129198Scognet 472129198Scognet /* 473129198Scognet * If we have a write-through cache, set B and C. If 474129198Scognet * we have a write-back cache, then we assume setting 475129198Scognet * only C will make those pages write-through. 476129198Scognet */ 477129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 478129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 479129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 480129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 481129198Scognet } else { 482129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 483129198Scognet pte_l2_l_cache_mode_pt = L2_C; 484129198Scognet pte_l2_s_cache_mode_pt = L2_C; 485129198Scognet } 486129198Scognet 487129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 488129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 489129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 490129198Scognet 491129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 492129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 493129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 494129198Scognet 495129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 496129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 497129198Scognet} 498129198Scognet 499129198Scognet#if defined(CPU_ARM8) 500129198Scognetvoid 501129198Scognetpmap_pte_init_arm8(void) 502129198Scognet{ 503129198Scognet 504129198Scognet /* 505129198Scognet * ARM8 is compatible with generic, but we need to use 506129198Scognet * the page tables uncached. 507129198Scognet */ 508129198Scognet pmap_pte_init_generic(); 509129198Scognet 510129198Scognet pte_l1_s_cache_mode_pt = 0; 511129198Scognet pte_l2_l_cache_mode_pt = 0; 512129198Scognet pte_l2_s_cache_mode_pt = 0; 513129198Scognet} 514129198Scognet#endif /* CPU_ARM8 */ 515129198Scognet 516129198Scognet#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 517129198Scognetvoid 518129198Scognetpmap_pte_init_arm9(void) 519129198Scognet{ 520129198Scognet 521129198Scognet /* 522129198Scognet * ARM9 is compatible with generic, but we want to use 523129198Scognet * write-through caching for now. 524129198Scognet */ 525129198Scognet pmap_pte_init_generic(); 526129198Scognet 527129198Scognet pte_l1_s_cache_mode = L1_S_C; 528129198Scognet pte_l2_l_cache_mode = L2_C; 529129198Scognet pte_l2_s_cache_mode = L2_C; 530129198Scognet 531129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 532129198Scognet pte_l2_l_cache_mode_pt = L2_C; 533129198Scognet pte_l2_s_cache_mode_pt = L2_C; 534129198Scognet} 535129198Scognet#endif /* CPU_ARM9 */ 536129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 537129198Scognet 538129198Scognet#if defined(CPU_ARM10) 539129198Scognetvoid 540129198Scognetpmap_pte_init_arm10(void) 541129198Scognet{ 542129198Scognet 543129198Scognet /* 544129198Scognet * ARM10 is compatible with generic, but we want to use 545129198Scognet * write-through caching for now. 546129198Scognet */ 547129198Scognet pmap_pte_init_generic(); 548129198Scognet 549129198Scognet pte_l1_s_cache_mode = L1_S_B | L1_S_C; 550129198Scognet pte_l2_l_cache_mode = L2_B | L2_C; 551129198Scognet pte_l2_s_cache_mode = L2_B | L2_C; 552129198Scognet 553129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 554129198Scognet pte_l2_l_cache_mode_pt = L2_C; 555129198Scognet pte_l2_s_cache_mode_pt = L2_C; 556129198Scognet 557129198Scognet} 558129198Scognet#endif /* CPU_ARM10 */ 559129198Scognet 560129198Scognet#if ARM_MMU_SA1 == 1 561129198Scognetvoid 562129198Scognetpmap_pte_init_sa1(void) 563129198Scognet{ 564129198Scognet 565129198Scognet /* 566129198Scognet * The StrongARM SA-1 cache does not have a write-through 567129198Scognet * mode. So, do the generic initialization, then reset 568129198Scognet * the page table cache mode to B=1,C=1, and note that 569129198Scognet * the PTEs need to be sync'd. 570129198Scognet */ 571129198Scognet pmap_pte_init_generic(); 572129198Scognet 573129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 574129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 575129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 576129198Scognet 577129198Scognet pmap_needs_pte_sync = 1; 578129198Scognet} 579129198Scognet#endif /* ARM_MMU_SA1 == 1*/ 580129198Scognet 581129198Scognet#if ARM_MMU_XSCALE == 1 582164778Scognet#if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) 583129198Scognetstatic u_int xscale_use_minidata; 584129198Scognet#endif 585129198Scognet 586129198Scognetvoid 587129198Scognetpmap_pte_init_xscale(void) 588129198Scognet{ 589129198Scognet uint32_t auxctl; 590129198Scognet int write_through = 0; 591129198Scognet 592135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 593129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 594129198Scognet 595129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 596129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 597129198Scognet 598129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 599129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 600129198Scognet 601129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 602129198Scognet pte_l2_l_cache_mode_pt = L2_C; 603129198Scognet pte_l2_s_cache_mode_pt = L2_C; 604129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 605129198Scognet /* 606129198Scognet * The XScale core has an enhanced mode where writes that 607129198Scognet * miss the cache cause a cache line to be allocated. This 608129198Scognet * is significantly faster than the traditional, write-through 609129198Scognet * behavior of this case. 610129198Scognet */ 611129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 612129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 613129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 614129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 615129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 616129198Scognet /* 617129198Scognet * Some versions of the XScale core have various bugs in 618129198Scognet * their cache units, the work-around for which is to run 619129198Scognet * the cache in write-through mode. Unfortunately, this 620129198Scognet * has a major (negative) impact on performance. So, we 621129198Scognet * go ahead and run fast-and-loose, in the hopes that we 622129198Scognet * don't line up the planets in a way that will trip the 623129198Scognet * bugs. 624129198Scognet * 625129198Scognet * However, we give you the option to be slow-but-correct. 626129198Scognet */ 627129198Scognet write_through = 1; 628129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 629129198Scognet /* force write back cache mode */ 630129198Scognet write_through = 0; 631129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 632129198Scognet /* 633129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 634129198Scognet * write-back cache on revision 4 and earlier (stepping 635129198Scognet * A[01] and B[012]). Fixed for C0 and later. 636129198Scognet */ 637129198Scognet { 638129198Scognet uint32_t id, type; 639129198Scognet 640129198Scognet id = cpufunc_id(); 641129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 642129198Scognet 643129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 644129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 645129198Scognet /* write through for stepping A0-1 and B0-2 */ 646129198Scognet write_through = 1; 647129198Scognet } 648129198Scognet } 649129198Scognet } 650129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 651129198Scognet 652129198Scognet if (write_through) { 653129198Scognet pte_l1_s_cache_mode = L1_S_C; 654129198Scognet pte_l2_l_cache_mode = L2_C; 655129198Scognet pte_l2_s_cache_mode = L2_C; 656129198Scognet } 657129198Scognet 658129198Scognet#if (ARM_NMMUS > 1) 659129198Scognet xscale_use_minidata = 1; 660129198Scognet#endif 661129198Scognet 662129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 663129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 664129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 665129198Scognet 666129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 667129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 668129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 669129198Scognet 670164778Scognet#ifdef CPU_XSCALE_CORE3 671164778Scognet pmap_copy_page_func = pmap_copy_page_generic; 672164778Scognet pmap_zero_page_func = pmap_zero_page_generic; 673164778Scognet xscale_use_minidata = 0; 674171620Scognet /* Make sure it is L2-cachable */ 675171620Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T); 676171620Scognet pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P; 677171620Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ; 678171620Scognet pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode; 679171620Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T); 680171620Scognet pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 681171620Scognet 682164778Scognet#else 683129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 684129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 685164778Scognet#endif 686129198Scognet 687129198Scognet /* 688129198Scognet * Disable ECC protection of page table access, for now. 689129198Scognet */ 690129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 691129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 692129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 693129198Scognet} 694129198Scognet 695129198Scognet/* 696129198Scognet * xscale_setup_minidata: 697129198Scognet * 698129198Scognet * Set up the mini-data cache clean area. We require the 699129198Scognet * caller to allocate the right amount of physically and 700129198Scognet * virtually contiguous space. 701129198Scognet */ 702129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 703129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 704129198Scognetvoid 705129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 706129198Scognet{ 707129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 708129198Scognet pt_entry_t *pte; 709129198Scognet vm_size_t size; 710129198Scognet uint32_t auxctl; 711129198Scognet 712129198Scognet xscale_minidata_clean_addr = va; 713129198Scognet 714129198Scognet /* Round it to page size. */ 715129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 716129198Scognet 717129198Scognet for (; size != 0; 718129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 719129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 720129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 721129198Scognet if (pte == NULL) 722129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 723129198Scognet "VA 0x%08x", (u_int32_t) va); 724129198Scognet pte[l2pte_index(va)] = 725129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 726129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 727129198Scognet } 728129198Scognet 729129198Scognet /* 730129198Scognet * Configure the mini-data cache for write-back with 731129198Scognet * read/write-allocate. 732129198Scognet * 733129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 734129198Scognet * make sure it contains no valid data! In order to do that, 735129198Scognet * we must issue a global data cache invalidate command! 736129198Scognet * 737129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 738129198Scognet * THIS IS VERY IMPORTANT! 739129198Scognet */ 740129198Scognet 741129198Scognet /* Invalidate data and mini-data. */ 742129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 743129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 744129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 745129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 746129198Scognet} 747129198Scognet#endif 748129198Scognet 749129198Scognet/* 750129198Scognet * Allocate an L1 translation table for the specified pmap. 751129198Scognet * This is called at pmap creation time. 752129198Scognet */ 753129198Scognetstatic void 754129198Scognetpmap_alloc_l1(pmap_t pm) 755129198Scognet{ 756129198Scognet struct l1_ttable *l1; 757129198Scognet u_int8_t domain; 758129198Scognet 759129198Scognet /* 760129198Scognet * Remove the L1 at the head of the LRU list 761129198Scognet */ 762129198Scognet mtx_lock(&l1_lru_lock); 763129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 764129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 765129198Scognet 766129198Scognet /* 767129198Scognet * Pick the first available domain number, and update 768129198Scognet * the link to the next number. 769129198Scognet */ 770129198Scognet domain = l1->l1_domain_first; 771129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 772129198Scognet 773129198Scognet /* 774129198Scognet * If there are still free domain numbers in this L1, 775129198Scognet * put it back on the TAIL of the LRU list. 776129198Scognet */ 777129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 778129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 779129198Scognet 780129198Scognet mtx_unlock(&l1_lru_lock); 781129198Scognet 782129198Scognet /* 783129198Scognet * Fix up the relevant bits in the pmap structure 784129198Scognet */ 785129198Scognet pm->pm_l1 = l1; 786174181Scognet pm->pm_domain = domain + 1; 787129198Scognet} 788129198Scognet 789129198Scognet/* 790129198Scognet * Free an L1 translation table. 791129198Scognet * This is called at pmap destruction time. 792129198Scognet */ 793129198Scognetstatic void 794129198Scognetpmap_free_l1(pmap_t pm) 795129198Scognet{ 796129198Scognet struct l1_ttable *l1 = pm->pm_l1; 797129198Scognet 798129198Scognet mtx_lock(&l1_lru_lock); 799129198Scognet 800129198Scognet /* 801129198Scognet * If this L1 is currently on the LRU list, remove it. 802129198Scognet */ 803129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 804129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 805129198Scognet 806129198Scognet /* 807129198Scognet * Free up the domain number which was allocated to the pmap 808129198Scognet */ 809174181Scognet l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 810174181Scognet l1->l1_domain_first = pm->pm_domain - 1; 811129198Scognet l1->l1_domain_use_count--; 812129198Scognet 813129198Scognet /* 814129198Scognet * The L1 now must have at least 1 free domain, so add 815129198Scognet * it back to the LRU list. If the use count is zero, 816129198Scognet * put it at the head of the list, otherwise it goes 817129198Scognet * to the tail. 818129198Scognet */ 819129198Scognet if (l1->l1_domain_use_count == 0) { 820129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 821129198Scognet } else 822129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 823129198Scognet 824129198Scognet mtx_unlock(&l1_lru_lock); 825129198Scognet} 826129198Scognet 827129198Scognet/* 828129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 829129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 830129198Scognet */ 831129198Scognetstatic PMAP_INLINE struct l2_bucket * 832129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 833129198Scognet{ 834129198Scognet struct l2_dtable *l2; 835129198Scognet struct l2_bucket *l2b; 836129198Scognet u_short l1idx; 837129198Scognet 838129198Scognet l1idx = L1_IDX(va); 839129198Scognet 840129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 841129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 842129198Scognet return (NULL); 843129198Scognet 844129198Scognet return (l2b); 845129198Scognet} 846129198Scognet 847129198Scognet/* 848129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 849129198Scognet * and VA. 850129198Scognet * 851129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 852129198Scognet * bucket/page table in place. 853129198Scognet * 854129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 855236991Simp * increment the bucket occupancy counter appropriately *before* 856129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 857129198Scognet * the bucket/page in the meantime. 858129198Scognet */ 859129198Scognetstatic struct l2_bucket * 860129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 861129198Scognet{ 862129198Scognet struct l2_dtable *l2; 863129198Scognet struct l2_bucket *l2b; 864129198Scognet u_short l1idx; 865129198Scognet 866129198Scognet l1idx = L1_IDX(va); 867129198Scognet 868159352Salc PMAP_ASSERT_LOCKED(pm); 869159108Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 870129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 871129198Scognet /* 872129198Scognet * No mapping at this address, as there is 873129198Scognet * no entry in the L1 table. 874129198Scognet * Need to allocate a new l2_dtable. 875129198Scognet */ 876159108Scognetagain_l2table: 877159352Salc PMAP_UNLOCK(pm); 878159108Scognet vm_page_unlock_queues(); 879129198Scognet if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 880159108Scognet vm_page_lock_queues(); 881159352Salc PMAP_LOCK(pm); 882129198Scognet return (NULL); 883129198Scognet } 884159108Scognet vm_page_lock_queues(); 885159352Salc PMAP_LOCK(pm); 886159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 887159352Salc PMAP_UNLOCK(pm); 888159108Scognet vm_page_unlock_queues(); 889159108Scognet uma_zfree(l2table_zone, l2); 890159108Scognet vm_page_lock_queues(); 891159352Salc PMAP_LOCK(pm); 892159108Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 893159108Scognet if (l2 == NULL) 894159108Scognet goto again_l2table; 895159108Scognet /* 896159108Scognet * Someone already allocated the l2_dtable while 897159108Scognet * we were doing the same. 898159108Scognet */ 899159108Scognet } else { 900159108Scognet bzero(l2, sizeof(*l2)); 901159108Scognet /* 902159108Scognet * Link it into the parent pmap 903159108Scognet */ 904159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 905159108Scognet } 906236991Simp } 907129198Scognet 908129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 909129198Scognet 910129198Scognet /* 911129198Scognet * Fetch pointer to the L2 page table associated with the address. 912129198Scognet */ 913129198Scognet if (l2b->l2b_kva == NULL) { 914129198Scognet pt_entry_t *ptep; 915129198Scognet 916129198Scognet /* 917129198Scognet * No L2 page table has been allocated. Chances are, this 918129198Scognet * is because we just allocated the l2_dtable, above. 919129198Scognet */ 920159108Scognetagain_ptep: 921159352Salc PMAP_UNLOCK(pm); 922159108Scognet vm_page_unlock_queues(); 923160260Scognet ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE); 924159108Scognet vm_page_lock_queues(); 925159352Salc PMAP_LOCK(pm); 926159108Scognet if (l2b->l2b_kva != 0) { 927159108Scognet /* We lost the race. */ 928159352Salc PMAP_UNLOCK(pm); 929159108Scognet vm_page_unlock_queues(); 930159108Scognet uma_zfree(l2zone, ptep); 931159108Scognet vm_page_lock_queues(); 932159352Salc PMAP_LOCK(pm); 933159108Scognet if (l2b->l2b_kva == 0) 934159108Scognet goto again_ptep; 935159108Scognet return (l2b); 936159108Scognet } 937129198Scognet l2b->l2b_phys = vtophys(ptep); 938129198Scognet if (ptep == NULL) { 939129198Scognet /* 940129198Scognet * Oops, no more L2 page tables available at this 941129198Scognet * time. We may need to deallocate the l2_dtable 942129198Scognet * if we allocated a new one above. 943129198Scognet */ 944129198Scognet if (l2->l2_occupancy == 0) { 945129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 946129198Scognet pmap_free_l2_dtable(l2); 947129198Scognet } 948129198Scognet return (NULL); 949129198Scognet } 950129198Scognet 951129198Scognet l2->l2_occupancy++; 952129198Scognet l2b->l2b_kva = ptep; 953129198Scognet l2b->l2b_l1idx = l1idx; 954129198Scognet } 955129198Scognet 956129198Scognet return (l2b); 957129198Scognet} 958129198Scognet 959129198Scognetstatic PMAP_INLINE void 960129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 961129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 962129198Scognet#else 963129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 964129198Scognet#endif 965129198Scognet{ 966129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 967129198Scognet /* 968129198Scognet * Note: With a write-back cache, we may need to sync this 969129198Scognet * L2 table before re-using it. 970129198Scognet * This is because it may have belonged to a non-current 971129198Scognet * pmap, in which case the cache syncs would have been 972129198Scognet * skipped when the pages were being unmapped. If the 973129198Scognet * L2 table were then to be immediately re-allocated to 974129198Scognet * the *current* pmap, it may well contain stale mappings 975129198Scognet * which have not yet been cleared by a cache write-back 976129198Scognet * and so would still be visible to the mmu. 977129198Scognet */ 978129198Scognet if (need_sync) 979129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 980129198Scognet#endif 981129198Scognet uma_zfree(l2zone, l2); 982129198Scognet} 983129198Scognet/* 984129198Scognet * One or more mappings in the specified L2 descriptor table have just been 985129198Scognet * invalidated. 986129198Scognet * 987129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 988129198Scognet * 989129198Scognet * The pmap lock must be acquired when this is called (not necessary 990129198Scognet * for the kernel pmap). 991129198Scognet */ 992129198Scognetstatic void 993129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 994129198Scognet{ 995129198Scognet struct l2_dtable *l2; 996129198Scognet pd_entry_t *pl1pd, l1pd; 997129198Scognet pt_entry_t *ptep; 998129198Scognet u_short l1idx; 999129198Scognet 1000129198Scognet 1001129198Scognet /* 1002129198Scognet * Update the bucket's reference count according to how many 1003129198Scognet * PTEs the caller has just invalidated. 1004129198Scognet */ 1005129198Scognet l2b->l2b_occupancy -= count; 1006129198Scognet 1007129198Scognet /* 1008129198Scognet * Note: 1009129198Scognet * 1010129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 1011129198Scognet * as that would require checking all Level 1 page tables and 1012129198Scognet * removing any references to the Level 2 page table. See also the 1013129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 1014129198Scognet * 1015129198Scognet * We make do with just invalidating the mapping in the L2 table. 1016129198Scognet * 1017129198Scognet * This isn't really a big deal in practice and, in fact, leads 1018129198Scognet * to a performance win over time as we don't need to continually 1019129198Scognet * alloc/free. 1020129198Scognet */ 1021129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1022129198Scognet return; 1023129198Scognet 1024129198Scognet /* 1025129198Scognet * There are no more valid mappings in this level 2 page table. 1026129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 1027129198Scognet * free the page table. 1028129198Scognet */ 1029129198Scognet l1idx = l2b->l2b_l1idx; 1030129198Scognet ptep = l2b->l2b_kva; 1031129198Scognet l2b->l2b_kva = NULL; 1032129198Scognet 1033129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1034129198Scognet 1035129198Scognet /* 1036129198Scognet * If the L1 slot matches the pmap's domain 1037129198Scognet * number, then invalidate it. 1038129198Scognet */ 1039129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1040129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1041129198Scognet *pl1pd = 0; 1042129198Scognet PTE_SYNC(pl1pd); 1043129198Scognet } 1044129198Scognet 1045129198Scognet /* 1046129198Scognet * Release the L2 descriptor table back to the pool cache. 1047129198Scognet */ 1048129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1049129198Scognet pmap_free_l2_ptp(ptep); 1050129198Scognet#else 1051135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1052129198Scognet#endif 1053129198Scognet 1054129198Scognet /* 1055129198Scognet * Update the reference count in the associated l2_dtable 1056129198Scognet */ 1057129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1058129198Scognet if (--l2->l2_occupancy > 0) 1059129198Scognet return; 1060129198Scognet 1061129198Scognet /* 1062129198Scognet * There are no more valid mappings in any of the Level 1 1063129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 1064129198Scognet * the pointer in the parent pmap and free the l2_dtable. 1065129198Scognet */ 1066129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 1067129198Scognet pmap_free_l2_dtable(l2); 1068129198Scognet} 1069129198Scognet 1070129198Scognet/* 1071129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 1072129198Scognet * structures. 1073129198Scognet */ 1074133237Scognetstatic int 1075133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1076129198Scognet{ 1077129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1078129198Scognet struct l2_bucket *l2b; 1079129198Scognet pt_entry_t *ptep, pte; 1080147417Scognet#ifdef ARM_USE_SMALL_ALLOC 1081147417Scognet pd_entry_t *pde; 1082147417Scognet#endif 1083129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1084129198Scognet 1085129198Scognet /* 1086129198Scognet * The mappings for these page tables were initially made using 1087135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1088129198Scognet * mode will not be right for page table mappings. To avoid 1089135641Scognet * polluting the pmap_kenter() code with a special case for 1090129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1091129198Scognet * correct. 1092129198Scognet */ 1093147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1094147417Scognet pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)]; 1095147417Scognet if (!l1pte_section_p(*pde)) { 1096147114Scognet#endif 1097147114Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1098147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1099147114Scognet pte = *ptep; 1100161105Scognet 1101147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1102147114Scognet /* 1103236991Simp * Page tables must have the cache-mode set to 1104147114Scognet * Write-Thru. 1105147114Scognet */ 1106147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1107147114Scognet PTE_SYNC(ptep); 1108147114Scognet cpu_tlb_flushD_SE(va); 1109147114Scognet cpu_cpwait(); 1110147114Scognet } 1111147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1112129198Scognet } 1113129198Scognet#endif 1114147114Scognet#endif 1115129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1116129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1117133237Scognet return (0); 1118129198Scognet} 1119129198Scognet 1120129198Scognet/* 1121129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1122129198Scognet * on whether the specified pmap actually needs to be flushed at any 1123129198Scognet * given time. 1124129198Scognet */ 1125129198Scognetstatic PMAP_INLINE void 1126129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1127129198Scognet{ 1128129198Scognet 1129135641Scognet if (pmap_is_current(pm)) 1130129198Scognet cpu_tlb_flushID_SE(va); 1131129198Scognet} 1132129198Scognet 1133129198Scognetstatic PMAP_INLINE void 1134129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1135129198Scognet{ 1136129198Scognet 1137135641Scognet if (pmap_is_current(pm)) 1138129198Scognet cpu_tlb_flushD_SE(va); 1139129198Scognet} 1140129198Scognet 1141129198Scognetstatic PMAP_INLINE void 1142129198Scognetpmap_tlb_flushID(pmap_t pm) 1143129198Scognet{ 1144129198Scognet 1145135641Scognet if (pmap_is_current(pm)) 1146129198Scognet cpu_tlb_flushID(); 1147129198Scognet} 1148129198Scognetstatic PMAP_INLINE void 1149129198Scognetpmap_tlb_flushD(pmap_t pm) 1150129198Scognet{ 1151129198Scognet 1152135641Scognet if (pmap_is_current(pm)) 1153129198Scognet cpu_tlb_flushD(); 1154129198Scognet} 1155129198Scognet 1156203637Srajstatic int 1157203637Srajpmap_has_valid_mapping(pmap_t pm, vm_offset_t va) 1158183838Sraj{ 1159183838Sraj pd_entry_t *pde; 1160183838Sraj pt_entry_t *ptep; 1161183838Sraj 1162203637Sraj if (pmap_get_pde_pte(pm, va, &pde, &ptep) && 1163203637Sraj ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV)) 1164203637Sraj return (1); 1165183838Sraj 1166203637Sraj return (0); 1167183838Sraj} 1168183838Sraj 1169183838Srajstatic PMAP_INLINE void 1170129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1171129198Scognet{ 1172183838Sraj vm_size_t rest; 1173129198Scognet 1174203637Sraj CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x" 1175203637Sraj " len 0x%x ", pm, pm == pmap_kernel(), va, len); 1176183838Sraj 1177203637Sraj if (pmap_is_current(pm) || pm == pmap_kernel()) { 1178203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1179203637Sraj while (len > 0) { 1180203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1181203637Sraj cpu_idcache_wbinv_range(va, rest); 1182203637Sraj cpu_l2cache_wbinv_range(va, rest); 1183203637Sraj } 1184203637Sraj len -= rest; 1185203637Sraj va += rest; 1186203637Sraj rest = MIN(PAGE_SIZE, len); 1187203637Sraj } 1188183838Sraj } 1189183838Sraj} 1190183838Sraj 1191183838Srajstatic PMAP_INLINE void 1192183838Srajpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv, 1193183838Sraj boolean_t rd_only) 1194183838Sraj{ 1195203637Sraj vm_size_t rest; 1196184730Sraj 1197183838Sraj CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x " 1198183838Sraj "len 0x%x ", pm, pm == pmap_kernel(), va, len); 1199183838Sraj CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only); 1200183838Sraj 1201135641Scognet if (pmap_is_current(pm)) { 1202203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1203203637Sraj while (len > 0) { 1204203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1205203637Sraj if (do_inv && rd_only) { 1206203637Sraj cpu_dcache_inv_range(va, rest); 1207203637Sraj cpu_l2cache_inv_range(va, rest); 1208203637Sraj } else if (do_inv) { 1209203637Sraj cpu_dcache_wbinv_range(va, rest); 1210203637Sraj cpu_l2cache_wbinv_range(va, rest); 1211203637Sraj } else if (!rd_only) { 1212203637Sraj cpu_dcache_wb_range(va, rest); 1213203637Sraj cpu_l2cache_wb_range(va, rest); 1214203637Sraj } 1215183838Sraj } 1216203637Sraj len -= rest; 1217203637Sraj va += rest; 1218203637Sraj 1219203637Sraj rest = MIN(PAGE_SIZE, len); 1220183838Sraj } 1221129198Scognet } 1222129198Scognet} 1223129198Scognet 1224129198Scognetstatic PMAP_INLINE void 1225129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1226129198Scognet{ 1227129198Scognet 1228183838Sraj if (pmap_is_current(pm)) { 1229129198Scognet cpu_idcache_wbinv_all(); 1230183838Sraj cpu_l2cache_wbinv_all(); 1231183838Sraj } 1232129198Scognet} 1233129198Scognet 1234197770Sstas#ifdef notyet 1235129198Scognetstatic PMAP_INLINE void 1236129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1237129198Scognet{ 1238129198Scognet 1239183838Sraj if (pmap_is_current(pm)) { 1240129198Scognet cpu_dcache_wbinv_all(); 1241183838Sraj cpu_l2cache_wbinv_all(); 1242183838Sraj } 1243129198Scognet} 1244197770Sstas#endif 1245129198Scognet 1246129198Scognet/* 1247129198Scognet * PTE_SYNC_CURRENT: 1248129198Scognet * 1249129198Scognet * Make sure the pte is written out to RAM. 1250129198Scognet * We need to do this for one of two cases: 1251129198Scognet * - We're dealing with the kernel pmap 1252129198Scognet * - There is no pmap active in the cache/tlb. 1253129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1254129198Scognet */ 1255129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1256129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1257129198Scognetdo { \ 1258129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1259135641Scognet pmap_is_current(pm)) \ 1260129198Scognet PTE_SYNC(ptep); \ 1261129198Scognet} while (/*CONSTCOND*/0) 1262129198Scognet#else 1263129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1264129198Scognet#endif 1265129198Scognet 1266129198Scognet/* 1267175840Scognet * cacheable == -1 means we must make the entry uncacheable, 1 means 1268175840Scognet * cacheable; 1269129198Scognet */ 1270129198Scognetstatic __inline void 1271175840Scognetpmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable) 1272129198Scognet{ 1273175840Scognet struct l2_bucket *l2b; 1274175840Scognet pt_entry_t *ptep, pte; 1275129198Scognet 1276175840Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1277175840Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1278129198Scognet 1279175840Scognet if (cacheable == 1) { 1280175840Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1281175840Scognet if (l2pte_valid(pte)) { 1282175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1283175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1284175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1285175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1286175840Scognet } 1287175840Scognet } 1288175840Scognet } else { 1289175840Scognet pte = *ptep &~ L2_S_CACHE_MASK; 1290175840Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1291175840Scognet l2pte_valid(pte)) { 1292175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1293175840Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1294175840Scognet pv->pv_va, PAGE_SIZE); 1295175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1296175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1297175840Scognet pmap_dcache_wb_range(pv->pv_pmap, 1298175840Scognet pv->pv_va, PAGE_SIZE, TRUE, 1299175840Scognet (pv->pv_flags & PVF_WRITE) == 0); 1300175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1301175840Scognet pv->pv_va); 1302175840Scognet } 1303175840Scognet } 1304129198Scognet } 1305175840Scognet *ptep = pte; 1306175840Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1307129198Scognet} 1308129198Scognet 1309129198Scognetstatic void 1310175840Scognetpmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1311129198Scognet{ 1312175840Scognet int pmwc = 0; 1313175840Scognet int writable = 0, kwritable = 0, uwritable = 0; 1314175840Scognet int entries = 0, kentries = 0, uentries = 0; 1315129198Scognet struct pv_entry *pv; 1316129198Scognet 1317175840Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1318129198Scognet 1319175840Scognet /* the cache gets written back/invalidated on context switch. 1320175840Scognet * therefore, if a user page shares an entry in the same page or 1321175840Scognet * with the kernel map and at least one is writable, then the 1322175840Scognet * cache entry must be set write-through. 1323129198Scognet */ 1324129198Scognet 1325175840Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1326175840Scognet /* generate a count of the pv_entry uses */ 1327175840Scognet if (pv->pv_flags & PVF_WRITE) { 1328175840Scognet if (pv->pv_pmap == pmap_kernel()) 1329175840Scognet kwritable++; 1330175840Scognet else if (pv->pv_pmap == pm) 1331175840Scognet uwritable++; 1332175840Scognet writable++; 1333129198Scognet } 1334175840Scognet if (pv->pv_pmap == pmap_kernel()) 1335175840Scognet kentries++; 1336175840Scognet else { 1337175840Scognet if (pv->pv_pmap == pm) 1338175840Scognet uentries++; 1339175840Scognet entries++; 1340175840Scognet } 1341129198Scognet } 1342175840Scognet /* 1343175840Scognet * check if the user duplicate mapping has 1344175840Scognet * been removed. 1345175840Scognet */ 1346175840Scognet if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) || 1347175840Scognet (uwritable > 1))) 1348175840Scognet pmwc = 1; 1349129198Scognet 1350129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1351175840Scognet /* check for user uncachable conditions - order is important */ 1352175840Scognet if (pm != pmap_kernel() && 1353175840Scognet (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) { 1354129198Scognet 1355175840Scognet if ((uentries > 1 && uwritable) || uwritable > 1) { 1356129198Scognet 1357175840Scognet /* user duplicate mapping */ 1358175840Scognet if (pv->pv_pmap != pmap_kernel()) 1359175840Scognet pv->pv_flags |= PVF_MWC; 1360129198Scognet 1361175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1362175840Scognet pv->pv_flags |= PVF_NC; 1363175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1364175840Scognet } 1365129198Scognet continue; 1366175840Scognet } else /* no longer a duplicate user */ 1367175840Scognet pv->pv_flags &= ~PVF_MWC; 1368175840Scognet } 1369129198Scognet 1370175840Scognet /* 1371175840Scognet * check for kernel uncachable conditions 1372175840Scognet * kernel writable or kernel readable with writable user entry 1373175840Scognet */ 1374209223Scognet if ((kwritable && (entries || kentries > 1)) || 1375194459Sthompsa (kwritable > 1) || 1376175840Scognet ((kwritable != writable) && kentries && 1377175840Scognet (pv->pv_pmap == pmap_kernel() || 1378175840Scognet (pv->pv_flags & PVF_WRITE) || 1379175840Scognet (pv->pv_flags & PVF_MWC)))) { 1380129198Scognet 1381175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1382175840Scognet pv->pv_flags |= PVF_NC; 1383175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1384129198Scognet } 1385175840Scognet continue; 1386129198Scognet } 1387129198Scognet 1388175840Scognet /* kernel and user are cachable */ 1389175840Scognet if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) && 1390175840Scognet (pv->pv_flags & PVF_NC)) { 1391175840Scognet 1392129198Scognet pv->pv_flags &= ~PVF_NC; 1393175840Scognet pmap_set_cache_entry(pv, pm, va, 1); 1394175840Scognet continue; 1395175840Scognet } 1396175840Scognet /* user is no longer sharable and writable */ 1397194459Sthompsa if (pm != pmap_kernel() && 1398194459Sthompsa (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) && 1399175840Scognet !pmwc && (pv->pv_flags & PVF_NC)) { 1400129198Scognet 1401175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1402175840Scognet pmap_set_cache_entry(pv, pm, va, 1); 1403129198Scognet } 1404129198Scognet } 1405175840Scognet 1406175840Scognet if ((kwritable == 0) && (writable == 0)) { 1407175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1408225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1409175840Scognet return; 1410175840Scognet } 1411129198Scognet} 1412129198Scognet 1413129198Scognet/* 1414129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1415129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1416129198Scognet * constants and the latter would require an extra inversion at run-time. 1417129198Scognet */ 1418236991Simpstatic int 1419129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1420129198Scognet{ 1421129198Scognet struct l2_bucket *l2b; 1422129198Scognet struct pv_entry *pv; 1423129198Scognet pt_entry_t *ptep, npte, opte; 1424129198Scognet pmap_t pm; 1425129198Scognet vm_offset_t va; 1426129198Scognet u_int oflags; 1427135641Scognet int count = 0; 1428129198Scognet 1429208990Salc vm_page_lock_queues(); 1430159352Salc 1431175840Scognet if (maskbits & PVF_WRITE) 1432175840Scognet maskbits |= PVF_MOD; 1433129198Scognet /* 1434129198Scognet * Clear saved attributes (modify, reference) 1435129198Scognet */ 1436129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1437129198Scognet 1438129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1439208990Salc vm_page_unlock_queues(); 1440135641Scognet return (0); 1441129198Scognet } 1442129198Scognet 1443129198Scognet /* 1444129198Scognet * Loop over all current mappings setting/clearing as appropos 1445129198Scognet */ 1446129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1447129198Scognet va = pv->pv_va; 1448129198Scognet pm = pv->pv_pmap; 1449129198Scognet oflags = pv->pv_flags; 1450175840Scognet 1451175840Scognet if (!(oflags & maskbits)) { 1452175840Scognet if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) { 1453175840Scognet /* It is safe to re-enable cacheing here. */ 1454175840Scognet PMAP_LOCK(pm); 1455175840Scognet l2b = pmap_get_l2_bucket(pm, va); 1456175840Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1457175840Scognet *ptep |= pte_l2_s_cache_mode; 1458175840Scognet PTE_SYNC(ptep); 1459175840Scognet PMAP_UNLOCK(pm); 1460175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1461175840Scognet 1462175840Scognet } 1463175840Scognet continue; 1464175840Scognet } 1465129198Scognet pv->pv_flags &= ~maskbits; 1466129198Scognet 1467159352Salc PMAP_LOCK(pm); 1468129198Scognet 1469129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1470129198Scognet 1471129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1472129198Scognet npte = opte = *ptep; 1473129198Scognet 1474157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1475129198Scognet if ((pv->pv_flags & PVF_NC)) { 1476236991Simp /* 1477129198Scognet * Entry is not cacheable: 1478129198Scognet * 1479236991Simp * Don't turn caching on again if this is a 1480129198Scognet * modified emulation. This would be 1481129198Scognet * inconsitent with the settings created by 1482175840Scognet * pmap_fix_cache(). Otherwise, it's safe 1483129198Scognet * to re-enable cacheing. 1484129198Scognet * 1485175840Scognet * There's no need to call pmap_fix_cache() 1486129198Scognet * here: all pages are losing their write 1487129198Scognet * permission. 1488129198Scognet */ 1489129198Scognet if (maskbits & PVF_WRITE) { 1490129198Scognet npte |= pte_l2_s_cache_mode; 1491175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1492129198Scognet } 1493129198Scognet } else 1494129198Scognet if (opte & L2_S_PROT_W) { 1495144760Scognet vm_page_dirty(pg); 1496236991Simp /* 1497129198Scognet * Entry is writable/cacheable: check if pmap 1498129198Scognet * is current if it is flush it, otherwise it 1499129198Scognet * won't be in the cache 1500129198Scognet */ 1501129198Scognet if (PV_BEEN_EXECD(oflags)) 1502129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1503129198Scognet PAGE_SIZE); 1504129198Scognet else 1505129198Scognet if (PV_BEEN_REFD(oflags)) 1506129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1507129198Scognet PAGE_SIZE, 1508129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1509129198Scognet FALSE); 1510129198Scognet } 1511129198Scognet 1512129198Scognet /* make the pte read only */ 1513129198Scognet npte &= ~L2_S_PROT_W; 1514129198Scognet } 1515129198Scognet 1516157970Scognet if (maskbits & PVF_REF) { 1517129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1518129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1519129198Scognet /* 1520129198Scognet * Check npte here; we may have already 1521129198Scognet * done the wbinv above, and the validity 1522129198Scognet * of the PTE is the same for opte and 1523129198Scognet * npte. 1524129198Scognet */ 1525129198Scognet if (npte & L2_S_PROT_W) { 1526129198Scognet if (PV_BEEN_EXECD(oflags)) 1527129198Scognet pmap_idcache_wbinv_range(pm, 1528129198Scognet pv->pv_va, PAGE_SIZE); 1529129198Scognet else 1530129198Scognet if (PV_BEEN_REFD(oflags)) 1531129198Scognet pmap_dcache_wb_range(pm, 1532129198Scognet pv->pv_va, PAGE_SIZE, 1533129198Scognet TRUE, FALSE); 1534129198Scognet } else 1535129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1536129198Scognet /* XXXJRT need idcache_inv_range */ 1537129198Scognet if (PV_BEEN_EXECD(oflags)) 1538129198Scognet pmap_idcache_wbinv_range(pm, 1539129198Scognet pv->pv_va, PAGE_SIZE); 1540129198Scognet else 1541129198Scognet if (PV_BEEN_REFD(oflags)) 1542129198Scognet pmap_dcache_wb_range(pm, 1543129198Scognet pv->pv_va, PAGE_SIZE, 1544129198Scognet TRUE, TRUE); 1545129198Scognet } 1546129198Scognet } 1547129198Scognet 1548129198Scognet /* 1549129198Scognet * Make the PTE invalid so that we will take a 1550129198Scognet * page fault the next time the mapping is 1551129198Scognet * referenced. 1552129198Scognet */ 1553129198Scognet npte &= ~L2_TYPE_MASK; 1554129198Scognet npte |= L2_TYPE_INV; 1555129198Scognet } 1556129198Scognet 1557129198Scognet if (npte != opte) { 1558135641Scognet count++; 1559129198Scognet *ptep = npte; 1560129198Scognet PTE_SYNC(ptep); 1561129198Scognet /* Flush the TLB entry if a current pmap. */ 1562129198Scognet if (PV_BEEN_EXECD(oflags)) 1563129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1564129198Scognet else 1565129198Scognet if (PV_BEEN_REFD(oflags)) 1566129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1567129198Scognet } 1568129198Scognet 1569159352Salc PMAP_UNLOCK(pm); 1570129198Scognet 1571129198Scognet } 1572129198Scognet 1573137664Scognet if (maskbits & PVF_WRITE) 1574225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1575208990Salc vm_page_unlock_queues(); 1576135641Scognet return (count); 1577129198Scognet} 1578129198Scognet 1579129198Scognet/* 1580129198Scognet * main pv_entry manipulation functions: 1581129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1582129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1583129198Scognet * 1584129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1585129198Scognet * pmap_remove_pv expects te caller to lock the pvh before calling 1586129198Scognet */ 1587129198Scognet 1588129198Scognet/* 1589129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page lst 1590129198Scognet * 1591129198Scognet * => caller should hold the proper lock on pmap_main_lock 1592129198Scognet * => caller should have pmap locked 1593129198Scognet * => we will gain the lock on the vm_page and allocate the new pv_entry 1594129198Scognet * => caller should adjust ptp's wire_count before calling 1595129198Scognet * => caller should not adjust pmap's wire_count 1596129198Scognet */ 1597129198Scognetstatic void 1598129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1599129198Scognet vm_offset_t va, u_int flags) 1600129198Scognet{ 1601129198Scognet 1602194459Sthompsa int km; 1603194459Sthompsa 1604159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1605194459Sthompsa 1606194459Sthompsa if (pg->md.pv_kva) { 1607194459Sthompsa /* PMAP_ASSERT_LOCKED(pmap_kernel()); */ 1608194459Sthompsa pve->pv_pmap = pmap_kernel(); 1609194459Sthompsa pve->pv_va = pg->md.pv_kva; 1610194459Sthompsa pve->pv_flags = PVF_WRITE | PVF_UNMAN; 1611194459Sthompsa pg->md.pv_kva = 0; 1612194459Sthompsa 1613205425Scognet if (!(km = PMAP_OWNED(pmap_kernel()))) 1614205425Scognet PMAP_LOCK(pmap_kernel()); 1615194459Sthompsa TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1616205425Scognet TAILQ_INSERT_HEAD(&pve->pv_pmap->pm_pvlist, pve, pv_plist); 1617205425Scognet PMAP_UNLOCK(pmap_kernel()); 1618194459Sthompsa vm_page_unlock_queues(); 1619194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 1620194459Sthompsa panic("pmap_kenter_internal: no pv entries"); 1621194459Sthompsa vm_page_lock_queues(); 1622194459Sthompsa if (km) 1623194459Sthompsa PMAP_LOCK(pmap_kernel()); 1624194459Sthompsa } 1625194459Sthompsa 1626159352Salc PMAP_ASSERT_LOCKED(pm); 1627129198Scognet pve->pv_pmap = pm; 1628129198Scognet pve->pv_va = va; 1629129198Scognet pve->pv_flags = flags; 1630129198Scognet 1631129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1632144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1633129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1634129198Scognet if (pve->pv_flags & PVF_WIRED) 1635129198Scognet ++pm->pm_stats.wired_count; 1636225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1637129198Scognet} 1638129198Scognet 1639129198Scognet/* 1640129198Scognet * 1641129198Scognet * pmap_find_pv: Find a pv entry 1642129198Scognet * 1643129198Scognet * => caller should hold lock on vm_page 1644129198Scognet */ 1645129198Scognetstatic PMAP_INLINE struct pv_entry * 1646129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1647129198Scognet{ 1648129198Scognet struct pv_entry *pv; 1649129198Scognet 1650159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1651129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1652129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1653129198Scognet break; 1654129198Scognet return (pv); 1655129198Scognet} 1656129198Scognet 1657129198Scognet/* 1658129198Scognet * vector_page_setprot: 1659129198Scognet * 1660129198Scognet * Manipulate the protection of the vector page. 1661129198Scognet */ 1662129198Scognetvoid 1663129198Scognetvector_page_setprot(int prot) 1664129198Scognet{ 1665129198Scognet struct l2_bucket *l2b; 1666129198Scognet pt_entry_t *ptep; 1667129198Scognet 1668129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1669129198Scognet 1670129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1671129198Scognet 1672129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1673129198Scognet PTE_SYNC(ptep); 1674129198Scognet cpu_tlb_flushD_SE(vector_page); 1675129198Scognet cpu_cpwait(); 1676129198Scognet} 1677129198Scognet 1678129198Scognet/* 1679129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1680129198Scognet * 1681129198Scognet * => caller should hold proper lock on pmap_main_lock 1682129198Scognet * => pmap should be locked 1683129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1684129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1685129198Scognet * => caller should NOT adjust pmap's wire_count 1686129198Scognet * => we return the removed pve 1687129198Scognet */ 1688135641Scognet 1689135641Scognetstatic void 1690135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1691135641Scognet{ 1692135641Scognet 1693194459Sthompsa struct pv_entry *pv; 1694159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1695159352Salc PMAP_ASSERT_LOCKED(pm); 1696135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1697144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1698135641Scognet if (pve->pv_flags & PVF_WIRED) 1699135641Scognet --pm->pm_stats.wired_count; 1700144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1701144760Scognet vm_page_dirty(pg); 1702175840Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1703175840Scognet pg->md.pvh_attrs &= ~PVF_REF; 1704175840Scognet else 1705225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1706175840Scognet if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) || 1707175840Scognet (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC))) 1708175840Scognet pmap_fix_cache(pg, pm, 0); 1709175840Scognet else if (pve->pv_flags & PVF_WRITE) { 1710175840Scognet TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list) 1711175840Scognet if (pve->pv_flags & PVF_WRITE) 1712175840Scognet break; 1713175840Scognet if (!pve) { 1714175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1715225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1716175840Scognet } 1717146647Scognet } 1718194459Sthompsa pv = TAILQ_FIRST(&pg->md.pv_list); 1719194459Sthompsa if (pv != NULL && (pv->pv_flags & PVF_UNMAN) && 1720194459Sthompsa TAILQ_NEXT(pv, pv_list) == NULL) { 1721205425Scognet pm = kernel_pmap; 1722194459Sthompsa pg->md.pv_kva = pv->pv_va; 1723194459Sthompsa /* a recursive pmap_nuke_pv */ 1724194459Sthompsa TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list); 1725194459Sthompsa TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist); 1726194459Sthompsa if (pv->pv_flags & PVF_WIRED) 1727194459Sthompsa --pm->pm_stats.wired_count; 1728194459Sthompsa pg->md.pvh_attrs &= ~PVF_REF; 1729194459Sthompsa pg->md.pvh_attrs &= ~PVF_MOD; 1730225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1731194459Sthompsa pmap_free_pv_entry(pv); 1732194459Sthompsa } 1733135641Scognet} 1734135641Scognet 1735129198Scognetstatic struct pv_entry * 1736129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1737129198Scognet{ 1738135641Scognet struct pv_entry *pve; 1739129198Scognet 1740159474Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1741135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1742129198Scognet 1743129198Scognet while (pve) { 1744129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1745135641Scognet pmap_nuke_pv(pg, pm, pve); 1746129198Scognet break; 1747129198Scognet } 1748129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1749129198Scognet } 1750129198Scognet 1751194459Sthompsa if (pve == NULL && pg->md.pv_kva == va) 1752194459Sthompsa pg->md.pv_kva = 0; 1753194459Sthompsa 1754129198Scognet return(pve); /* return removed pve */ 1755129198Scognet} 1756129198Scognet/* 1757129198Scognet * 1758129198Scognet * pmap_modify_pv: Update pv flags 1759129198Scognet * 1760129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1761129198Scognet * => caller should NOT adjust pmap's wire_count 1762129198Scognet * => we return the old flags 1763236991Simp * 1764129198Scognet * Modify a physical-virtual mapping in the pv table 1765129198Scognet */ 1766129198Scognetstatic u_int 1767129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1768129198Scognet u_int clr_mask, u_int set_mask) 1769129198Scognet{ 1770129198Scognet struct pv_entry *npv; 1771129198Scognet u_int flags, oflags; 1772129198Scognet 1773159352Salc PMAP_ASSERT_LOCKED(pm); 1774159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1775129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1776129198Scognet return (0); 1777129198Scognet 1778129198Scognet /* 1779129198Scognet * There is at least one VA mapping this page. 1780129198Scognet */ 1781129198Scognet 1782129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1783129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1784129198Scognet 1785129198Scognet oflags = npv->pv_flags; 1786129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1787129198Scognet 1788129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1789129198Scognet if (flags & PVF_WIRED) 1790129198Scognet ++pm->pm_stats.wired_count; 1791129198Scognet else 1792129198Scognet --pm->pm_stats.wired_count; 1793129198Scognet } 1794129198Scognet 1795175840Scognet if ((flags ^ oflags) & PVF_WRITE) 1796175840Scognet pmap_fix_cache(pg, pm, 0); 1797129198Scognet 1798129198Scognet return (oflags); 1799129198Scognet} 1800129198Scognet 1801129198Scognet/* Function to set the debug level of the pmap code */ 1802129198Scognet#ifdef PMAP_DEBUG 1803129198Scognetvoid 1804129198Scognetpmap_debug(int level) 1805129198Scognet{ 1806129198Scognet pmap_debug_level = level; 1807129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1808129198Scognet} 1809129198Scognet#endif /* PMAP_DEBUG */ 1810129198Scognet 1811129198Scognetvoid 1812129198Scognetpmap_pinit0(struct pmap *pmap) 1813129198Scognet{ 1814129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1815129198Scognet 1816129198Scognet dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1817129198Scognet (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1818135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1819159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1820159325Salc PMAP_LOCK_INIT(pmap); 1821129198Scognet} 1822129198Scognet 1823147217Salc/* 1824147217Salc * Initialize a vm_page's machine-dependent fields. 1825147217Salc */ 1826147217Salcvoid 1827147217Salcpmap_page_init(vm_page_t m) 1828147217Salc{ 1829129198Scognet 1830147217Salc TAILQ_INIT(&m->md.pv_list); 1831147217Salc} 1832147217Salc 1833129198Scognet/* 1834129198Scognet * Initialize the pmap module. 1835129198Scognet * Called by vm_init, to initialize any structures that the pmap 1836129198Scognet * system needs to map virtual memory. 1837129198Scognet */ 1838129198Scognetvoid 1839129198Scognetpmap_init(void) 1840129198Scognet{ 1841152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1842129198Scognet 1843197770Sstas PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR)); 1844147114Scognet 1845129198Scognet /* 1846129198Scognet * init the pv free list 1847129198Scognet */ 1848236991Simp pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1849129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1850129198Scognet /* 1851129198Scognet * Now it is safe to enable pv_table recording. 1852129198Scognet */ 1853129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1854147114Scognet 1855152128Scognet TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1856152128Scognet 1857170170Sattilio pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1858152128Scognet pv_entry_high_water = 9 * (pv_entry_max / 10); 1859152128Scognet l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1860152128Scognet NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1861152128Scognet l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 1862152128Scognet NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1863152128Scognet UMA_ZONE_VM | UMA_ZONE_NOFREE); 1864152128Scognet 1865152128Scognet uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1866152128Scognet 1867129198Scognet} 1868129198Scognet 1869129198Scognetint 1870129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1871129198Scognet{ 1872129198Scognet struct l2_dtable *l2; 1873129198Scognet struct l2_bucket *l2b; 1874129198Scognet pd_entry_t *pl1pd, l1pd; 1875129198Scognet pt_entry_t *ptep, pte; 1876129198Scognet vm_paddr_t pa; 1877129198Scognet u_int l1idx; 1878129198Scognet int rv = 0; 1879129198Scognet 1880129198Scognet l1idx = L1_IDX(va); 1881159384Salc vm_page_lock_queues(); 1882159384Salc PMAP_LOCK(pm); 1883129198Scognet 1884129198Scognet /* 1885129198Scognet * If there is no l2_dtable for this address, then the process 1886129198Scognet * has no business accessing it. 1887129198Scognet * 1888129198Scognet * Note: This will catch userland processes trying to access 1889129198Scognet * kernel addresses. 1890129198Scognet */ 1891129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1892129198Scognet if (l2 == NULL) 1893129198Scognet goto out; 1894129198Scognet 1895129198Scognet /* 1896129198Scognet * Likewise if there is no L2 descriptor table 1897129198Scognet */ 1898129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1899129198Scognet if (l2b->l2b_kva == NULL) 1900129198Scognet goto out; 1901129198Scognet 1902129198Scognet /* 1903129198Scognet * Check the PTE itself. 1904129198Scognet */ 1905129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1906129198Scognet pte = *ptep; 1907129198Scognet if (pte == 0) 1908129198Scognet goto out; 1909129198Scognet 1910129198Scognet /* 1911129198Scognet * Catch a userland access to the vector page mapped at 0x0 1912129198Scognet */ 1913129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 1914129198Scognet goto out; 1915157027Scognet if (va == vector_page) 1916157027Scognet goto out; 1917129198Scognet 1918129198Scognet pa = l2pte_pa(pte); 1919129198Scognet 1920129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 1921129198Scognet /* 1922129198Scognet * This looks like a good candidate for "page modified" 1923129198Scognet * emulation... 1924129198Scognet */ 1925129198Scognet struct pv_entry *pv; 1926129198Scognet struct vm_page *pg; 1927129198Scognet 1928129198Scognet /* Extract the physical address of the page */ 1929129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 1930129198Scognet goto out; 1931129198Scognet } 1932129198Scognet /* Get the current flags for this page. */ 1933129198Scognet 1934129198Scognet pv = pmap_find_pv(pg, pm, va); 1935129198Scognet if (pv == NULL) { 1936129198Scognet goto out; 1937129198Scognet } 1938129198Scognet 1939129198Scognet /* 1940129198Scognet * Do the flags say this page is writable? If not then it 1941129198Scognet * is a genuine write fault. If yes then the write fault is 1942129198Scognet * our fault as we did not reflect the write access in the 1943129198Scognet * PTE. Now we know a write has occurred we can correct this 1944129198Scognet * and also set the modified bit 1945129198Scognet */ 1946129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 1947129198Scognet goto out; 1948129198Scognet } 1949129198Scognet 1950157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 1951157970Scognet vm_page_dirty(pg); 1952129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 1953129198Scognet 1954236991Simp /* 1955129198Scognet * Re-enable write permissions for the page. No need to call 1956175840Scognet * pmap_fix_cache(), since this is just a 1957129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 1958129198Scognet * changing. We've already set the cacheable bits based on 1959129198Scognet * the assumption that we can write to this page. 1960129198Scognet */ 1961147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 1962129198Scognet PTE_SYNC(ptep); 1963129198Scognet rv = 1; 1964129198Scognet } else 1965129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 1966129198Scognet /* 1967129198Scognet * This looks like a good candidate for "page referenced" 1968129198Scognet * emulation. 1969129198Scognet */ 1970129198Scognet struct pv_entry *pv; 1971129198Scognet struct vm_page *pg; 1972129198Scognet 1973129198Scognet /* Extract the physical address of the page */ 1974159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 1975129198Scognet goto out; 1976129198Scognet /* Get the current flags for this page. */ 1977129198Scognet 1978129198Scognet pv = pmap_find_pv(pg, pm, va); 1979159384Salc if (pv == NULL) 1980129198Scognet goto out; 1981129198Scognet 1982129198Scognet pg->md.pvh_attrs |= PVF_REF; 1983129198Scognet pv->pv_flags |= PVF_REF; 1984129198Scognet 1985129198Scognet 1986129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 1987129198Scognet PTE_SYNC(ptep); 1988129198Scognet rv = 1; 1989129198Scognet } 1990129198Scognet 1991129198Scognet /* 1992129198Scognet * We know there is a valid mapping here, so simply 1993129198Scognet * fix up the L1 if necessary. 1994129198Scognet */ 1995129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1996129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 1997129198Scognet if (*pl1pd != l1pd) { 1998129198Scognet *pl1pd = l1pd; 1999129198Scognet PTE_SYNC(pl1pd); 2000129198Scognet rv = 1; 2001129198Scognet } 2002129198Scognet 2003129198Scognet#ifdef CPU_SA110 2004129198Scognet /* 2005129198Scognet * There are bugs in the rev K SA110. This is a check for one 2006129198Scognet * of them. 2007129198Scognet */ 2008129198Scognet if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2009129198Scognet curcpu()->ci_arm_cpurev < 3) { 2010129198Scognet /* Always current pmap */ 2011129198Scognet if (l2pte_valid(pte)) { 2012129198Scognet extern int kernel_debug; 2013129198Scognet if (kernel_debug & 1) { 2014129198Scognet struct proc *p = curlwp->l_proc; 2015129198Scognet printf("prefetch_abort: page is already " 2016129198Scognet "mapped - pte=%p *pte=%08x\n", ptep, pte); 2017129198Scognet printf("prefetch_abort: pc=%08lx proc=%p " 2018129198Scognet "process=%s\n", va, p, p->p_comm); 2019129198Scognet printf("prefetch_abort: far=%08x fs=%x\n", 2020129198Scognet cpu_faultaddress(), cpu_faultstatus()); 2021129198Scognet } 2022129198Scognet#ifdef DDB 2023129198Scognet if (kernel_debug & 2) 2024129198Scognet Debugger(); 2025129198Scognet#endif 2026129198Scognet rv = 1; 2027129198Scognet } 2028129198Scognet } 2029129198Scognet#endif /* CPU_SA110 */ 2030129198Scognet 2031129198Scognet#ifdef DEBUG 2032129198Scognet /* 2033129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 2034129198Scognet * stale TLB entry for the faulting address. This happens when two or 2035129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 2036129198Scognet * a context switch between such processes, we can take domain faults 2037129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 2038129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2039129198Scognet * example. 2040129198Scognet * 2041129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 2042129198Scognet * entry for a recently entered mapping. In this case, the TLB is 2043129198Scognet * flushed for the new mapping, but there may still be TLB entries for 2044129198Scognet * other mappings belonging to other processes in the 1MB range 2045129198Scognet * covered by the L1 entry. 2046129198Scognet * 2047129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 2048129198Scognet * value, so the fault must be due to a stale TLB entry. 2049129198Scognet * 2050129198Scognet * Since we always need to flush the TLB anyway in the case where we 2051129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2052129198Scognet * stale TLB entries dynamically. 2053129198Scognet * 2054129198Scognet * However, the above condition can ONLY happen if the current L1 is 2055129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 2056129198Scognet * that other parts of the pmap are not doing their job WRT managing 2057129198Scognet * the TLB. 2058129198Scognet */ 2059129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2060129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2061225988Smarcel pm, (u_long)va, ftype); 2062129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2063129198Scognet l2, l2b, ptep, pl1pd); 2064129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2065129198Scognet pte, l1pd, last_fault_code); 2066129198Scognet#ifdef DDB 2067129198Scognet Debugger(); 2068129198Scognet#endif 2069129198Scognet } 2070129198Scognet#endif 2071129198Scognet 2072129198Scognet cpu_tlb_flushID_SE(va); 2073129198Scognet cpu_cpwait(); 2074129198Scognet 2075129198Scognet rv = 1; 2076129198Scognet 2077129198Scognetout: 2078159384Salc vm_page_unlock_queues(); 2079159384Salc PMAP_UNLOCK(pm); 2080129198Scognet return (rv); 2081129198Scognet} 2082129198Scognet 2083129198Scognetvoid 2084152128Scognetpmap_postinit(void) 2085152128Scognet{ 2086129198Scognet struct l2_bucket *l2b; 2087129198Scognet struct l1_ttable *l1; 2088129198Scognet pd_entry_t *pl1pt; 2089129198Scognet pt_entry_t *ptep, pte; 2090129198Scognet vm_offset_t va, eva; 2091129198Scognet u_int loop, needed; 2092129198Scognet 2093129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2094129198Scognet needed -= 1; 2095129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2096129198Scognet 2097129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 2098129198Scognet /* Allocate a L1 page table */ 2099132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2100132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 2101129198Scognet 2102129198Scognet if (va == 0) 2103129198Scognet panic("Cannot allocate L1 KVM"); 2104129198Scognet 2105129198Scognet eva = va + L1_TABLE_SIZE; 2106129198Scognet pl1pt = (pd_entry_t *)va; 2107129198Scognet 2108135641Scognet while (va < eva) { 2109129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2110129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2111129198Scognet pte = *ptep; 2112129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2113129198Scognet *ptep = pte; 2114129198Scognet PTE_SYNC(ptep); 2115129198Scognet cpu_tlb_flushD_SE(va); 2116129198Scognet 2117129198Scognet va += PAGE_SIZE; 2118129198Scognet } 2119129198Scognet pmap_init_l1(l1, pl1pt); 2120129198Scognet } 2121129198Scognet 2122129198Scognet 2123129198Scognet#ifdef DEBUG 2124129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2125129198Scognet needed); 2126129198Scognet#endif 2127129198Scognet} 2128129198Scognet 2129129198Scognet/* 2130129198Scognet * This is used to stuff certain critical values into the PCB where they 2131129198Scognet * can be accessed quickly from cpu_switch() et al. 2132129198Scognet */ 2133129198Scognetvoid 2134129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2135129198Scognet{ 2136129198Scognet struct l2_bucket *l2b; 2137129198Scognet 2138129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2139129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2140129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2141129198Scognet 2142129198Scognet if (vector_page < KERNBASE) { 2143129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2144129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2145129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2146145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2147129198Scognet } else 2148129198Scognet pcb->pcb_pl1vec = NULL; 2149129198Scognet} 2150129198Scognet 2151129198Scognetvoid 2152129198Scognetpmap_activate(struct thread *td) 2153129198Scognet{ 2154129198Scognet pmap_t pm; 2155129198Scognet struct pcb *pcb; 2156129198Scognet 2157135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2158129198Scognet pcb = td->td_pcb; 2159129198Scognet 2160129198Scognet critical_enter(); 2161129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2162129198Scognet 2163129198Scognet if (td == curthread) { 2164129198Scognet u_int cur_dacr, cur_ttb; 2165129198Scognet 2166129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2167129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2168129198Scognet 2169129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2170129198Scognet 2171129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2172129198Scognet cur_dacr == pcb->pcb_dacr) { 2173129198Scognet /* 2174129198Scognet * No need to switch address spaces. 2175129198Scognet */ 2176129198Scognet critical_exit(); 2177129198Scognet return; 2178129198Scognet } 2179129198Scognet 2180129198Scognet 2181129198Scognet /* 2182129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2183129198Scognet * to 'vector_page' in the incoming L1 table before switching 2184129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2185129198Scognet * domain faults!) will jump into hyperspace. 2186129198Scognet */ 2187129198Scognet if (pcb->pcb_pl1vec) { 2188129198Scognet 2189129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2190129198Scognet /* 2191129198Scognet * Don't need to PTE_SYNC() at this point since 2192129198Scognet * cpu_setttb() is about to flush both the cache 2193129198Scognet * and the TLB. 2194129198Scognet */ 2195129198Scognet } 2196129198Scognet 2197129198Scognet cpu_domains(pcb->pcb_dacr); 2198129198Scognet cpu_setttb(pcb->pcb_pagedir); 2199129198Scognet } 2200129198Scognet critical_exit(); 2201129198Scognet} 2202129198Scognet 2203129198Scognetstatic int 2204129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2205129198Scognet{ 2206129198Scognet pd_entry_t *pdep, pde; 2207129198Scognet pt_entry_t *ptep, pte; 2208129198Scognet vm_offset_t pa; 2209129198Scognet int rv = 0; 2210129198Scognet 2211129198Scognet /* 2212129198Scognet * Make sure the descriptor itself has the correct cache mode 2213129198Scognet */ 2214129198Scognet pdep = &kl1[L1_IDX(va)]; 2215129198Scognet pde = *pdep; 2216129198Scognet 2217129198Scognet if (l1pte_section_p(pde)) { 2218129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2219129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2220129198Scognet pte_l1_s_cache_mode_pt; 2221129198Scognet PTE_SYNC(pdep); 2222129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2223129198Scognet sizeof(*pdep)); 2224183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)pdep, 2225183838Sraj sizeof(*pdep)); 2226129198Scognet rv = 1; 2227129198Scognet } 2228129198Scognet } else { 2229129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2230129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2231129198Scognet if (ptep == NULL) 2232129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2233129198Scognet 2234129198Scognet ptep = &ptep[l2pte_index(va)]; 2235129198Scognet pte = *ptep; 2236129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2237129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2238129198Scognet pte_l2_s_cache_mode_pt; 2239129198Scognet PTE_SYNC(ptep); 2240129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2241129198Scognet sizeof(*ptep)); 2242183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)ptep, 2243183838Sraj sizeof(*ptep)); 2244129198Scognet rv = 1; 2245129198Scognet } 2246129198Scognet } 2247129198Scognet 2248129198Scognet return (rv); 2249129198Scognet} 2250129198Scognet 2251129198Scognetstatic void 2252236991Simppmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2253129198Scognet pt_entry_t **ptep) 2254129198Scognet{ 2255129198Scognet vm_offset_t va = *availp; 2256129198Scognet struct l2_bucket *l2b; 2257129198Scognet 2258129198Scognet if (ptep) { 2259129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2260129198Scognet if (l2b == NULL) 2261129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2262129198Scognet 2263129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2264129198Scognet } 2265129198Scognet 2266129198Scognet *vap = va; 2267129198Scognet *availp = va + (PAGE_SIZE * pages); 2268129198Scognet} 2269129198Scognet 2270129198Scognet/* 2271129198Scognet * Bootstrap the system enough to run with virtual memory. 2272129198Scognet * 2273129198Scognet * On the arm this is called after mapping has already been enabled 2274129198Scognet * and just syncs the pmap module with what has already been done. 2275129198Scognet * [We can't call it easily with mapping off since the kernel is not 2276129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2277129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2278129198Scognet * (physical) address starting relative to 0] 2279129198Scognet */ 2280129198Scognet#define PMAP_STATIC_L2_SIZE 16 2281147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2282147114Scognetextern struct mtx smallalloc_mtx; 2283147114Scognet#endif 2284147114Scognet 2285129198Scognetvoid 2286129198Scognetpmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2287129198Scognet{ 2288129198Scognet static struct l1_ttable static_l1; 2289129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2290129198Scognet struct l1_ttable *l1 = &static_l1; 2291129198Scognet struct l2_dtable *l2; 2292129198Scognet struct l2_bucket *l2b; 2293129198Scognet pd_entry_t pde; 2294129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2295129198Scognet pt_entry_t *ptep; 2296129198Scognet vm_paddr_t pa; 2297129198Scognet vm_offset_t va; 2298135641Scognet vm_size_t size; 2299129198Scognet int l1idx, l2idx, l2next = 0; 2300129198Scognet 2301197770Sstas PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", 2302197770Sstas firstaddr, lastaddr)); 2303129198Scognet 2304129198Scognet virtual_avail = firstaddr; 2305129198Scognet kernel_pmap->pm_l1 = l1; 2306150865Scognet kernel_l1pa = l1pt->pv_pa; 2307143192Scognet 2308143192Scognet /* 2309129198Scognet * Scan the L1 translation table created by initarm() and create 2310129198Scognet * the required metadata for all valid mappings found in it. 2311129198Scognet */ 2312129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2313129198Scognet pde = kernel_l1pt[l1idx]; 2314129198Scognet 2315129198Scognet /* 2316129198Scognet * We're only interested in Coarse mappings. 2317129198Scognet * pmap_extract() can deal with section mappings without 2318129198Scognet * recourse to checking L2 metadata. 2319129198Scognet */ 2320129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2321129198Scognet continue; 2322129198Scognet 2323129198Scognet /* 2324129198Scognet * Lookup the KVA of this L2 descriptor table 2325129198Scognet */ 2326129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2327129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2328129198Scognet 2329129198Scognet if (ptep == NULL) { 2330129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2331129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2332129198Scognet } 2333129198Scognet 2334129198Scognet /* 2335129198Scognet * Fetch the associated L2 metadata structure. 2336129198Scognet * Allocate a new one if necessary. 2337129198Scognet */ 2338129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2339129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2340129198Scognet panic("pmap_bootstrap: out of static L2s"); 2341236991Simp kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2342129198Scognet &static_l2[l2next++]; 2343129198Scognet } 2344129198Scognet 2345129198Scognet /* 2346129198Scognet * One more L1 slot tracked... 2347129198Scognet */ 2348129198Scognet l2->l2_occupancy++; 2349129198Scognet 2350129198Scognet /* 2351129198Scognet * Fill in the details of the L2 descriptor in the 2352129198Scognet * appropriate bucket. 2353129198Scognet */ 2354129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2355129198Scognet l2b->l2b_kva = ptep; 2356129198Scognet l2b->l2b_phys = pa; 2357129198Scognet l2b->l2b_l1idx = l1idx; 2358129198Scognet 2359129198Scognet /* 2360129198Scognet * Establish an initial occupancy count for this descriptor 2361129198Scognet */ 2362129198Scognet for (l2idx = 0; 2363129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2364129198Scognet l2idx++) { 2365129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2366129198Scognet l2b->l2b_occupancy++; 2367129198Scognet } 2368129198Scognet } 2369129198Scognet 2370129198Scognet /* 2371129198Scognet * Make sure the descriptor itself has the correct cache mode. 2372129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2373129198Scognet * should consider this a clue to fix up their initarm() 2374129198Scognet * function. :) 2375129198Scognet */ 2376129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2377129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2378129198Scognet "L2 pte @ %p\n", ptep); 2379129198Scognet } 2380129198Scognet } 2381129198Scognet 2382129198Scognet 2383129198Scognet /* 2384129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2385129198Scognet * a page table. Bitch if it is not correctly set. 2386129198Scognet */ 2387129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2388129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2389129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2390129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2391129198Scognet "primary L1 @ 0x%x\n", va); 2392129198Scognet } 2393129198Scognet 2394129198Scognet cpu_dcache_wbinv_all(); 2395183838Sraj cpu_l2cache_wbinv_all(); 2396129198Scognet cpu_tlb_flushID(); 2397129198Scognet cpu_cpwait(); 2398129198Scognet 2399159325Salc PMAP_LOCK_INIT(kernel_pmap); 2400222813Sattilio CPU_FILL(&kernel_pmap->pm_active); 2401129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2402144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2403129198Scognet 2404129198Scognet /* 2405129198Scognet * Reserve some special page table entries/VA space for temporary 2406129198Scognet * mapping of pages. 2407129198Scognet */ 2408129198Scognet#define SYSMAP(c, p, v, n) \ 2409129198Scognet v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2410236991Simp 2411129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2412129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2413129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2414129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2415135641Scognet size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2416135641Scognet pmap_alloc_specials(&virtual_avail, 2417135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2418135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2419135641Scognet 2420135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2421135641Scognet pmap_alloc_specials(&virtual_avail, 2422135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2423135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2424135641Scognet 2425137362Scognet pmap_alloc_specials(&virtual_avail, 2426137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2427184728Sraj pmap_alloc_specials(&virtual_avail, 2428184728Sraj MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL); 2429135641Scognet SLIST_INIT(&l1_list); 2430129198Scognet TAILQ_INIT(&l1_lru_list); 2431129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2432129198Scognet pmap_init_l1(l1, kernel_l1pt); 2433129198Scognet cpu_dcache_wbinv_all(); 2434183838Sraj cpu_l2cache_wbinv_all(); 2435129198Scognet 2436129198Scognet virtual_avail = round_page(virtual_avail); 2437129198Scognet virtual_end = lastaddr; 2438135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2439156191Scognet arm_nocache_startaddr = lastaddr; 2440159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2441156191Scognet 2442147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2443147114Scognet mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF); 2444161105Scognet arm_init_smallalloc(); 2445147114Scognet#endif 2446161105Scognet pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 2447129198Scognet} 2448129198Scognet 2449129198Scognet/*************************************************** 2450129198Scognet * Pmap allocation/deallocation routines. 2451129198Scognet ***************************************************/ 2452129198Scognet 2453129198Scognet/* 2454129198Scognet * Release any resources held by the given physical map. 2455129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2456129198Scognet * Should only be called if the map contains no valid mappings. 2457129198Scognet */ 2458129198Scognetvoid 2459129198Scognetpmap_release(pmap_t pmap) 2460129198Scognet{ 2461135641Scognet struct pcb *pcb; 2462135641Scognet 2463135641Scognet pmap_idcache_wbinv_all(pmap); 2464183838Sraj cpu_l2cache_wbinv_all(); 2465135641Scognet pmap_tlb_flushID(pmap); 2466135641Scognet cpu_cpwait(); 2467135641Scognet if (vector_page < KERNBASE) { 2468135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2469135641Scognet pcb = thread0.td_pcb; 2470135641Scognet if (pmap_is_current(pmap)) { 2471135641Scognet /* 2472135641Scognet * Frob the L1 entry corresponding to the vector 2473135641Scognet * page so that it contains the kernel pmap's domain 2474135641Scognet * number. This will ensure pmap_remove() does not 2475135641Scognet * pull the current vector page out from under us. 2476135641Scognet */ 2477135641Scognet critical_enter(); 2478135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2479135641Scognet cpu_domains(pcb->pcb_dacr); 2480135641Scognet cpu_setttb(pcb->pcb_pagedir); 2481135641Scognet critical_exit(); 2482135641Scognet } 2483135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2484135641Scognet /* 2485135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2486135641Scognet * since this process has no remaining mappings of its own. 2487135641Scognet */ 2488135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2489135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2490135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2491135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2492135641Scognet 2493135641Scognet } 2494129198Scognet pmap_free_l1(pmap); 2495159325Salc PMAP_LOCK_DESTROY(pmap); 2496135641Scognet 2497129198Scognet dprintf("pmap_release()\n"); 2498129198Scognet} 2499129198Scognet 2500129198Scognet 2501135641Scognet 2502129198Scognet/* 2503135641Scognet * Helper function for pmap_grow_l2_bucket() 2504135641Scognet */ 2505135641Scognetstatic __inline int 2506135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2507135641Scognet{ 2508135641Scognet struct l2_bucket *l2b; 2509135641Scognet pt_entry_t *ptep; 2510135641Scognet vm_paddr_t pa; 2511135641Scognet struct vm_page *pg; 2512135641Scognet 2513150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2514135641Scognet if (pg == NULL) 2515135641Scognet return (1); 2516135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2517135641Scognet 2518135641Scognet if (pap) 2519135641Scognet *pap = pa; 2520135641Scognet 2521135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2522135641Scognet 2523135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2524135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2525135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2526135641Scognet PTE_SYNC(ptep); 2527135641Scognet return (0); 2528135641Scognet} 2529135641Scognet 2530135641Scognet/* 2531135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2532135641Scognet * used by pmap_growkernel(). 2533135641Scognet */ 2534135641Scognetstatic __inline struct l2_bucket * 2535135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2536135641Scognet{ 2537135641Scognet struct l2_dtable *l2; 2538135641Scognet struct l2_bucket *l2b; 2539135641Scognet struct l1_ttable *l1; 2540135641Scognet pd_entry_t *pl1pd; 2541135641Scognet u_short l1idx; 2542135641Scognet vm_offset_t nva; 2543135641Scognet 2544135641Scognet l1idx = L1_IDX(va); 2545135641Scognet 2546135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2547135641Scognet /* 2548135641Scognet * No mapping at this address, as there is 2549135641Scognet * no entry in the L1 table. 2550135641Scognet * Need to allocate a new l2_dtable. 2551135641Scognet */ 2552135641Scognet nva = pmap_kernel_l2dtable_kva; 2553135641Scognet if ((nva & PAGE_MASK) == 0) { 2554135641Scognet /* 2555135641Scognet * Need to allocate a backing page 2556135641Scognet */ 2557135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2558135641Scognet return (NULL); 2559135641Scognet } 2560135641Scognet 2561135641Scognet l2 = (struct l2_dtable *)nva; 2562135641Scognet nva += sizeof(struct l2_dtable); 2563135641Scognet 2564236991Simp if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2565135641Scognet PAGE_MASK)) { 2566135641Scognet /* 2567135641Scognet * The new l2_dtable straddles a page boundary. 2568135641Scognet * Map in another page to cover it. 2569135641Scognet */ 2570135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2571135641Scognet return (NULL); 2572135641Scognet } 2573135641Scognet 2574135641Scognet pmap_kernel_l2dtable_kva = nva; 2575135641Scognet 2576135641Scognet /* 2577135641Scognet * Link it into the parent pmap 2578135641Scognet */ 2579135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2580150865Scognet memset(l2, 0, sizeof(*l2)); 2581135641Scognet } 2582135641Scognet 2583135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2584135641Scognet 2585135641Scognet /* 2586135641Scognet * Fetch pointer to the L2 page table associated with the address. 2587135641Scognet */ 2588135641Scognet if (l2b->l2b_kva == NULL) { 2589135641Scognet pt_entry_t *ptep; 2590135641Scognet 2591135641Scognet /* 2592135641Scognet * No L2 page table has been allocated. Chances are, this 2593135641Scognet * is because we just allocated the l2_dtable, above. 2594135641Scognet */ 2595135641Scognet nva = pmap_kernel_l2ptp_kva; 2596135641Scognet ptep = (pt_entry_t *)nva; 2597135641Scognet if ((nva & PAGE_MASK) == 0) { 2598135641Scognet /* 2599135641Scognet * Need to allocate a backing page 2600135641Scognet */ 2601135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2602135641Scognet &pmap_kernel_l2ptp_phys)) 2603135641Scognet return (NULL); 2604135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2605135641Scognet } 2606150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2607135641Scognet l2->l2_occupancy++; 2608135641Scognet l2b->l2b_kva = ptep; 2609135641Scognet l2b->l2b_l1idx = l1idx; 2610135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2611135641Scognet 2612135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2613135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2614135641Scognet } 2615135641Scognet 2616135641Scognet /* Distribute new L1 entry to all other L1s */ 2617135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2618145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2619135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2620135641Scognet L1_C_PROTO; 2621135641Scognet PTE_SYNC(pl1pd); 2622135641Scognet } 2623135641Scognet 2624135641Scognet return (l2b); 2625135641Scognet} 2626135641Scognet 2627135641Scognet 2628135641Scognet/* 2629129198Scognet * grow the number of kernel page table entries, if needed 2630129198Scognet */ 2631129198Scognetvoid 2632129198Scognetpmap_growkernel(vm_offset_t addr) 2633129198Scognet{ 2634135641Scognet pmap_t kpm = pmap_kernel(); 2635129198Scognet 2636135641Scognet if (addr <= pmap_curmaxkvaddr) 2637135641Scognet return; /* we are OK */ 2638135641Scognet 2639135641Scognet /* 2640135641Scognet * whoops! we need to add kernel PTPs 2641135641Scognet */ 2642135641Scognet 2643135641Scognet /* Map 1MB at a time */ 2644135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2645135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2646135641Scognet 2647135641Scognet /* 2648135641Scognet * flush out the cache, expensive but growkernel will happen so 2649135641Scognet * rarely 2650135641Scognet */ 2651135641Scognet cpu_dcache_wbinv_all(); 2652183838Sraj cpu_l2cache_wbinv_all(); 2653135641Scognet cpu_tlb_flushD(); 2654135641Scognet cpu_cpwait(); 2655135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2656129198Scognet} 2657129198Scognet 2658129198Scognet 2659129198Scognet/* 2660129198Scognet * Remove all pages from specified address space 2661129198Scognet * this aids process exit speeds. Also, this code 2662129198Scognet * is special cased for current process only, but 2663129198Scognet * can have the more generic (and slightly slower) 2664129198Scognet * mode enabled. This is much faster than pmap_remove 2665129198Scognet * in the case of running down an entire address space. 2666129198Scognet */ 2667129198Scognetvoid 2668157443Speterpmap_remove_pages(pmap_t pmap) 2669129198Scognet{ 2670144760Scognet struct pv_entry *pv, *npv; 2671144760Scognet struct l2_bucket *l2b = NULL; 2672144760Scognet vm_page_t m; 2673144760Scognet pt_entry_t *pt; 2674144760Scognet 2675144760Scognet vm_page_lock_queues(); 2676159352Salc PMAP_LOCK(pmap); 2677175840Scognet cpu_idcache_wbinv_all(); 2678183838Sraj cpu_l2cache_wbinv_all(); 2679144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2680194459Sthompsa if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) { 2681194459Sthompsa /* Cannot remove wired or unmanaged pages now. */ 2682144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2683144760Scognet continue; 2684144760Scognet } 2685144760Scognet pmap->pm_stats.resident_count--; 2686144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2687144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2688144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2689144760Scognet m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2690164079Scognet#ifdef ARM_USE_SMALL_ALLOC 2691164079Scognet KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2692164079Scognet#else 2693164079Scognet KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2694164079Scognet#endif 2695144760Scognet *pt = 0; 2696144760Scognet PTE_SYNC(pt); 2697144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2698144760Scognet pmap_nuke_pv(m, pmap, pv); 2699150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2700225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2701144760Scognet pmap_free_pv_entry(pv); 2702164874Scognet pmap_free_l2_bucket(pmap, l2b, 1); 2703144760Scognet } 2704144760Scognet vm_page_unlock_queues(); 2705135641Scognet cpu_tlb_flushID(); 2706135641Scognet cpu_cpwait(); 2707159352Salc PMAP_UNLOCK(pmap); 2708129198Scognet} 2709129198Scognet 2710129198Scognet 2711129198Scognet/*************************************************** 2712129198Scognet * Low level mapping routines..... 2713129198Scognet ***************************************************/ 2714129198Scognet 2715171620Scognet#ifdef ARM_HAVE_SUPERSECTIONS 2716170582Scognet/* Map a super section into the KVA. */ 2717170582Scognet 2718170582Scognetvoid 2719170582Scognetpmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags) 2720170582Scognet{ 2721171620Scognet pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) | 2722171620Scognet (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL, 2723170582Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2724170582Scognet struct l1_ttable *l1; 2725171620Scognet vm_offset_t va0, va_end; 2726170582Scognet 2727170582Scognet KASSERT(((va | pa) & L1_SUP_OFFSET) == 0, 2728171620Scognet ("Not a valid super section mapping")); 2729170582Scognet if (flags & SECTION_CACHE) 2730170582Scognet pd |= pte_l1_s_cache_mode; 2731170582Scognet else if (flags & SECTION_PT) 2732170582Scognet pd |= pte_l1_s_cache_mode_pt; 2733171620Scognet va0 = va & L1_SUP_FRAME; 2734170582Scognet va_end = va + L1_SUP_SIZE; 2735170582Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2736171620Scognet va = va0; 2737170582Scognet for (; va < va_end; va += L1_S_SIZE) { 2738170582Scognet l1->l1_kva[L1_IDX(va)] = pd; 2739170582Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2740170582Scognet } 2741170582Scognet } 2742170582Scognet} 2743171620Scognet#endif 2744170582Scognet 2745147114Scognet/* Map a section into the KVA. */ 2746147114Scognet 2747147114Scognetvoid 2748147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2749147114Scognet{ 2750147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2751147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2752147114Scognet struct l1_ttable *l1; 2753147114Scognet 2754147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2755147114Scognet ("Not a valid section mapping")); 2756147114Scognet if (flags & SECTION_CACHE) 2757147114Scognet pd |= pte_l1_s_cache_mode; 2758147114Scognet else if (flags & SECTION_PT) 2759147114Scognet pd |= pte_l1_s_cache_mode_pt; 2760147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2761147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2762147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2763147114Scognet } 2764147114Scognet} 2765147114Scognet 2766129198Scognet/* 2767184728Sraj * Make a temporary mapping for a physical address. This is only intended 2768184728Sraj * to be used for panic dumps. 2769184728Sraj */ 2770184728Srajvoid * 2771184728Srajpmap_kenter_temp(vm_paddr_t pa, int i) 2772184728Sraj{ 2773184728Sraj vm_offset_t va; 2774184728Sraj 2775184728Sraj va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 2776184728Sraj pmap_kenter(va, pa); 2777184728Sraj return ((void *)crashdumpmap); 2778184728Sraj} 2779184728Sraj 2780184728Sraj/* 2781129198Scognet * add a wired page to the kva 2782129198Scognet * note that in order for the mapping to take effect -- you 2783129198Scognet * should do a invltlb after doing the pmap_kenter... 2784129198Scognet */ 2785135641Scognetstatic PMAP_INLINE void 2786135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2787129198Scognet{ 2788129198Scognet struct l2_bucket *l2b; 2789129198Scognet pt_entry_t *pte; 2790129198Scognet pt_entry_t opte; 2791194459Sthompsa struct pv_entry *pve; 2792194459Sthompsa vm_page_t m; 2793194459Sthompsa 2794129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2795129198Scognet (uint32_t) va, (uint32_t) pa)); 2796129198Scognet 2797129198Scognet 2798129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2799135641Scognet if (l2b == NULL) 2800135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2801129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2802129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2803129198Scognet opte = *pte; 2804129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2805129198Scognet (uint32_t) pte, opte, *pte)); 2806129198Scognet if (l2pte_valid(opte)) { 2807194459Sthompsa pmap_kremove(va); 2808135641Scognet } else { 2809129198Scognet if (opte == 0) 2810129198Scognet l2b->l2b_occupancy++; 2811135641Scognet } 2812236991Simp *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2813135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2814135641Scognet if (flags & KENTER_CACHE) 2815135641Scognet *pte |= pte_l2_s_cache_mode; 2816142570Scognet if (flags & KENTER_USER) 2817142570Scognet *pte |= L2_S_PROT_U; 2818129198Scognet PTE_SYNC(pte); 2819194459Sthompsa 2820194459Sthompsa /* kernel direct mappings can be shared, so use a pv_entry 2821194459Sthompsa * to ensure proper caching. 2822194459Sthompsa * 2823194459Sthompsa * The pvzone is used to delay the recording of kernel 2824194459Sthompsa * mappings until the VM is running. 2825236991Simp * 2826194459Sthompsa * This expects the physical memory to have vm_page_array entry. 2827194459Sthompsa */ 2828194459Sthompsa if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa))) { 2829194459Sthompsa vm_page_lock_queues(); 2830194459Sthompsa if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva) { 2831198341Smarcel /* release vm_page lock for pv_entry UMA */ 2832194459Sthompsa vm_page_unlock_queues(); 2833194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 2834194459Sthompsa panic("pmap_kenter_internal: no pv entries"); 2835194459Sthompsa vm_page_lock_queues(); 2836194459Sthompsa PMAP_LOCK(pmap_kernel()); 2837194459Sthompsa pmap_enter_pv(m, pve, pmap_kernel(), va, 2838198341Smarcel PVF_WRITE | PVF_UNMAN); 2839194459Sthompsa pmap_fix_cache(m, pmap_kernel(), va); 2840194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2841194459Sthompsa } else { 2842194459Sthompsa m->md.pv_kva = va; 2843194459Sthompsa } 2844194459Sthompsa vm_page_unlock_queues(); 2845194459Sthompsa } 2846135641Scognet} 2847129198Scognet 2848135641Scognetvoid 2849135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2850135641Scognet{ 2851135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2852129198Scognet} 2853129198Scognet 2854142570Scognetvoid 2855156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2856156191Scognet{ 2857156191Scognet 2858156191Scognet pmap_kenter_internal(va, pa, 0); 2859156191Scognet} 2860156191Scognet 2861156191Scognetvoid 2862142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2863142570Scognet{ 2864143192Scognet 2865142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2866143192Scognet /* 2867143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2868143192Scognet * at the first use of the new address, or bad things will happen, 2869143192Scognet * as we use one of these addresses in the exception handlers. 2870143192Scognet */ 2871143192Scognet pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2872142570Scognet} 2873129198Scognet 2874129198Scognet/* 2875194908Scognet * remove a page from the kernel pagetables 2876129198Scognet */ 2877169763Scognetvoid 2878129198Scognetpmap_kremove(vm_offset_t va) 2879129198Scognet{ 2880135641Scognet struct l2_bucket *l2b; 2881135641Scognet pt_entry_t *pte, opte; 2882194459Sthompsa struct pv_entry *pve; 2883194459Sthompsa vm_page_t m; 2884194459Sthompsa vm_offset_t pa; 2885135641Scognet 2886135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2887145071Scognet if (!l2b) 2888145071Scognet return; 2889135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2890135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2891135641Scognet opte = *pte; 2892135641Scognet if (l2pte_valid(opte)) { 2893194459Sthompsa /* pa = vtophs(va) taken from pmap_extract() */ 2894194459Sthompsa switch (opte & L2_TYPE_MASK) { 2895194459Sthompsa case L2_TYPE_L: 2896194459Sthompsa pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET); 2897194459Sthompsa break; 2898194459Sthompsa default: 2899194459Sthompsa pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET); 2900194459Sthompsa break; 2901194459Sthompsa } 2902194459Sthompsa /* note: should never have to remove an allocation 2903194459Sthompsa * before the pvzone is initialized. 2904194459Sthompsa */ 2905194459Sthompsa vm_page_lock_queues(); 2906194459Sthompsa PMAP_LOCK(pmap_kernel()); 2907194459Sthompsa if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) && 2908194459Sthompsa (pve = pmap_remove_pv(m, pmap_kernel(), va))) 2909236991Simp pmap_free_pv_entry(pve); 2910194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2911194459Sthompsa vm_page_unlock_queues(); 2912195779Sraj va = va & ~PAGE_MASK; 2913135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2914183838Sraj cpu_l2cache_wbinv_range(va, PAGE_SIZE); 2915135641Scognet cpu_tlb_flushD_SE(va); 2916135641Scognet cpu_cpwait(); 2917144760Scognet *pte = 0; 2918135641Scognet } 2919129198Scognet} 2920129198Scognet 2921129198Scognet 2922129198Scognet/* 2923129198Scognet * Used to map a range of physical addresses into kernel 2924129198Scognet * virtual address space. 2925129198Scognet * 2926129198Scognet * The value passed in '*virt' is a suggested virtual address for 2927129198Scognet * the mapping. Architectures which can support a direct-mapped 2928129198Scognet * physical to virtual region can return the appropriate address 2929129198Scognet * within that region, leaving '*virt' unchanged. Other 2930129198Scognet * architectures should map the pages starting at '*virt' and 2931129198Scognet * update '*virt' with the first usable address after the mapped 2932129198Scognet * region. 2933129198Scognet */ 2934129198Scognetvm_offset_t 2935129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2936129198Scognet{ 2937161105Scognet#ifdef ARM_USE_SMALL_ALLOC 2938161105Scognet return (arm_ptovirt(start)); 2939161105Scognet#else 2940129198Scognet vm_offset_t sva = *virt; 2941129198Scognet vm_offset_t va = sva; 2942129198Scognet 2943129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2944129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2945129198Scognet prot)); 2946236991Simp 2947129198Scognet while (start < end) { 2948129198Scognet pmap_kenter(va, start); 2949129198Scognet va += PAGE_SIZE; 2950129198Scognet start += PAGE_SIZE; 2951129198Scognet } 2952129198Scognet *virt = va; 2953129198Scognet return (sva); 2954161105Scognet#endif 2955129198Scognet} 2956129198Scognet 2957143724Scognetstatic void 2958150865Scognetpmap_wb_page(vm_page_t m) 2959143724Scognet{ 2960143724Scognet struct pv_entry *pv; 2961129198Scognet 2962143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2963150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2964144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2965143724Scognet} 2966143724Scognet 2967150865Scognetstatic void 2968150865Scognetpmap_inv_page(vm_page_t m) 2969150865Scognet{ 2970150865Scognet struct pv_entry *pv; 2971150865Scognet 2972150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2973150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2974150865Scognet} 2975129198Scognet/* 2976129198Scognet * Add a list of wired pages to the kva 2977129198Scognet * this routine is only used for temporary 2978129198Scognet * kernel mappings that do not need to have 2979129198Scognet * page modification or references recorded. 2980129198Scognet * Note that old mappings are simply written 2981129198Scognet * over. The page *must* be wired. 2982129198Scognet */ 2983129198Scognetvoid 2984129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2985129198Scognet{ 2986129198Scognet int i; 2987129198Scognet 2988129198Scognet for (i = 0; i < count; i++) { 2989150865Scognet pmap_wb_page(m[i]); 2990236991Simp pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2991135641Scognet KENTER_CACHE); 2992129198Scognet va += PAGE_SIZE; 2993129198Scognet } 2994129198Scognet} 2995129198Scognet 2996129198Scognet 2997129198Scognet/* 2998129198Scognet * this routine jerks page mappings from the 2999129198Scognet * kernel -- it is meant only for temporary mappings. 3000129198Scognet */ 3001129198Scognetvoid 3002129198Scognetpmap_qremove(vm_offset_t va, int count) 3003129198Scognet{ 3004146596Scognet vm_paddr_t pa; 3005129198Scognet int i; 3006129198Scognet 3007129198Scognet for (i = 0; i < count; i++) { 3008146596Scognet pa = vtophys(va); 3009146596Scognet if (pa) { 3010150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 3011146596Scognet pmap_kremove(va); 3012146596Scognet } 3013129198Scognet va += PAGE_SIZE; 3014129198Scognet } 3015129198Scognet} 3016129198Scognet 3017129198Scognet 3018129198Scognet/* 3019129198Scognet * pmap_object_init_pt preloads the ptes for a given object 3020129198Scognet * into the specified pmap. This eliminates the blast of soft 3021129198Scognet * faults on process startup and immediately after an mmap. 3022129198Scognet */ 3023129198Scognetvoid 3024129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3025129198Scognet vm_pindex_t pindex, vm_size_t size) 3026129198Scognet{ 3027157156Scognet 3028157156Scognet VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3029195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3030157156Scognet ("pmap_object_init_pt: non-device object")); 3031129198Scognet} 3032129198Scognet 3033129198Scognet 3034129198Scognet/* 3035129198Scognet * pmap_is_prefaultable: 3036129198Scognet * 3037129198Scognet * Return whether or not the specified virtual address is elgible 3038129198Scognet * for prefault. 3039129198Scognet */ 3040129198Scognetboolean_t 3041129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3042129198Scognet{ 3043135641Scognet pd_entry_t *pde; 3044129198Scognet pt_entry_t *pte; 3045129198Scognet 3046135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3047135641Scognet return (FALSE); 3048159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 3049135641Scognet if (*pte == 0) 3050135641Scognet return (TRUE); 3051135641Scognet return (FALSE); 3052129198Scognet} 3053129198Scognet 3054129198Scognet/* 3055129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3056129198Scognet * Returns TRUE if the mapping exists, else FALSE. 3057129198Scognet * 3058129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 3059129198Scognet * It is not safe to take any pmap locks here, since we could be right 3060129198Scognet * in the middle of debugging the pmap anyway... 3061129198Scognet * 3062129198Scognet * It is possible for this routine to return FALSE even though a valid 3063129198Scognet * mapping does exist. This is because we don't lock, so the metadata 3064129198Scognet * state may be inconsistent. 3065129198Scognet * 3066129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3067129198Scognet * a "section" mapping. 3068129198Scognet */ 3069129198Scognetboolean_t 3070129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3071129198Scognet{ 3072129198Scognet struct l2_dtable *l2; 3073129198Scognet pd_entry_t *pl1pd, l1pd; 3074129198Scognet pt_entry_t *ptep; 3075129198Scognet u_short l1idx; 3076129198Scognet 3077129198Scognet if (pm->pm_l1 == NULL) 3078129198Scognet return (FALSE); 3079129198Scognet 3080129198Scognet l1idx = L1_IDX(va); 3081129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3082129198Scognet l1pd = *pl1pd; 3083129198Scognet 3084129198Scognet if (l1pte_section_p(l1pd)) { 3085129198Scognet *ptp = NULL; 3086129198Scognet return (TRUE); 3087129198Scognet } 3088129198Scognet 3089129198Scognet if (pm->pm_l2 == NULL) 3090129198Scognet return (FALSE); 3091129198Scognet 3092129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3093129198Scognet 3094129198Scognet if (l2 == NULL || 3095129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3096129198Scognet return (FALSE); 3097129198Scognet } 3098129198Scognet 3099129198Scognet *ptp = &ptep[l2pte_index(va)]; 3100129198Scognet return (TRUE); 3101129198Scognet} 3102129198Scognet 3103129198Scognet/* 3104129198Scognet * Routine: pmap_remove_all 3105129198Scognet * Function: 3106129198Scognet * Removes this physical page from 3107129198Scognet * all physical maps in which it resides. 3108129198Scognet * Reflects back modify bits to the pager. 3109129198Scognet * 3110129198Scognet * Notes: 3111129198Scognet * Original versions of this routine were very 3112129198Scognet * inefficient because they iteratively called 3113129198Scognet * pmap_remove (slow...) 3114129198Scognet */ 3115129198Scognetvoid 3116129198Scognetpmap_remove_all(vm_page_t m) 3117129198Scognet{ 3118129198Scognet pv_entry_t pv; 3119188019Scognet pt_entry_t *ptep; 3120135641Scognet struct l2_bucket *l2b; 3121135641Scognet boolean_t flush = FALSE; 3122135641Scognet pmap_t curpm; 3123135641Scognet int flags = 0; 3124129198Scognet 3125224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3126223677Salc ("pmap_remove_all: page %p is not managed", m)); 3127135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3128135641Scognet return; 3129207796Salc vm_page_lock_queues(); 3130175840Scognet pmap_remove_write(m); 3131135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3132129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3133135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3134135641Scognet pv->pv_pmap == pmap_kernel())) 3135135641Scognet flush = TRUE; 3136193712Sraj 3137159352Salc PMAP_LOCK(pv->pv_pmap); 3138193712Sraj /* 3139193712Sraj * Cached contents were written-back in pmap_remove_write(), 3140193712Sraj * but we still have to invalidate the cache entry to make 3141193712Sraj * sure stale data are not retrieved when another page will be 3142193712Sraj * mapped under this virtual address. 3143193712Sraj */ 3144193712Sraj if (pmap_is_current(pv->pv_pmap)) { 3145193712Sraj cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE); 3146203637Sraj if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va)) 3147203637Sraj cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE); 3148193712Sraj } 3149193712Sraj 3150194459Sthompsa if (pv->pv_flags & PVF_UNMAN) { 3151194459Sthompsa /* remove the pv entry, but do not remove the mapping 3152194459Sthompsa * and remember this is a kernel mapped page 3153194459Sthompsa */ 3154194459Sthompsa m->md.pv_kva = pv->pv_va; 3155194459Sthompsa } else { 3156194459Sthompsa /* remove the mapping and pv entry */ 3157194459Sthompsa l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3158194459Sthompsa KASSERT(l2b != NULL, ("No l2 bucket")); 3159194459Sthompsa ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3160194459Sthompsa *ptep = 0; 3161194459Sthompsa PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3162194459Sthompsa pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3163194459Sthompsa pv->pv_pmap->pm_stats.resident_count--; 3164194459Sthompsa flags |= pv->pv_flags; 3165194459Sthompsa } 3166135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3167159352Salc PMAP_UNLOCK(pv->pv_pmap); 3168129198Scognet pmap_free_pv_entry(pv); 3169129198Scognet } 3170129198Scognet 3171135641Scognet if (flush) { 3172135641Scognet if (PV_BEEN_EXECD(flags)) 3173135641Scognet pmap_tlb_flushID(curpm); 3174135641Scognet else 3175135641Scognet pmap_tlb_flushD(curpm); 3176135641Scognet } 3177225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3178207796Salc vm_page_unlock_queues(); 3179129198Scognet} 3180129198Scognet 3181129198Scognet 3182129198Scognet/* 3183129198Scognet * Set the physical protection on the 3184129198Scognet * specified range of this map as requested. 3185129198Scognet */ 3186129198Scognetvoid 3187129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3188129198Scognet{ 3189129198Scognet struct l2_bucket *l2b; 3190129198Scognet pt_entry_t *ptep, pte; 3191129198Scognet vm_offset_t next_bucket; 3192129198Scognet u_int flags; 3193129198Scognet int flush; 3194129198Scognet 3195183838Sraj CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x", 3196183838Sraj pm, sva, eva, prot); 3197183838Sraj 3198129198Scognet if ((prot & VM_PROT_READ) == 0) { 3199129198Scognet pmap_remove(pm, sva, eva); 3200129198Scognet return; 3201129198Scognet } 3202129198Scognet 3203129198Scognet if (prot & VM_PROT_WRITE) { 3204129198Scognet /* 3205129198Scognet * If this is a read->write transition, just ignore it and let 3206135641Scognet * vm_fault() take care of it later. 3207129198Scognet */ 3208129198Scognet return; 3209129198Scognet } 3210129198Scognet 3211159352Salc vm_page_lock_queues(); 3212159352Salc PMAP_LOCK(pm); 3213129198Scognet 3214129198Scognet /* 3215129198Scognet * OK, at this point, we know we're doing write-protect operation. 3216129198Scognet * If the pmap is active, write-back the range. 3217129198Scognet */ 3218129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3219129198Scognet 3220129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3221129198Scognet flags = 0; 3222129198Scognet 3223129198Scognet while (sva < eva) { 3224129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3225129198Scognet if (next_bucket > eva) 3226129198Scognet next_bucket = eva; 3227129198Scognet 3228129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3229129198Scognet if (l2b == NULL) { 3230129198Scognet sva = next_bucket; 3231129198Scognet continue; 3232129198Scognet } 3233129198Scognet 3234129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3235129198Scognet 3236129198Scognet while (sva < next_bucket) { 3237129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3238129198Scognet struct vm_page *pg; 3239129198Scognet u_int f; 3240129198Scognet 3241129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3242129198Scognet pte &= ~L2_S_PROT_W; 3243129198Scognet *ptep = pte; 3244129198Scognet PTE_SYNC(ptep); 3245129198Scognet 3246239268Sgonzo if (!(pg->oflags & VPO_UNMANAGED)) { 3247239268Sgonzo f = pmap_modify_pv(pg, pm, sva, 3248239268Sgonzo PVF_WRITE, 0); 3249239268Sgonzo if (f & PVF_WRITE) 3250224049Smarcel vm_page_dirty(pg); 3251129198Scognet } else 3252239268Sgonzo f = 0; 3253129198Scognet 3254129198Scognet if (flush >= 0) { 3255129198Scognet flush++; 3256129198Scognet flags |= f; 3257129198Scognet } else 3258129198Scognet if (PV_BEEN_EXECD(f)) 3259129198Scognet pmap_tlb_flushID_SE(pm, sva); 3260129198Scognet else 3261129198Scognet if (PV_BEEN_REFD(f)) 3262129198Scognet pmap_tlb_flushD_SE(pm, sva); 3263129198Scognet } 3264129198Scognet 3265129198Scognet sva += PAGE_SIZE; 3266129198Scognet ptep++; 3267129198Scognet } 3268129198Scognet } 3269129198Scognet 3270129198Scognet 3271129198Scognet if (flush) { 3272129198Scognet if (PV_BEEN_EXECD(flags)) 3273129198Scognet pmap_tlb_flushID(pm); 3274129198Scognet else 3275129198Scognet if (PV_BEEN_REFD(flags)) 3276129198Scognet pmap_tlb_flushD(pm); 3277129198Scognet } 3278144760Scognet vm_page_unlock_queues(); 3279129198Scognet 3280159352Salc PMAP_UNLOCK(pm); 3281129198Scognet} 3282129198Scognet 3283129198Scognet 3284129198Scognet/* 3285129198Scognet * Insert the given physical page (p) at 3286129198Scognet * the specified virtual address (v) in the 3287129198Scognet * target physical map with the protection requested. 3288129198Scognet * 3289129198Scognet * If specified, the page will be wired down, meaning 3290129198Scognet * that the related pte can not be reclaimed. 3291129198Scognet * 3292129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3293129198Scognet * or lose information. That is, this routine must actually 3294129198Scognet * insert this page into the given map NOW. 3295129198Scognet */ 3296135641Scognet 3297129198Scognetvoid 3298175067Salcpmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3299175067Salc vm_prot_t prot, boolean_t wired) 3300129198Scognet{ 3301159127Salc 3302159127Salc vm_page_lock_queues(); 3303159352Salc PMAP_LOCK(pmap); 3304160260Scognet pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK); 3305159127Salc vm_page_unlock_queues(); 3306159352Salc PMAP_UNLOCK(pmap); 3307159127Salc} 3308159127Salc 3309159127Salc/* 3310159127Salc * The page queues and pmap must be locked. 3311159127Salc */ 3312159127Salcstatic void 3313159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3314160260Scognet boolean_t wired, int flags) 3315159127Salc{ 3316135641Scognet struct l2_bucket *l2b = NULL; 3317129198Scognet struct vm_page *opg; 3318144760Scognet struct pv_entry *pve = NULL; 3319129198Scognet pt_entry_t *ptep, npte, opte; 3320129198Scognet u_int nflags; 3321129198Scognet u_int oflags; 3322129198Scognet vm_paddr_t pa; 3323129198Scognet 3324159325Salc PMAP_ASSERT_LOCKED(pmap); 3325159127Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3326129198Scognet if (va == vector_page) { 3327129198Scognet pa = systempage.pv_pa; 3328129198Scognet m = NULL; 3329208688Salc } else { 3330224746Skib KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 3331224746Skib (flags & M_NOWAIT) != 0, 3332208688Salc ("pmap_enter_locked: page %p is not busy", m)); 3333129198Scognet pa = VM_PAGE_TO_PHYS(m); 3334208688Salc } 3335129198Scognet nflags = 0; 3336129198Scognet if (prot & VM_PROT_WRITE) 3337129198Scognet nflags |= PVF_WRITE; 3338129198Scognet if (prot & VM_PROT_EXECUTE) 3339129198Scognet nflags |= PVF_EXEC; 3340129198Scognet if (wired) 3341129198Scognet nflags |= PVF_WIRED; 3342129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3343129198Scognet "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3344236991Simp 3345135641Scognet if (pmap == pmap_kernel()) { 3346129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3347135641Scognet if (l2b == NULL) 3348135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3349160260Scognet } else { 3350160260Scognetdo_l2b_alloc: 3351129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3352160260Scognet if (l2b == NULL) { 3353160260Scognet if (flags & M_WAITOK) { 3354160260Scognet PMAP_UNLOCK(pmap); 3355160260Scognet vm_page_unlock_queues(); 3356160260Scognet VM_WAIT; 3357160260Scognet vm_page_lock_queues(); 3358160260Scognet PMAP_LOCK(pmap); 3359160260Scognet goto do_l2b_alloc; 3360160260Scognet } 3361160260Scognet return; 3362160260Scognet } 3363160260Scognet } 3364160260Scognet 3365129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3366236991Simp 3367135641Scognet opte = *ptep; 3368129198Scognet npte = pa; 3369129198Scognet oflags = 0; 3370129198Scognet if (opte) { 3371129198Scognet /* 3372129198Scognet * There is already a mapping at this address. 3373129198Scognet * If the physical address is different, lookup the 3374129198Scognet * vm_page. 3375129198Scognet */ 3376129198Scognet if (l2pte_pa(opte) != pa) 3377129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3378129198Scognet else 3379129198Scognet opg = m; 3380129198Scognet } else 3381129198Scognet opg = NULL; 3382129198Scognet 3383135641Scognet if ((prot & (VM_PROT_ALL)) || 3384135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3385129198Scognet /* 3386135641Scognet * - The access type indicates that we don't need 3387135641Scognet * to do referenced emulation. 3388135641Scognet * OR 3389135641Scognet * - The physical page has already been referenced 3390135641Scognet * so no need to re-do referenced emulation here. 3391129198Scognet */ 3392135641Scognet npte |= L2_S_PROTO; 3393135641Scognet 3394135641Scognet nflags |= PVF_REF; 3395135641Scognet 3396144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3397144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3398129198Scognet /* 3399135641Scognet * This is a writable mapping, and the 3400135641Scognet * page's mod state indicates it has 3401135641Scognet * already been modified. Make it 3402135641Scognet * writable from the outset. 3403129198Scognet */ 3404135641Scognet nflags |= PVF_MOD; 3405157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3406144760Scognet vm_page_dirty(m); 3407129198Scognet } 3408144760Scognet if (m && opte) 3409225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 3410135641Scognet } else { 3411135641Scognet /* 3412135641Scognet * Need to do page referenced emulation. 3413135641Scognet */ 3414135641Scognet npte |= L2_TYPE_INV; 3415135641Scognet } 3416135641Scognet 3417164229Salc if (prot & VM_PROT_WRITE) { 3418135641Scognet npte |= L2_S_PROT_W; 3419208846Salc if (m != NULL && 3420224746Skib (m->oflags & VPO_UNMANAGED) == 0) 3421225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 3422164229Salc } 3423135641Scognet npte |= pte_l2_s_cache_mode; 3424135641Scognet if (m && m == opg) { 3425135641Scognet /* 3426135641Scognet * We're changing the attrs of an existing mapping. 3427135641Scognet */ 3428135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3429135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3430135641Scognet PVF_MOD | PVF_REF, nflags); 3431135641Scognet 3432135641Scognet /* 3433135641Scognet * We may need to flush the cache if we're 3434135641Scognet * doing rw-ro... 3435135641Scognet */ 3436135641Scognet if (pmap_is_current(pmap) && 3437135641Scognet (oflags & PVF_NC) == 0 && 3438183838Sraj (opte & L2_S_PROT_W) != 0 && 3439203637Sraj (prot & VM_PROT_WRITE) == 0 && 3440203637Sraj (opte & L2_TYPE_MASK) != L2_TYPE_INV) { 3441135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3442203637Sraj cpu_l2cache_wb_range(va, PAGE_SIZE); 3443183838Sraj } 3444129198Scognet } else { 3445129198Scognet /* 3446135641Scognet * New mapping, or changing the backing page 3447135641Scognet * of an existing mapping. 3448129198Scognet */ 3449129198Scognet if (opg) { 3450129198Scognet /* 3451135641Scognet * Replacing an existing mapping with a new one. 3452135641Scognet * It is part of our managed memory so we 3453135641Scognet * must remove it from the PV list 3454129198Scognet */ 3455194459Sthompsa if ((pve = pmap_remove_pv(opg, pmap, va))) { 3456194459Sthompsa 3457194459Sthompsa /* note for patch: the oflags/invalidation was moved 3458194459Sthompsa * because PG_FICTITIOUS pages could free the pve 3459194459Sthompsa */ 3460194459Sthompsa oflags = pve->pv_flags; 3461135641Scognet /* 3462135641Scognet * If the old mapping was valid (ref/mod 3463135641Scognet * emulation creates 'invalid' mappings 3464135641Scognet * initially) then make sure to frob 3465135641Scognet * the cache. 3466135641Scognet */ 3467194459Sthompsa if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 3468135641Scognet if (PV_BEEN_EXECD(oflags)) { 3469129198Scognet pmap_idcache_wbinv_range(pmap, va, 3470129198Scognet PAGE_SIZE); 3471135641Scognet } else 3472135641Scognet if (PV_BEEN_REFD(oflags)) { 3473135641Scognet pmap_dcache_wb_range(pmap, va, 3474135641Scognet PAGE_SIZE, TRUE, 3475135641Scognet (oflags & PVF_WRITE) == 0); 3476135641Scognet } 3477194459Sthompsa } 3478194459Sthompsa 3479194459Sthompsa /* free/allocate a pv_entry for UNMANAGED pages if 3480194459Sthompsa * this physical page is not/is already mapped. 3481194459Sthompsa */ 3482194459Sthompsa 3483224746Skib if (m && (m->oflags & VPO_UNMANAGED) && 3484194459Sthompsa !m->md.pv_kva && 3485224746Skib TAILQ_EMPTY(&m->md.pv_list)) { 3486194459Sthompsa pmap_free_pv_entry(pve); 3487194459Sthompsa pve = NULL; 3488194459Sthompsa } 3489224746Skib } else if (m && 3490224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3491194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3492194459Sthompsa pve = pmap_get_pv_entry(); 3493224746Skib } else if (m && 3494224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3495194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3496194459Sthompsa pve = pmap_get_pv_entry(); 3497194459Sthompsa 3498224746Skib if (m) { 3499224746Skib if ((m->oflags & VPO_UNMANAGED)) { 3500194459Sthompsa if (!TAILQ_EMPTY(&m->md.pv_list) || 3501224746Skib m->md.pv_kva) { 3502194459Sthompsa KASSERT(pve != NULL, ("No pv")); 3503194459Sthompsa nflags |= PVF_UNMAN; 3504194459Sthompsa pmap_enter_pv(m, pve, pmap, va, nflags); 3505194459Sthompsa } else 3506194459Sthompsa m->md.pv_kva = va; 3507194459Sthompsa } else { 3508224746Skib KASSERT(va < kmi.clean_sva || 3509224746Skib va >= kmi.clean_eva, 3510224746Skib ("pmap_enter: managed mapping within the clean submap")); 3511224746Skib KASSERT(pve != NULL, ("No pv")); 3512224746Skib pmap_enter_pv(m, pve, pmap, va, nflags); 3513129198Scognet } 3514157970Scognet } 3515129198Scognet } 3516129198Scognet /* 3517129198Scognet * Make sure userland mappings get the right permissions 3518129198Scognet */ 3519129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3520129198Scognet npte |= L2_S_PROT_U; 3521129198Scognet } 3522129198Scognet 3523129198Scognet /* 3524129198Scognet * Keep the stats up to date 3525129198Scognet */ 3526129198Scognet if (opte == 0) { 3527129198Scognet l2b->l2b_occupancy++; 3528129198Scognet pmap->pm_stats.resident_count++; 3529236991Simp } 3530129198Scognet 3531129198Scognet /* 3532129198Scognet * If this is just a wiring change, the two PTEs will be 3533129198Scognet * identical, so there's no need to update the page table. 3534129198Scognet */ 3535129198Scognet if (npte != opte) { 3536135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3537129198Scognet 3538129198Scognet *ptep = npte; 3539129198Scognet if (is_cached) { 3540129198Scognet /* 3541129198Scognet * We only need to frob the cache/tlb if this pmap 3542129198Scognet * is current 3543129198Scognet */ 3544129198Scognet PTE_SYNC(ptep); 3545236991Simp if (L1_IDX(va) != L1_IDX(vector_page) && 3546129198Scognet l2pte_valid(npte)) { 3547129198Scognet /* 3548129198Scognet * This mapping is likely to be accessed as 3549129198Scognet * soon as we return to userland. Fix up the 3550129198Scognet * L1 entry to avoid taking another 3551129198Scognet * page/domain fault. 3552129198Scognet */ 3553129198Scognet pd_entry_t *pl1pd, l1pd; 3554129198Scognet 3555129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3556129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3557144760Scognet L1_C_PROTO; 3558129198Scognet if (*pl1pd != l1pd) { 3559129198Scognet *pl1pd = l1pd; 3560129198Scognet PTE_SYNC(pl1pd); 3561129198Scognet } 3562129198Scognet } 3563129198Scognet } 3564129198Scognet 3565129198Scognet if (PV_BEEN_EXECD(oflags)) 3566129198Scognet pmap_tlb_flushID_SE(pmap, va); 3567135641Scognet else if (PV_BEEN_REFD(oflags)) 3568129198Scognet pmap_tlb_flushD_SE(pmap, va); 3569129198Scognet 3570129198Scognet 3571157025Scognet if (m) 3572175840Scognet pmap_fix_cache(m, pmap, va); 3573129198Scognet } 3574129198Scognet} 3575129198Scognet 3576129198Scognet/* 3577159303Salc * Maps a sequence of resident pages belonging to the same object. 3578159303Salc * The sequence begins with the given page m_start. This page is 3579159303Salc * mapped at the given virtual address start. Each subsequent page is 3580159303Salc * mapped at a virtual address that is offset from start by the same 3581159303Salc * amount as the page is offset from m_start within the object. The 3582159303Salc * last page in the sequence is the page with the largest offset from 3583159303Salc * m_start that can be mapped at a virtual address less than the given 3584159303Salc * virtual address end. Not every virtual page between start and end 3585159303Salc * is mapped; only those for which a resident page exists with the 3586159303Salc * corresponding offset from m_start are mapped. 3587159303Salc */ 3588159303Salcvoid 3589159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3590159303Salc vm_page_t m_start, vm_prot_t prot) 3591159303Salc{ 3592159303Salc vm_page_t m; 3593159303Salc vm_pindex_t diff, psize; 3594159303Salc 3595159303Salc psize = atop(end - start); 3596159303Salc m = m_start; 3597208574Salc vm_page_lock_queues(); 3598159325Salc PMAP_LOCK(pmap); 3599159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3600159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3601160260Scognet (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT); 3602159303Salc m = TAILQ_NEXT(m, listq); 3603159303Salc } 3604208574Salc vm_page_unlock_queues(); 3605159325Salc PMAP_UNLOCK(pmap); 3606159303Salc} 3607159303Salc 3608159303Salc/* 3609129198Scognet * this code makes some *MAJOR* assumptions: 3610129198Scognet * 1. Current pmap & pmap exists. 3611129198Scognet * 2. Not wired. 3612129198Scognet * 3. Read access. 3613129198Scognet * 4. No page table pages. 3614129198Scognet * but is *MUCH* faster than pmap_enter... 3615129198Scognet */ 3616129198Scognet 3617159627Supsvoid 3618159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3619129198Scognet{ 3620138897Salc 3621207796Salc vm_page_lock_queues(); 3622159325Salc PMAP_LOCK(pmap); 3623159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3624160260Scognet FALSE, M_NOWAIT); 3625207796Salc vm_page_unlock_queues(); 3626159325Salc PMAP_UNLOCK(pmap); 3627129198Scognet} 3628129198Scognet 3629129198Scognet/* 3630129198Scognet * Routine: pmap_change_wiring 3631129198Scognet * Function: Change the wiring attribute for a map/virtual-address 3632129198Scognet * pair. 3633129198Scognet * In/out conditions: 3634129198Scognet * The mapping must already exist in the pmap. 3635129198Scognet */ 3636129198Scognetvoid 3637129198Scognetpmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3638129198Scognet{ 3639129198Scognet struct l2_bucket *l2b; 3640129198Scognet pt_entry_t *ptep, pte; 3641129198Scognet vm_page_t pg; 3642129198Scognet 3643159352Salc vm_page_lock_queues(); 3644159325Salc PMAP_LOCK(pmap); 3645129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3646129198Scognet KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3647129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3648129198Scognet pte = *ptep; 3649129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3650236991Simp if (pg) 3651221844Scognet pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired ? PVF_WIRED : 0); 3652159352Salc vm_page_unlock_queues(); 3653159325Salc PMAP_UNLOCK(pmap); 3654129198Scognet} 3655129198Scognet 3656129198Scognet 3657129198Scognet/* 3658129198Scognet * Copy the range specified by src_addr/len 3659129198Scognet * from the source map to the range dst_addr/len 3660129198Scognet * in the destination map. 3661129198Scognet * 3662129198Scognet * This routine is only advisory and need not do anything. 3663129198Scognet */ 3664129198Scognetvoid 3665129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3666129198Scognet vm_size_t len, vm_offset_t src_addr) 3667129198Scognet{ 3668129198Scognet} 3669129198Scognet 3670129198Scognet 3671129198Scognet/* 3672129198Scognet * Routine: pmap_extract 3673129198Scognet * Function: 3674129198Scognet * Extract the physical page address associated 3675129198Scognet * with the given map/virtual_address pair. 3676129198Scognet */ 3677131658Salcvm_paddr_t 3678129198Scognetpmap_extract(pmap_t pm, vm_offset_t va) 3679129198Scognet{ 3680129198Scognet struct l2_dtable *l2; 3681159450Salc pd_entry_t l1pd; 3682129198Scognet pt_entry_t *ptep, pte; 3683129198Scognet vm_paddr_t pa; 3684129198Scognet u_int l1idx; 3685129198Scognet l1idx = L1_IDX(va); 3686129198Scognet 3687159450Salc PMAP_LOCK(pm); 3688159450Salc l1pd = pm->pm_l1->l1_kva[l1idx]; 3689129198Scognet if (l1pte_section_p(l1pd)) { 3690129198Scognet /* 3691129198Scognet * These should only happen for pmap_kernel() 3692129198Scognet */ 3693129198Scognet KASSERT(pm == pmap_kernel(), ("huh")); 3694171620Scognet /* XXX: what to do about the bits > 32 ? */ 3695236991Simp if (l1pd & L1_S_SUPERSEC) 3696171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3697171620Scognet else 3698171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3699129198Scognet } else { 3700129198Scognet /* 3701129198Scognet * Note that we can't rely on the validity of the L1 3702129198Scognet * descriptor as an indication that a mapping exists. 3703129198Scognet * We have to look it up in the L2 dtable. 3704129198Scognet */ 3705129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3706129198Scognet 3707129198Scognet if (l2 == NULL || 3708129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3709159450Salc PMAP_UNLOCK(pm); 3710129198Scognet return (0); 3711129198Scognet } 3712129198Scognet 3713129198Scognet ptep = &ptep[l2pte_index(va)]; 3714129198Scognet pte = *ptep; 3715129198Scognet 3716159450Salc if (pte == 0) { 3717159450Salc PMAP_UNLOCK(pm); 3718129198Scognet return (0); 3719159450Salc } 3720129198Scognet 3721129198Scognet switch (pte & L2_TYPE_MASK) { 3722129198Scognet case L2_TYPE_L: 3723129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3724129198Scognet break; 3725129198Scognet 3726129198Scognet default: 3727129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3728129198Scognet break; 3729129198Scognet } 3730129198Scognet } 3731129198Scognet 3732159450Salc PMAP_UNLOCK(pm); 3733129198Scognet return (pa); 3734129198Scognet} 3735129198Scognet 3736133453Salc/* 3737133453Salc * Atomically extract and hold the physical page with the given 3738133453Salc * pmap and virtual address pair if that mapping permits the given 3739133453Salc * protection. 3740133453Salc * 3741133453Salc */ 3742129198Scognetvm_page_t 3743129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3744129198Scognet{ 3745135641Scognet struct l2_dtable *l2; 3746159378Salc pd_entry_t l1pd; 3747135641Scognet pt_entry_t *ptep, pte; 3748207410Skmacy vm_paddr_t pa, paddr; 3749135641Scognet vm_page_t m = NULL; 3750135641Scognet u_int l1idx; 3751135641Scognet l1idx = L1_IDX(va); 3752207410Skmacy paddr = 0; 3753129198Scognet 3754159325Salc PMAP_LOCK(pmap); 3755207410Skmacyretry: 3756159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3757135641Scognet if (l1pte_section_p(l1pd)) { 3758135641Scognet /* 3759135641Scognet * These should only happen for pmap_kernel() 3760135641Scognet */ 3761135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3762171620Scognet /* XXX: what to do about the bits > 32 ? */ 3763236991Simp if (l1pd & L1_S_SUPERSEC) 3764171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3765171620Scognet else 3766171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3767207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3768207410Skmacy goto retry; 3769135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3770135641Scognet m = PHYS_TO_VM_PAGE(pa); 3771135641Scognet vm_page_hold(m); 3772135641Scognet } 3773135641Scognet 3774135641Scognet } else { 3775135641Scognet /* 3776135641Scognet * Note that we can't rely on the validity of the L1 3777135641Scognet * descriptor as an indication that a mapping exists. 3778135641Scognet * We have to look it up in the L2 dtable. 3779135641Scognet */ 3780135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3781135641Scognet 3782135641Scognet if (l2 == NULL || 3783135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3784159325Salc PMAP_UNLOCK(pmap); 3785135641Scognet return (NULL); 3786135641Scognet } 3787135641Scognet 3788135641Scognet ptep = &ptep[l2pte_index(va)]; 3789135641Scognet pte = *ptep; 3790135641Scognet 3791150865Scognet if (pte == 0) { 3792159325Salc PMAP_UNLOCK(pmap); 3793135641Scognet return (NULL); 3794150865Scognet } 3795135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3796135641Scognet switch (pte & L2_TYPE_MASK) { 3797135641Scognet case L2_TYPE_L: 3798135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3799135641Scognet break; 3800135641Scognet 3801135641Scognet default: 3802135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3803135641Scognet break; 3804135641Scognet } 3805207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3806207410Skmacy goto retry; 3807135641Scognet m = PHYS_TO_VM_PAGE(pa); 3808135641Scognet vm_page_hold(m); 3809135641Scognet } 3810129198Scognet } 3811135641Scognet 3812159325Salc PMAP_UNLOCK(pmap); 3813207410Skmacy PA_UNLOCK_COND(paddr); 3814129198Scognet return (m); 3815129198Scognet} 3816129198Scognet 3817129198Scognet/* 3818129198Scognet * Initialize a preallocated and zeroed pmap structure, 3819129198Scognet * such as one in a vmspace structure. 3820129198Scognet */ 3821129198Scognet 3822173361Skibint 3823129198Scognetpmap_pinit(pmap_t pmap) 3824129198Scognet{ 3825129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3826129198Scognet 3827159325Salc PMAP_LOCK_INIT(pmap); 3828129198Scognet pmap_alloc_l1(pmap); 3829129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3830129198Scognet 3831222813Sattilio CPU_ZERO(&pmap->pm_active); 3832129198Scognet 3833144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3834129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3835129198Scognet pmap->pm_stats.resident_count = 1; 3836129198Scognet if (vector_page < KERNBASE) { 3837175840Scognet pmap_enter(pmap, vector_page, 3838175397Scognet VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa), 3839129198Scognet VM_PROT_READ, 1); 3840236991Simp } 3841173361Skib return (1); 3842129198Scognet} 3843129198Scognet 3844129198Scognet 3845129198Scognet/*************************************************** 3846129198Scognet * page management routines. 3847129198Scognet ***************************************************/ 3848129198Scognet 3849129198Scognet 3850135641Scognetstatic void 3851129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3852129198Scognet{ 3853129198Scognet pv_entry_count--; 3854129198Scognet uma_zfree(pvzone, pv); 3855129198Scognet} 3856129198Scognet 3857129198Scognet 3858129198Scognet/* 3859129198Scognet * get a new pv_entry, allocating a block from the system 3860129198Scognet * when needed. 3861129198Scognet * the memory allocation is performed bypassing the malloc code 3862129198Scognet * because of the possibility of allocations at interrupt time. 3863129198Scognet */ 3864129198Scognetstatic pv_entry_t 3865129198Scognetpmap_get_pv_entry(void) 3866129198Scognet{ 3867129198Scognet pv_entry_t ret_value; 3868129198Scognet 3869129198Scognet pv_entry_count++; 3870159500Salc if (pv_entry_count > pv_entry_high_water) 3871159500Salc pagedaemon_wakeup(); 3872129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3873129198Scognet return ret_value; 3874129198Scognet} 3875129198Scognet 3876129198Scognet/* 3877129198Scognet * Remove the given range of addresses from the specified map. 3878129198Scognet * 3879129198Scognet * It is assumed that the start and end are properly 3880129198Scognet * rounded to the page size. 3881129198Scognet */ 3882175840Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3883129198Scognetvoid 3884129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3885129198Scognet{ 3886129198Scognet struct l2_bucket *l2b; 3887129198Scognet vm_offset_t next_bucket; 3888129198Scognet pt_entry_t *ptep; 3889175840Scognet u_int total; 3890129198Scognet u_int mappings, is_exec, is_refd; 3891135641Scognet int flushall = 0; 3892129198Scognet 3893129198Scognet 3894129198Scognet /* 3895129198Scognet * we lock in the pmap => pv_head direction 3896129198Scognet */ 3897129198Scognet 3898137664Scognet vm_page_lock_queues(); 3899159352Salc PMAP_LOCK(pm); 3900129198Scognet total = 0; 3901129198Scognet while (sva < eva) { 3902129198Scognet /* 3903129198Scognet * Do one L2 bucket's worth at a time. 3904129198Scognet */ 3905129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3906129198Scognet if (next_bucket > eva) 3907129198Scognet next_bucket = eva; 3908129198Scognet 3909129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3910129198Scognet if (l2b == NULL) { 3911129198Scognet sva = next_bucket; 3912129198Scognet continue; 3913129198Scognet } 3914129198Scognet 3915129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3916129198Scognet mappings = 0; 3917129198Scognet 3918129198Scognet while (sva < next_bucket) { 3919129198Scognet struct vm_page *pg; 3920129198Scognet pt_entry_t pte; 3921129198Scognet vm_paddr_t pa; 3922129198Scognet 3923129198Scognet pte = *ptep; 3924129198Scognet 3925129198Scognet if (pte == 0) { 3926129198Scognet /* 3927129198Scognet * Nothing here, move along 3928129198Scognet */ 3929129198Scognet sva += PAGE_SIZE; 3930129198Scognet ptep++; 3931129198Scognet continue; 3932129198Scognet } 3933129198Scognet 3934129198Scognet pm->pm_stats.resident_count--; 3935129198Scognet pa = l2pte_pa(pte); 3936129198Scognet is_exec = 0; 3937129198Scognet is_refd = 1; 3938129198Scognet 3939129198Scognet /* 3940129198Scognet * Update flags. In a number of circumstances, 3941129198Scognet * we could cluster a lot of these and do a 3942129198Scognet * number of sequential pages in one go. 3943129198Scognet */ 3944129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3945129198Scognet struct pv_entry *pve; 3946159474Salc 3947129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3948135641Scognet if (pve) { 3949159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3950159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3951129198Scognet pmap_free_pv_entry(pve); 3952129198Scognet } 3953129198Scognet } 3954129198Scognet 3955175840Scognet if (l2pte_valid(pte) && pmap_is_current(pm)) { 3956175840Scognet if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3957175840Scognet total++; 3958175840Scognet if (is_exec) { 3959175840Scognet cpu_idcache_wbinv_range(sva, 3960183838Sraj PAGE_SIZE); 3961183838Sraj cpu_l2cache_wbinv_range(sva, 3962183838Sraj PAGE_SIZE); 3963175840Scognet cpu_tlb_flushID_SE(sva); 3964175840Scognet } else if (is_refd) { 3965175840Scognet cpu_dcache_wbinv_range(sva, 3966183838Sraj PAGE_SIZE); 3967183838Sraj cpu_l2cache_wbinv_range(sva, 3968183838Sraj PAGE_SIZE); 3969175840Scognet cpu_tlb_flushD_SE(sva); 3970175840Scognet } 3971175840Scognet } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3972175840Scognet /* flushall will also only get set for 3973175840Scognet * for a current pmap 3974175840Scognet */ 3975175840Scognet cpu_idcache_wbinv_all(); 3976183838Sraj cpu_l2cache_wbinv_all(); 3977175840Scognet flushall = 1; 3978175840Scognet total++; 3979129198Scognet } 3980129198Scognet } 3981175840Scognet *ptep = 0; 3982175840Scognet PTE_SYNC(ptep); 3983129198Scognet 3984129198Scognet sva += PAGE_SIZE; 3985129198Scognet ptep++; 3986129198Scognet mappings++; 3987129198Scognet } 3988129198Scognet 3989129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 3990129198Scognet } 3991129198Scognet 3992137664Scognet vm_page_unlock_queues(); 3993135641Scognet if (flushall) 3994135641Scognet cpu_tlb_flushID(); 3995159352Salc PMAP_UNLOCK(pm); 3996129198Scognet} 3997129198Scognet 3998129198Scognet/* 3999129198Scognet * pmap_zero_page() 4000236991Simp * 4001129198Scognet * Zero a given physical page by mapping it at a page hook point. 4002129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 4003129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 4004129198Scognet * _any_ bulk data very slow. 4005129198Scognet */ 4006164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) 4007129198Scognetvoid 4008129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 4009129198Scognet{ 4010161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4011161105Scognet char *dstpg; 4012161105Scognet#endif 4013161105Scognet 4014172300Scognet if (_arm_bzero && size >= _min_bzero_size && 4015150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4016150865Scognet return; 4017129198Scognet 4018161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4019161105Scognet dstpg = (char *)arm_ptovirt(phys); 4020161105Scognet if (off || size != PAGE_SIZE) { 4021161105Scognet bzero(dstpg + off, size); 4022161105Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4023183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size); 4024161105Scognet } else { 4025161105Scognet bzero_page((vm_offset_t)dstpg); 4026161105Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4027183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4028161105Scognet } 4029161105Scognet#else 4030150865Scognet 4031159088Scognet mtx_lock(&cmtx); 4032129198Scognet /* 4033183836Sraj * Hook in the page, zero it, invalidate the TLB as needed. 4034183836Sraj * 4035183836Sraj * Note the temporary zero-page mapping must be a non-cached page in 4036184730Sraj * order to work without corruption when write-allocate is enabled. 4037129198Scognet */ 4038183836Sraj *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 4039228530Sraj PTE_SYNC(cdst_pte); 4040129198Scognet cpu_tlb_flushD_SE(cdstp); 4041129198Scognet cpu_cpwait(); 4042183836Sraj if (off || size != PAGE_SIZE) 4043129198Scognet bzero((void *)(cdstp + off), size); 4044183836Sraj else 4045129198Scognet bzero_page(cdstp); 4046183836Sraj 4047159088Scognet mtx_unlock(&cmtx); 4048161105Scognet#endif 4049129198Scognet} 4050129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4051129198Scognet 4052129198Scognet#if ARM_MMU_XSCALE == 1 4053129198Scognetvoid 4054129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 4055129198Scognet{ 4056172713Scognet#ifdef ARM_USE_SMALL_ALLOC 4057172713Scognet char *dstpg; 4058172713Scognet#endif 4059172713Scognet 4060172300Scognet if (_arm_bzero && size >= _min_bzero_size && 4061150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4062150865Scognet return; 4063172713Scognet#ifdef ARM_USE_SMALL_ALLOC 4064172713Scognet dstpg = (char *)arm_ptovirt(phys); 4065172713Scognet if (off || size != PAGE_SIZE) { 4066172713Scognet bzero(dstpg + off, size); 4067172713Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4068172713Scognet } else { 4069172713Scognet bzero_page((vm_offset_t)dstpg); 4070172713Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4071172713Scognet } 4072172713Scognet#else 4073159088Scognet mtx_lock(&cmtx); 4074129198Scognet /* 4075129198Scognet * Hook in the page, zero it, and purge the cache for that 4076129198Scognet * zeroed page. Invalidate the TLB as needed. 4077129198Scognet */ 4078129198Scognet *cdst_pte = L2_S_PROTO | phys | 4079129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4080129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4081129198Scognet PTE_SYNC(cdst_pte); 4082129198Scognet cpu_tlb_flushD_SE(cdstp); 4083129198Scognet cpu_cpwait(); 4084135641Scognet if (off || size != PAGE_SIZE) 4085129198Scognet bzero((void *)(cdstp + off), size); 4086129198Scognet else 4087129198Scognet bzero_page(cdstp); 4088159088Scognet mtx_unlock(&cmtx); 4089129198Scognet xscale_cache_clean_minidata(); 4090172713Scognet#endif 4091129198Scognet} 4092129198Scognet 4093129198Scognet/* 4094129198Scognet * Change the PTEs for the specified kernel mappings such that they 4095129198Scognet * will use the mini data cache instead of the main data cache. 4096129198Scognet */ 4097129198Scognetvoid 4098135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 4099129198Scognet{ 4100129198Scognet struct l2_bucket *l2b; 4101129198Scognet pt_entry_t *ptep, *sptep, pte; 4102129198Scognet vm_offset_t next_bucket, eva; 4103129198Scognet 4104164778Scognet#if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3) 4105129198Scognet if (xscale_use_minidata == 0) 4106129198Scognet return; 4107129198Scognet#endif 4108129198Scognet 4109135641Scognet eva = va + size; 4110129198Scognet 4111129198Scognet while (va < eva) { 4112129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4113129198Scognet if (next_bucket > eva) 4114129198Scognet next_bucket = eva; 4115129198Scognet 4116129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4117129198Scognet 4118129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4119129198Scognet 4120129198Scognet while (va < next_bucket) { 4121129198Scognet pte = *ptep; 4122129198Scognet if (!l2pte_minidata(pte)) { 4123129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4124129198Scognet cpu_tlb_flushD_SE(va); 4125129198Scognet *ptep = pte & ~L2_B; 4126129198Scognet } 4127129198Scognet ptep++; 4128129198Scognet va += PAGE_SIZE; 4129129198Scognet } 4130129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4131129198Scognet } 4132129198Scognet cpu_cpwait(); 4133129198Scognet} 4134129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4135129198Scognet 4136129198Scognet/* 4137236991Simp * pmap_zero_page zeros the specified hardware page by mapping 4138129198Scognet * the page into KVM and using bzero to clear its contents. 4139129198Scognet */ 4140129198Scognetvoid 4141129198Scognetpmap_zero_page(vm_page_t m) 4142129198Scognet{ 4143135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4144129198Scognet} 4145129198Scognet 4146129198Scognet 4147129198Scognet/* 4148236991Simp * pmap_zero_page_area zeros the specified hardware page by mapping 4149129198Scognet * the page into KVM and using bzero to clear its contents. 4150129198Scognet * 4151129198Scognet * off and size may not cover an area beyond a single hardware page. 4152129198Scognet */ 4153129198Scognetvoid 4154129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4155129198Scognet{ 4156129198Scognet 4157129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4158129198Scognet} 4159129198Scognet 4160129198Scognet 4161129198Scognet/* 4162236991Simp * pmap_zero_page_idle zeros the specified hardware page by mapping 4163129198Scognet * the page into KVM and using bzero to clear its contents. This 4164129198Scognet * is intended to be called from the vm_pagezero process only and 4165129198Scognet * outside of Giant. 4166129198Scognet */ 4167129198Scognetvoid 4168129198Scognetpmap_zero_page_idle(vm_page_t m) 4169129198Scognet{ 4170129198Scognet 4171129198Scognet pmap_zero_page(m); 4172129198Scognet} 4173129198Scognet 4174150865Scognet#if 0 4175129198Scognet/* 4176129198Scognet * pmap_clean_page() 4177129198Scognet * 4178129198Scognet * This is a local function used to work out the best strategy to clean 4179197770Sstas * a single page referenced by its entry in the PV table. It should be used by 4180129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4181129198Scognet * 4182129198Scognet * Its policy is effectively: 4183129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4184129198Scognet * o If there is one mapping, we clean just that page. 4185129198Scognet * o If there are multiple mappings, we clean the entire cache. 4186129198Scognet * 4187129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4188129198Scognet * clean the entire cache, or 1 if it did. 4189129198Scognet * 4190129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4191129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4192129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4193129198Scognet * it will just result in not the most efficient clean for the page. 4194197770Sstas * 4195197770Sstas * We don't yet use this function but may want to. 4196129198Scognet */ 4197129198Scognetstatic int 4198129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4199129198Scognet{ 4200129198Scognet pmap_t pm, pm_to_clean = NULL; 4201129198Scognet struct pv_entry *npv; 4202129198Scognet u_int cache_needs_cleaning = 0; 4203129198Scognet u_int flags = 0; 4204129198Scognet vm_offset_t page_to_clean = 0; 4205129198Scognet 4206129198Scognet if (pv == NULL) { 4207129198Scognet /* nothing mapped in so nothing to flush */ 4208129198Scognet return (0); 4209129198Scognet } 4210129198Scognet 4211129198Scognet /* 4212129198Scognet * Since we flush the cache each time we change to a different 4213129198Scognet * user vmspace, we only need to flush the page if it is in the 4214129198Scognet * current pmap. 4215129198Scognet */ 4216135641Scognet if (curthread) 4217135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4218129198Scognet else 4219129198Scognet pm = pmap_kernel(); 4220129198Scognet 4221129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4222129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4223129198Scognet flags |= npv->pv_flags; 4224129198Scognet /* 4225236991Simp * The page is mapped non-cacheable in 4226129198Scognet * this map. No need to flush the cache. 4227129198Scognet */ 4228129198Scognet if (npv->pv_flags & PVF_NC) { 4229129198Scognet#ifdef DIAGNOSTIC 4230129198Scognet if (cache_needs_cleaning) 4231129198Scognet panic("pmap_clean_page: " 4232129198Scognet "cache inconsistency"); 4233129198Scognet#endif 4234129198Scognet break; 4235129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4236129198Scognet continue; 4237129198Scognet if (cache_needs_cleaning) { 4238129198Scognet page_to_clean = 0; 4239129198Scognet break; 4240129198Scognet } else { 4241129198Scognet page_to_clean = npv->pv_va; 4242129198Scognet pm_to_clean = npv->pv_pmap; 4243129198Scognet } 4244129198Scognet cache_needs_cleaning = 1; 4245129198Scognet } 4246129198Scognet } 4247129198Scognet if (page_to_clean) { 4248129198Scognet if (PV_BEEN_EXECD(flags)) 4249129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4250129198Scognet PAGE_SIZE); 4251129198Scognet else 4252129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4253129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4254129198Scognet } else if (cache_needs_cleaning) { 4255129198Scognet if (PV_BEEN_EXECD(flags)) 4256129198Scognet pmap_idcache_wbinv_all(pm); 4257129198Scognet else 4258129198Scognet pmap_dcache_wbinv_all(pm); 4259129198Scognet return (1); 4260129198Scognet } 4261129198Scognet return (0); 4262129198Scognet} 4263150865Scognet#endif 4264129198Scognet 4265129198Scognet/* 4266129198Scognet * pmap_copy_page copies the specified (machine independent) 4267129198Scognet * page by mapping the page into virtual memory and using 4268129198Scognet * bcopy to copy the page, one machine dependent page at a 4269129198Scognet * time. 4270129198Scognet */ 4271129198Scognet 4272129198Scognet/* 4273129198Scognet * pmap_copy_page() 4274129198Scognet * 4275129198Scognet * Copy one physical page into another, by mapping the pages into 4276129198Scognet * hook points. The same comment regarding cachability as in 4277129198Scognet * pmap_zero_page also applies here. 4278129198Scognet */ 4279164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) 4280129198Scognetvoid 4281129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4282129198Scognet{ 4283151596Scognet#if 0 4284129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4285151596Scognet#endif 4286129198Scognet 4287129198Scognet /* 4288129198Scognet * Clean the source page. Hold the source page's lock for 4289129198Scognet * the duration of the copy so that no other mappings can 4290129198Scognet * be created while we have a potentially aliased mapping. 4291129198Scognet */ 4292129198Scognet#if 0 4293150865Scognet /* 4294150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4295150865Scognet * pmap_copy_page(). 4296150865Scognet */ 4297129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4298150865Scognet#endif 4299129198Scognet /* 4300129198Scognet * Map the pages into the page hook points, copy them, and purge 4301129198Scognet * the cache for the appropriate page. Invalidate the TLB 4302129198Scognet * as required. 4303129198Scognet */ 4304159088Scognet mtx_lock(&cmtx); 4305129198Scognet *csrc_pte = L2_S_PROTO | src | 4306129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4307129198Scognet PTE_SYNC(csrc_pte); 4308129198Scognet *cdst_pte = L2_S_PROTO | dst | 4309129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4310129198Scognet PTE_SYNC(cdst_pte); 4311129198Scognet cpu_tlb_flushD_SE(csrcp); 4312129198Scognet cpu_tlb_flushD_SE(cdstp); 4313129198Scognet cpu_cpwait(); 4314129198Scognet bcopy_page(csrcp, cdstp); 4315159088Scognet mtx_unlock(&cmtx); 4316129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4317129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4318183838Sraj cpu_l2cache_inv_range(csrcp, PAGE_SIZE); 4319183838Sraj cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE); 4320129198Scognet} 4321129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4322129198Scognet 4323129198Scognet#if ARM_MMU_XSCALE == 1 4324129198Scognetvoid 4325129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4326129198Scognet{ 4327150865Scognet#if 0 4328150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4329129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4330150865Scognet#endif 4331129198Scognet 4332129198Scognet /* 4333129198Scognet * Clean the source page. Hold the source page's lock for 4334129198Scognet * the duration of the copy so that no other mappings can 4335129198Scognet * be created while we have a potentially aliased mapping. 4336129198Scognet */ 4337150865Scognet#if 0 4338150865Scognet /* 4339150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4340150865Scognet * pmap_copy_page(). 4341150865Scognet */ 4342130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4343150865Scognet#endif 4344129198Scognet /* 4345129198Scognet * Map the pages into the page hook points, copy them, and purge 4346129198Scognet * the cache for the appropriate page. Invalidate the TLB 4347129198Scognet * as required. 4348129198Scognet */ 4349159088Scognet mtx_lock(&cmtx); 4350129198Scognet *csrc_pte = L2_S_PROTO | src | 4351129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4352129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4353129198Scognet PTE_SYNC(csrc_pte); 4354129198Scognet *cdst_pte = L2_S_PROTO | dst | 4355129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4356129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4357129198Scognet PTE_SYNC(cdst_pte); 4358129198Scognet cpu_tlb_flushD_SE(csrcp); 4359129198Scognet cpu_tlb_flushD_SE(cdstp); 4360129198Scognet cpu_cpwait(); 4361129198Scognet bcopy_page(csrcp, cdstp); 4362159088Scognet mtx_unlock(&cmtx); 4363129198Scognet xscale_cache_clean_minidata(); 4364129198Scognet} 4365129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4366129198Scognet 4367129198Scognetvoid 4368129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4369129198Scognet{ 4370161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4371161105Scognet vm_offset_t srcpg, dstpg; 4372161105Scognet#endif 4373161105Scognet 4374146596Scognet cpu_dcache_wbinv_all(); 4375183838Sraj cpu_l2cache_wbinv_all(); 4376172300Scognet if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size && 4377236991Simp _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4378150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4379150865Scognet return; 4380161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4381161105Scognet srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src)); 4382161105Scognet dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst)); 4383161105Scognet bcopy_page(srcpg, dstpg); 4384161105Scognet cpu_dcache_wbinv_range(dstpg, PAGE_SIZE); 4385183838Sraj cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE); 4386161105Scognet#else 4387129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4388161105Scognet#endif 4389129198Scognet} 4390129198Scognet 4391129198Scognet 4392129198Scognet 4393129198Scognet 4394129198Scognet/* 4395129198Scognet * this routine returns true if a physical page resides 4396129198Scognet * in the given pmap. 4397129198Scognet */ 4398129198Scognetboolean_t 4399129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4400129198Scognet{ 4401129198Scognet pv_entry_t pv; 4402129198Scognet int loops = 0; 4403208990Salc boolean_t rv; 4404129198Scognet 4405224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4406208990Salc ("pmap_page_exists_quick: page %p is not managed", m)); 4407208990Salc rv = FALSE; 4408208990Salc vm_page_lock_queues(); 4409208990Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4410129198Scognet if (pv->pv_pmap == pmap) { 4411208990Salc rv = TRUE; 4412208990Salc break; 4413129198Scognet } 4414129198Scognet loops++; 4415129198Scognet if (loops >= 16) 4416129198Scognet break; 4417129198Scognet } 4418208990Salc vm_page_unlock_queues(); 4419208990Salc return (rv); 4420129198Scognet} 4421129198Scognet 4422173708Salc/* 4423173708Salc * pmap_page_wired_mappings: 4424173708Salc * 4425173708Salc * Return the number of managed mappings to the given physical page 4426173708Salc * that are wired. 4427173708Salc */ 4428173708Salcint 4429173708Salcpmap_page_wired_mappings(vm_page_t m) 4430173708Salc{ 4431173708Salc pv_entry_t pv; 4432173708Salc int count; 4433129198Scognet 4434173708Salc count = 0; 4435224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 4436173708Salc return (count); 4437207796Salc vm_page_lock_queues(); 4438173708Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 4439173708Salc if ((pv->pv_flags & PVF_WIRED) != 0) 4440173708Salc count++; 4441207796Salc vm_page_unlock_queues(); 4442173708Salc return (count); 4443173708Salc} 4444173708Salc 4445129198Scognet/* 4446129198Scognet * pmap_ts_referenced: 4447129198Scognet * 4448129198Scognet * Return the count of reference bits for a page, clearing all of them. 4449129198Scognet */ 4450129198Scognetint 4451129198Scognetpmap_ts_referenced(vm_page_t m) 4452129198Scognet{ 4453164778Scognet 4454224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4455208990Salc ("pmap_ts_referenced: page %p is not managed", m)); 4456135641Scognet return (pmap_clearbit(m, PVF_REF)); 4457129198Scognet} 4458129198Scognet 4459129198Scognet 4460129198Scognetboolean_t 4461129198Scognetpmap_is_modified(vm_page_t m) 4462129198Scognet{ 4463135641Scognet 4464224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4465208504Salc ("pmap_is_modified: page %p is not managed", m)); 4466135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4467135641Scognet return (TRUE); 4468129198Scognet 4469129198Scognet return(FALSE); 4470129198Scognet} 4471129198Scognet 4472129198Scognet 4473129198Scognet/* 4474129198Scognet * Clear the modify bits on the specified physical page. 4475129198Scognet */ 4476129198Scognetvoid 4477129198Scognetpmap_clear_modify(vm_page_t m) 4478129198Scognet{ 4479129198Scognet 4480224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4481208504Salc ("pmap_clear_modify: page %p is not managed", m)); 4482208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4483208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 4484208504Salc ("pmap_clear_modify: page %p is busy", m)); 4485208504Salc 4486208504Salc /* 4487225418Skib * If the page is not PGA_WRITEABLE, then no mappings can be modified. 4488208504Salc * If the object containing the page is locked and the page is not 4489225418Skib * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 4490208504Salc */ 4491225418Skib if ((m->aflags & PGA_WRITEABLE) == 0) 4492208504Salc return; 4493129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4494129198Scognet pmap_clearbit(m, PVF_MOD); 4495129198Scognet} 4496129198Scognet 4497129198Scognet 4498129198Scognet/* 4499207155Salc * pmap_is_referenced: 4500207155Salc * 4501207155Salc * Return whether or not the specified physical page was referenced 4502207155Salc * in any physical maps. 4503207155Salc */ 4504207155Salcboolean_t 4505207155Salcpmap_is_referenced(vm_page_t m) 4506207155Salc{ 4507207155Salc 4508224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4509208574Salc ("pmap_is_referenced: page %p is not managed", m)); 4510208574Salc return ((m->md.pvh_attrs & PVF_REF) != 0); 4511207155Salc} 4512207155Salc 4513207155Salc/* 4514129198Scognet * pmap_clear_reference: 4515129198Scognet * 4516129198Scognet * Clear the reference bit on the specified physical page. 4517129198Scognet */ 4518129198Scognetvoid 4519129198Scognetpmap_clear_reference(vm_page_t m) 4520129198Scognet{ 4521129198Scognet 4522224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4523208504Salc ("pmap_clear_reference: page %p is not managed", m)); 4524236991Simp if (m->md.pvh_attrs & PVF_REF) 4525129198Scognet pmap_clearbit(m, PVF_REF); 4526129198Scognet} 4527129198Scognet 4528129198Scognet 4529129198Scognet/* 4530160537Salc * Clear the write and modified bits in each of the given page's mappings. 4531160537Salc */ 4532160537Salcvoid 4533160889Salcpmap_remove_write(vm_page_t m) 4534160537Salc{ 4535160537Salc 4536224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4537208175Salc ("pmap_remove_write: page %p is not managed", m)); 4538208175Salc 4539208175Salc /* 4540225418Skib * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 4541225418Skib * another thread while the object is locked. Thus, if PGA_WRITEABLE 4542208175Salc * is clear, no page table entries need updating. 4543208175Salc */ 4544208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4545208175Salc if ((m->oflags & VPO_BUSY) != 0 || 4546225418Skib (m->aflags & PGA_WRITEABLE) != 0) 4547160537Salc pmap_clearbit(m, PVF_WRITE); 4548160537Salc} 4549160537Salc 4550160537Salc 4551160537Salc/* 4552129198Scognet * perform the pmap work for mincore 4553129198Scognet */ 4554129198Scognetint 4555208504Salcpmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4556129198Scognet{ 4557235717Simp struct l2_bucket *l2b; 4558235717Simp pt_entry_t *ptep, pte; 4559235717Simp vm_paddr_t pa; 4560235717Simp vm_page_t m; 4561235717Simp int val; 4562235717Simp boolean_t managed; 4563235717Simp 4564235717Simp PMAP_LOCK(pmap); 4565235717Simpretry: 4566235717Simp l2b = pmap_get_l2_bucket(pmap, addr); 4567235717Simp if (l2b == NULL) { 4568235717Simp val = 0; 4569235717Simp goto out; 4570235717Simp } 4571235717Simp ptep = &l2b->l2b_kva[l2pte_index(addr)]; 4572235717Simp pte = *ptep; 4573235717Simp if (!l2pte_valid(pte)) { 4574235717Simp val = 0; 4575235717Simp goto out; 4576235717Simp } 4577235717Simp val = MINCORE_INCORE; 4578235717Simp if (pte & L2_S_PROT_W) 4579235717Simp val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4580235717Simp managed = false; 4581235717Simp pa = l2pte_pa(pte); 4582235717Simp m = PHYS_TO_VM_PAGE(pa); 4583235717Simp if (m != NULL && !(m->oflags & VPO_UNMANAGED)) 4584235717Simp managed = true; 4585235717Simp if (managed) { 4586235717Simp /* 4587235717Simp * the ARM pmap tries to maintain a per-mapping 4588235717Simp * reference bit. The trouble is that it's kept in 4589235717Simp * the PV entry, not the PTE, so it's costly to access 4590235717Simp * here. You would need to acquire the page queues 4591235717Simp * lock, call pmap_find_pv(), and introduce a custom 4592235717Simp * version of vm_page_pa_tryrelock() that releases and 4593235717Simp * reacquires the page queues lock. In the end, I 4594235717Simp * doubt it's worthwhile. This may falsely report 4595235717Simp * the given address as referenced. 4596235717Simp */ 4597235717Simp if ((m->md.pvh_attrs & PVF_REF) != 0) 4598235717Simp val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4599235717Simp } 4600235717Simp if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4601235717Simp (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 4602235717Simp /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4603235717Simp if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4604235717Simp goto retry; 4605235717Simp } else 4606235717Simpout: 4607235717Simp PA_UNLOCK_COND(*locked_pa); 4608235717Simp PMAP_UNLOCK(pmap); 4609235717Simp return (val); 4610129198Scognet} 4611129198Scognet 4612129198Scognet 4613198341Smarcelvoid 4614198341Smarcelpmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4615198341Smarcel{ 4616198341Smarcel} 4617198341Smarcel 4618198341Smarcel 4619178893Salc/* 4620178893Salc * Increase the starting virtual address of the given mapping if a 4621178893Salc * different alignment might result in more superpage mappings. 4622178893Salc */ 4623178893Salcvoid 4624178893Salcpmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4625178893Salc vm_offset_t *addr, vm_size_t size) 4626178893Salc{ 4627178893Salc} 4628129198Scognet 4629178893Salc 4630129198Scognet/* 4631129198Scognet * Map a set of physical memory pages into the kernel virtual 4632129198Scognet * address space. Return a pointer to where it is mapped. This 4633129198Scognet * routine is intended to be used for mapping device memory, 4634129198Scognet * NOT real memory. 4635129198Scognet */ 4636129198Scognetvoid * 4637129198Scognetpmap_mapdev(vm_offset_t pa, vm_size_t size) 4638129198Scognet{ 4639129198Scognet vm_offset_t va, tmpva, offset; 4640129198Scognet 4641129198Scognet offset = pa & PAGE_MASK; 4642135641Scognet size = roundup(size, PAGE_SIZE); 4643129198Scognet 4644129198Scognet GIANT_REQUIRED; 4645129198Scognet 4646132560Salc va = kmem_alloc_nofault(kernel_map, size); 4647129198Scognet if (!va) 4648129198Scognet panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4649129198Scognet for (tmpva = va; size > 0;) { 4650135641Scognet pmap_kenter_internal(tmpva, pa, 0); 4651129198Scognet size -= PAGE_SIZE; 4652129198Scognet tmpva += PAGE_SIZE; 4653129198Scognet pa += PAGE_SIZE; 4654129198Scognet } 4655129198Scognet 4656159068Sbenno return ((void *)(va + offset)); 4657129198Scognet} 4658129198Scognet 4659129198Scognet#define BOOTSTRAP_DEBUG 4660129198Scognet 4661129198Scognet/* 4662129198Scognet * pmap_map_section: 4663129198Scognet * 4664129198Scognet * Create a single section mapping. 4665129198Scognet */ 4666129198Scognetvoid 4667129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4668129198Scognet int prot, int cache) 4669129198Scognet{ 4670129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4671129198Scognet pd_entry_t fl; 4672129198Scognet 4673129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4674129198Scognet 4675129198Scognet switch (cache) { 4676129198Scognet case PTE_NOCACHE: 4677129198Scognet default: 4678129198Scognet fl = 0; 4679129198Scognet break; 4680129198Scognet 4681129198Scognet case PTE_CACHE: 4682129198Scognet fl = pte_l1_s_cache_mode; 4683129198Scognet break; 4684129198Scognet 4685129198Scognet case PTE_PAGETABLE: 4686129198Scognet fl = pte_l1_s_cache_mode_pt; 4687129198Scognet break; 4688129198Scognet } 4689129198Scognet 4690129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4691129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4692129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4693129198Scognet 4694129198Scognet} 4695129198Scognet 4696129198Scognet/* 4697129198Scognet * pmap_link_l2pt: 4698129198Scognet * 4699164079Scognet * Link the L2 page table specified by l2pv.pv_pa into the L1 4700129198Scognet * page table at the slot for "va". 4701129198Scognet */ 4702129198Scognetvoid 4703129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4704129198Scognet{ 4705129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4706129198Scognet u_int slot = va >> L1_S_SHIFT; 4707129198Scognet 4708129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4709129198Scognet 4710236991Simp#ifdef VERBOSE_INIT_ARM 4711164079Scognet printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 4712164079Scognet#endif 4713164079Scognet 4714129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4715164079Scognet 4716129198Scognet PTE_SYNC(&pde[slot]); 4717129198Scognet 4718129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4719129198Scognet 4720129198Scognet 4721129198Scognet} 4722129198Scognet 4723129198Scognet/* 4724129198Scognet * pmap_map_entry 4725129198Scognet * 4726129198Scognet * Create a single page mapping. 4727129198Scognet */ 4728129198Scognetvoid 4729129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4730129198Scognet int cache) 4731129198Scognet{ 4732129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4733129198Scognet pt_entry_t fl; 4734129198Scognet pt_entry_t *pte; 4735129198Scognet 4736129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4737129198Scognet 4738129198Scognet switch (cache) { 4739129198Scognet case PTE_NOCACHE: 4740129198Scognet default: 4741129198Scognet fl = 0; 4742129198Scognet break; 4743129198Scognet 4744129198Scognet case PTE_CACHE: 4745129198Scognet fl = pte_l2_s_cache_mode; 4746129198Scognet break; 4747129198Scognet 4748129198Scognet case PTE_PAGETABLE: 4749129198Scognet fl = pte_l2_s_cache_mode_pt; 4750129198Scognet break; 4751129198Scognet } 4752129198Scognet 4753129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4754129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4755129198Scognet 4756129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4757129198Scognet 4758129198Scognet if (pte == NULL) 4759129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4760129198Scognet 4761129198Scognet pte[l2pte_index(va)] = 4762129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4763129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4764129198Scognet} 4765129198Scognet 4766129198Scognet/* 4767129198Scognet * pmap_map_chunk: 4768129198Scognet * 4769129198Scognet * Map a chunk of memory using the most efficient mappings 4770129198Scognet * possible (section. large page, small page) into the 4771129198Scognet * provided L1 and L2 tables at the specified virtual address. 4772129198Scognet */ 4773129198Scognetvm_size_t 4774129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4775129198Scognet vm_size_t size, int prot, int cache) 4776129198Scognet{ 4777129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4778129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4779236991Simp vm_size_t resid; 4780129198Scognet int i; 4781129198Scognet 4782129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4783129198Scognet 4784129198Scognet if (l1pt == 0) 4785129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4786129198Scognet 4787236991Simp#ifdef VERBOSE_INIT_ARM 4788159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4789129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4790129198Scognet#endif 4791129198Scognet 4792129198Scognet switch (cache) { 4793129198Scognet case PTE_NOCACHE: 4794129198Scognet default: 4795129198Scognet f1 = 0; 4796129198Scognet f2l = 0; 4797129198Scognet f2s = 0; 4798129198Scognet break; 4799129198Scognet 4800129198Scognet case PTE_CACHE: 4801129198Scognet f1 = pte_l1_s_cache_mode; 4802129198Scognet f2l = pte_l2_l_cache_mode; 4803129198Scognet f2s = pte_l2_s_cache_mode; 4804129198Scognet break; 4805129198Scognet 4806129198Scognet case PTE_PAGETABLE: 4807129198Scognet f1 = pte_l1_s_cache_mode_pt; 4808129198Scognet f2l = pte_l2_l_cache_mode_pt; 4809129198Scognet f2s = pte_l2_s_cache_mode_pt; 4810129198Scognet break; 4811129198Scognet } 4812129198Scognet 4813129198Scognet size = resid; 4814129198Scognet 4815129198Scognet while (resid > 0) { 4816129198Scognet /* See if we can use a section mapping. */ 4817129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4818129198Scognet#ifdef VERBOSE_INIT_ARM 4819129198Scognet printf("S"); 4820129198Scognet#endif 4821129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4822129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4823129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4824129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4825129198Scognet va += L1_S_SIZE; 4826129198Scognet pa += L1_S_SIZE; 4827129198Scognet resid -= L1_S_SIZE; 4828129198Scognet continue; 4829129198Scognet } 4830129198Scognet 4831129198Scognet /* 4832129198Scognet * Ok, we're going to use an L2 table. Make sure 4833129198Scognet * one is actually in the corresponding L1 slot 4834129198Scognet * for the current VA. 4835129198Scognet */ 4836129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4837129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4838129198Scognet 4839129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4840129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4841129198Scognet if (pte == NULL) 4842129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4843129198Scognet "0x%08x", va); 4844129198Scognet /* See if we can use a L2 large page mapping. */ 4845129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4846129198Scognet#ifdef VERBOSE_INIT_ARM 4847129198Scognet printf("L"); 4848129198Scognet#endif 4849129198Scognet for (i = 0; i < 16; i++) { 4850129198Scognet pte[l2pte_index(va) + i] = 4851129198Scognet L2_L_PROTO | pa | 4852129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4853129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4854129198Scognet } 4855129198Scognet va += L2_L_SIZE; 4856129198Scognet pa += L2_L_SIZE; 4857129198Scognet resid -= L2_L_SIZE; 4858129198Scognet continue; 4859129198Scognet } 4860129198Scognet 4861129198Scognet /* Use a small page mapping. */ 4862129198Scognet#ifdef VERBOSE_INIT_ARM 4863129198Scognet printf("P"); 4864129198Scognet#endif 4865129198Scognet pte[l2pte_index(va)] = 4866129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4867129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4868129198Scognet va += PAGE_SIZE; 4869129198Scognet pa += PAGE_SIZE; 4870129198Scognet resid -= PAGE_SIZE; 4871129198Scognet } 4872129198Scognet#ifdef VERBOSE_INIT_ARM 4873129198Scognet printf("\n"); 4874129198Scognet#endif 4875129198Scognet return (size); 4876129198Scognet 4877129198Scognet} 4878129198Scognet 4879135641Scognet/********************** Static device map routines ***************************/ 4880135641Scognet 4881135641Scognetstatic const struct pmap_devmap *pmap_devmap_table; 4882135641Scognet 4883135641Scognet/* 4884135641Scognet * Register the devmap table. This is provided in case early console 4885135641Scognet * initialization needs to register mappings created by bootstrap code 4886135641Scognet * before pmap_devmap_bootstrap() is called. 4887135641Scognet */ 4888135641Scognetvoid 4889135641Scognetpmap_devmap_register(const struct pmap_devmap *table) 4890135641Scognet{ 4891135641Scognet 4892135641Scognet pmap_devmap_table = table; 4893135641Scognet} 4894135641Scognet 4895135641Scognet/* 4896135641Scognet * Map all of the static regions in the devmap table, and remember 4897135641Scognet * the devmap table so other parts of the kernel can look up entries 4898135641Scognet * later. 4899135641Scognet */ 4900135641Scognetvoid 4901135641Scognetpmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4902135641Scognet{ 4903135641Scognet int i; 4904135641Scognet 4905135641Scognet pmap_devmap_table = table; 4906135641Scognet 4907135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4908135641Scognet#ifdef VERBOSE_INIT_ARM 4909159322Scognet printf("devmap: %08x -> %08x @ %08x\n", 4910135641Scognet pmap_devmap_table[i].pd_pa, 4911135641Scognet pmap_devmap_table[i].pd_pa + 4912135641Scognet pmap_devmap_table[i].pd_size - 1, 4913135641Scognet pmap_devmap_table[i].pd_va); 4914135641Scognet#endif 4915135641Scognet pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4916135641Scognet pmap_devmap_table[i].pd_pa, 4917135641Scognet pmap_devmap_table[i].pd_size, 4918135641Scognet pmap_devmap_table[i].pd_prot, 4919135641Scognet pmap_devmap_table[i].pd_cache); 4920135641Scognet } 4921135641Scognet} 4922135641Scognet 4923135641Scognetconst struct pmap_devmap * 4924135641Scognetpmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4925135641Scognet{ 4926135641Scognet int i; 4927135641Scognet 4928135641Scognet if (pmap_devmap_table == NULL) 4929135641Scognet return (NULL); 4930135641Scognet 4931135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4932135641Scognet if (pa >= pmap_devmap_table[i].pd_pa && 4933135641Scognet pa + size <= pmap_devmap_table[i].pd_pa + 4934135641Scognet pmap_devmap_table[i].pd_size) 4935135641Scognet return (&pmap_devmap_table[i]); 4936135641Scognet } 4937135641Scognet 4938135641Scognet return (NULL); 4939135641Scognet} 4940135641Scognet 4941135641Scognetconst struct pmap_devmap * 4942135641Scognetpmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4943135641Scognet{ 4944135641Scognet int i; 4945135641Scognet 4946135641Scognet if (pmap_devmap_table == NULL) 4947135641Scognet return (NULL); 4948135641Scognet 4949135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4950135641Scognet if (va >= pmap_devmap_table[i].pd_va && 4951135641Scognet va + size <= pmap_devmap_table[i].pd_va + 4952135641Scognet pmap_devmap_table[i].pd_size) 4953135641Scognet return (&pmap_devmap_table[i]); 4954135641Scognet } 4955135641Scognet 4956135641Scognet return (NULL); 4957135641Scognet} 4958135641Scognet 4959