pmap-v4.c revision 208175
1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 81129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 82129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 83129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 84129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 85129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 86129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 87129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 88129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 89129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 90129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 91129198Scognet * POSSIBILITY OF SUCH DAMAGE. 92129198Scognet */ 93129198Scognet 94139735Simp/*- 95129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 96129198Scognet * Copyright (c) 1994 Brini. 97129198Scognet * All rights reserved. 98139735Simp * 99129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 100129198Scognet * 101129198Scognet * Redistribution and use in source and binary forms, with or without 102129198Scognet * modification, are permitted provided that the following conditions 103129198Scognet * are met: 104129198Scognet * 1. Redistributions of source code must retain the above copyright 105129198Scognet * notice, this list of conditions and the following disclaimer. 106129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 107129198Scognet * notice, this list of conditions and the following disclaimer in the 108129198Scognet * documentation and/or other materials provided with the distribution. 109129198Scognet * 3. All advertising materials mentioning features or use of this software 110129198Scognet * must display the following acknowledgement: 111129198Scognet * This product includes software developed by Mark Brinicombe. 112129198Scognet * 4. The name of the author may not be used to endorse or promote products 113129198Scognet * derived from this software without specific prior written permission. 114129198Scognet * 115129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 116129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 117129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 118129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 119129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 120129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 121129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 122129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 123129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 124129198Scognet * 125129198Scognet * RiscBSD kernel project 126129198Scognet * 127129198Scognet * pmap.c 128129198Scognet * 129129198Scognet * Machine dependant vm stuff 130129198Scognet * 131129198Scognet * Created : 20/09/94 132129198Scognet */ 133129198Scognet 134129198Scognet/* 135129198Scognet * Special compilation symbols 136129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 137129198Scognet */ 138129198Scognet/* Include header files */ 139135641Scognet 140137552Scognet#include "opt_vm.h" 141137552Scognet 142129198Scognet#include <sys/cdefs.h> 143129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 208175 2010-05-16 23:45:10Z alc $"); 144129198Scognet#include <sys/param.h> 145129198Scognet#include <sys/systm.h> 146129198Scognet#include <sys/kernel.h> 147183838Sraj#include <sys/ktr.h> 148129198Scognet#include <sys/proc.h> 149129198Scognet#include <sys/malloc.h> 150129198Scognet#include <sys/msgbuf.h> 151129198Scognet#include <sys/vmmeter.h> 152129198Scognet#include <sys/mman.h> 153129198Scognet#include <sys/smp.h> 154129198Scognet#include <sys/sched.h> 155129198Scognet 156129198Scognet#include <vm/vm.h> 157129198Scognet#include <vm/uma.h> 158129198Scognet#include <vm/pmap.h> 159129198Scognet#include <vm/vm_kern.h> 160129198Scognet#include <vm/vm_object.h> 161129198Scognet#include <vm/vm_map.h> 162129198Scognet#include <vm/vm_page.h> 163129198Scognet#include <vm/vm_pageout.h> 164129198Scognet#include <vm/vm_extern.h> 165129198Scognet#include <sys/lock.h> 166129198Scognet#include <sys/mutex.h> 167129198Scognet#include <machine/md_var.h> 168129198Scognet#include <machine/vmparam.h> 169129198Scognet#include <machine/cpu.h> 170129198Scognet#include <machine/cpufunc.h> 171129198Scognet#include <machine/pcb.h> 172129198Scognet 173129198Scognet#ifdef PMAP_DEBUG 174129198Scognet#define PDEBUG(_lev_,_stat_) \ 175129198Scognet if (pmap_debug_level >= (_lev_)) \ 176129198Scognet ((_stat_)) 177129198Scognet#define dprintf printf 178129198Scognet 179129198Scognetint pmap_debug_level = 0; 180135641Scognet#define PMAP_INLINE 181129198Scognet#else /* PMAP_DEBUG */ 182129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 183129198Scognet#define dprintf(x, arg...) 184135641Scognet#define PMAP_INLINE __inline 185129198Scognet#endif /* PMAP_DEBUG */ 186129198Scognet 187129198Scognetextern struct pv_addr systempage; 188129198Scognet/* 189129198Scognet * Internal function prototypes 190129198Scognet */ 191135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 192129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 193129198Scognet 194159127Salcstatic void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 195160260Scognet vm_prot_t, boolean_t, int); 196194459Sthompsastatic void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t); 197129198Scognetstatic void pmap_alloc_l1(pmap_t); 198129198Scognetstatic void pmap_free_l1(pmap_t); 199129198Scognet 200135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 201129198Scognet 202129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 203129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 204129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 205129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 206129198Scognet 207129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 208129198Scognet 209129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 210129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 211135641Scognetvm_offset_t pmap_curmaxkvaddr; 212150865Scognetvm_paddr_t kernel_l1pa; 213129198Scognet 214129198Scognetextern void *end; 215129198Scognetvm_offset_t kernel_vm_end = 0; 216129198Scognet 217129198Scognetstruct pmap kernel_pmap_store; 218129198Scognet 219129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 220129198Scognetstatic vm_offset_t csrcp, cdstp; 221159088Scognetstatic struct mtx cmtx; 222159088Scognet 223129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 224129198Scognet/* 225129198Scognet * These routines are called when the CPU type is identified to set up 226129198Scognet * the PTE prototypes, cache modes, etc. 227129198Scognet * 228129198Scognet * The variables are always here, just in case LKMs need to reference 229129198Scognet * them (though, they shouldn't). 230129198Scognet */ 231129198Scognet 232129198Scognetpt_entry_t pte_l1_s_cache_mode; 233129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 234129198Scognetpt_entry_t pte_l1_s_cache_mask; 235129198Scognet 236129198Scognetpt_entry_t pte_l2_l_cache_mode; 237129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 238129198Scognetpt_entry_t pte_l2_l_cache_mask; 239129198Scognet 240129198Scognetpt_entry_t pte_l2_s_cache_mode; 241129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 242129198Scognetpt_entry_t pte_l2_s_cache_mask; 243129198Scognet 244129198Scognetpt_entry_t pte_l2_s_prot_u; 245129198Scognetpt_entry_t pte_l2_s_prot_w; 246129198Scognetpt_entry_t pte_l2_s_prot_mask; 247129198Scognet 248129198Scognetpt_entry_t pte_l1_s_proto; 249129198Scognetpt_entry_t pte_l1_c_proto; 250129198Scognetpt_entry_t pte_l2_s_proto; 251129198Scognet 252129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 253129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 254129198Scognet/* 255129198Scognet * Which pmap is currently 'live' in the cache 256129198Scognet * 257129198Scognet * XXXSCW: Fix for SMP ... 258129198Scognet */ 259129198Scognetunion pmap_cache_state *pmap_cache_state; 260129198Scognet 261129198Scognetstruct msgbuf *msgbufp = 0; 262129198Scognet 263184728Sraj/* 264184728Sraj * Crashdump maps. 265184728Sraj */ 266184728Srajstatic caddr_t crashdumpmap; 267184728Sraj 268129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 269129198Scognetextern void bzero_page(vm_offset_t); 270137362Scognet 271164079Scognetextern vm_offset_t alloc_firstaddr; 272164079Scognet 273137362Scognetchar *_tmppt; 274137362Scognet 275129198Scognet/* 276129198Scognet * Metadata for L1 translation tables. 277129198Scognet */ 278129198Scognetstruct l1_ttable { 279129198Scognet /* Entry on the L1 Table list */ 280129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 281129198Scognet 282129198Scognet /* Entry on the L1 Least Recently Used list */ 283129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 284129198Scognet 285129198Scognet /* Track how many domains are allocated from this L1 */ 286129198Scognet volatile u_int l1_domain_use_count; 287129198Scognet 288129198Scognet /* 289129198Scognet * A free-list of domain numbers for this L1. 290129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 291129198Scognet * is slow on ARM. 292129198Scognet */ 293129198Scognet u_int8_t l1_domain_first; 294129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 295129198Scognet 296129198Scognet /* Physical address of this L1 page table */ 297129198Scognet vm_paddr_t l1_physaddr; 298129198Scognet 299129198Scognet /* KVA of this L1 page table */ 300129198Scognet pd_entry_t *l1_kva; 301129198Scognet}; 302129198Scognet 303129198Scognet/* 304129198Scognet * Convert a virtual address into its L1 table index. That is, the 305129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 306129198Scognet * This is basically used to index l1->l1_kva[]. 307129198Scognet * 308129198Scognet * Each L2 descriptor table represents 1MB of VA space. 309129198Scognet */ 310129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 311129198Scognet 312129198Scognet/* 313129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 314129198Scognet * - New L1s are allocated from the HEAD. 315129198Scognet * - Freed L1s are added to the TAIl. 316129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 317129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 318129198Scognet */ 319129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 320135641Scognet/* 321135641Scognet * A list of all L1 tables 322135641Scognet */ 323135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 324129198Scognetstatic struct mtx l1_lru_lock; 325129198Scognet 326129198Scognet/* 327129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 328129198Scognet * 329129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 330129198Scognet * Reference counts are maintained for L2 descriptors so they can be 331129198Scognet * freed when empty. 332129198Scognet */ 333129198Scognetstruct l2_dtable { 334129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 335129198Scognet u_int l2_occupancy; 336129198Scognet 337129198Scognet /* List of L2 page descriptors */ 338129198Scognet struct l2_bucket { 339129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 340129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 341129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 342129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 343129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 344129198Scognet}; 345129198Scognet 346135641Scognet/* pmap_kenter_internal flags */ 347135641Scognet#define KENTER_CACHE 0x1 348142570Scognet#define KENTER_USER 0x2 349135641Scognet 350129198Scognet/* 351129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 352129198Scognet * and bucket index within the l2_dtable. 353129198Scognet */ 354129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 355129198Scognet (L2_SIZE - 1)) 356129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 357129198Scognet 358129198Scognet/* 359129198Scognet * Given a virtual address, this macro returns the 360129198Scognet * virtual address required to drop into the next L2 bucket. 361129198Scognet */ 362129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 363129198Scognet 364129198Scognet/* 365129198Scognet * L2 allocation. 366129198Scognet */ 367129198Scognet#define pmap_alloc_l2_dtable() \ 368160260Scognet (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE) 369129198Scognet#define pmap_free_l2_dtable(l2) \ 370129198Scognet uma_zfree(l2table_zone, l2) 371129198Scognet 372129198Scognet/* 373129198Scognet * We try to map the page tables write-through, if possible. However, not 374129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 375129198Scognet * the cache when we frob page tables. 376129198Scognet * 377129198Scognet * We try to evaluate this at compile time, if possible. However, it's 378129198Scognet * not always possible to do that, hence this run-time var. 379129198Scognet */ 380129198Scognetint pmap_needs_pte_sync; 381129198Scognet 382129198Scognet/* 383129198Scognet * Macro to determine if a mapping might be resident in the 384129198Scognet * instruction cache and/or TLB 385129198Scognet */ 386129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 387129198Scognet 388129198Scognet/* 389129198Scognet * Macro to determine if a mapping might be resident in the 390129198Scognet * data cache and/or TLB 391129198Scognet */ 392129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 393129198Scognet 394129198Scognet#ifndef PMAP_SHPGPERPROC 395129198Scognet#define PMAP_SHPGPERPROC 200 396129198Scognet#endif 397129198Scognet 398135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 399135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 400194459Sthompsastatic uma_zone_t pvzone = NULL; 401147114Scognetuma_zone_t l2zone; 402129198Scognetstatic uma_zone_t l2table_zone; 403135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 404135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 405135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 406129198Scognetstatic struct vm_object pvzone_obj; 407129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 408129198Scognet 409129198Scognet/* 410129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 411129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 412129198Scognet * find them as necessary. 413129198Scognet * 414129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 415129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 416129198Scognet */ 417129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 418129198Scognet 419129198Scognetstatic void 420129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 421129198Scognet{ 422129198Scognet int i; 423129198Scognet 424129198Scognet l1->l1_kva = l1pt; 425129198Scognet l1->l1_domain_use_count = 0; 426174181Scognet l1->l1_domain_first = 0; 427129198Scognet 428129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 429174181Scognet l1->l1_domain_free[i] = i + 1; 430129198Scognet 431129198Scognet /* 432129198Scognet * Copy the kernel's L1 entries to each new L1. 433129198Scognet */ 434147249Scognet if (l1pt != pmap_kernel()->pm_l1->l1_kva) 435129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 436129198Scognet 437129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 438129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 439135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 440129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 441129198Scognet} 442129198Scognet 443129198Scognetstatic vm_offset_t 444129198Scognetkernel_pt_lookup(vm_paddr_t pa) 445129198Scognet{ 446129198Scognet struct pv_addr *pv; 447129198Scognet 448129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 449129198Scognet if (pv->pv_pa == pa) 450129198Scognet return (pv->pv_va); 451129198Scognet } 452129198Scognet return (0); 453129198Scognet} 454129198Scognet 455129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 456129198Scognetvoid 457129198Scognetpmap_pte_init_generic(void) 458129198Scognet{ 459129198Scognet 460129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 461129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 462129198Scognet 463129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 464129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 465129198Scognet 466129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 467129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 468129198Scognet 469129198Scognet /* 470129198Scognet * If we have a write-through cache, set B and C. If 471129198Scognet * we have a write-back cache, then we assume setting 472129198Scognet * only C will make those pages write-through. 473129198Scognet */ 474129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 475129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 476129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 477129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 478129198Scognet } else { 479129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 480129198Scognet pte_l2_l_cache_mode_pt = L2_C; 481129198Scognet pte_l2_s_cache_mode_pt = L2_C; 482129198Scognet } 483129198Scognet 484129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 485129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 486129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 487129198Scognet 488129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 489129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 490129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 491129198Scognet 492129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 493129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 494129198Scognet} 495129198Scognet 496129198Scognet#if defined(CPU_ARM8) 497129198Scognetvoid 498129198Scognetpmap_pte_init_arm8(void) 499129198Scognet{ 500129198Scognet 501129198Scognet /* 502129198Scognet * ARM8 is compatible with generic, but we need to use 503129198Scognet * the page tables uncached. 504129198Scognet */ 505129198Scognet pmap_pte_init_generic(); 506129198Scognet 507129198Scognet pte_l1_s_cache_mode_pt = 0; 508129198Scognet pte_l2_l_cache_mode_pt = 0; 509129198Scognet pte_l2_s_cache_mode_pt = 0; 510129198Scognet} 511129198Scognet#endif /* CPU_ARM8 */ 512129198Scognet 513129198Scognet#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 514129198Scognetvoid 515129198Scognetpmap_pte_init_arm9(void) 516129198Scognet{ 517129198Scognet 518129198Scognet /* 519129198Scognet * ARM9 is compatible with generic, but we want to use 520129198Scognet * write-through caching for now. 521129198Scognet */ 522129198Scognet pmap_pte_init_generic(); 523129198Scognet 524129198Scognet pte_l1_s_cache_mode = L1_S_C; 525129198Scognet pte_l2_l_cache_mode = L2_C; 526129198Scognet pte_l2_s_cache_mode = L2_C; 527129198Scognet 528129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 529129198Scognet pte_l2_l_cache_mode_pt = L2_C; 530129198Scognet pte_l2_s_cache_mode_pt = L2_C; 531129198Scognet} 532129198Scognet#endif /* CPU_ARM9 */ 533129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 534129198Scognet 535129198Scognet#if defined(CPU_ARM10) 536129198Scognetvoid 537129198Scognetpmap_pte_init_arm10(void) 538129198Scognet{ 539129198Scognet 540129198Scognet /* 541129198Scognet * ARM10 is compatible with generic, but we want to use 542129198Scognet * write-through caching for now. 543129198Scognet */ 544129198Scognet pmap_pte_init_generic(); 545129198Scognet 546129198Scognet pte_l1_s_cache_mode = L1_S_B | L1_S_C; 547129198Scognet pte_l2_l_cache_mode = L2_B | L2_C; 548129198Scognet pte_l2_s_cache_mode = L2_B | L2_C; 549129198Scognet 550129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 551129198Scognet pte_l2_l_cache_mode_pt = L2_C; 552129198Scognet pte_l2_s_cache_mode_pt = L2_C; 553129198Scognet 554129198Scognet} 555129198Scognet#endif /* CPU_ARM10 */ 556129198Scognet 557129198Scognet#if ARM_MMU_SA1 == 1 558129198Scognetvoid 559129198Scognetpmap_pte_init_sa1(void) 560129198Scognet{ 561129198Scognet 562129198Scognet /* 563129198Scognet * The StrongARM SA-1 cache does not have a write-through 564129198Scognet * mode. So, do the generic initialization, then reset 565129198Scognet * the page table cache mode to B=1,C=1, and note that 566129198Scognet * the PTEs need to be sync'd. 567129198Scognet */ 568129198Scognet pmap_pte_init_generic(); 569129198Scognet 570129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 571129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 572129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 573129198Scognet 574129198Scognet pmap_needs_pte_sync = 1; 575129198Scognet} 576129198Scognet#endif /* ARM_MMU_SA1 == 1*/ 577129198Scognet 578129198Scognet#if ARM_MMU_XSCALE == 1 579164778Scognet#if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) 580129198Scognetstatic u_int xscale_use_minidata; 581129198Scognet#endif 582129198Scognet 583129198Scognetvoid 584129198Scognetpmap_pte_init_xscale(void) 585129198Scognet{ 586129198Scognet uint32_t auxctl; 587129198Scognet int write_through = 0; 588129198Scognet 589135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 590129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 591129198Scognet 592129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 593129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 594129198Scognet 595129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 596129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 597129198Scognet 598129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 599129198Scognet pte_l2_l_cache_mode_pt = L2_C; 600129198Scognet pte_l2_s_cache_mode_pt = L2_C; 601129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 602129198Scognet /* 603129198Scognet * The XScale core has an enhanced mode where writes that 604129198Scognet * miss the cache cause a cache line to be allocated. This 605129198Scognet * is significantly faster than the traditional, write-through 606129198Scognet * behavior of this case. 607129198Scognet */ 608129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 609129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 610129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 611129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 612129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 613129198Scognet /* 614129198Scognet * Some versions of the XScale core have various bugs in 615129198Scognet * their cache units, the work-around for which is to run 616129198Scognet * the cache in write-through mode. Unfortunately, this 617129198Scognet * has a major (negative) impact on performance. So, we 618129198Scognet * go ahead and run fast-and-loose, in the hopes that we 619129198Scognet * don't line up the planets in a way that will trip the 620129198Scognet * bugs. 621129198Scognet * 622129198Scognet * However, we give you the option to be slow-but-correct. 623129198Scognet */ 624129198Scognet write_through = 1; 625129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 626129198Scognet /* force write back cache mode */ 627129198Scognet write_through = 0; 628129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 629129198Scognet /* 630129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 631129198Scognet * write-back cache on revision 4 and earlier (stepping 632129198Scognet * A[01] and B[012]). Fixed for C0 and later. 633129198Scognet */ 634129198Scognet { 635129198Scognet uint32_t id, type; 636129198Scognet 637129198Scognet id = cpufunc_id(); 638129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 639129198Scognet 640129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 641129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 642129198Scognet /* write through for stepping A0-1 and B0-2 */ 643129198Scognet write_through = 1; 644129198Scognet } 645129198Scognet } 646129198Scognet } 647129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 648129198Scognet 649129198Scognet if (write_through) { 650129198Scognet pte_l1_s_cache_mode = L1_S_C; 651129198Scognet pte_l2_l_cache_mode = L2_C; 652129198Scognet pte_l2_s_cache_mode = L2_C; 653129198Scognet } 654129198Scognet 655129198Scognet#if (ARM_NMMUS > 1) 656129198Scognet xscale_use_minidata = 1; 657129198Scognet#endif 658129198Scognet 659129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 660129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 661129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 662129198Scognet 663129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 664129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 665129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 666129198Scognet 667164778Scognet#ifdef CPU_XSCALE_CORE3 668164778Scognet pmap_copy_page_func = pmap_copy_page_generic; 669164778Scognet pmap_zero_page_func = pmap_zero_page_generic; 670164778Scognet xscale_use_minidata = 0; 671171620Scognet /* Make sure it is L2-cachable */ 672171620Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T); 673171620Scognet pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P; 674171620Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ; 675171620Scognet pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode; 676171620Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T); 677171620Scognet pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 678171620Scognet 679164778Scognet#else 680129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 681129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 682164778Scognet#endif 683129198Scognet 684129198Scognet /* 685129198Scognet * Disable ECC protection of page table access, for now. 686129198Scognet */ 687129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 688129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 689129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 690129198Scognet} 691129198Scognet 692129198Scognet/* 693129198Scognet * xscale_setup_minidata: 694129198Scognet * 695129198Scognet * Set up the mini-data cache clean area. We require the 696129198Scognet * caller to allocate the right amount of physically and 697129198Scognet * virtually contiguous space. 698129198Scognet */ 699129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 700129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 701129198Scognetvoid 702129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 703129198Scognet{ 704129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 705129198Scognet pt_entry_t *pte; 706129198Scognet vm_size_t size; 707129198Scognet uint32_t auxctl; 708129198Scognet 709129198Scognet xscale_minidata_clean_addr = va; 710129198Scognet 711129198Scognet /* Round it to page size. */ 712129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 713129198Scognet 714129198Scognet for (; size != 0; 715129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 716129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 717129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 718129198Scognet if (pte == NULL) 719129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 720129198Scognet "VA 0x%08x", (u_int32_t) va); 721129198Scognet pte[l2pte_index(va)] = 722129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 723129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 724129198Scognet } 725129198Scognet 726129198Scognet /* 727129198Scognet * Configure the mini-data cache for write-back with 728129198Scognet * read/write-allocate. 729129198Scognet * 730129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 731129198Scognet * make sure it contains no valid data! In order to do that, 732129198Scognet * we must issue a global data cache invalidate command! 733129198Scognet * 734129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 735129198Scognet * THIS IS VERY IMPORTANT! 736129198Scognet */ 737129198Scognet 738129198Scognet /* Invalidate data and mini-data. */ 739129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 740129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 741129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 742129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 743129198Scognet} 744129198Scognet#endif 745129198Scognet 746129198Scognet/* 747129198Scognet * Allocate an L1 translation table for the specified pmap. 748129198Scognet * This is called at pmap creation time. 749129198Scognet */ 750129198Scognetstatic void 751129198Scognetpmap_alloc_l1(pmap_t pm) 752129198Scognet{ 753129198Scognet struct l1_ttable *l1; 754129198Scognet u_int8_t domain; 755129198Scognet 756129198Scognet /* 757129198Scognet * Remove the L1 at the head of the LRU list 758129198Scognet */ 759129198Scognet mtx_lock(&l1_lru_lock); 760129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 761129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 762129198Scognet 763129198Scognet /* 764129198Scognet * Pick the first available domain number, and update 765129198Scognet * the link to the next number. 766129198Scognet */ 767129198Scognet domain = l1->l1_domain_first; 768129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 769129198Scognet 770129198Scognet /* 771129198Scognet * If there are still free domain numbers in this L1, 772129198Scognet * put it back on the TAIL of the LRU list. 773129198Scognet */ 774129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 775129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 776129198Scognet 777129198Scognet mtx_unlock(&l1_lru_lock); 778129198Scognet 779129198Scognet /* 780129198Scognet * Fix up the relevant bits in the pmap structure 781129198Scognet */ 782129198Scognet pm->pm_l1 = l1; 783174181Scognet pm->pm_domain = domain + 1; 784129198Scognet} 785129198Scognet 786129198Scognet/* 787129198Scognet * Free an L1 translation table. 788129198Scognet * This is called at pmap destruction time. 789129198Scognet */ 790129198Scognetstatic void 791129198Scognetpmap_free_l1(pmap_t pm) 792129198Scognet{ 793129198Scognet struct l1_ttable *l1 = pm->pm_l1; 794129198Scognet 795129198Scognet mtx_lock(&l1_lru_lock); 796129198Scognet 797129198Scognet /* 798129198Scognet * If this L1 is currently on the LRU list, remove it. 799129198Scognet */ 800129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 801129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 802129198Scognet 803129198Scognet /* 804129198Scognet * Free up the domain number which was allocated to the pmap 805129198Scognet */ 806174181Scognet l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 807174181Scognet l1->l1_domain_first = pm->pm_domain - 1; 808129198Scognet l1->l1_domain_use_count--; 809129198Scognet 810129198Scognet /* 811129198Scognet * The L1 now must have at least 1 free domain, so add 812129198Scognet * it back to the LRU list. If the use count is zero, 813129198Scognet * put it at the head of the list, otherwise it goes 814129198Scognet * to the tail. 815129198Scognet */ 816129198Scognet if (l1->l1_domain_use_count == 0) { 817129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 818129198Scognet } else 819129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 820129198Scognet 821129198Scognet mtx_unlock(&l1_lru_lock); 822129198Scognet} 823129198Scognet 824129198Scognet/* 825129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 826129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 827129198Scognet */ 828129198Scognetstatic PMAP_INLINE struct l2_bucket * 829129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 830129198Scognet{ 831129198Scognet struct l2_dtable *l2; 832129198Scognet struct l2_bucket *l2b; 833129198Scognet u_short l1idx; 834129198Scognet 835129198Scognet l1idx = L1_IDX(va); 836129198Scognet 837129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 838129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 839129198Scognet return (NULL); 840129198Scognet 841129198Scognet return (l2b); 842129198Scognet} 843129198Scognet 844129198Scognet/* 845129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 846129198Scognet * and VA. 847129198Scognet * 848129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 849129198Scognet * bucket/page table in place. 850129198Scognet * 851129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 852129198Scognet * increment the bucket occupancy counter appropriately *before* 853129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 854129198Scognet * the bucket/page in the meantime. 855129198Scognet */ 856129198Scognetstatic struct l2_bucket * 857129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 858129198Scognet{ 859129198Scognet struct l2_dtable *l2; 860129198Scognet struct l2_bucket *l2b; 861129198Scognet u_short l1idx; 862129198Scognet 863129198Scognet l1idx = L1_IDX(va); 864129198Scognet 865159352Salc PMAP_ASSERT_LOCKED(pm); 866159108Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 867129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 868129198Scognet /* 869129198Scognet * No mapping at this address, as there is 870129198Scognet * no entry in the L1 table. 871129198Scognet * Need to allocate a new l2_dtable. 872129198Scognet */ 873159108Scognetagain_l2table: 874159352Salc PMAP_UNLOCK(pm); 875159108Scognet vm_page_unlock_queues(); 876129198Scognet if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 877159108Scognet vm_page_lock_queues(); 878159352Salc PMAP_LOCK(pm); 879129198Scognet return (NULL); 880129198Scognet } 881159108Scognet vm_page_lock_queues(); 882159352Salc PMAP_LOCK(pm); 883159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 884159352Salc PMAP_UNLOCK(pm); 885159108Scognet vm_page_unlock_queues(); 886159108Scognet uma_zfree(l2table_zone, l2); 887159108Scognet vm_page_lock_queues(); 888159352Salc PMAP_LOCK(pm); 889159108Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 890159108Scognet if (l2 == NULL) 891159108Scognet goto again_l2table; 892159108Scognet /* 893159108Scognet * Someone already allocated the l2_dtable while 894159108Scognet * we were doing the same. 895159108Scognet */ 896159108Scognet } else { 897159108Scognet bzero(l2, sizeof(*l2)); 898159108Scognet /* 899159108Scognet * Link it into the parent pmap 900159108Scognet */ 901159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 902159108Scognet } 903129198Scognet } 904129198Scognet 905129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 906129198Scognet 907129198Scognet /* 908129198Scognet * Fetch pointer to the L2 page table associated with the address. 909129198Scognet */ 910129198Scognet if (l2b->l2b_kva == NULL) { 911129198Scognet pt_entry_t *ptep; 912129198Scognet 913129198Scognet /* 914129198Scognet * No L2 page table has been allocated. Chances are, this 915129198Scognet * is because we just allocated the l2_dtable, above. 916129198Scognet */ 917159108Scognetagain_ptep: 918159352Salc PMAP_UNLOCK(pm); 919159108Scognet vm_page_unlock_queues(); 920160260Scognet ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE); 921159108Scognet vm_page_lock_queues(); 922159352Salc PMAP_LOCK(pm); 923159108Scognet if (l2b->l2b_kva != 0) { 924159108Scognet /* We lost the race. */ 925159352Salc PMAP_UNLOCK(pm); 926159108Scognet vm_page_unlock_queues(); 927159108Scognet uma_zfree(l2zone, ptep); 928159108Scognet vm_page_lock_queues(); 929159352Salc PMAP_LOCK(pm); 930159108Scognet if (l2b->l2b_kva == 0) 931159108Scognet goto again_ptep; 932159108Scognet return (l2b); 933159108Scognet } 934129198Scognet l2b->l2b_phys = vtophys(ptep); 935129198Scognet if (ptep == NULL) { 936129198Scognet /* 937129198Scognet * Oops, no more L2 page tables available at this 938129198Scognet * time. We may need to deallocate the l2_dtable 939129198Scognet * if we allocated a new one above. 940129198Scognet */ 941129198Scognet if (l2->l2_occupancy == 0) { 942129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 943129198Scognet pmap_free_l2_dtable(l2); 944129198Scognet } 945129198Scognet return (NULL); 946129198Scognet } 947129198Scognet 948129198Scognet l2->l2_occupancy++; 949129198Scognet l2b->l2b_kva = ptep; 950129198Scognet l2b->l2b_l1idx = l1idx; 951129198Scognet } 952129198Scognet 953129198Scognet return (l2b); 954129198Scognet} 955129198Scognet 956129198Scognetstatic PMAP_INLINE void 957129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 958129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 959129198Scognet#else 960129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 961129198Scognet#endif 962129198Scognet{ 963129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 964129198Scognet /* 965129198Scognet * Note: With a write-back cache, we may need to sync this 966129198Scognet * L2 table before re-using it. 967129198Scognet * This is because it may have belonged to a non-current 968129198Scognet * pmap, in which case the cache syncs would have been 969129198Scognet * skipped when the pages were being unmapped. If the 970129198Scognet * L2 table were then to be immediately re-allocated to 971129198Scognet * the *current* pmap, it may well contain stale mappings 972129198Scognet * which have not yet been cleared by a cache write-back 973129198Scognet * and so would still be visible to the mmu. 974129198Scognet */ 975129198Scognet if (need_sync) 976129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 977129198Scognet#endif 978129198Scognet uma_zfree(l2zone, l2); 979129198Scognet} 980129198Scognet/* 981129198Scognet * One or more mappings in the specified L2 descriptor table have just been 982129198Scognet * invalidated. 983129198Scognet * 984129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 985129198Scognet * 986129198Scognet * The pmap lock must be acquired when this is called (not necessary 987129198Scognet * for the kernel pmap). 988129198Scognet */ 989129198Scognetstatic void 990129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 991129198Scognet{ 992129198Scognet struct l2_dtable *l2; 993129198Scognet pd_entry_t *pl1pd, l1pd; 994129198Scognet pt_entry_t *ptep; 995129198Scognet u_short l1idx; 996129198Scognet 997129198Scognet 998129198Scognet /* 999129198Scognet * Update the bucket's reference count according to how many 1000129198Scognet * PTEs the caller has just invalidated. 1001129198Scognet */ 1002129198Scognet l2b->l2b_occupancy -= count; 1003129198Scognet 1004129198Scognet /* 1005129198Scognet * Note: 1006129198Scognet * 1007129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 1008129198Scognet * as that would require checking all Level 1 page tables and 1009129198Scognet * removing any references to the Level 2 page table. See also the 1010129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 1011129198Scognet * 1012129198Scognet * We make do with just invalidating the mapping in the L2 table. 1013129198Scognet * 1014129198Scognet * This isn't really a big deal in practice and, in fact, leads 1015129198Scognet * to a performance win over time as we don't need to continually 1016129198Scognet * alloc/free. 1017129198Scognet */ 1018129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1019129198Scognet return; 1020129198Scognet 1021129198Scognet /* 1022129198Scognet * There are no more valid mappings in this level 2 page table. 1023129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 1024129198Scognet * free the page table. 1025129198Scognet */ 1026129198Scognet l1idx = l2b->l2b_l1idx; 1027129198Scognet ptep = l2b->l2b_kva; 1028129198Scognet l2b->l2b_kva = NULL; 1029129198Scognet 1030129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1031129198Scognet 1032129198Scognet /* 1033129198Scognet * If the L1 slot matches the pmap's domain 1034129198Scognet * number, then invalidate it. 1035129198Scognet */ 1036129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1037129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1038129198Scognet *pl1pd = 0; 1039129198Scognet PTE_SYNC(pl1pd); 1040129198Scognet } 1041129198Scognet 1042129198Scognet /* 1043129198Scognet * Release the L2 descriptor table back to the pool cache. 1044129198Scognet */ 1045129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1046129198Scognet pmap_free_l2_ptp(ptep); 1047129198Scognet#else 1048135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1049129198Scognet#endif 1050129198Scognet 1051129198Scognet /* 1052129198Scognet * Update the reference count in the associated l2_dtable 1053129198Scognet */ 1054129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1055129198Scognet if (--l2->l2_occupancy > 0) 1056129198Scognet return; 1057129198Scognet 1058129198Scognet /* 1059129198Scognet * There are no more valid mappings in any of the Level 1 1060129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 1061129198Scognet * the pointer in the parent pmap and free the l2_dtable. 1062129198Scognet */ 1063129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 1064129198Scognet pmap_free_l2_dtable(l2); 1065129198Scognet} 1066129198Scognet 1067129198Scognet/* 1068129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 1069129198Scognet * structures. 1070129198Scognet */ 1071133237Scognetstatic int 1072133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1073129198Scognet{ 1074129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1075129198Scognet struct l2_bucket *l2b; 1076129198Scognet pt_entry_t *ptep, pte; 1077147417Scognet#ifdef ARM_USE_SMALL_ALLOC 1078147417Scognet pd_entry_t *pde; 1079147417Scognet#endif 1080129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1081129198Scognet 1082129198Scognet /* 1083129198Scognet * The mappings for these page tables were initially made using 1084135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1085129198Scognet * mode will not be right for page table mappings. To avoid 1086135641Scognet * polluting the pmap_kenter() code with a special case for 1087129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1088129198Scognet * correct. 1089129198Scognet */ 1090147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1091147417Scognet pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)]; 1092147417Scognet if (!l1pte_section_p(*pde)) { 1093147114Scognet#endif 1094147114Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1095147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1096147114Scognet pte = *ptep; 1097161105Scognet 1098147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1099147114Scognet /* 1100147114Scognet * Page tables must have the cache-mode set to 1101147114Scognet * Write-Thru. 1102147114Scognet */ 1103147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1104147114Scognet PTE_SYNC(ptep); 1105147114Scognet cpu_tlb_flushD_SE(va); 1106147114Scognet cpu_cpwait(); 1107147114Scognet } 1108147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1109129198Scognet } 1110129198Scognet#endif 1111147114Scognet#endif 1112129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1113129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1114133237Scognet return (0); 1115129198Scognet} 1116129198Scognet 1117129198Scognet/* 1118129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1119129198Scognet * on whether the specified pmap actually needs to be flushed at any 1120129198Scognet * given time. 1121129198Scognet */ 1122129198Scognetstatic PMAP_INLINE void 1123129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1124129198Scognet{ 1125129198Scognet 1126135641Scognet if (pmap_is_current(pm)) 1127129198Scognet cpu_tlb_flushID_SE(va); 1128129198Scognet} 1129129198Scognet 1130129198Scognetstatic PMAP_INLINE void 1131129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1132129198Scognet{ 1133129198Scognet 1134135641Scognet if (pmap_is_current(pm)) 1135129198Scognet cpu_tlb_flushD_SE(va); 1136129198Scognet} 1137129198Scognet 1138129198Scognetstatic PMAP_INLINE void 1139129198Scognetpmap_tlb_flushID(pmap_t pm) 1140129198Scognet{ 1141129198Scognet 1142135641Scognet if (pmap_is_current(pm)) 1143129198Scognet cpu_tlb_flushID(); 1144129198Scognet} 1145129198Scognetstatic PMAP_INLINE void 1146129198Scognetpmap_tlb_flushD(pmap_t pm) 1147129198Scognet{ 1148129198Scognet 1149135641Scognet if (pmap_is_current(pm)) 1150129198Scognet cpu_tlb_flushD(); 1151129198Scognet} 1152129198Scognet 1153203637Srajstatic int 1154203637Srajpmap_has_valid_mapping(pmap_t pm, vm_offset_t va) 1155183838Sraj{ 1156183838Sraj pd_entry_t *pde; 1157183838Sraj pt_entry_t *ptep; 1158183838Sraj 1159203637Sraj if (pmap_get_pde_pte(pm, va, &pde, &ptep) && 1160203637Sraj ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV)) 1161203637Sraj return (1); 1162183838Sraj 1163203637Sraj return (0); 1164183838Sraj} 1165183838Sraj 1166183838Srajstatic PMAP_INLINE void 1167129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1168129198Scognet{ 1169183838Sraj vm_size_t rest; 1170129198Scognet 1171203637Sraj CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x" 1172203637Sraj " len 0x%x ", pm, pm == pmap_kernel(), va, len); 1173183838Sraj 1174203637Sraj if (pmap_is_current(pm) || pm == pmap_kernel()) { 1175203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1176203637Sraj while (len > 0) { 1177203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1178203637Sraj cpu_idcache_wbinv_range(va, rest); 1179203637Sraj cpu_l2cache_wbinv_range(va, rest); 1180203637Sraj } 1181203637Sraj len -= rest; 1182203637Sraj va += rest; 1183203637Sraj rest = MIN(PAGE_SIZE, len); 1184203637Sraj } 1185183838Sraj } 1186183838Sraj} 1187183838Sraj 1188183838Srajstatic PMAP_INLINE void 1189183838Srajpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv, 1190183838Sraj boolean_t rd_only) 1191183838Sraj{ 1192203637Sraj vm_size_t rest; 1193184730Sraj 1194183838Sraj CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x " 1195183838Sraj "len 0x%x ", pm, pm == pmap_kernel(), va, len); 1196183838Sraj CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only); 1197183838Sraj 1198135641Scognet if (pmap_is_current(pm)) { 1199203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1200203637Sraj while (len > 0) { 1201203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1202203637Sraj if (do_inv && rd_only) { 1203203637Sraj cpu_dcache_inv_range(va, rest); 1204203637Sraj cpu_l2cache_inv_range(va, rest); 1205203637Sraj } else if (do_inv) { 1206203637Sraj cpu_dcache_wbinv_range(va, rest); 1207203637Sraj cpu_l2cache_wbinv_range(va, rest); 1208203637Sraj } else if (!rd_only) { 1209203637Sraj cpu_dcache_wb_range(va, rest); 1210203637Sraj cpu_l2cache_wb_range(va, rest); 1211203637Sraj } 1212183838Sraj } 1213203637Sraj len -= rest; 1214203637Sraj va += rest; 1215203637Sraj 1216203637Sraj rest = MIN(PAGE_SIZE, len); 1217183838Sraj } 1218129198Scognet } 1219129198Scognet} 1220129198Scognet 1221129198Scognetstatic PMAP_INLINE void 1222129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1223129198Scognet{ 1224129198Scognet 1225183838Sraj if (pmap_is_current(pm)) { 1226129198Scognet cpu_idcache_wbinv_all(); 1227183838Sraj cpu_l2cache_wbinv_all(); 1228183838Sraj } 1229129198Scognet} 1230129198Scognet 1231197770Sstas#ifdef notyet 1232129198Scognetstatic PMAP_INLINE void 1233129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1234129198Scognet{ 1235129198Scognet 1236183838Sraj if (pmap_is_current(pm)) { 1237129198Scognet cpu_dcache_wbinv_all(); 1238183838Sraj cpu_l2cache_wbinv_all(); 1239183838Sraj } 1240129198Scognet} 1241197770Sstas#endif 1242129198Scognet 1243129198Scognet/* 1244129198Scognet * PTE_SYNC_CURRENT: 1245129198Scognet * 1246129198Scognet * Make sure the pte is written out to RAM. 1247129198Scognet * We need to do this for one of two cases: 1248129198Scognet * - We're dealing with the kernel pmap 1249129198Scognet * - There is no pmap active in the cache/tlb. 1250129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1251129198Scognet */ 1252129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1253129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1254129198Scognetdo { \ 1255129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1256135641Scognet pmap_is_current(pm)) \ 1257129198Scognet PTE_SYNC(ptep); \ 1258129198Scognet} while (/*CONSTCOND*/0) 1259129198Scognet#else 1260129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1261129198Scognet#endif 1262129198Scognet 1263129198Scognet/* 1264175840Scognet * cacheable == -1 means we must make the entry uncacheable, 1 means 1265175840Scognet * cacheable; 1266129198Scognet */ 1267129198Scognetstatic __inline void 1268175840Scognetpmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable) 1269129198Scognet{ 1270175840Scognet struct l2_bucket *l2b; 1271175840Scognet pt_entry_t *ptep, pte; 1272129198Scognet 1273175840Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1274175840Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1275129198Scognet 1276175840Scognet if (cacheable == 1) { 1277175840Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1278175840Scognet if (l2pte_valid(pte)) { 1279175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1280175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1281175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1282175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1283175840Scognet } 1284175840Scognet } 1285175840Scognet } else { 1286175840Scognet pte = *ptep &~ L2_S_CACHE_MASK; 1287175840Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1288175840Scognet l2pte_valid(pte)) { 1289175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1290175840Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1291175840Scognet pv->pv_va, PAGE_SIZE); 1292175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1293175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1294175840Scognet pmap_dcache_wb_range(pv->pv_pmap, 1295175840Scognet pv->pv_va, PAGE_SIZE, TRUE, 1296175840Scognet (pv->pv_flags & PVF_WRITE) == 0); 1297175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1298175840Scognet pv->pv_va); 1299175840Scognet } 1300175840Scognet } 1301129198Scognet } 1302175840Scognet *ptep = pte; 1303175840Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1304129198Scognet} 1305129198Scognet 1306129198Scognetstatic void 1307175840Scognetpmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1308129198Scognet{ 1309175840Scognet int pmwc = 0; 1310175840Scognet int writable = 0, kwritable = 0, uwritable = 0; 1311175840Scognet int entries = 0, kentries = 0, uentries = 0; 1312129198Scognet struct pv_entry *pv; 1313129198Scognet 1314175840Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1315129198Scognet 1316175840Scognet /* the cache gets written back/invalidated on context switch. 1317175840Scognet * therefore, if a user page shares an entry in the same page or 1318175840Scognet * with the kernel map and at least one is writable, then the 1319175840Scognet * cache entry must be set write-through. 1320129198Scognet */ 1321129198Scognet 1322175840Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1323175840Scognet /* generate a count of the pv_entry uses */ 1324175840Scognet if (pv->pv_flags & PVF_WRITE) { 1325175840Scognet if (pv->pv_pmap == pmap_kernel()) 1326175840Scognet kwritable++; 1327175840Scognet else if (pv->pv_pmap == pm) 1328175840Scognet uwritable++; 1329175840Scognet writable++; 1330129198Scognet } 1331175840Scognet if (pv->pv_pmap == pmap_kernel()) 1332175840Scognet kentries++; 1333175840Scognet else { 1334175840Scognet if (pv->pv_pmap == pm) 1335175840Scognet uentries++; 1336175840Scognet entries++; 1337175840Scognet } 1338129198Scognet } 1339175840Scognet /* 1340175840Scognet * check if the user duplicate mapping has 1341175840Scognet * been removed. 1342175840Scognet */ 1343175840Scognet if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) || 1344175840Scognet (uwritable > 1))) 1345175840Scognet pmwc = 1; 1346129198Scognet 1347129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1348175840Scognet /* check for user uncachable conditions - order is important */ 1349175840Scognet if (pm != pmap_kernel() && 1350175840Scognet (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) { 1351129198Scognet 1352175840Scognet if ((uentries > 1 && uwritable) || uwritable > 1) { 1353129198Scognet 1354175840Scognet /* user duplicate mapping */ 1355175840Scognet if (pv->pv_pmap != pmap_kernel()) 1356175840Scognet pv->pv_flags |= PVF_MWC; 1357129198Scognet 1358175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1359175840Scognet pv->pv_flags |= PVF_NC; 1360175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1361175840Scognet } 1362129198Scognet continue; 1363175840Scognet } else /* no longer a duplicate user */ 1364175840Scognet pv->pv_flags &= ~PVF_MWC; 1365175840Scognet } 1366129198Scognet 1367175840Scognet /* 1368175840Scognet * check for kernel uncachable conditions 1369175840Scognet * kernel writable or kernel readable with writable user entry 1370175840Scognet */ 1371175840Scognet if ((kwritable && entries) || 1372194459Sthompsa (kwritable > 1) || 1373175840Scognet ((kwritable != writable) && kentries && 1374175840Scognet (pv->pv_pmap == pmap_kernel() || 1375175840Scognet (pv->pv_flags & PVF_WRITE) || 1376175840Scognet (pv->pv_flags & PVF_MWC)))) { 1377129198Scognet 1378175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1379175840Scognet pv->pv_flags |= PVF_NC; 1380175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1381129198Scognet } 1382175840Scognet continue; 1383129198Scognet } 1384129198Scognet 1385175840Scognet /* kernel and user are cachable */ 1386175840Scognet if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) && 1387175840Scognet (pv->pv_flags & PVF_NC)) { 1388175840Scognet 1389129198Scognet pv->pv_flags &= ~PVF_NC; 1390175840Scognet pmap_set_cache_entry(pv, pm, va, 1); 1391175840Scognet continue; 1392175840Scognet } 1393175840Scognet /* user is no longer sharable and writable */ 1394194459Sthompsa if (pm != pmap_kernel() && 1395194459Sthompsa (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) && 1396175840Scognet !pmwc && (pv->pv_flags & PVF_NC)) { 1397129198Scognet 1398175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1399175840Scognet pmap_set_cache_entry(pv, pm, va, 1); 1400129198Scognet } 1401129198Scognet } 1402175840Scognet 1403175840Scognet if ((kwritable == 0) && (writable == 0)) { 1404175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1405175840Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1406175840Scognet return; 1407175840Scognet } 1408129198Scognet} 1409129198Scognet 1410129198Scognet/* 1411129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1412129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1413129198Scognet * constants and the latter would require an extra inversion at run-time. 1414129198Scognet */ 1415135641Scognetstatic int 1416129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1417129198Scognet{ 1418129198Scognet struct l2_bucket *l2b; 1419129198Scognet struct pv_entry *pv; 1420129198Scognet pt_entry_t *ptep, npte, opte; 1421129198Scognet pmap_t pm; 1422129198Scognet vm_offset_t va; 1423129198Scognet u_int oflags; 1424135641Scognet int count = 0; 1425129198Scognet 1426159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1427159352Salc 1428175840Scognet if (maskbits & PVF_WRITE) 1429175840Scognet maskbits |= PVF_MOD; 1430129198Scognet /* 1431129198Scognet * Clear saved attributes (modify, reference) 1432129198Scognet */ 1433129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1434129198Scognet 1435129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1436135641Scognet return (0); 1437129198Scognet } 1438129198Scognet 1439129198Scognet /* 1440129198Scognet * Loop over all current mappings setting/clearing as appropos 1441129198Scognet */ 1442129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1443129198Scognet va = pv->pv_va; 1444129198Scognet pm = pv->pv_pmap; 1445129198Scognet oflags = pv->pv_flags; 1446175840Scognet 1447175840Scognet if (!(oflags & maskbits)) { 1448175840Scognet if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) { 1449175840Scognet /* It is safe to re-enable cacheing here. */ 1450175840Scognet PMAP_LOCK(pm); 1451175840Scognet l2b = pmap_get_l2_bucket(pm, va); 1452175840Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1453175840Scognet *ptep |= pte_l2_s_cache_mode; 1454175840Scognet PTE_SYNC(ptep); 1455175840Scognet PMAP_UNLOCK(pm); 1456175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1457175840Scognet 1458175840Scognet } 1459175840Scognet continue; 1460175840Scognet } 1461129198Scognet pv->pv_flags &= ~maskbits; 1462129198Scognet 1463159352Salc PMAP_LOCK(pm); 1464129198Scognet 1465129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1466129198Scognet 1467129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1468129198Scognet npte = opte = *ptep; 1469129198Scognet 1470157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1471129198Scognet if ((pv->pv_flags & PVF_NC)) { 1472129198Scognet /* 1473129198Scognet * Entry is not cacheable: 1474129198Scognet * 1475129198Scognet * Don't turn caching on again if this is a 1476129198Scognet * modified emulation. This would be 1477129198Scognet * inconsitent with the settings created by 1478175840Scognet * pmap_fix_cache(). Otherwise, it's safe 1479129198Scognet * to re-enable cacheing. 1480129198Scognet * 1481175840Scognet * There's no need to call pmap_fix_cache() 1482129198Scognet * here: all pages are losing their write 1483129198Scognet * permission. 1484129198Scognet */ 1485129198Scognet if (maskbits & PVF_WRITE) { 1486129198Scognet npte |= pte_l2_s_cache_mode; 1487175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1488129198Scognet } 1489129198Scognet } else 1490129198Scognet if (opte & L2_S_PROT_W) { 1491144760Scognet vm_page_dirty(pg); 1492129198Scognet /* 1493129198Scognet * Entry is writable/cacheable: check if pmap 1494129198Scognet * is current if it is flush it, otherwise it 1495129198Scognet * won't be in the cache 1496129198Scognet */ 1497129198Scognet if (PV_BEEN_EXECD(oflags)) 1498129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1499129198Scognet PAGE_SIZE); 1500129198Scognet else 1501129198Scognet if (PV_BEEN_REFD(oflags)) 1502129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1503129198Scognet PAGE_SIZE, 1504129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1505129198Scognet FALSE); 1506129198Scognet } 1507129198Scognet 1508129198Scognet /* make the pte read only */ 1509129198Scognet npte &= ~L2_S_PROT_W; 1510129198Scognet } 1511129198Scognet 1512157970Scognet if (maskbits & PVF_REF) { 1513129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1514129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1515129198Scognet /* 1516129198Scognet * Check npte here; we may have already 1517129198Scognet * done the wbinv above, and the validity 1518129198Scognet * of the PTE is the same for opte and 1519129198Scognet * npte. 1520129198Scognet */ 1521129198Scognet if (npte & L2_S_PROT_W) { 1522129198Scognet if (PV_BEEN_EXECD(oflags)) 1523129198Scognet pmap_idcache_wbinv_range(pm, 1524129198Scognet pv->pv_va, PAGE_SIZE); 1525129198Scognet else 1526129198Scognet if (PV_BEEN_REFD(oflags)) 1527129198Scognet pmap_dcache_wb_range(pm, 1528129198Scognet pv->pv_va, PAGE_SIZE, 1529129198Scognet TRUE, FALSE); 1530129198Scognet } else 1531129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1532129198Scognet /* XXXJRT need idcache_inv_range */ 1533129198Scognet if (PV_BEEN_EXECD(oflags)) 1534129198Scognet pmap_idcache_wbinv_range(pm, 1535129198Scognet pv->pv_va, PAGE_SIZE); 1536129198Scognet else 1537129198Scognet if (PV_BEEN_REFD(oflags)) 1538129198Scognet pmap_dcache_wb_range(pm, 1539129198Scognet pv->pv_va, PAGE_SIZE, 1540129198Scognet TRUE, TRUE); 1541129198Scognet } 1542129198Scognet } 1543129198Scognet 1544129198Scognet /* 1545129198Scognet * Make the PTE invalid so that we will take a 1546129198Scognet * page fault the next time the mapping is 1547129198Scognet * referenced. 1548129198Scognet */ 1549129198Scognet npte &= ~L2_TYPE_MASK; 1550129198Scognet npte |= L2_TYPE_INV; 1551129198Scognet } 1552129198Scognet 1553129198Scognet if (npte != opte) { 1554135641Scognet count++; 1555129198Scognet *ptep = npte; 1556129198Scognet PTE_SYNC(ptep); 1557129198Scognet /* Flush the TLB entry if a current pmap. */ 1558129198Scognet if (PV_BEEN_EXECD(oflags)) 1559129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1560129198Scognet else 1561129198Scognet if (PV_BEEN_REFD(oflags)) 1562129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1563129198Scognet } 1564129198Scognet 1565159352Salc PMAP_UNLOCK(pm); 1566129198Scognet 1567129198Scognet } 1568129198Scognet 1569137664Scognet if (maskbits & PVF_WRITE) 1570137664Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1571135641Scognet return (count); 1572129198Scognet} 1573129198Scognet 1574129198Scognet/* 1575129198Scognet * main pv_entry manipulation functions: 1576129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1577129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1578129198Scognet * 1579129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1580129198Scognet * pmap_remove_pv expects te caller to lock the pvh before calling 1581129198Scognet */ 1582129198Scognet 1583129198Scognet/* 1584129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page lst 1585129198Scognet * 1586129198Scognet * => caller should hold the proper lock on pmap_main_lock 1587129198Scognet * => caller should have pmap locked 1588129198Scognet * => we will gain the lock on the vm_page and allocate the new pv_entry 1589129198Scognet * => caller should adjust ptp's wire_count before calling 1590129198Scognet * => caller should not adjust pmap's wire_count 1591129198Scognet */ 1592129198Scognetstatic void 1593129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1594129198Scognet vm_offset_t va, u_int flags) 1595129198Scognet{ 1596129198Scognet 1597194459Sthompsa int km; 1598194459Sthompsa 1599159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1600194459Sthompsa 1601194459Sthompsa if (pg->md.pv_kva) { 1602194459Sthompsa /* PMAP_ASSERT_LOCKED(pmap_kernel()); */ 1603194459Sthompsa pve->pv_pmap = pmap_kernel(); 1604194459Sthompsa pve->pv_va = pg->md.pv_kva; 1605194459Sthompsa pve->pv_flags = PVF_WRITE | PVF_UNMAN; 1606194459Sthompsa pg->md.pv_kva = 0; 1607194459Sthompsa 1608205425Scognet if (!(km = PMAP_OWNED(pmap_kernel()))) 1609205425Scognet PMAP_LOCK(pmap_kernel()); 1610194459Sthompsa TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1611205425Scognet TAILQ_INSERT_HEAD(&pve->pv_pmap->pm_pvlist, pve, pv_plist); 1612205425Scognet PMAP_UNLOCK(pmap_kernel()); 1613194459Sthompsa vm_page_unlock_queues(); 1614194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 1615194459Sthompsa panic("pmap_kenter_internal: no pv entries"); 1616194459Sthompsa vm_page_lock_queues(); 1617194459Sthompsa if (km) 1618194459Sthompsa PMAP_LOCK(pmap_kernel()); 1619194459Sthompsa } 1620194459Sthompsa 1621159352Salc PMAP_ASSERT_LOCKED(pm); 1622129198Scognet pve->pv_pmap = pm; 1623129198Scognet pve->pv_va = va; 1624129198Scognet pve->pv_flags = flags; 1625129198Scognet 1626129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1627144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1628129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1629129198Scognet if (pve->pv_flags & PVF_WIRED) 1630129198Scognet ++pm->pm_stats.wired_count; 1631144760Scognet vm_page_flag_set(pg, PG_REFERENCED); 1632129198Scognet} 1633129198Scognet 1634129198Scognet/* 1635129198Scognet * 1636129198Scognet * pmap_find_pv: Find a pv entry 1637129198Scognet * 1638129198Scognet * => caller should hold lock on vm_page 1639129198Scognet */ 1640129198Scognetstatic PMAP_INLINE struct pv_entry * 1641129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1642129198Scognet{ 1643129198Scognet struct pv_entry *pv; 1644129198Scognet 1645159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1646129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1647129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1648129198Scognet break; 1649129198Scognet return (pv); 1650129198Scognet} 1651129198Scognet 1652129198Scognet/* 1653129198Scognet * vector_page_setprot: 1654129198Scognet * 1655129198Scognet * Manipulate the protection of the vector page. 1656129198Scognet */ 1657129198Scognetvoid 1658129198Scognetvector_page_setprot(int prot) 1659129198Scognet{ 1660129198Scognet struct l2_bucket *l2b; 1661129198Scognet pt_entry_t *ptep; 1662129198Scognet 1663129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1664129198Scognet 1665129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1666129198Scognet 1667129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1668129198Scognet PTE_SYNC(ptep); 1669129198Scognet cpu_tlb_flushD_SE(vector_page); 1670129198Scognet cpu_cpwait(); 1671129198Scognet} 1672129198Scognet 1673129198Scognet/* 1674129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1675129198Scognet * 1676129198Scognet * => caller should hold proper lock on pmap_main_lock 1677129198Scognet * => pmap should be locked 1678129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1679129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1680129198Scognet * => caller should NOT adjust pmap's wire_count 1681129198Scognet * => we return the removed pve 1682129198Scognet */ 1683135641Scognet 1684135641Scognetstatic void 1685135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1686135641Scognet{ 1687135641Scognet 1688194459Sthompsa struct pv_entry *pv; 1689159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1690159352Salc PMAP_ASSERT_LOCKED(pm); 1691135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1692144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1693135641Scognet if (pve->pv_flags & PVF_WIRED) 1694135641Scognet --pm->pm_stats.wired_count; 1695144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1696144760Scognet vm_page_dirty(pg); 1697175840Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1698175840Scognet pg->md.pvh_attrs &= ~PVF_REF; 1699175840Scognet else 1700175840Scognet vm_page_flag_set(pg, PG_REFERENCED); 1701175840Scognet if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) || 1702175840Scognet (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC))) 1703175840Scognet pmap_fix_cache(pg, pm, 0); 1704175840Scognet else if (pve->pv_flags & PVF_WRITE) { 1705175840Scognet TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list) 1706175840Scognet if (pve->pv_flags & PVF_WRITE) 1707175840Scognet break; 1708175840Scognet if (!pve) { 1709175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1710175840Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1711175840Scognet } 1712146647Scognet } 1713194459Sthompsa pv = TAILQ_FIRST(&pg->md.pv_list); 1714194459Sthompsa if (pv != NULL && (pv->pv_flags & PVF_UNMAN) && 1715194459Sthompsa TAILQ_NEXT(pv, pv_list) == NULL) { 1716205425Scognet pm = kernel_pmap; 1717194459Sthompsa pg->md.pv_kva = pv->pv_va; 1718194459Sthompsa /* a recursive pmap_nuke_pv */ 1719194459Sthompsa TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list); 1720194459Sthompsa TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist); 1721194459Sthompsa if (pv->pv_flags & PVF_WIRED) 1722194459Sthompsa --pm->pm_stats.wired_count; 1723194459Sthompsa pg->md.pvh_attrs &= ~PVF_REF; 1724194459Sthompsa pg->md.pvh_attrs &= ~PVF_MOD; 1725194459Sthompsa vm_page_flag_clear(pg, PG_WRITEABLE); 1726194459Sthompsa pmap_free_pv_entry(pv); 1727194459Sthompsa } 1728135641Scognet} 1729135641Scognet 1730129198Scognetstatic struct pv_entry * 1731129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1732129198Scognet{ 1733135641Scognet struct pv_entry *pve; 1734129198Scognet 1735159474Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1736135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1737129198Scognet 1738129198Scognet while (pve) { 1739129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1740135641Scognet pmap_nuke_pv(pg, pm, pve); 1741129198Scognet break; 1742129198Scognet } 1743129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1744129198Scognet } 1745129198Scognet 1746194459Sthompsa if (pve == NULL && pg->md.pv_kva == va) 1747194459Sthompsa pg->md.pv_kva = 0; 1748194459Sthompsa 1749129198Scognet return(pve); /* return removed pve */ 1750129198Scognet} 1751129198Scognet/* 1752129198Scognet * 1753129198Scognet * pmap_modify_pv: Update pv flags 1754129198Scognet * 1755129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1756129198Scognet * => caller should NOT adjust pmap's wire_count 1757129198Scognet * => we return the old flags 1758129198Scognet * 1759129198Scognet * Modify a physical-virtual mapping in the pv table 1760129198Scognet */ 1761129198Scognetstatic u_int 1762129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1763129198Scognet u_int clr_mask, u_int set_mask) 1764129198Scognet{ 1765129198Scognet struct pv_entry *npv; 1766129198Scognet u_int flags, oflags; 1767129198Scognet 1768159352Salc PMAP_ASSERT_LOCKED(pm); 1769159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1770129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1771129198Scognet return (0); 1772129198Scognet 1773129198Scognet /* 1774129198Scognet * There is at least one VA mapping this page. 1775129198Scognet */ 1776129198Scognet 1777129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1778129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1779129198Scognet 1780129198Scognet oflags = npv->pv_flags; 1781129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1782129198Scognet 1783129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1784129198Scognet if (flags & PVF_WIRED) 1785129198Scognet ++pm->pm_stats.wired_count; 1786129198Scognet else 1787129198Scognet --pm->pm_stats.wired_count; 1788129198Scognet } 1789129198Scognet 1790175840Scognet if ((flags ^ oflags) & PVF_WRITE) 1791175840Scognet pmap_fix_cache(pg, pm, 0); 1792129198Scognet 1793129198Scognet return (oflags); 1794129198Scognet} 1795129198Scognet 1796129198Scognet/* Function to set the debug level of the pmap code */ 1797129198Scognet#ifdef PMAP_DEBUG 1798129198Scognetvoid 1799129198Scognetpmap_debug(int level) 1800129198Scognet{ 1801129198Scognet pmap_debug_level = level; 1802129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1803129198Scognet} 1804129198Scognet#endif /* PMAP_DEBUG */ 1805129198Scognet 1806129198Scognetvoid 1807129198Scognetpmap_pinit0(struct pmap *pmap) 1808129198Scognet{ 1809129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1810129198Scognet 1811129198Scognet dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1812129198Scognet (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1813135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1814159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1815159325Salc PMAP_LOCK_INIT(pmap); 1816129198Scognet} 1817129198Scognet 1818147217Salc/* 1819147217Salc * Initialize a vm_page's machine-dependent fields. 1820147217Salc */ 1821147217Salcvoid 1822147217Salcpmap_page_init(vm_page_t m) 1823147217Salc{ 1824129198Scognet 1825147217Salc TAILQ_INIT(&m->md.pv_list); 1826147217Salc} 1827147217Salc 1828129198Scognet/* 1829129198Scognet * Initialize the pmap module. 1830129198Scognet * Called by vm_init, to initialize any structures that the pmap 1831129198Scognet * system needs to map virtual memory. 1832129198Scognet */ 1833129198Scognetvoid 1834129198Scognetpmap_init(void) 1835129198Scognet{ 1836152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1837129198Scognet 1838197770Sstas PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR)); 1839147114Scognet 1840129198Scognet /* 1841129198Scognet * init the pv free list 1842129198Scognet */ 1843129198Scognet pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1844129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1845129198Scognet /* 1846129198Scognet * Now it is safe to enable pv_table recording. 1847129198Scognet */ 1848129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1849147114Scognet 1850152128Scognet TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1851152128Scognet 1852170170Sattilio pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1853152128Scognet pv_entry_high_water = 9 * (pv_entry_max / 10); 1854152128Scognet l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1855152128Scognet NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1856152128Scognet l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 1857152128Scognet NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1858152128Scognet UMA_ZONE_VM | UMA_ZONE_NOFREE); 1859152128Scognet 1860152128Scognet uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1861152128Scognet 1862129198Scognet} 1863129198Scognet 1864129198Scognetint 1865129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1866129198Scognet{ 1867129198Scognet struct l2_dtable *l2; 1868129198Scognet struct l2_bucket *l2b; 1869129198Scognet pd_entry_t *pl1pd, l1pd; 1870129198Scognet pt_entry_t *ptep, pte; 1871129198Scognet vm_paddr_t pa; 1872129198Scognet u_int l1idx; 1873129198Scognet int rv = 0; 1874129198Scognet 1875129198Scognet l1idx = L1_IDX(va); 1876159384Salc vm_page_lock_queues(); 1877159384Salc PMAP_LOCK(pm); 1878129198Scognet 1879129198Scognet /* 1880129198Scognet * If there is no l2_dtable for this address, then the process 1881129198Scognet * has no business accessing it. 1882129198Scognet * 1883129198Scognet * Note: This will catch userland processes trying to access 1884129198Scognet * kernel addresses. 1885129198Scognet */ 1886129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1887129198Scognet if (l2 == NULL) 1888129198Scognet goto out; 1889129198Scognet 1890129198Scognet /* 1891129198Scognet * Likewise if there is no L2 descriptor table 1892129198Scognet */ 1893129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1894129198Scognet if (l2b->l2b_kva == NULL) 1895129198Scognet goto out; 1896129198Scognet 1897129198Scognet /* 1898129198Scognet * Check the PTE itself. 1899129198Scognet */ 1900129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1901129198Scognet pte = *ptep; 1902129198Scognet if (pte == 0) 1903129198Scognet goto out; 1904129198Scognet 1905129198Scognet /* 1906129198Scognet * Catch a userland access to the vector page mapped at 0x0 1907129198Scognet */ 1908129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 1909129198Scognet goto out; 1910157027Scognet if (va == vector_page) 1911157027Scognet goto out; 1912129198Scognet 1913129198Scognet pa = l2pte_pa(pte); 1914129198Scognet 1915129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 1916129198Scognet /* 1917129198Scognet * This looks like a good candidate for "page modified" 1918129198Scognet * emulation... 1919129198Scognet */ 1920129198Scognet struct pv_entry *pv; 1921129198Scognet struct vm_page *pg; 1922129198Scognet 1923129198Scognet /* Extract the physical address of the page */ 1924129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 1925129198Scognet goto out; 1926129198Scognet } 1927129198Scognet /* Get the current flags for this page. */ 1928129198Scognet 1929129198Scognet pv = pmap_find_pv(pg, pm, va); 1930129198Scognet if (pv == NULL) { 1931129198Scognet goto out; 1932129198Scognet } 1933129198Scognet 1934129198Scognet /* 1935129198Scognet * Do the flags say this page is writable? If not then it 1936129198Scognet * is a genuine write fault. If yes then the write fault is 1937129198Scognet * our fault as we did not reflect the write access in the 1938129198Scognet * PTE. Now we know a write has occurred we can correct this 1939129198Scognet * and also set the modified bit 1940129198Scognet */ 1941129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 1942129198Scognet goto out; 1943129198Scognet } 1944129198Scognet 1945157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 1946157970Scognet vm_page_dirty(pg); 1947129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 1948129198Scognet 1949129198Scognet /* 1950129198Scognet * Re-enable write permissions for the page. No need to call 1951175840Scognet * pmap_fix_cache(), since this is just a 1952129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 1953129198Scognet * changing. We've already set the cacheable bits based on 1954129198Scognet * the assumption that we can write to this page. 1955129198Scognet */ 1956147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 1957129198Scognet PTE_SYNC(ptep); 1958129198Scognet rv = 1; 1959129198Scognet } else 1960129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 1961129198Scognet /* 1962129198Scognet * This looks like a good candidate for "page referenced" 1963129198Scognet * emulation. 1964129198Scognet */ 1965129198Scognet struct pv_entry *pv; 1966129198Scognet struct vm_page *pg; 1967129198Scognet 1968129198Scognet /* Extract the physical address of the page */ 1969159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 1970129198Scognet goto out; 1971129198Scognet /* Get the current flags for this page. */ 1972129198Scognet 1973129198Scognet pv = pmap_find_pv(pg, pm, va); 1974159384Salc if (pv == NULL) 1975129198Scognet goto out; 1976129198Scognet 1977129198Scognet pg->md.pvh_attrs |= PVF_REF; 1978129198Scognet pv->pv_flags |= PVF_REF; 1979129198Scognet 1980129198Scognet 1981129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 1982129198Scognet PTE_SYNC(ptep); 1983129198Scognet rv = 1; 1984129198Scognet } 1985129198Scognet 1986129198Scognet /* 1987129198Scognet * We know there is a valid mapping here, so simply 1988129198Scognet * fix up the L1 if necessary. 1989129198Scognet */ 1990129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1991129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 1992129198Scognet if (*pl1pd != l1pd) { 1993129198Scognet *pl1pd = l1pd; 1994129198Scognet PTE_SYNC(pl1pd); 1995129198Scognet rv = 1; 1996129198Scognet } 1997129198Scognet 1998129198Scognet#ifdef CPU_SA110 1999129198Scognet /* 2000129198Scognet * There are bugs in the rev K SA110. This is a check for one 2001129198Scognet * of them. 2002129198Scognet */ 2003129198Scognet if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2004129198Scognet curcpu()->ci_arm_cpurev < 3) { 2005129198Scognet /* Always current pmap */ 2006129198Scognet if (l2pte_valid(pte)) { 2007129198Scognet extern int kernel_debug; 2008129198Scognet if (kernel_debug & 1) { 2009129198Scognet struct proc *p = curlwp->l_proc; 2010129198Scognet printf("prefetch_abort: page is already " 2011129198Scognet "mapped - pte=%p *pte=%08x\n", ptep, pte); 2012129198Scognet printf("prefetch_abort: pc=%08lx proc=%p " 2013129198Scognet "process=%s\n", va, p, p->p_comm); 2014129198Scognet printf("prefetch_abort: far=%08x fs=%x\n", 2015129198Scognet cpu_faultaddress(), cpu_faultstatus()); 2016129198Scognet } 2017129198Scognet#ifdef DDB 2018129198Scognet if (kernel_debug & 2) 2019129198Scognet Debugger(); 2020129198Scognet#endif 2021129198Scognet rv = 1; 2022129198Scognet } 2023129198Scognet } 2024129198Scognet#endif /* CPU_SA110 */ 2025129198Scognet 2026129198Scognet#ifdef DEBUG 2027129198Scognet /* 2028129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 2029129198Scognet * stale TLB entry for the faulting address. This happens when two or 2030129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 2031129198Scognet * a context switch between such processes, we can take domain faults 2032129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 2033129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2034129198Scognet * example. 2035129198Scognet * 2036129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 2037129198Scognet * entry for a recently entered mapping. In this case, the TLB is 2038129198Scognet * flushed for the new mapping, but there may still be TLB entries for 2039129198Scognet * other mappings belonging to other processes in the 1MB range 2040129198Scognet * covered by the L1 entry. 2041129198Scognet * 2042129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 2043129198Scognet * value, so the fault must be due to a stale TLB entry. 2044129198Scognet * 2045129198Scognet * Since we always need to flush the TLB anyway in the case where we 2046129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2047129198Scognet * stale TLB entries dynamically. 2048129198Scognet * 2049129198Scognet * However, the above condition can ONLY happen if the current L1 is 2050129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 2051129198Scognet * that other parts of the pmap are not doing their job WRT managing 2052129198Scognet * the TLB. 2053129198Scognet */ 2054129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2055129198Scognet extern int last_fault_code; 2056129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2057129198Scognet pm, va, ftype); 2058129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2059129198Scognet l2, l2b, ptep, pl1pd); 2060129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2061129198Scognet pte, l1pd, last_fault_code); 2062129198Scognet#ifdef DDB 2063129198Scognet Debugger(); 2064129198Scognet#endif 2065129198Scognet } 2066129198Scognet#endif 2067129198Scognet 2068129198Scognet cpu_tlb_flushID_SE(va); 2069129198Scognet cpu_cpwait(); 2070129198Scognet 2071129198Scognet rv = 1; 2072129198Scognet 2073129198Scognetout: 2074159384Salc vm_page_unlock_queues(); 2075159384Salc PMAP_UNLOCK(pm); 2076129198Scognet return (rv); 2077129198Scognet} 2078129198Scognet 2079129198Scognetvoid 2080152128Scognetpmap_postinit(void) 2081152128Scognet{ 2082129198Scognet struct l2_bucket *l2b; 2083129198Scognet struct l1_ttable *l1; 2084129198Scognet pd_entry_t *pl1pt; 2085129198Scognet pt_entry_t *ptep, pte; 2086129198Scognet vm_offset_t va, eva; 2087129198Scognet u_int loop, needed; 2088129198Scognet 2089129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2090129198Scognet needed -= 1; 2091129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2092129198Scognet 2093129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 2094129198Scognet /* Allocate a L1 page table */ 2095132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2096132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 2097129198Scognet 2098129198Scognet if (va == 0) 2099129198Scognet panic("Cannot allocate L1 KVM"); 2100129198Scognet 2101129198Scognet eva = va + L1_TABLE_SIZE; 2102129198Scognet pl1pt = (pd_entry_t *)va; 2103129198Scognet 2104135641Scognet while (va < eva) { 2105129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2106129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2107129198Scognet pte = *ptep; 2108129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2109129198Scognet *ptep = pte; 2110129198Scognet PTE_SYNC(ptep); 2111129198Scognet cpu_tlb_flushD_SE(va); 2112129198Scognet 2113129198Scognet va += PAGE_SIZE; 2114129198Scognet } 2115129198Scognet pmap_init_l1(l1, pl1pt); 2116129198Scognet } 2117129198Scognet 2118129198Scognet 2119129198Scognet#ifdef DEBUG 2120129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2121129198Scognet needed); 2122129198Scognet#endif 2123129198Scognet} 2124129198Scognet 2125129198Scognet/* 2126129198Scognet * This is used to stuff certain critical values into the PCB where they 2127129198Scognet * can be accessed quickly from cpu_switch() et al. 2128129198Scognet */ 2129129198Scognetvoid 2130129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2131129198Scognet{ 2132129198Scognet struct l2_bucket *l2b; 2133129198Scognet 2134129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2135129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2136129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2137129198Scognet 2138129198Scognet if (vector_page < KERNBASE) { 2139129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2140129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2141129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2142145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2143129198Scognet } else 2144129198Scognet pcb->pcb_pl1vec = NULL; 2145129198Scognet} 2146129198Scognet 2147129198Scognetvoid 2148129198Scognetpmap_activate(struct thread *td) 2149129198Scognet{ 2150129198Scognet pmap_t pm; 2151129198Scognet struct pcb *pcb; 2152129198Scognet 2153135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2154129198Scognet pcb = td->td_pcb; 2155129198Scognet 2156129198Scognet critical_enter(); 2157129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2158129198Scognet 2159129198Scognet if (td == curthread) { 2160129198Scognet u_int cur_dacr, cur_ttb; 2161129198Scognet 2162129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2163129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2164129198Scognet 2165129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2166129198Scognet 2167129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2168129198Scognet cur_dacr == pcb->pcb_dacr) { 2169129198Scognet /* 2170129198Scognet * No need to switch address spaces. 2171129198Scognet */ 2172129198Scognet critical_exit(); 2173129198Scognet return; 2174129198Scognet } 2175129198Scognet 2176129198Scognet 2177129198Scognet /* 2178129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2179129198Scognet * to 'vector_page' in the incoming L1 table before switching 2180129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2181129198Scognet * domain faults!) will jump into hyperspace. 2182129198Scognet */ 2183129198Scognet if (pcb->pcb_pl1vec) { 2184129198Scognet 2185129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2186129198Scognet /* 2187129198Scognet * Don't need to PTE_SYNC() at this point since 2188129198Scognet * cpu_setttb() is about to flush both the cache 2189129198Scognet * and the TLB. 2190129198Scognet */ 2191129198Scognet } 2192129198Scognet 2193129198Scognet cpu_domains(pcb->pcb_dacr); 2194129198Scognet cpu_setttb(pcb->pcb_pagedir); 2195129198Scognet } 2196129198Scognet critical_exit(); 2197129198Scognet} 2198129198Scognet 2199129198Scognetstatic int 2200129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2201129198Scognet{ 2202129198Scognet pd_entry_t *pdep, pde; 2203129198Scognet pt_entry_t *ptep, pte; 2204129198Scognet vm_offset_t pa; 2205129198Scognet int rv = 0; 2206129198Scognet 2207129198Scognet /* 2208129198Scognet * Make sure the descriptor itself has the correct cache mode 2209129198Scognet */ 2210129198Scognet pdep = &kl1[L1_IDX(va)]; 2211129198Scognet pde = *pdep; 2212129198Scognet 2213129198Scognet if (l1pte_section_p(pde)) { 2214129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2215129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2216129198Scognet pte_l1_s_cache_mode_pt; 2217129198Scognet PTE_SYNC(pdep); 2218129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2219129198Scognet sizeof(*pdep)); 2220183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)pdep, 2221183838Sraj sizeof(*pdep)); 2222129198Scognet rv = 1; 2223129198Scognet } 2224129198Scognet } else { 2225129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2226129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2227129198Scognet if (ptep == NULL) 2228129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2229129198Scognet 2230129198Scognet ptep = &ptep[l2pte_index(va)]; 2231129198Scognet pte = *ptep; 2232129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2233129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2234129198Scognet pte_l2_s_cache_mode_pt; 2235129198Scognet PTE_SYNC(ptep); 2236129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2237129198Scognet sizeof(*ptep)); 2238183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)ptep, 2239183838Sraj sizeof(*ptep)); 2240129198Scognet rv = 1; 2241129198Scognet } 2242129198Scognet } 2243129198Scognet 2244129198Scognet return (rv); 2245129198Scognet} 2246129198Scognet 2247129198Scognetstatic void 2248129198Scognetpmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2249129198Scognet pt_entry_t **ptep) 2250129198Scognet{ 2251129198Scognet vm_offset_t va = *availp; 2252129198Scognet struct l2_bucket *l2b; 2253129198Scognet 2254129198Scognet if (ptep) { 2255129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2256129198Scognet if (l2b == NULL) 2257129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2258129198Scognet 2259129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2260129198Scognet } 2261129198Scognet 2262129198Scognet *vap = va; 2263129198Scognet *availp = va + (PAGE_SIZE * pages); 2264129198Scognet} 2265129198Scognet 2266129198Scognet/* 2267129198Scognet * Bootstrap the system enough to run with virtual memory. 2268129198Scognet * 2269129198Scognet * On the arm this is called after mapping has already been enabled 2270129198Scognet * and just syncs the pmap module with what has already been done. 2271129198Scognet * [We can't call it easily with mapping off since the kernel is not 2272129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2273129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2274129198Scognet * (physical) address starting relative to 0] 2275129198Scognet */ 2276129198Scognet#define PMAP_STATIC_L2_SIZE 16 2277147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2278147114Scognetextern struct mtx smallalloc_mtx; 2279147114Scognet#endif 2280147114Scognet 2281129198Scognetvoid 2282129198Scognetpmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2283129198Scognet{ 2284129198Scognet static struct l1_ttable static_l1; 2285129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2286129198Scognet struct l1_ttable *l1 = &static_l1; 2287129198Scognet struct l2_dtable *l2; 2288129198Scognet struct l2_bucket *l2b; 2289129198Scognet pd_entry_t pde; 2290129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2291129198Scognet pt_entry_t *ptep; 2292129198Scognet vm_paddr_t pa; 2293129198Scognet vm_offset_t va; 2294135641Scognet vm_size_t size; 2295129198Scognet int l1idx, l2idx, l2next = 0; 2296129198Scognet 2297197770Sstas PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", 2298197770Sstas firstaddr, lastaddr)); 2299129198Scognet 2300129198Scognet virtual_avail = firstaddr; 2301129198Scognet kernel_pmap->pm_l1 = l1; 2302150865Scognet kernel_l1pa = l1pt->pv_pa; 2303143192Scognet 2304143192Scognet /* 2305129198Scognet * Scan the L1 translation table created by initarm() and create 2306129198Scognet * the required metadata for all valid mappings found in it. 2307129198Scognet */ 2308129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2309129198Scognet pde = kernel_l1pt[l1idx]; 2310129198Scognet 2311129198Scognet /* 2312129198Scognet * We're only interested in Coarse mappings. 2313129198Scognet * pmap_extract() can deal with section mappings without 2314129198Scognet * recourse to checking L2 metadata. 2315129198Scognet */ 2316129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2317129198Scognet continue; 2318129198Scognet 2319129198Scognet /* 2320129198Scognet * Lookup the KVA of this L2 descriptor table 2321129198Scognet */ 2322129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2323129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2324129198Scognet 2325129198Scognet if (ptep == NULL) { 2326129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2327129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2328129198Scognet } 2329129198Scognet 2330129198Scognet /* 2331129198Scognet * Fetch the associated L2 metadata structure. 2332129198Scognet * Allocate a new one if necessary. 2333129198Scognet */ 2334129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2335129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2336129198Scognet panic("pmap_bootstrap: out of static L2s"); 2337129198Scognet kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2338129198Scognet &static_l2[l2next++]; 2339129198Scognet } 2340129198Scognet 2341129198Scognet /* 2342129198Scognet * One more L1 slot tracked... 2343129198Scognet */ 2344129198Scognet l2->l2_occupancy++; 2345129198Scognet 2346129198Scognet /* 2347129198Scognet * Fill in the details of the L2 descriptor in the 2348129198Scognet * appropriate bucket. 2349129198Scognet */ 2350129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2351129198Scognet l2b->l2b_kva = ptep; 2352129198Scognet l2b->l2b_phys = pa; 2353129198Scognet l2b->l2b_l1idx = l1idx; 2354129198Scognet 2355129198Scognet /* 2356129198Scognet * Establish an initial occupancy count for this descriptor 2357129198Scognet */ 2358129198Scognet for (l2idx = 0; 2359129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2360129198Scognet l2idx++) { 2361129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2362129198Scognet l2b->l2b_occupancy++; 2363129198Scognet } 2364129198Scognet } 2365129198Scognet 2366129198Scognet /* 2367129198Scognet * Make sure the descriptor itself has the correct cache mode. 2368129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2369129198Scognet * should consider this a clue to fix up their initarm() 2370129198Scognet * function. :) 2371129198Scognet */ 2372129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2373129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2374129198Scognet "L2 pte @ %p\n", ptep); 2375129198Scognet } 2376129198Scognet } 2377129198Scognet 2378129198Scognet 2379129198Scognet /* 2380129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2381129198Scognet * a page table. Bitch if it is not correctly set. 2382129198Scognet */ 2383129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2384129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2385129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2386129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2387129198Scognet "primary L1 @ 0x%x\n", va); 2388129198Scognet } 2389129198Scognet 2390129198Scognet cpu_dcache_wbinv_all(); 2391183838Sraj cpu_l2cache_wbinv_all(); 2392129198Scognet cpu_tlb_flushID(); 2393129198Scognet cpu_cpwait(); 2394129198Scognet 2395159325Salc PMAP_LOCK_INIT(kernel_pmap); 2396129198Scognet kernel_pmap->pm_active = -1; 2397129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2398144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2399129198Scognet 2400129198Scognet /* 2401129198Scognet * Reserve some special page table entries/VA space for temporary 2402129198Scognet * mapping of pages. 2403129198Scognet */ 2404129198Scognet#define SYSMAP(c, p, v, n) \ 2405129198Scognet v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2406129198Scognet 2407129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2408129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2409129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2410129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2411135641Scognet size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2412135641Scognet pmap_alloc_specials(&virtual_avail, 2413135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2414135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2415135641Scognet 2416135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2417135641Scognet pmap_alloc_specials(&virtual_avail, 2418135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2419135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2420135641Scognet 2421137362Scognet pmap_alloc_specials(&virtual_avail, 2422137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2423184728Sraj pmap_alloc_specials(&virtual_avail, 2424184728Sraj MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL); 2425135641Scognet SLIST_INIT(&l1_list); 2426129198Scognet TAILQ_INIT(&l1_lru_list); 2427129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2428129198Scognet pmap_init_l1(l1, kernel_l1pt); 2429129198Scognet cpu_dcache_wbinv_all(); 2430183838Sraj cpu_l2cache_wbinv_all(); 2431129198Scognet 2432129198Scognet virtual_avail = round_page(virtual_avail); 2433129198Scognet virtual_end = lastaddr; 2434135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2435156191Scognet arm_nocache_startaddr = lastaddr; 2436159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2437156191Scognet 2438147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2439147114Scognet mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF); 2440161105Scognet arm_init_smallalloc(); 2441147114Scognet#endif 2442161105Scognet pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 2443129198Scognet} 2444129198Scognet 2445129198Scognet/*************************************************** 2446129198Scognet * Pmap allocation/deallocation routines. 2447129198Scognet ***************************************************/ 2448129198Scognet 2449129198Scognet/* 2450129198Scognet * Release any resources held by the given physical map. 2451129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2452129198Scognet * Should only be called if the map contains no valid mappings. 2453129198Scognet */ 2454129198Scognetvoid 2455129198Scognetpmap_release(pmap_t pmap) 2456129198Scognet{ 2457135641Scognet struct pcb *pcb; 2458135641Scognet 2459135641Scognet pmap_idcache_wbinv_all(pmap); 2460183838Sraj cpu_l2cache_wbinv_all(); 2461135641Scognet pmap_tlb_flushID(pmap); 2462135641Scognet cpu_cpwait(); 2463135641Scognet if (vector_page < KERNBASE) { 2464135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2465135641Scognet pcb = thread0.td_pcb; 2466135641Scognet if (pmap_is_current(pmap)) { 2467135641Scognet /* 2468135641Scognet * Frob the L1 entry corresponding to the vector 2469135641Scognet * page so that it contains the kernel pmap's domain 2470135641Scognet * number. This will ensure pmap_remove() does not 2471135641Scognet * pull the current vector page out from under us. 2472135641Scognet */ 2473135641Scognet critical_enter(); 2474135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2475135641Scognet cpu_domains(pcb->pcb_dacr); 2476135641Scognet cpu_setttb(pcb->pcb_pagedir); 2477135641Scognet critical_exit(); 2478135641Scognet } 2479135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2480135641Scognet /* 2481135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2482135641Scognet * since this process has no remaining mappings of its own. 2483135641Scognet */ 2484135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2485135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2486135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2487135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2488135641Scognet 2489135641Scognet } 2490129198Scognet pmap_free_l1(pmap); 2491159325Salc PMAP_LOCK_DESTROY(pmap); 2492135641Scognet 2493129198Scognet dprintf("pmap_release()\n"); 2494129198Scognet} 2495129198Scognet 2496129198Scognet 2497135641Scognet 2498129198Scognet/* 2499135641Scognet * Helper function for pmap_grow_l2_bucket() 2500135641Scognet */ 2501135641Scognetstatic __inline int 2502135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2503135641Scognet{ 2504135641Scognet struct l2_bucket *l2b; 2505135641Scognet pt_entry_t *ptep; 2506135641Scognet vm_paddr_t pa; 2507135641Scognet struct vm_page *pg; 2508135641Scognet 2509150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2510135641Scognet if (pg == NULL) 2511135641Scognet return (1); 2512135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2513135641Scognet 2514135641Scognet if (pap) 2515135641Scognet *pap = pa; 2516135641Scognet 2517135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2518135641Scognet 2519135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2520135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2521135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2522135641Scognet PTE_SYNC(ptep); 2523135641Scognet return (0); 2524135641Scognet} 2525135641Scognet 2526135641Scognet/* 2527135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2528135641Scognet * used by pmap_growkernel(). 2529135641Scognet */ 2530135641Scognetstatic __inline struct l2_bucket * 2531135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2532135641Scognet{ 2533135641Scognet struct l2_dtable *l2; 2534135641Scognet struct l2_bucket *l2b; 2535135641Scognet struct l1_ttable *l1; 2536135641Scognet pd_entry_t *pl1pd; 2537135641Scognet u_short l1idx; 2538135641Scognet vm_offset_t nva; 2539135641Scognet 2540135641Scognet l1idx = L1_IDX(va); 2541135641Scognet 2542135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2543135641Scognet /* 2544135641Scognet * No mapping at this address, as there is 2545135641Scognet * no entry in the L1 table. 2546135641Scognet * Need to allocate a new l2_dtable. 2547135641Scognet */ 2548135641Scognet nva = pmap_kernel_l2dtable_kva; 2549135641Scognet if ((nva & PAGE_MASK) == 0) { 2550135641Scognet /* 2551135641Scognet * Need to allocate a backing page 2552135641Scognet */ 2553135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2554135641Scognet return (NULL); 2555135641Scognet } 2556135641Scognet 2557135641Scognet l2 = (struct l2_dtable *)nva; 2558135641Scognet nva += sizeof(struct l2_dtable); 2559135641Scognet 2560135641Scognet if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2561135641Scognet PAGE_MASK)) { 2562135641Scognet /* 2563135641Scognet * The new l2_dtable straddles a page boundary. 2564135641Scognet * Map in another page to cover it. 2565135641Scognet */ 2566135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2567135641Scognet return (NULL); 2568135641Scognet } 2569135641Scognet 2570135641Scognet pmap_kernel_l2dtable_kva = nva; 2571135641Scognet 2572135641Scognet /* 2573135641Scognet * Link it into the parent pmap 2574135641Scognet */ 2575135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2576150865Scognet memset(l2, 0, sizeof(*l2)); 2577135641Scognet } 2578135641Scognet 2579135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2580135641Scognet 2581135641Scognet /* 2582135641Scognet * Fetch pointer to the L2 page table associated with the address. 2583135641Scognet */ 2584135641Scognet if (l2b->l2b_kva == NULL) { 2585135641Scognet pt_entry_t *ptep; 2586135641Scognet 2587135641Scognet /* 2588135641Scognet * No L2 page table has been allocated. Chances are, this 2589135641Scognet * is because we just allocated the l2_dtable, above. 2590135641Scognet */ 2591135641Scognet nva = pmap_kernel_l2ptp_kva; 2592135641Scognet ptep = (pt_entry_t *)nva; 2593135641Scognet if ((nva & PAGE_MASK) == 0) { 2594135641Scognet /* 2595135641Scognet * Need to allocate a backing page 2596135641Scognet */ 2597135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2598135641Scognet &pmap_kernel_l2ptp_phys)) 2599135641Scognet return (NULL); 2600135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2601135641Scognet } 2602150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2603135641Scognet l2->l2_occupancy++; 2604135641Scognet l2b->l2b_kva = ptep; 2605135641Scognet l2b->l2b_l1idx = l1idx; 2606135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2607135641Scognet 2608135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2609135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2610135641Scognet } 2611135641Scognet 2612135641Scognet /* Distribute new L1 entry to all other L1s */ 2613135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2614145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2615135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2616135641Scognet L1_C_PROTO; 2617135641Scognet PTE_SYNC(pl1pd); 2618135641Scognet } 2619135641Scognet 2620135641Scognet return (l2b); 2621135641Scognet} 2622135641Scognet 2623135641Scognet 2624135641Scognet/* 2625129198Scognet * grow the number of kernel page table entries, if needed 2626129198Scognet */ 2627129198Scognetvoid 2628129198Scognetpmap_growkernel(vm_offset_t addr) 2629129198Scognet{ 2630135641Scognet pmap_t kpm = pmap_kernel(); 2631129198Scognet 2632135641Scognet if (addr <= pmap_curmaxkvaddr) 2633135641Scognet return; /* we are OK */ 2634135641Scognet 2635135641Scognet /* 2636135641Scognet * whoops! we need to add kernel PTPs 2637135641Scognet */ 2638135641Scognet 2639135641Scognet /* Map 1MB at a time */ 2640135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2641135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2642135641Scognet 2643135641Scognet /* 2644135641Scognet * flush out the cache, expensive but growkernel will happen so 2645135641Scognet * rarely 2646135641Scognet */ 2647135641Scognet cpu_dcache_wbinv_all(); 2648183838Sraj cpu_l2cache_wbinv_all(); 2649135641Scognet cpu_tlb_flushD(); 2650135641Scognet cpu_cpwait(); 2651135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2652129198Scognet} 2653129198Scognet 2654129198Scognet 2655129198Scognet/* 2656129198Scognet * Remove all pages from specified address space 2657129198Scognet * this aids process exit speeds. Also, this code 2658129198Scognet * is special cased for current process only, but 2659129198Scognet * can have the more generic (and slightly slower) 2660129198Scognet * mode enabled. This is much faster than pmap_remove 2661129198Scognet * in the case of running down an entire address space. 2662129198Scognet */ 2663129198Scognetvoid 2664157443Speterpmap_remove_pages(pmap_t pmap) 2665129198Scognet{ 2666144760Scognet struct pv_entry *pv, *npv; 2667144760Scognet struct l2_bucket *l2b = NULL; 2668144760Scognet vm_page_t m; 2669144760Scognet pt_entry_t *pt; 2670144760Scognet 2671144760Scognet vm_page_lock_queues(); 2672159352Salc PMAP_LOCK(pmap); 2673175840Scognet cpu_idcache_wbinv_all(); 2674183838Sraj cpu_l2cache_wbinv_all(); 2675144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2676194459Sthompsa if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) { 2677194459Sthompsa /* Cannot remove wired or unmanaged pages now. */ 2678144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2679144760Scognet continue; 2680144760Scognet } 2681144760Scognet pmap->pm_stats.resident_count--; 2682144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2683144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2684144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2685144760Scognet m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2686164079Scognet#ifdef ARM_USE_SMALL_ALLOC 2687164079Scognet KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2688164079Scognet#else 2689164079Scognet KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2690164079Scognet#endif 2691144760Scognet *pt = 0; 2692144760Scognet PTE_SYNC(pt); 2693144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2694144760Scognet pmap_nuke_pv(m, pmap, pv); 2695150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2696150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 2697144760Scognet pmap_free_pv_entry(pv); 2698164874Scognet pmap_free_l2_bucket(pmap, l2b, 1); 2699144760Scognet } 2700144760Scognet vm_page_unlock_queues(); 2701135641Scognet cpu_tlb_flushID(); 2702135641Scognet cpu_cpwait(); 2703159352Salc PMAP_UNLOCK(pmap); 2704129198Scognet} 2705129198Scognet 2706129198Scognet 2707129198Scognet/*************************************************** 2708129198Scognet * Low level mapping routines..... 2709129198Scognet ***************************************************/ 2710129198Scognet 2711171620Scognet#ifdef ARM_HAVE_SUPERSECTIONS 2712170582Scognet/* Map a super section into the KVA. */ 2713170582Scognet 2714170582Scognetvoid 2715170582Scognetpmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags) 2716170582Scognet{ 2717171620Scognet pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) | 2718171620Scognet (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL, 2719170582Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2720170582Scognet struct l1_ttable *l1; 2721171620Scognet vm_offset_t va0, va_end; 2722170582Scognet 2723170582Scognet KASSERT(((va | pa) & L1_SUP_OFFSET) == 0, 2724171620Scognet ("Not a valid super section mapping")); 2725170582Scognet if (flags & SECTION_CACHE) 2726170582Scognet pd |= pte_l1_s_cache_mode; 2727170582Scognet else if (flags & SECTION_PT) 2728170582Scognet pd |= pte_l1_s_cache_mode_pt; 2729171620Scognet va0 = va & L1_SUP_FRAME; 2730170582Scognet va_end = va + L1_SUP_SIZE; 2731170582Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2732171620Scognet va = va0; 2733170582Scognet for (; va < va_end; va += L1_S_SIZE) { 2734170582Scognet l1->l1_kva[L1_IDX(va)] = pd; 2735170582Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2736170582Scognet } 2737170582Scognet } 2738170582Scognet} 2739171620Scognet#endif 2740170582Scognet 2741147114Scognet/* Map a section into the KVA. */ 2742147114Scognet 2743147114Scognetvoid 2744147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2745147114Scognet{ 2746147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2747147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2748147114Scognet struct l1_ttable *l1; 2749147114Scognet 2750147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2751147114Scognet ("Not a valid section mapping")); 2752147114Scognet if (flags & SECTION_CACHE) 2753147114Scognet pd |= pte_l1_s_cache_mode; 2754147114Scognet else if (flags & SECTION_PT) 2755147114Scognet pd |= pte_l1_s_cache_mode_pt; 2756147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2757147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2758147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2759147114Scognet } 2760147114Scognet} 2761147114Scognet 2762129198Scognet/* 2763184728Sraj * Make a temporary mapping for a physical address. This is only intended 2764184728Sraj * to be used for panic dumps. 2765184728Sraj */ 2766184728Srajvoid * 2767184728Srajpmap_kenter_temp(vm_paddr_t pa, int i) 2768184728Sraj{ 2769184728Sraj vm_offset_t va; 2770184728Sraj 2771184728Sraj va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 2772184728Sraj pmap_kenter(va, pa); 2773184728Sraj return ((void *)crashdumpmap); 2774184728Sraj} 2775184728Sraj 2776184728Sraj/* 2777129198Scognet * add a wired page to the kva 2778129198Scognet * note that in order for the mapping to take effect -- you 2779129198Scognet * should do a invltlb after doing the pmap_kenter... 2780129198Scognet */ 2781135641Scognetstatic PMAP_INLINE void 2782135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2783129198Scognet{ 2784129198Scognet struct l2_bucket *l2b; 2785129198Scognet pt_entry_t *pte; 2786129198Scognet pt_entry_t opte; 2787194459Sthompsa struct pv_entry *pve; 2788194459Sthompsa vm_page_t m; 2789194459Sthompsa 2790129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2791129198Scognet (uint32_t) va, (uint32_t) pa)); 2792129198Scognet 2793129198Scognet 2794129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2795135641Scognet if (l2b == NULL) 2796135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2797129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2798129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2799129198Scognet opte = *pte; 2800129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2801129198Scognet (uint32_t) pte, opte, *pte)); 2802129198Scognet if (l2pte_valid(opte)) { 2803194459Sthompsa pmap_kremove(va); 2804135641Scognet } else { 2805129198Scognet if (opte == 0) 2806129198Scognet l2b->l2b_occupancy++; 2807135641Scognet } 2808129198Scognet *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2809135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2810135641Scognet if (flags & KENTER_CACHE) 2811135641Scognet *pte |= pte_l2_s_cache_mode; 2812142570Scognet if (flags & KENTER_USER) 2813142570Scognet *pte |= L2_S_PROT_U; 2814129198Scognet PTE_SYNC(pte); 2815194459Sthompsa 2816194459Sthompsa /* kernel direct mappings can be shared, so use a pv_entry 2817194459Sthompsa * to ensure proper caching. 2818194459Sthompsa * 2819194459Sthompsa * The pvzone is used to delay the recording of kernel 2820194459Sthompsa * mappings until the VM is running. 2821194459Sthompsa * 2822194459Sthompsa * This expects the physical memory to have vm_page_array entry. 2823194459Sthompsa */ 2824194459Sthompsa if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa))) { 2825194459Sthompsa vm_page_lock_queues(); 2826194459Sthompsa if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva) { 2827198341Smarcel /* release vm_page lock for pv_entry UMA */ 2828194459Sthompsa vm_page_unlock_queues(); 2829194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 2830194459Sthompsa panic("pmap_kenter_internal: no pv entries"); 2831194459Sthompsa vm_page_lock_queues(); 2832194459Sthompsa PMAP_LOCK(pmap_kernel()); 2833194459Sthompsa pmap_enter_pv(m, pve, pmap_kernel(), va, 2834198341Smarcel PVF_WRITE | PVF_UNMAN); 2835194459Sthompsa pmap_fix_cache(m, pmap_kernel(), va); 2836194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2837194459Sthompsa } else { 2838194459Sthompsa m->md.pv_kva = va; 2839194459Sthompsa } 2840194459Sthompsa vm_page_unlock_queues(); 2841194459Sthompsa } 2842135641Scognet} 2843129198Scognet 2844135641Scognetvoid 2845135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2846135641Scognet{ 2847135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2848129198Scognet} 2849129198Scognet 2850142570Scognetvoid 2851156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2852156191Scognet{ 2853156191Scognet 2854156191Scognet pmap_kenter_internal(va, pa, 0); 2855156191Scognet} 2856156191Scognet 2857156191Scognetvoid 2858142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2859142570Scognet{ 2860143192Scognet 2861142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2862143192Scognet /* 2863143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2864143192Scognet * at the first use of the new address, or bad things will happen, 2865143192Scognet * as we use one of these addresses in the exception handlers. 2866143192Scognet */ 2867143192Scognet pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2868142570Scognet} 2869129198Scognet 2870129198Scognet/* 2871194908Scognet * remove a page from the kernel pagetables 2872129198Scognet */ 2873169763Scognetvoid 2874129198Scognetpmap_kremove(vm_offset_t va) 2875129198Scognet{ 2876135641Scognet struct l2_bucket *l2b; 2877135641Scognet pt_entry_t *pte, opte; 2878194459Sthompsa struct pv_entry *pve; 2879194459Sthompsa vm_page_t m; 2880194459Sthompsa vm_offset_t pa; 2881135641Scognet 2882135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2883145071Scognet if (!l2b) 2884145071Scognet return; 2885135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2886135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2887135641Scognet opte = *pte; 2888135641Scognet if (l2pte_valid(opte)) { 2889194459Sthompsa /* pa = vtophs(va) taken from pmap_extract() */ 2890194459Sthompsa switch (opte & L2_TYPE_MASK) { 2891194459Sthompsa case L2_TYPE_L: 2892194459Sthompsa pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET); 2893194459Sthompsa break; 2894194459Sthompsa default: 2895194459Sthompsa pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET); 2896194459Sthompsa break; 2897194459Sthompsa } 2898194459Sthompsa /* note: should never have to remove an allocation 2899194459Sthompsa * before the pvzone is initialized. 2900194459Sthompsa */ 2901194459Sthompsa vm_page_lock_queues(); 2902194459Sthompsa PMAP_LOCK(pmap_kernel()); 2903194459Sthompsa if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) && 2904194459Sthompsa (pve = pmap_remove_pv(m, pmap_kernel(), va))) 2905194459Sthompsa pmap_free_pv_entry(pve); 2906194459Sthompsa PMAP_UNLOCK(pmap_kernel()); 2907194459Sthompsa vm_page_unlock_queues(); 2908195779Sraj va = va & ~PAGE_MASK; 2909135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2910183838Sraj cpu_l2cache_wbinv_range(va, PAGE_SIZE); 2911135641Scognet cpu_tlb_flushD_SE(va); 2912135641Scognet cpu_cpwait(); 2913144760Scognet *pte = 0; 2914135641Scognet } 2915129198Scognet} 2916129198Scognet 2917129198Scognet 2918129198Scognet/* 2919129198Scognet * Used to map a range of physical addresses into kernel 2920129198Scognet * virtual address space. 2921129198Scognet * 2922129198Scognet * The value passed in '*virt' is a suggested virtual address for 2923129198Scognet * the mapping. Architectures which can support a direct-mapped 2924129198Scognet * physical to virtual region can return the appropriate address 2925129198Scognet * within that region, leaving '*virt' unchanged. Other 2926129198Scognet * architectures should map the pages starting at '*virt' and 2927129198Scognet * update '*virt' with the first usable address after the mapped 2928129198Scognet * region. 2929129198Scognet */ 2930129198Scognetvm_offset_t 2931129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2932129198Scognet{ 2933161105Scognet#ifdef ARM_USE_SMALL_ALLOC 2934161105Scognet return (arm_ptovirt(start)); 2935161105Scognet#else 2936129198Scognet vm_offset_t sva = *virt; 2937129198Scognet vm_offset_t va = sva; 2938129198Scognet 2939129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2940129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2941129198Scognet prot)); 2942129198Scognet 2943129198Scognet while (start < end) { 2944129198Scognet pmap_kenter(va, start); 2945129198Scognet va += PAGE_SIZE; 2946129198Scognet start += PAGE_SIZE; 2947129198Scognet } 2948129198Scognet *virt = va; 2949129198Scognet return (sva); 2950161105Scognet#endif 2951129198Scognet} 2952129198Scognet 2953143724Scognetstatic void 2954150865Scognetpmap_wb_page(vm_page_t m) 2955143724Scognet{ 2956143724Scognet struct pv_entry *pv; 2957129198Scognet 2958143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2959150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2960144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2961143724Scognet} 2962143724Scognet 2963150865Scognetstatic void 2964150865Scognetpmap_inv_page(vm_page_t m) 2965150865Scognet{ 2966150865Scognet struct pv_entry *pv; 2967150865Scognet 2968150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2969150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2970150865Scognet} 2971129198Scognet/* 2972129198Scognet * Add a list of wired pages to the kva 2973129198Scognet * this routine is only used for temporary 2974129198Scognet * kernel mappings that do not need to have 2975129198Scognet * page modification or references recorded. 2976129198Scognet * Note that old mappings are simply written 2977129198Scognet * over. The page *must* be wired. 2978129198Scognet */ 2979129198Scognetvoid 2980129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2981129198Scognet{ 2982129198Scognet int i; 2983129198Scognet 2984129198Scognet for (i = 0; i < count; i++) { 2985150865Scognet pmap_wb_page(m[i]); 2986135641Scognet pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2987135641Scognet KENTER_CACHE); 2988129198Scognet va += PAGE_SIZE; 2989129198Scognet } 2990129198Scognet} 2991129198Scognet 2992129198Scognet 2993129198Scognet/* 2994129198Scognet * this routine jerks page mappings from the 2995129198Scognet * kernel -- it is meant only for temporary mappings. 2996129198Scognet */ 2997129198Scognetvoid 2998129198Scognetpmap_qremove(vm_offset_t va, int count) 2999129198Scognet{ 3000146596Scognet vm_paddr_t pa; 3001129198Scognet int i; 3002129198Scognet 3003129198Scognet for (i = 0; i < count; i++) { 3004146596Scognet pa = vtophys(va); 3005146596Scognet if (pa) { 3006150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 3007146596Scognet pmap_kremove(va); 3008146596Scognet } 3009129198Scognet va += PAGE_SIZE; 3010129198Scognet } 3011129198Scognet} 3012129198Scognet 3013129198Scognet 3014129198Scognet/* 3015129198Scognet * pmap_object_init_pt preloads the ptes for a given object 3016129198Scognet * into the specified pmap. This eliminates the blast of soft 3017129198Scognet * faults on process startup and immediately after an mmap. 3018129198Scognet */ 3019129198Scognetvoid 3020129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3021129198Scognet vm_pindex_t pindex, vm_size_t size) 3022129198Scognet{ 3023157156Scognet 3024157156Scognet VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3025195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3026157156Scognet ("pmap_object_init_pt: non-device object")); 3027129198Scognet} 3028129198Scognet 3029129198Scognet 3030129198Scognet/* 3031129198Scognet * pmap_is_prefaultable: 3032129198Scognet * 3033129198Scognet * Return whether or not the specified virtual address is elgible 3034129198Scognet * for prefault. 3035129198Scognet */ 3036129198Scognetboolean_t 3037129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3038129198Scognet{ 3039135641Scognet pd_entry_t *pde; 3040129198Scognet pt_entry_t *pte; 3041129198Scognet 3042135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3043135641Scognet return (FALSE); 3044159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 3045135641Scognet if (*pte == 0) 3046135641Scognet return (TRUE); 3047135641Scognet return (FALSE); 3048129198Scognet} 3049129198Scognet 3050129198Scognet/* 3051129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3052129198Scognet * Returns TRUE if the mapping exists, else FALSE. 3053129198Scognet * 3054129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 3055129198Scognet * It is not safe to take any pmap locks here, since we could be right 3056129198Scognet * in the middle of debugging the pmap anyway... 3057129198Scognet * 3058129198Scognet * It is possible for this routine to return FALSE even though a valid 3059129198Scognet * mapping does exist. This is because we don't lock, so the metadata 3060129198Scognet * state may be inconsistent. 3061129198Scognet * 3062129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3063129198Scognet * a "section" mapping. 3064129198Scognet */ 3065129198Scognetboolean_t 3066129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3067129198Scognet{ 3068129198Scognet struct l2_dtable *l2; 3069129198Scognet pd_entry_t *pl1pd, l1pd; 3070129198Scognet pt_entry_t *ptep; 3071129198Scognet u_short l1idx; 3072129198Scognet 3073129198Scognet if (pm->pm_l1 == NULL) 3074129198Scognet return (FALSE); 3075129198Scognet 3076129198Scognet l1idx = L1_IDX(va); 3077129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3078129198Scognet l1pd = *pl1pd; 3079129198Scognet 3080129198Scognet if (l1pte_section_p(l1pd)) { 3081129198Scognet *ptp = NULL; 3082129198Scognet return (TRUE); 3083129198Scognet } 3084129198Scognet 3085129198Scognet if (pm->pm_l2 == NULL) 3086129198Scognet return (FALSE); 3087129198Scognet 3088129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3089129198Scognet 3090129198Scognet if (l2 == NULL || 3091129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3092129198Scognet return (FALSE); 3093129198Scognet } 3094129198Scognet 3095129198Scognet *ptp = &ptep[l2pte_index(va)]; 3096129198Scognet return (TRUE); 3097129198Scognet} 3098129198Scognet 3099129198Scognet/* 3100129198Scognet * Routine: pmap_remove_all 3101129198Scognet * Function: 3102129198Scognet * Removes this physical page from 3103129198Scognet * all physical maps in which it resides. 3104129198Scognet * Reflects back modify bits to the pager. 3105129198Scognet * 3106129198Scognet * Notes: 3107129198Scognet * Original versions of this routine were very 3108129198Scognet * inefficient because they iteratively called 3109129198Scognet * pmap_remove (slow...) 3110129198Scognet */ 3111129198Scognetvoid 3112129198Scognetpmap_remove_all(vm_page_t m) 3113129198Scognet{ 3114129198Scognet pv_entry_t pv; 3115188019Scognet pt_entry_t *ptep; 3116135641Scognet struct l2_bucket *l2b; 3117135641Scognet boolean_t flush = FALSE; 3118135641Scognet pmap_t curpm; 3119135641Scognet int flags = 0; 3120129198Scognet 3121207796Salc KASSERT((m->flags & PG_FICTITIOUS) == 0, 3122207796Salc ("pmap_remove_all: page %p is fictitious", m)); 3123135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3124135641Scognet return; 3125207796Salc vm_page_lock_queues(); 3126175840Scognet pmap_remove_write(m); 3127135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3128129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3129135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3130135641Scognet pv->pv_pmap == pmap_kernel())) 3131135641Scognet flush = TRUE; 3132193712Sraj 3133159352Salc PMAP_LOCK(pv->pv_pmap); 3134193712Sraj /* 3135193712Sraj * Cached contents were written-back in pmap_remove_write(), 3136193712Sraj * but we still have to invalidate the cache entry to make 3137193712Sraj * sure stale data are not retrieved when another page will be 3138193712Sraj * mapped under this virtual address. 3139193712Sraj */ 3140193712Sraj if (pmap_is_current(pv->pv_pmap)) { 3141193712Sraj cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE); 3142203637Sraj if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va)) 3143203637Sraj cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE); 3144193712Sraj } 3145193712Sraj 3146194459Sthompsa if (pv->pv_flags & PVF_UNMAN) { 3147194459Sthompsa /* remove the pv entry, but do not remove the mapping 3148194459Sthompsa * and remember this is a kernel mapped page 3149194459Sthompsa */ 3150194459Sthompsa m->md.pv_kva = pv->pv_va; 3151194459Sthompsa } else { 3152194459Sthompsa /* remove the mapping and pv entry */ 3153194459Sthompsa l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3154194459Sthompsa KASSERT(l2b != NULL, ("No l2 bucket")); 3155194459Sthompsa ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3156194459Sthompsa *ptep = 0; 3157194459Sthompsa PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3158194459Sthompsa pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3159194459Sthompsa if (pv->pv_flags & PVF_WIRED) 3160194459Sthompsa pv->pv_pmap->pm_stats.wired_count--; 3161194459Sthompsa pv->pv_pmap->pm_stats.resident_count--; 3162194459Sthompsa flags |= pv->pv_flags; 3163194459Sthompsa } 3164135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3165159352Salc PMAP_UNLOCK(pv->pv_pmap); 3166129198Scognet pmap_free_pv_entry(pv); 3167129198Scognet } 3168129198Scognet 3169135641Scognet if (flush) { 3170135641Scognet if (PV_BEEN_EXECD(flags)) 3171135641Scognet pmap_tlb_flushID(curpm); 3172135641Scognet else 3173135641Scognet pmap_tlb_flushD(curpm); 3174135641Scognet } 3175150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 3176207796Salc vm_page_unlock_queues(); 3177129198Scognet} 3178129198Scognet 3179129198Scognet 3180129198Scognet/* 3181129198Scognet * Set the physical protection on the 3182129198Scognet * specified range of this map as requested. 3183129198Scognet */ 3184129198Scognetvoid 3185129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3186129198Scognet{ 3187129198Scognet struct l2_bucket *l2b; 3188129198Scognet pt_entry_t *ptep, pte; 3189129198Scognet vm_offset_t next_bucket; 3190129198Scognet u_int flags; 3191129198Scognet int flush; 3192129198Scognet 3193183838Sraj CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x", 3194183838Sraj pm, sva, eva, prot); 3195183838Sraj 3196129198Scognet if ((prot & VM_PROT_READ) == 0) { 3197129198Scognet pmap_remove(pm, sva, eva); 3198129198Scognet return; 3199129198Scognet } 3200129198Scognet 3201129198Scognet if (prot & VM_PROT_WRITE) { 3202129198Scognet /* 3203129198Scognet * If this is a read->write transition, just ignore it and let 3204135641Scognet * vm_fault() take care of it later. 3205129198Scognet */ 3206129198Scognet return; 3207129198Scognet } 3208129198Scognet 3209159352Salc vm_page_lock_queues(); 3210159352Salc PMAP_LOCK(pm); 3211129198Scognet 3212129198Scognet /* 3213129198Scognet * OK, at this point, we know we're doing write-protect operation. 3214129198Scognet * If the pmap is active, write-back the range. 3215129198Scognet */ 3216129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3217129198Scognet 3218129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3219129198Scognet flags = 0; 3220129198Scognet 3221129198Scognet while (sva < eva) { 3222129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3223129198Scognet if (next_bucket > eva) 3224129198Scognet next_bucket = eva; 3225129198Scognet 3226129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3227129198Scognet if (l2b == NULL) { 3228129198Scognet sva = next_bucket; 3229129198Scognet continue; 3230129198Scognet } 3231129198Scognet 3232129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3233129198Scognet 3234129198Scognet while (sva < next_bucket) { 3235129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3236129198Scognet struct vm_page *pg; 3237129198Scognet u_int f; 3238129198Scognet 3239129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3240129198Scognet pte &= ~L2_S_PROT_W; 3241129198Scognet *ptep = pte; 3242129198Scognet PTE_SYNC(ptep); 3243129198Scognet 3244129198Scognet if (pg != NULL) { 3245129198Scognet f = pmap_modify_pv(pg, pm, sva, 3246129198Scognet PVF_WRITE, 0); 3247157970Scognet vm_page_dirty(pg); 3248129198Scognet } else 3249129198Scognet f = PVF_REF | PVF_EXEC; 3250129198Scognet 3251129198Scognet if (flush >= 0) { 3252129198Scognet flush++; 3253129198Scognet flags |= f; 3254129198Scognet } else 3255129198Scognet if (PV_BEEN_EXECD(f)) 3256129198Scognet pmap_tlb_flushID_SE(pm, sva); 3257129198Scognet else 3258129198Scognet if (PV_BEEN_REFD(f)) 3259129198Scognet pmap_tlb_flushD_SE(pm, sva); 3260129198Scognet } 3261129198Scognet 3262129198Scognet sva += PAGE_SIZE; 3263129198Scognet ptep++; 3264129198Scognet } 3265129198Scognet } 3266129198Scognet 3267129198Scognet 3268129198Scognet if (flush) { 3269129198Scognet if (PV_BEEN_EXECD(flags)) 3270129198Scognet pmap_tlb_flushID(pm); 3271129198Scognet else 3272129198Scognet if (PV_BEEN_REFD(flags)) 3273129198Scognet pmap_tlb_flushD(pm); 3274129198Scognet } 3275144760Scognet vm_page_unlock_queues(); 3276129198Scognet 3277159352Salc PMAP_UNLOCK(pm); 3278129198Scognet} 3279129198Scognet 3280129198Scognet 3281129198Scognet/* 3282129198Scognet * Insert the given physical page (p) at 3283129198Scognet * the specified virtual address (v) in the 3284129198Scognet * target physical map with the protection requested. 3285129198Scognet * 3286129198Scognet * If specified, the page will be wired down, meaning 3287129198Scognet * that the related pte can not be reclaimed. 3288129198Scognet * 3289129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3290129198Scognet * or lose information. That is, this routine must actually 3291129198Scognet * insert this page into the given map NOW. 3292129198Scognet */ 3293135641Scognet 3294129198Scognetvoid 3295175067Salcpmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3296175067Salc vm_prot_t prot, boolean_t wired) 3297129198Scognet{ 3298159127Salc 3299159127Salc vm_page_lock_queues(); 3300159352Salc PMAP_LOCK(pmap); 3301160260Scognet pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK); 3302159127Salc vm_page_unlock_queues(); 3303159352Salc PMAP_UNLOCK(pmap); 3304159127Salc} 3305159127Salc 3306159127Salc/* 3307159127Salc * The page queues and pmap must be locked. 3308159127Salc */ 3309159127Salcstatic void 3310159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3311160260Scognet boolean_t wired, int flags) 3312159127Salc{ 3313135641Scognet struct l2_bucket *l2b = NULL; 3314129198Scognet struct vm_page *opg; 3315144760Scognet struct pv_entry *pve = NULL; 3316129198Scognet pt_entry_t *ptep, npte, opte; 3317129198Scognet u_int nflags; 3318129198Scognet u_int oflags; 3319129198Scognet vm_paddr_t pa; 3320129198Scognet 3321208175Salc KASSERT((m->oflags & VPO_BUSY) != 0 || (flags & M_NOWAIT) != 0, 3322208175Salc ("pmap_enter_locked: page %p is not busy", m)); 3323159325Salc PMAP_ASSERT_LOCKED(pmap); 3324159127Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3325129198Scognet if (va == vector_page) { 3326129198Scognet pa = systempage.pv_pa; 3327129198Scognet m = NULL; 3328129198Scognet } else 3329129198Scognet pa = VM_PAGE_TO_PHYS(m); 3330129198Scognet nflags = 0; 3331129198Scognet if (prot & VM_PROT_WRITE) 3332129198Scognet nflags |= PVF_WRITE; 3333129198Scognet if (prot & VM_PROT_EXECUTE) 3334129198Scognet nflags |= PVF_EXEC; 3335129198Scognet if (wired) 3336129198Scognet nflags |= PVF_WIRED; 3337129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3338129198Scognet "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3339129198Scognet 3340135641Scognet if (pmap == pmap_kernel()) { 3341129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3342135641Scognet if (l2b == NULL) 3343135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3344160260Scognet } else { 3345160260Scognetdo_l2b_alloc: 3346129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3347160260Scognet if (l2b == NULL) { 3348160260Scognet if (flags & M_WAITOK) { 3349160260Scognet PMAP_UNLOCK(pmap); 3350160260Scognet vm_page_unlock_queues(); 3351160260Scognet VM_WAIT; 3352160260Scognet vm_page_lock_queues(); 3353160260Scognet PMAP_LOCK(pmap); 3354160260Scognet goto do_l2b_alloc; 3355160260Scognet } 3356160260Scognet return; 3357160260Scognet } 3358160260Scognet } 3359160260Scognet 3360129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3361129198Scognet 3362135641Scognet opte = *ptep; 3363129198Scognet npte = pa; 3364129198Scognet oflags = 0; 3365129198Scognet if (opte) { 3366129198Scognet /* 3367129198Scognet * There is already a mapping at this address. 3368129198Scognet * If the physical address is different, lookup the 3369129198Scognet * vm_page. 3370129198Scognet */ 3371129198Scognet if (l2pte_pa(opte) != pa) 3372129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3373129198Scognet else 3374129198Scognet opg = m; 3375129198Scognet } else 3376129198Scognet opg = NULL; 3377129198Scognet 3378135641Scognet if ((prot & (VM_PROT_ALL)) || 3379135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3380129198Scognet /* 3381135641Scognet * - The access type indicates that we don't need 3382135641Scognet * to do referenced emulation. 3383135641Scognet * OR 3384135641Scognet * - The physical page has already been referenced 3385135641Scognet * so no need to re-do referenced emulation here. 3386129198Scognet */ 3387135641Scognet npte |= L2_S_PROTO; 3388135641Scognet 3389135641Scognet nflags |= PVF_REF; 3390135641Scognet 3391144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3392144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3393129198Scognet /* 3394135641Scognet * This is a writable mapping, and the 3395135641Scognet * page's mod state indicates it has 3396135641Scognet * already been modified. Make it 3397135641Scognet * writable from the outset. 3398129198Scognet */ 3399135641Scognet nflags |= PVF_MOD; 3400157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3401144760Scognet vm_page_dirty(m); 3402129198Scognet } 3403144760Scognet if (m && opte) 3404144760Scognet vm_page_flag_set(m, PG_REFERENCED); 3405135641Scognet } else { 3406135641Scognet /* 3407135641Scognet * Need to do page referenced emulation. 3408135641Scognet */ 3409135641Scognet npte |= L2_TYPE_INV; 3410135641Scognet } 3411135641Scognet 3412164229Salc if (prot & VM_PROT_WRITE) { 3413135641Scognet npte |= L2_S_PROT_W; 3414164229Salc if (m != NULL) 3415164229Salc vm_page_flag_set(m, PG_WRITEABLE); 3416164229Salc } 3417135641Scognet npte |= pte_l2_s_cache_mode; 3418135641Scognet if (m && m == opg) { 3419135641Scognet /* 3420135641Scognet * We're changing the attrs of an existing mapping. 3421135641Scognet */ 3422135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3423135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3424135641Scognet PVF_MOD | PVF_REF, nflags); 3425135641Scognet 3426135641Scognet /* 3427135641Scognet * We may need to flush the cache if we're 3428135641Scognet * doing rw-ro... 3429135641Scognet */ 3430135641Scognet if (pmap_is_current(pmap) && 3431135641Scognet (oflags & PVF_NC) == 0 && 3432183838Sraj (opte & L2_S_PROT_W) != 0 && 3433203637Sraj (prot & VM_PROT_WRITE) == 0 && 3434203637Sraj (opte & L2_TYPE_MASK) != L2_TYPE_INV) { 3435135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3436203637Sraj cpu_l2cache_wb_range(va, PAGE_SIZE); 3437183838Sraj } 3438129198Scognet } else { 3439129198Scognet /* 3440135641Scognet * New mapping, or changing the backing page 3441135641Scognet * of an existing mapping. 3442129198Scognet */ 3443129198Scognet if (opg) { 3444129198Scognet /* 3445135641Scognet * Replacing an existing mapping with a new one. 3446135641Scognet * It is part of our managed memory so we 3447135641Scognet * must remove it from the PV list 3448129198Scognet */ 3449194459Sthompsa if ((pve = pmap_remove_pv(opg, pmap, va))) { 3450194459Sthompsa 3451194459Sthompsa /* note for patch: the oflags/invalidation was moved 3452194459Sthompsa * because PG_FICTITIOUS pages could free the pve 3453194459Sthompsa */ 3454194459Sthompsa oflags = pve->pv_flags; 3455135641Scognet /* 3456135641Scognet * If the old mapping was valid (ref/mod 3457135641Scognet * emulation creates 'invalid' mappings 3458135641Scognet * initially) then make sure to frob 3459135641Scognet * the cache. 3460135641Scognet */ 3461194459Sthompsa if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 3462135641Scognet if (PV_BEEN_EXECD(oflags)) { 3463129198Scognet pmap_idcache_wbinv_range(pmap, va, 3464129198Scognet PAGE_SIZE); 3465135641Scognet } else 3466135641Scognet if (PV_BEEN_REFD(oflags)) { 3467135641Scognet pmap_dcache_wb_range(pmap, va, 3468135641Scognet PAGE_SIZE, TRUE, 3469135641Scognet (oflags & PVF_WRITE) == 0); 3470135641Scognet } 3471194459Sthompsa } 3472194459Sthompsa 3473194459Sthompsa /* free/allocate a pv_entry for UNMANAGED pages if 3474194459Sthompsa * this physical page is not/is already mapped. 3475194459Sthompsa */ 3476194459Sthompsa 3477194459Sthompsa if (m && ((m->flags & PG_FICTITIOUS) || 3478194459Sthompsa ((m->flags & PG_UNMANAGED) && 3479194459Sthompsa !m->md.pv_kva && 3480194459Sthompsa TAILQ_EMPTY(&m->md.pv_list)))) { 3481194459Sthompsa pmap_free_pv_entry(pve); 3482194459Sthompsa pve = NULL; 3483194459Sthompsa } 3484194459Sthompsa } else if (m && !(m->flags & PG_FICTITIOUS) && 3485194459Sthompsa (!(m->flags & PG_UNMANAGED) || m->md.pv_kva || 3486194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3487194459Sthompsa pve = pmap_get_pv_entry(); 3488194459Sthompsa } else if (m && !(m->flags & PG_FICTITIOUS) && 3489194459Sthompsa (!(m->flags & PG_UNMANAGED) || m->md.pv_kva || 3490194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3491194459Sthompsa pve = pmap_get_pv_entry(); 3492194459Sthompsa 3493194459Sthompsa if (m && !(m->flags & PG_FICTITIOUS)) { 3494194459Sthompsa KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3495194459Sthompsa ("pmap_enter: managed mapping within the clean submap")); 3496194459Sthompsa if (m->flags & PG_UNMANAGED) { 3497194459Sthompsa if (!TAILQ_EMPTY(&m->md.pv_list) || 3498194459Sthompsa m->md.pv_kva) { 3499194459Sthompsa KASSERT(pve != NULL, ("No pv")); 3500194459Sthompsa nflags |= PVF_UNMAN; 3501194459Sthompsa pmap_enter_pv(m, pve, pmap, va, nflags); 3502194459Sthompsa } else 3503194459Sthompsa m->md.pv_kva = va; 3504194459Sthompsa } else { 3505194459Sthompsa KASSERT(pve != NULL, ("No pv")); 3506194459Sthompsa pmap_enter_pv(m, pve, pmap, va, nflags); 3507129198Scognet } 3508157970Scognet } 3509129198Scognet } 3510129198Scognet /* 3511129198Scognet * Make sure userland mappings get the right permissions 3512129198Scognet */ 3513129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3514129198Scognet npte |= L2_S_PROT_U; 3515129198Scognet } 3516129198Scognet 3517129198Scognet /* 3518129198Scognet * Keep the stats up to date 3519129198Scognet */ 3520129198Scognet if (opte == 0) { 3521129198Scognet l2b->l2b_occupancy++; 3522129198Scognet pmap->pm_stats.resident_count++; 3523129198Scognet } 3524129198Scognet 3525129198Scognet 3526129198Scognet /* 3527129198Scognet * If this is just a wiring change, the two PTEs will be 3528129198Scognet * identical, so there's no need to update the page table. 3529129198Scognet */ 3530129198Scognet if (npte != opte) { 3531135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3532129198Scognet 3533129198Scognet *ptep = npte; 3534129198Scognet if (is_cached) { 3535129198Scognet /* 3536129198Scognet * We only need to frob the cache/tlb if this pmap 3537129198Scognet * is current 3538129198Scognet */ 3539129198Scognet PTE_SYNC(ptep); 3540161105Scognet if (L1_IDX(va) != L1_IDX(vector_page) && 3541129198Scognet l2pte_valid(npte)) { 3542129198Scognet /* 3543129198Scognet * This mapping is likely to be accessed as 3544129198Scognet * soon as we return to userland. Fix up the 3545129198Scognet * L1 entry to avoid taking another 3546129198Scognet * page/domain fault. 3547129198Scognet */ 3548129198Scognet pd_entry_t *pl1pd, l1pd; 3549129198Scognet 3550129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3551129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3552144760Scognet L1_C_PROTO; 3553129198Scognet if (*pl1pd != l1pd) { 3554129198Scognet *pl1pd = l1pd; 3555129198Scognet PTE_SYNC(pl1pd); 3556129198Scognet } 3557129198Scognet } 3558129198Scognet } 3559129198Scognet 3560129198Scognet if (PV_BEEN_EXECD(oflags)) 3561129198Scognet pmap_tlb_flushID_SE(pmap, va); 3562135641Scognet else if (PV_BEEN_REFD(oflags)) 3563129198Scognet pmap_tlb_flushD_SE(pmap, va); 3564129198Scognet 3565129198Scognet 3566157025Scognet if (m) 3567175840Scognet pmap_fix_cache(m, pmap, va); 3568129198Scognet } 3569129198Scognet} 3570129198Scognet 3571129198Scognet/* 3572159303Salc * Maps a sequence of resident pages belonging to the same object. 3573159303Salc * The sequence begins with the given page m_start. This page is 3574159303Salc * mapped at the given virtual address start. Each subsequent page is 3575159303Salc * mapped at a virtual address that is offset from start by the same 3576159303Salc * amount as the page is offset from m_start within the object. The 3577159303Salc * last page in the sequence is the page with the largest offset from 3578159303Salc * m_start that can be mapped at a virtual address less than the given 3579159303Salc * virtual address end. Not every virtual page between start and end 3580159303Salc * is mapped; only those for which a resident page exists with the 3581159303Salc * corresponding offset from m_start are mapped. 3582159303Salc */ 3583159303Salcvoid 3584159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3585159303Salc vm_page_t m_start, vm_prot_t prot) 3586159303Salc{ 3587159303Salc vm_page_t m; 3588159303Salc vm_pindex_t diff, psize; 3589159303Salc 3590159303Salc psize = atop(end - start); 3591159303Salc m = m_start; 3592159325Salc PMAP_LOCK(pmap); 3593159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3594159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3595160260Scognet (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT); 3596159303Salc m = TAILQ_NEXT(m, listq); 3597159303Salc } 3598159325Salc PMAP_UNLOCK(pmap); 3599159303Salc} 3600159303Salc 3601159303Salc/* 3602129198Scognet * this code makes some *MAJOR* assumptions: 3603129198Scognet * 1. Current pmap & pmap exists. 3604129198Scognet * 2. Not wired. 3605129198Scognet * 3. Read access. 3606129198Scognet * 4. No page table pages. 3607129198Scognet * but is *MUCH* faster than pmap_enter... 3608129198Scognet */ 3609129198Scognet 3610159627Supsvoid 3611159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3612129198Scognet{ 3613138897Salc 3614207796Salc vm_page_lock_queues(); 3615159325Salc PMAP_LOCK(pmap); 3616159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3617160260Scognet FALSE, M_NOWAIT); 3618207796Salc vm_page_unlock_queues(); 3619159325Salc PMAP_UNLOCK(pmap); 3620129198Scognet} 3621129198Scognet 3622129198Scognet/* 3623129198Scognet * Routine: pmap_change_wiring 3624129198Scognet * Function: Change the wiring attribute for a map/virtual-address 3625129198Scognet * pair. 3626129198Scognet * In/out conditions: 3627129198Scognet * The mapping must already exist in the pmap. 3628129198Scognet */ 3629129198Scognetvoid 3630129198Scognetpmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3631129198Scognet{ 3632129198Scognet struct l2_bucket *l2b; 3633129198Scognet pt_entry_t *ptep, pte; 3634129198Scognet vm_page_t pg; 3635129198Scognet 3636159352Salc vm_page_lock_queues(); 3637159325Salc PMAP_LOCK(pmap); 3638129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3639129198Scognet KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3640129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3641129198Scognet pte = *ptep; 3642129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3643129198Scognet if (pg) 3644129198Scognet pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired); 3645159352Salc vm_page_unlock_queues(); 3646159325Salc PMAP_UNLOCK(pmap); 3647129198Scognet} 3648129198Scognet 3649129198Scognet 3650129198Scognet/* 3651129198Scognet * Copy the range specified by src_addr/len 3652129198Scognet * from the source map to the range dst_addr/len 3653129198Scognet * in the destination map. 3654129198Scognet * 3655129198Scognet * This routine is only advisory and need not do anything. 3656129198Scognet */ 3657129198Scognetvoid 3658129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3659129198Scognet vm_size_t len, vm_offset_t src_addr) 3660129198Scognet{ 3661129198Scognet} 3662129198Scognet 3663129198Scognet 3664129198Scognet/* 3665129198Scognet * Routine: pmap_extract 3666129198Scognet * Function: 3667129198Scognet * Extract the physical page address associated 3668129198Scognet * with the given map/virtual_address pair. 3669129198Scognet */ 3670131658Salcvm_paddr_t 3671129198Scognetpmap_extract(pmap_t pm, vm_offset_t va) 3672129198Scognet{ 3673129198Scognet struct l2_dtable *l2; 3674159450Salc pd_entry_t l1pd; 3675129198Scognet pt_entry_t *ptep, pte; 3676129198Scognet vm_paddr_t pa; 3677129198Scognet u_int l1idx; 3678129198Scognet l1idx = L1_IDX(va); 3679129198Scognet 3680159450Salc PMAP_LOCK(pm); 3681159450Salc l1pd = pm->pm_l1->l1_kva[l1idx]; 3682129198Scognet if (l1pte_section_p(l1pd)) { 3683129198Scognet /* 3684129198Scognet * These should only happen for pmap_kernel() 3685129198Scognet */ 3686129198Scognet KASSERT(pm == pmap_kernel(), ("huh")); 3687171620Scognet /* XXX: what to do about the bits > 32 ? */ 3688171620Scognet if (l1pd & L1_S_SUPERSEC) 3689171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3690171620Scognet else 3691171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3692129198Scognet } else { 3693129198Scognet /* 3694129198Scognet * Note that we can't rely on the validity of the L1 3695129198Scognet * descriptor as an indication that a mapping exists. 3696129198Scognet * We have to look it up in the L2 dtable. 3697129198Scognet */ 3698129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3699129198Scognet 3700129198Scognet if (l2 == NULL || 3701129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3702159450Salc PMAP_UNLOCK(pm); 3703129198Scognet return (0); 3704129198Scognet } 3705129198Scognet 3706129198Scognet ptep = &ptep[l2pte_index(va)]; 3707129198Scognet pte = *ptep; 3708129198Scognet 3709159450Salc if (pte == 0) { 3710159450Salc PMAP_UNLOCK(pm); 3711129198Scognet return (0); 3712159450Salc } 3713129198Scognet 3714129198Scognet switch (pte & L2_TYPE_MASK) { 3715129198Scognet case L2_TYPE_L: 3716129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3717129198Scognet break; 3718129198Scognet 3719129198Scognet default: 3720129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3721129198Scognet break; 3722129198Scognet } 3723129198Scognet } 3724129198Scognet 3725159450Salc PMAP_UNLOCK(pm); 3726129198Scognet return (pa); 3727129198Scognet} 3728129198Scognet 3729133453Salc/* 3730133453Salc * Atomically extract and hold the physical page with the given 3731133453Salc * pmap and virtual address pair if that mapping permits the given 3732133453Salc * protection. 3733133453Salc * 3734133453Salc */ 3735129198Scognetvm_page_t 3736129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3737129198Scognet{ 3738135641Scognet struct l2_dtable *l2; 3739159378Salc pd_entry_t l1pd; 3740135641Scognet pt_entry_t *ptep, pte; 3741207410Skmacy vm_paddr_t pa, paddr; 3742135641Scognet vm_page_t m = NULL; 3743135641Scognet u_int l1idx; 3744135641Scognet l1idx = L1_IDX(va); 3745207410Skmacy paddr = 0; 3746129198Scognet 3747159325Salc PMAP_LOCK(pmap); 3748207410Skmacyretry: 3749159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3750135641Scognet if (l1pte_section_p(l1pd)) { 3751135641Scognet /* 3752135641Scognet * These should only happen for pmap_kernel() 3753135641Scognet */ 3754135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3755171620Scognet /* XXX: what to do about the bits > 32 ? */ 3756171620Scognet if (l1pd & L1_S_SUPERSEC) 3757171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3758171620Scognet else 3759171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3760207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3761207410Skmacy goto retry; 3762135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3763135641Scognet m = PHYS_TO_VM_PAGE(pa); 3764135641Scognet vm_page_hold(m); 3765135641Scognet } 3766135641Scognet 3767135641Scognet } else { 3768135641Scognet /* 3769135641Scognet * Note that we can't rely on the validity of the L1 3770135641Scognet * descriptor as an indication that a mapping exists. 3771135641Scognet * We have to look it up in the L2 dtable. 3772135641Scognet */ 3773135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3774135641Scognet 3775135641Scognet if (l2 == NULL || 3776135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3777159325Salc PMAP_UNLOCK(pmap); 3778135641Scognet return (NULL); 3779135641Scognet } 3780135641Scognet 3781135641Scognet ptep = &ptep[l2pte_index(va)]; 3782135641Scognet pte = *ptep; 3783135641Scognet 3784150865Scognet if (pte == 0) { 3785159325Salc PMAP_UNLOCK(pmap); 3786135641Scognet return (NULL); 3787150865Scognet } 3788135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3789135641Scognet switch (pte & L2_TYPE_MASK) { 3790135641Scognet case L2_TYPE_L: 3791135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3792135641Scognet break; 3793135641Scognet 3794135641Scognet default: 3795135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3796135641Scognet break; 3797135641Scognet } 3798207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3799207410Skmacy goto retry; 3800135641Scognet m = PHYS_TO_VM_PAGE(pa); 3801135641Scognet vm_page_hold(m); 3802135641Scognet } 3803129198Scognet } 3804135641Scognet 3805159325Salc PMAP_UNLOCK(pmap); 3806207410Skmacy PA_UNLOCK_COND(paddr); 3807129198Scognet return (m); 3808129198Scognet} 3809129198Scognet 3810129198Scognet/* 3811129198Scognet * Initialize a preallocated and zeroed pmap structure, 3812129198Scognet * such as one in a vmspace structure. 3813129198Scognet */ 3814129198Scognet 3815173361Skibint 3816129198Scognetpmap_pinit(pmap_t pmap) 3817129198Scognet{ 3818129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3819129198Scognet 3820159325Salc PMAP_LOCK_INIT(pmap); 3821129198Scognet pmap_alloc_l1(pmap); 3822129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3823129198Scognet 3824129198Scognet pmap->pm_active = 0; 3825129198Scognet 3826144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3827129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3828129198Scognet pmap->pm_stats.resident_count = 1; 3829129198Scognet if (vector_page < KERNBASE) { 3830175840Scognet pmap_enter(pmap, vector_page, 3831175397Scognet VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa), 3832129198Scognet VM_PROT_READ, 1); 3833129198Scognet } 3834173361Skib return (1); 3835129198Scognet} 3836129198Scognet 3837129198Scognet 3838129198Scognet/*************************************************** 3839129198Scognet * page management routines. 3840129198Scognet ***************************************************/ 3841129198Scognet 3842129198Scognet 3843135641Scognetstatic void 3844129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3845129198Scognet{ 3846129198Scognet pv_entry_count--; 3847129198Scognet uma_zfree(pvzone, pv); 3848129198Scognet} 3849129198Scognet 3850129198Scognet 3851129198Scognet/* 3852129198Scognet * get a new pv_entry, allocating a block from the system 3853129198Scognet * when needed. 3854129198Scognet * the memory allocation is performed bypassing the malloc code 3855129198Scognet * because of the possibility of allocations at interrupt time. 3856129198Scognet */ 3857129198Scognetstatic pv_entry_t 3858129198Scognetpmap_get_pv_entry(void) 3859129198Scognet{ 3860129198Scognet pv_entry_t ret_value; 3861129198Scognet 3862129198Scognet pv_entry_count++; 3863159500Salc if (pv_entry_count > pv_entry_high_water) 3864159500Salc pagedaemon_wakeup(); 3865129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3866129198Scognet return ret_value; 3867129198Scognet} 3868129198Scognet 3869129198Scognet/* 3870129198Scognet * Remove the given range of addresses from the specified map. 3871129198Scognet * 3872129198Scognet * It is assumed that the start and end are properly 3873129198Scognet * rounded to the page size. 3874129198Scognet */ 3875175840Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3876129198Scognetvoid 3877129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3878129198Scognet{ 3879129198Scognet struct l2_bucket *l2b; 3880129198Scognet vm_offset_t next_bucket; 3881129198Scognet pt_entry_t *ptep; 3882175840Scognet u_int total; 3883129198Scognet u_int mappings, is_exec, is_refd; 3884135641Scognet int flushall = 0; 3885129198Scognet 3886129198Scognet 3887129198Scognet /* 3888129198Scognet * we lock in the pmap => pv_head direction 3889129198Scognet */ 3890129198Scognet 3891137664Scognet vm_page_lock_queues(); 3892159352Salc PMAP_LOCK(pm); 3893129198Scognet total = 0; 3894129198Scognet while (sva < eva) { 3895129198Scognet /* 3896129198Scognet * Do one L2 bucket's worth at a time. 3897129198Scognet */ 3898129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3899129198Scognet if (next_bucket > eva) 3900129198Scognet next_bucket = eva; 3901129198Scognet 3902129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3903129198Scognet if (l2b == NULL) { 3904129198Scognet sva = next_bucket; 3905129198Scognet continue; 3906129198Scognet } 3907129198Scognet 3908129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3909129198Scognet mappings = 0; 3910129198Scognet 3911129198Scognet while (sva < next_bucket) { 3912129198Scognet struct vm_page *pg; 3913129198Scognet pt_entry_t pte; 3914129198Scognet vm_paddr_t pa; 3915129198Scognet 3916129198Scognet pte = *ptep; 3917129198Scognet 3918129198Scognet if (pte == 0) { 3919129198Scognet /* 3920129198Scognet * Nothing here, move along 3921129198Scognet */ 3922129198Scognet sva += PAGE_SIZE; 3923129198Scognet ptep++; 3924129198Scognet continue; 3925129198Scognet } 3926129198Scognet 3927129198Scognet pm->pm_stats.resident_count--; 3928129198Scognet pa = l2pte_pa(pte); 3929129198Scognet is_exec = 0; 3930129198Scognet is_refd = 1; 3931129198Scognet 3932129198Scognet /* 3933129198Scognet * Update flags. In a number of circumstances, 3934129198Scognet * we could cluster a lot of these and do a 3935129198Scognet * number of sequential pages in one go. 3936129198Scognet */ 3937129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3938129198Scognet struct pv_entry *pve; 3939159474Salc 3940129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3941135641Scognet if (pve) { 3942159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3943159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3944129198Scognet pmap_free_pv_entry(pve); 3945129198Scognet } 3946129198Scognet } 3947129198Scognet 3948175840Scognet if (l2pte_valid(pte) && pmap_is_current(pm)) { 3949175840Scognet if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3950175840Scognet total++; 3951175840Scognet if (is_exec) { 3952175840Scognet cpu_idcache_wbinv_range(sva, 3953183838Sraj PAGE_SIZE); 3954183838Sraj cpu_l2cache_wbinv_range(sva, 3955183838Sraj PAGE_SIZE); 3956175840Scognet cpu_tlb_flushID_SE(sva); 3957175840Scognet } else if (is_refd) { 3958175840Scognet cpu_dcache_wbinv_range(sva, 3959183838Sraj PAGE_SIZE); 3960183838Sraj cpu_l2cache_wbinv_range(sva, 3961183838Sraj PAGE_SIZE); 3962175840Scognet cpu_tlb_flushD_SE(sva); 3963175840Scognet } 3964175840Scognet } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3965175840Scognet /* flushall will also only get set for 3966175840Scognet * for a current pmap 3967175840Scognet */ 3968175840Scognet cpu_idcache_wbinv_all(); 3969183838Sraj cpu_l2cache_wbinv_all(); 3970175840Scognet flushall = 1; 3971175840Scognet total++; 3972129198Scognet } 3973129198Scognet } 3974175840Scognet *ptep = 0; 3975175840Scognet PTE_SYNC(ptep); 3976129198Scognet 3977129198Scognet sva += PAGE_SIZE; 3978129198Scognet ptep++; 3979129198Scognet mappings++; 3980129198Scognet } 3981129198Scognet 3982129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 3983129198Scognet } 3984129198Scognet 3985137664Scognet vm_page_unlock_queues(); 3986135641Scognet if (flushall) 3987135641Scognet cpu_tlb_flushID(); 3988159352Salc PMAP_UNLOCK(pm); 3989129198Scognet} 3990129198Scognet 3991129198Scognet/* 3992129198Scognet * pmap_zero_page() 3993129198Scognet * 3994129198Scognet * Zero a given physical page by mapping it at a page hook point. 3995129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 3996129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 3997129198Scognet * _any_ bulk data very slow. 3998129198Scognet */ 3999164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) 4000129198Scognetvoid 4001129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 4002129198Scognet{ 4003161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4004161105Scognet char *dstpg; 4005161105Scognet#endif 4006161105Scognet 4007129198Scognet#ifdef DEBUG 4008129198Scognet struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4009129198Scognet 4010129198Scognet if (pg->md.pvh_list != NULL) 4011129198Scognet panic("pmap_zero_page: page has mappings"); 4012129198Scognet#endif 4013129198Scognet 4014172300Scognet if (_arm_bzero && size >= _min_bzero_size && 4015150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4016150865Scognet return; 4017129198Scognet 4018161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4019161105Scognet dstpg = (char *)arm_ptovirt(phys); 4020161105Scognet if (off || size != PAGE_SIZE) { 4021161105Scognet bzero(dstpg + off, size); 4022161105Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4023183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size); 4024161105Scognet } else { 4025161105Scognet bzero_page((vm_offset_t)dstpg); 4026161105Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4027183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4028161105Scognet } 4029161105Scognet#else 4030150865Scognet 4031159088Scognet mtx_lock(&cmtx); 4032129198Scognet /* 4033183836Sraj * Hook in the page, zero it, invalidate the TLB as needed. 4034183836Sraj * 4035183836Sraj * Note the temporary zero-page mapping must be a non-cached page in 4036184730Sraj * order to work without corruption when write-allocate is enabled. 4037129198Scognet */ 4038183836Sraj *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 4039129198Scognet cpu_tlb_flushD_SE(cdstp); 4040129198Scognet cpu_cpwait(); 4041183836Sraj if (off || size != PAGE_SIZE) 4042129198Scognet bzero((void *)(cdstp + off), size); 4043183836Sraj else 4044129198Scognet bzero_page(cdstp); 4045183836Sraj 4046159088Scognet mtx_unlock(&cmtx); 4047161105Scognet#endif 4048129198Scognet} 4049129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4050129198Scognet 4051129198Scognet#if ARM_MMU_XSCALE == 1 4052129198Scognetvoid 4053129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 4054129198Scognet{ 4055172713Scognet#ifdef ARM_USE_SMALL_ALLOC 4056172713Scognet char *dstpg; 4057172713Scognet#endif 4058172713Scognet 4059172300Scognet if (_arm_bzero && size >= _min_bzero_size && 4060150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4061150865Scognet return; 4062172713Scognet#ifdef ARM_USE_SMALL_ALLOC 4063172713Scognet dstpg = (char *)arm_ptovirt(phys); 4064172713Scognet if (off || size != PAGE_SIZE) { 4065172713Scognet bzero(dstpg + off, size); 4066172713Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4067172713Scognet } else { 4068172713Scognet bzero_page((vm_offset_t)dstpg); 4069172713Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4070172713Scognet } 4071172713Scognet#else 4072159088Scognet mtx_lock(&cmtx); 4073129198Scognet /* 4074129198Scognet * Hook in the page, zero it, and purge the cache for that 4075129198Scognet * zeroed page. Invalidate the TLB as needed. 4076129198Scognet */ 4077129198Scognet *cdst_pte = L2_S_PROTO | phys | 4078129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4079129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4080129198Scognet PTE_SYNC(cdst_pte); 4081129198Scognet cpu_tlb_flushD_SE(cdstp); 4082129198Scognet cpu_cpwait(); 4083135641Scognet if (off || size != PAGE_SIZE) 4084129198Scognet bzero((void *)(cdstp + off), size); 4085129198Scognet else 4086129198Scognet bzero_page(cdstp); 4087159088Scognet mtx_unlock(&cmtx); 4088129198Scognet xscale_cache_clean_minidata(); 4089172713Scognet#endif 4090129198Scognet} 4091129198Scognet 4092129198Scognet/* 4093129198Scognet * Change the PTEs for the specified kernel mappings such that they 4094129198Scognet * will use the mini data cache instead of the main data cache. 4095129198Scognet */ 4096129198Scognetvoid 4097135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 4098129198Scognet{ 4099129198Scognet struct l2_bucket *l2b; 4100129198Scognet pt_entry_t *ptep, *sptep, pte; 4101129198Scognet vm_offset_t next_bucket, eva; 4102129198Scognet 4103164778Scognet#if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3) 4104129198Scognet if (xscale_use_minidata == 0) 4105129198Scognet return; 4106129198Scognet#endif 4107129198Scognet 4108135641Scognet eva = va + size; 4109129198Scognet 4110129198Scognet while (va < eva) { 4111129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4112129198Scognet if (next_bucket > eva) 4113129198Scognet next_bucket = eva; 4114129198Scognet 4115129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4116129198Scognet 4117129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4118129198Scognet 4119129198Scognet while (va < next_bucket) { 4120129198Scognet pte = *ptep; 4121129198Scognet if (!l2pte_minidata(pte)) { 4122129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4123129198Scognet cpu_tlb_flushD_SE(va); 4124129198Scognet *ptep = pte & ~L2_B; 4125129198Scognet } 4126129198Scognet ptep++; 4127129198Scognet va += PAGE_SIZE; 4128129198Scognet } 4129129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4130129198Scognet } 4131129198Scognet cpu_cpwait(); 4132129198Scognet} 4133129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4134129198Scognet 4135129198Scognet/* 4136129198Scognet * pmap_zero_page zeros the specified hardware page by mapping 4137129198Scognet * the page into KVM and using bzero to clear its contents. 4138129198Scognet */ 4139129198Scognetvoid 4140129198Scognetpmap_zero_page(vm_page_t m) 4141129198Scognet{ 4142135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4143129198Scognet} 4144129198Scognet 4145129198Scognet 4146129198Scognet/* 4147129198Scognet * pmap_zero_page_area zeros the specified hardware page by mapping 4148129198Scognet * the page into KVM and using bzero to clear its contents. 4149129198Scognet * 4150129198Scognet * off and size may not cover an area beyond a single hardware page. 4151129198Scognet */ 4152129198Scognetvoid 4153129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4154129198Scognet{ 4155129198Scognet 4156129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4157129198Scognet} 4158129198Scognet 4159129198Scognet 4160129198Scognet/* 4161129198Scognet * pmap_zero_page_idle zeros the specified hardware page by mapping 4162129198Scognet * the page into KVM and using bzero to clear its contents. This 4163129198Scognet * is intended to be called from the vm_pagezero process only and 4164129198Scognet * outside of Giant. 4165129198Scognet */ 4166129198Scognetvoid 4167129198Scognetpmap_zero_page_idle(vm_page_t m) 4168129198Scognet{ 4169129198Scognet 4170129198Scognet pmap_zero_page(m); 4171129198Scognet} 4172129198Scognet 4173150865Scognet#if 0 4174129198Scognet/* 4175129198Scognet * pmap_clean_page() 4176129198Scognet * 4177129198Scognet * This is a local function used to work out the best strategy to clean 4178197770Sstas * a single page referenced by its entry in the PV table. It should be used by 4179129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4180129198Scognet * 4181129198Scognet * Its policy is effectively: 4182129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4183129198Scognet * o If there is one mapping, we clean just that page. 4184129198Scognet * o If there are multiple mappings, we clean the entire cache. 4185129198Scognet * 4186129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4187129198Scognet * clean the entire cache, or 1 if it did. 4188129198Scognet * 4189129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4190129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4191129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4192129198Scognet * it will just result in not the most efficient clean for the page. 4193197770Sstas * 4194197770Sstas * We don't yet use this function but may want to. 4195129198Scognet */ 4196129198Scognetstatic int 4197129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4198129198Scognet{ 4199129198Scognet pmap_t pm, pm_to_clean = NULL; 4200129198Scognet struct pv_entry *npv; 4201129198Scognet u_int cache_needs_cleaning = 0; 4202129198Scognet u_int flags = 0; 4203129198Scognet vm_offset_t page_to_clean = 0; 4204129198Scognet 4205129198Scognet if (pv == NULL) { 4206129198Scognet /* nothing mapped in so nothing to flush */ 4207129198Scognet return (0); 4208129198Scognet } 4209129198Scognet 4210129198Scognet /* 4211129198Scognet * Since we flush the cache each time we change to a different 4212129198Scognet * user vmspace, we only need to flush the page if it is in the 4213129198Scognet * current pmap. 4214129198Scognet */ 4215135641Scognet if (curthread) 4216135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4217129198Scognet else 4218129198Scognet pm = pmap_kernel(); 4219129198Scognet 4220129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4221129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4222129198Scognet flags |= npv->pv_flags; 4223129198Scognet /* 4224129198Scognet * The page is mapped non-cacheable in 4225129198Scognet * this map. No need to flush the cache. 4226129198Scognet */ 4227129198Scognet if (npv->pv_flags & PVF_NC) { 4228129198Scognet#ifdef DIAGNOSTIC 4229129198Scognet if (cache_needs_cleaning) 4230129198Scognet panic("pmap_clean_page: " 4231129198Scognet "cache inconsistency"); 4232129198Scognet#endif 4233129198Scognet break; 4234129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4235129198Scognet continue; 4236129198Scognet if (cache_needs_cleaning) { 4237129198Scognet page_to_clean = 0; 4238129198Scognet break; 4239129198Scognet } else { 4240129198Scognet page_to_clean = npv->pv_va; 4241129198Scognet pm_to_clean = npv->pv_pmap; 4242129198Scognet } 4243129198Scognet cache_needs_cleaning = 1; 4244129198Scognet } 4245129198Scognet } 4246129198Scognet if (page_to_clean) { 4247129198Scognet if (PV_BEEN_EXECD(flags)) 4248129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4249129198Scognet PAGE_SIZE); 4250129198Scognet else 4251129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4252129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4253129198Scognet } else if (cache_needs_cleaning) { 4254129198Scognet if (PV_BEEN_EXECD(flags)) 4255129198Scognet pmap_idcache_wbinv_all(pm); 4256129198Scognet else 4257129198Scognet pmap_dcache_wbinv_all(pm); 4258129198Scognet return (1); 4259129198Scognet } 4260129198Scognet return (0); 4261129198Scognet} 4262150865Scognet#endif 4263129198Scognet 4264129198Scognet/* 4265129198Scognet * pmap_copy_page copies the specified (machine independent) 4266129198Scognet * page by mapping the page into virtual memory and using 4267129198Scognet * bcopy to copy the page, one machine dependent page at a 4268129198Scognet * time. 4269129198Scognet */ 4270129198Scognet 4271129198Scognet/* 4272129198Scognet * pmap_copy_page() 4273129198Scognet * 4274129198Scognet * Copy one physical page into another, by mapping the pages into 4275129198Scognet * hook points. The same comment regarding cachability as in 4276129198Scognet * pmap_zero_page also applies here. 4277129198Scognet */ 4278164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) 4279129198Scognetvoid 4280129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4281129198Scognet{ 4282151596Scognet#if 0 4283129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4284151596Scognet#endif 4285129198Scognet#ifdef DEBUG 4286129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4287129198Scognet 4288129198Scognet if (dst_pg->md.pvh_list != NULL) 4289129198Scognet panic("pmap_copy_page: dst page has mappings"); 4290129198Scognet#endif 4291129198Scognet 4292129198Scognet 4293129198Scognet /* 4294129198Scognet * Clean the source page. Hold the source page's lock for 4295129198Scognet * the duration of the copy so that no other mappings can 4296129198Scognet * be created while we have a potentially aliased mapping. 4297129198Scognet */ 4298129198Scognet#if 0 4299150865Scognet /* 4300150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4301150865Scognet * pmap_copy_page(). 4302150865Scognet */ 4303129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4304150865Scognet#endif 4305129198Scognet /* 4306129198Scognet * Map the pages into the page hook points, copy them, and purge 4307129198Scognet * the cache for the appropriate page. Invalidate the TLB 4308129198Scognet * as required. 4309129198Scognet */ 4310159088Scognet mtx_lock(&cmtx); 4311129198Scognet *csrc_pte = L2_S_PROTO | src | 4312129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4313129198Scognet PTE_SYNC(csrc_pte); 4314129198Scognet *cdst_pte = L2_S_PROTO | dst | 4315129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4316129198Scognet PTE_SYNC(cdst_pte); 4317129198Scognet cpu_tlb_flushD_SE(csrcp); 4318129198Scognet cpu_tlb_flushD_SE(cdstp); 4319129198Scognet cpu_cpwait(); 4320129198Scognet bcopy_page(csrcp, cdstp); 4321159088Scognet mtx_unlock(&cmtx); 4322129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4323129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4324183838Sraj cpu_l2cache_inv_range(csrcp, PAGE_SIZE); 4325183838Sraj cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE); 4326129198Scognet} 4327129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4328129198Scognet 4329129198Scognet#if ARM_MMU_XSCALE == 1 4330129198Scognetvoid 4331129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4332129198Scognet{ 4333150865Scognet#if 0 4334150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4335129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4336150865Scognet#endif 4337129198Scognet#ifdef DEBUG 4338129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4339129198Scognet 4340129198Scognet if (dst_pg->md.pvh_list != NULL) 4341129198Scognet panic("pmap_copy_page: dst page has mappings"); 4342129198Scognet#endif 4343129198Scognet 4344129198Scognet 4345129198Scognet /* 4346129198Scognet * Clean the source page. Hold the source page's lock for 4347129198Scognet * the duration of the copy so that no other mappings can 4348129198Scognet * be created while we have a potentially aliased mapping. 4349129198Scognet */ 4350150865Scognet#if 0 4351150865Scognet /* 4352150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4353150865Scognet * pmap_copy_page(). 4354150865Scognet */ 4355130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4356150865Scognet#endif 4357129198Scognet /* 4358129198Scognet * Map the pages into the page hook points, copy them, and purge 4359129198Scognet * the cache for the appropriate page. Invalidate the TLB 4360129198Scognet * as required. 4361129198Scognet */ 4362159088Scognet mtx_lock(&cmtx); 4363129198Scognet *csrc_pte = L2_S_PROTO | src | 4364129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4365129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4366129198Scognet PTE_SYNC(csrc_pte); 4367129198Scognet *cdst_pte = L2_S_PROTO | dst | 4368129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4369129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4370129198Scognet PTE_SYNC(cdst_pte); 4371129198Scognet cpu_tlb_flushD_SE(csrcp); 4372129198Scognet cpu_tlb_flushD_SE(cdstp); 4373129198Scognet cpu_cpwait(); 4374129198Scognet bcopy_page(csrcp, cdstp); 4375159088Scognet mtx_unlock(&cmtx); 4376129198Scognet xscale_cache_clean_minidata(); 4377129198Scognet} 4378129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4379129198Scognet 4380129198Scognetvoid 4381129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4382129198Scognet{ 4383161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4384161105Scognet vm_offset_t srcpg, dstpg; 4385161105Scognet#endif 4386161105Scognet 4387146596Scognet cpu_dcache_wbinv_all(); 4388183838Sraj cpu_l2cache_wbinv_all(); 4389172300Scognet if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size && 4390150865Scognet _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4391150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4392150865Scognet return; 4393161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4394161105Scognet srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src)); 4395161105Scognet dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst)); 4396161105Scognet bcopy_page(srcpg, dstpg); 4397161105Scognet cpu_dcache_wbinv_range(dstpg, PAGE_SIZE); 4398183838Sraj cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE); 4399161105Scognet#else 4400129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4401161105Scognet#endif 4402129198Scognet} 4403129198Scognet 4404129198Scognet 4405129198Scognet 4406129198Scognet 4407129198Scognet/* 4408129198Scognet * this routine returns true if a physical page resides 4409129198Scognet * in the given pmap. 4410129198Scognet */ 4411129198Scognetboolean_t 4412129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4413129198Scognet{ 4414129198Scognet pv_entry_t pv; 4415129198Scognet int loops = 0; 4416129198Scognet 4417147217Salc if (m->flags & PG_FICTITIOUS) 4418129198Scognet return (FALSE); 4419129198Scognet 4420129198Scognet /* 4421129198Scognet * Not found, check current mappings returning immediately 4422129198Scognet */ 4423129198Scognet for (pv = TAILQ_FIRST(&m->md.pv_list); 4424129198Scognet pv; 4425129198Scognet pv = TAILQ_NEXT(pv, pv_list)) { 4426129198Scognet if (pv->pv_pmap == pmap) { 4427129198Scognet return (TRUE); 4428129198Scognet } 4429129198Scognet loops++; 4430129198Scognet if (loops >= 16) 4431129198Scognet break; 4432129198Scognet } 4433129198Scognet return (FALSE); 4434129198Scognet} 4435129198Scognet 4436173708Salc/* 4437173708Salc * pmap_page_wired_mappings: 4438173708Salc * 4439173708Salc * Return the number of managed mappings to the given physical page 4440173708Salc * that are wired. 4441173708Salc */ 4442173708Salcint 4443173708Salcpmap_page_wired_mappings(vm_page_t m) 4444173708Salc{ 4445173708Salc pv_entry_t pv; 4446173708Salc int count; 4447129198Scognet 4448173708Salc count = 0; 4449173708Salc if ((m->flags & PG_FICTITIOUS) != 0) 4450173708Salc return (count); 4451207796Salc vm_page_lock_queues(); 4452173708Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 4453173708Salc if ((pv->pv_flags & PVF_WIRED) != 0) 4454173708Salc count++; 4455207796Salc vm_page_unlock_queues(); 4456173708Salc return (count); 4457173708Salc} 4458173708Salc 4459129198Scognet/* 4460129198Scognet * pmap_ts_referenced: 4461129198Scognet * 4462129198Scognet * Return the count of reference bits for a page, clearing all of them. 4463129198Scognet */ 4464129198Scognetint 4465129198Scognetpmap_ts_referenced(vm_page_t m) 4466129198Scognet{ 4467164778Scognet 4468164779Scognet if (m->flags & PG_FICTITIOUS) 4469164779Scognet return (0); 4470135641Scognet return (pmap_clearbit(m, PVF_REF)); 4471129198Scognet} 4472129198Scognet 4473129198Scognet 4474129198Scognetboolean_t 4475129198Scognetpmap_is_modified(vm_page_t m) 4476129198Scognet{ 4477135641Scognet 4478135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4479135641Scognet return (TRUE); 4480129198Scognet 4481129198Scognet return(FALSE); 4482129198Scognet} 4483129198Scognet 4484129198Scognet 4485129198Scognet/* 4486129198Scognet * Clear the modify bits on the specified physical page. 4487129198Scognet */ 4488129198Scognetvoid 4489129198Scognetpmap_clear_modify(vm_page_t m) 4490129198Scognet{ 4491129198Scognet 4492129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4493129198Scognet pmap_clearbit(m, PVF_MOD); 4494129198Scognet} 4495129198Scognet 4496129198Scognet 4497129198Scognet/* 4498207155Salc * pmap_is_referenced: 4499207155Salc * 4500207155Salc * Return whether or not the specified physical page was referenced 4501207155Salc * in any physical maps. 4502207155Salc */ 4503207155Salcboolean_t 4504207155Salcpmap_is_referenced(vm_page_t m) 4505207155Salc{ 4506207155Salc 4507207155Salc return ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 4508207155Salc (m->md.pvh_attrs & PVF_REF) != 0); 4509207155Salc} 4510207155Salc 4511207155Salc/* 4512129198Scognet * pmap_clear_reference: 4513129198Scognet * 4514129198Scognet * Clear the reference bit on the specified physical page. 4515129198Scognet */ 4516129198Scognetvoid 4517129198Scognetpmap_clear_reference(vm_page_t m) 4518129198Scognet{ 4519129198Scognet 4520129198Scognet if (m->md.pvh_attrs & PVF_REF) 4521129198Scognet pmap_clearbit(m, PVF_REF); 4522129198Scognet} 4523129198Scognet 4524129198Scognet 4525129198Scognet/* 4526160537Salc * Clear the write and modified bits in each of the given page's mappings. 4527160537Salc */ 4528160537Salcvoid 4529160889Salcpmap_remove_write(vm_page_t m) 4530160537Salc{ 4531160537Salc 4532208175Salc KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4533208175Salc ("pmap_remove_write: page %p is not managed", m)); 4534208175Salc 4535208175Salc /* 4536208175Salc * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 4537208175Salc * another thread while the object is locked. Thus, if PG_WRITEABLE 4538208175Salc * is clear, no page table entries need updating. 4539208175Salc */ 4540208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4541208175Salc if ((m->oflags & VPO_BUSY) != 0 || 4542208175Salc (m->flags & PG_WRITEABLE) != 0) { 4543207796Salc vm_page_lock_queues(); 4544160537Salc pmap_clearbit(m, PVF_WRITE); 4545207796Salc vm_page_unlock_queues(); 4546207796Salc } 4547160537Salc} 4548160537Salc 4549160537Salc 4550160537Salc/* 4551129198Scognet * perform the pmap work for mincore 4552129198Scognet */ 4553129198Scognetint 4554129198Scognetpmap_mincore(pmap_t pmap, vm_offset_t addr) 4555129198Scognet{ 4556129198Scognet printf("pmap_mincore()\n"); 4557129198Scognet 4558129198Scognet return (0); 4559129198Scognet} 4560129198Scognet 4561129198Scognet 4562198341Smarcelvoid 4563198341Smarcelpmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4564198341Smarcel{ 4565198341Smarcel} 4566198341Smarcel 4567198341Smarcel 4568178893Salc/* 4569178893Salc * Increase the starting virtual address of the given mapping if a 4570178893Salc * different alignment might result in more superpage mappings. 4571178893Salc */ 4572178893Salcvoid 4573178893Salcpmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4574178893Salc vm_offset_t *addr, vm_size_t size) 4575178893Salc{ 4576178893Salc} 4577129198Scognet 4578178893Salc 4579129198Scognet/* 4580129198Scognet * Map a set of physical memory pages into the kernel virtual 4581129198Scognet * address space. Return a pointer to where it is mapped. This 4582129198Scognet * routine is intended to be used for mapping device memory, 4583129198Scognet * NOT real memory. 4584129198Scognet */ 4585129198Scognetvoid * 4586129198Scognetpmap_mapdev(vm_offset_t pa, vm_size_t size) 4587129198Scognet{ 4588129198Scognet vm_offset_t va, tmpva, offset; 4589129198Scognet 4590129198Scognet offset = pa & PAGE_MASK; 4591135641Scognet size = roundup(size, PAGE_SIZE); 4592129198Scognet 4593129198Scognet GIANT_REQUIRED; 4594129198Scognet 4595132560Salc va = kmem_alloc_nofault(kernel_map, size); 4596129198Scognet if (!va) 4597129198Scognet panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4598129198Scognet for (tmpva = va; size > 0;) { 4599135641Scognet pmap_kenter_internal(tmpva, pa, 0); 4600129198Scognet size -= PAGE_SIZE; 4601129198Scognet tmpva += PAGE_SIZE; 4602129198Scognet pa += PAGE_SIZE; 4603129198Scognet } 4604129198Scognet 4605159068Sbenno return ((void *)(va + offset)); 4606129198Scognet} 4607129198Scognet 4608129198Scognet#define BOOTSTRAP_DEBUG 4609129198Scognet 4610129198Scognet/* 4611129198Scognet * pmap_map_section: 4612129198Scognet * 4613129198Scognet * Create a single section mapping. 4614129198Scognet */ 4615129198Scognetvoid 4616129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4617129198Scognet int prot, int cache) 4618129198Scognet{ 4619129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4620129198Scognet pd_entry_t fl; 4621129198Scognet 4622129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4623129198Scognet 4624129198Scognet switch (cache) { 4625129198Scognet case PTE_NOCACHE: 4626129198Scognet default: 4627129198Scognet fl = 0; 4628129198Scognet break; 4629129198Scognet 4630129198Scognet case PTE_CACHE: 4631129198Scognet fl = pte_l1_s_cache_mode; 4632129198Scognet break; 4633129198Scognet 4634129198Scognet case PTE_PAGETABLE: 4635129198Scognet fl = pte_l1_s_cache_mode_pt; 4636129198Scognet break; 4637129198Scognet } 4638129198Scognet 4639129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4640129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4641129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4642129198Scognet 4643129198Scognet} 4644129198Scognet 4645129198Scognet/* 4646129198Scognet * pmap_link_l2pt: 4647129198Scognet * 4648164079Scognet * Link the L2 page table specified by l2pv.pv_pa into the L1 4649129198Scognet * page table at the slot for "va". 4650129198Scognet */ 4651129198Scognetvoid 4652129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4653129198Scognet{ 4654129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4655129198Scognet u_int slot = va >> L1_S_SHIFT; 4656129198Scognet 4657129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4658129198Scognet 4659164079Scognet#ifdef VERBOSE_INIT_ARM 4660164079Scognet printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 4661164079Scognet#endif 4662164079Scognet 4663129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4664164079Scognet 4665129198Scognet PTE_SYNC(&pde[slot]); 4666129198Scognet 4667129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4668129198Scognet 4669129198Scognet 4670129198Scognet} 4671129198Scognet 4672129198Scognet/* 4673129198Scognet * pmap_map_entry 4674129198Scognet * 4675129198Scognet * Create a single page mapping. 4676129198Scognet */ 4677129198Scognetvoid 4678129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4679129198Scognet int cache) 4680129198Scognet{ 4681129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4682129198Scognet pt_entry_t fl; 4683129198Scognet pt_entry_t *pte; 4684129198Scognet 4685129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4686129198Scognet 4687129198Scognet switch (cache) { 4688129198Scognet case PTE_NOCACHE: 4689129198Scognet default: 4690129198Scognet fl = 0; 4691129198Scognet break; 4692129198Scognet 4693129198Scognet case PTE_CACHE: 4694129198Scognet fl = pte_l2_s_cache_mode; 4695129198Scognet break; 4696129198Scognet 4697129198Scognet case PTE_PAGETABLE: 4698129198Scognet fl = pte_l2_s_cache_mode_pt; 4699129198Scognet break; 4700129198Scognet } 4701129198Scognet 4702129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4703129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4704129198Scognet 4705129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4706129198Scognet 4707129198Scognet if (pte == NULL) 4708129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4709129198Scognet 4710129198Scognet pte[l2pte_index(va)] = 4711129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4712129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4713129198Scognet} 4714129198Scognet 4715129198Scognet/* 4716129198Scognet * pmap_map_chunk: 4717129198Scognet * 4718129198Scognet * Map a chunk of memory using the most efficient mappings 4719129198Scognet * possible (section. large page, small page) into the 4720129198Scognet * provided L1 and L2 tables at the specified virtual address. 4721129198Scognet */ 4722129198Scognetvm_size_t 4723129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4724129198Scognet vm_size_t size, int prot, int cache) 4725129198Scognet{ 4726129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4727129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4728129198Scognet vm_size_t resid; 4729129198Scognet int i; 4730129198Scognet 4731129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4732129198Scognet 4733129198Scognet if (l1pt == 0) 4734129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4735129198Scognet 4736129198Scognet#ifdef VERBOSE_INIT_ARM 4737159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4738129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4739129198Scognet#endif 4740129198Scognet 4741129198Scognet switch (cache) { 4742129198Scognet case PTE_NOCACHE: 4743129198Scognet default: 4744129198Scognet f1 = 0; 4745129198Scognet f2l = 0; 4746129198Scognet f2s = 0; 4747129198Scognet break; 4748129198Scognet 4749129198Scognet case PTE_CACHE: 4750129198Scognet f1 = pte_l1_s_cache_mode; 4751129198Scognet f2l = pte_l2_l_cache_mode; 4752129198Scognet f2s = pte_l2_s_cache_mode; 4753129198Scognet break; 4754129198Scognet 4755129198Scognet case PTE_PAGETABLE: 4756129198Scognet f1 = pte_l1_s_cache_mode_pt; 4757129198Scognet f2l = pte_l2_l_cache_mode_pt; 4758129198Scognet f2s = pte_l2_s_cache_mode_pt; 4759129198Scognet break; 4760129198Scognet } 4761129198Scognet 4762129198Scognet size = resid; 4763129198Scognet 4764129198Scognet while (resid > 0) { 4765129198Scognet /* See if we can use a section mapping. */ 4766129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4767129198Scognet#ifdef VERBOSE_INIT_ARM 4768129198Scognet printf("S"); 4769129198Scognet#endif 4770129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4771129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4772129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4773129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4774129198Scognet va += L1_S_SIZE; 4775129198Scognet pa += L1_S_SIZE; 4776129198Scognet resid -= L1_S_SIZE; 4777129198Scognet continue; 4778129198Scognet } 4779129198Scognet 4780129198Scognet /* 4781129198Scognet * Ok, we're going to use an L2 table. Make sure 4782129198Scognet * one is actually in the corresponding L1 slot 4783129198Scognet * for the current VA. 4784129198Scognet */ 4785129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4786129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4787129198Scognet 4788129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4789129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4790129198Scognet if (pte == NULL) 4791129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4792129198Scognet "0x%08x", va); 4793129198Scognet /* See if we can use a L2 large page mapping. */ 4794129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4795129198Scognet#ifdef VERBOSE_INIT_ARM 4796129198Scognet printf("L"); 4797129198Scognet#endif 4798129198Scognet for (i = 0; i < 16; i++) { 4799129198Scognet pte[l2pte_index(va) + i] = 4800129198Scognet L2_L_PROTO | pa | 4801129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4802129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4803129198Scognet } 4804129198Scognet va += L2_L_SIZE; 4805129198Scognet pa += L2_L_SIZE; 4806129198Scognet resid -= L2_L_SIZE; 4807129198Scognet continue; 4808129198Scognet } 4809129198Scognet 4810129198Scognet /* Use a small page mapping. */ 4811129198Scognet#ifdef VERBOSE_INIT_ARM 4812129198Scognet printf("P"); 4813129198Scognet#endif 4814129198Scognet pte[l2pte_index(va)] = 4815129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4816129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4817129198Scognet va += PAGE_SIZE; 4818129198Scognet pa += PAGE_SIZE; 4819129198Scognet resid -= PAGE_SIZE; 4820129198Scognet } 4821129198Scognet#ifdef VERBOSE_INIT_ARM 4822129198Scognet printf("\n"); 4823129198Scognet#endif 4824129198Scognet return (size); 4825129198Scognet 4826129198Scognet} 4827129198Scognet 4828135641Scognet/********************** Static device map routines ***************************/ 4829135641Scognet 4830135641Scognetstatic const struct pmap_devmap *pmap_devmap_table; 4831135641Scognet 4832135641Scognet/* 4833135641Scognet * Register the devmap table. This is provided in case early console 4834135641Scognet * initialization needs to register mappings created by bootstrap code 4835135641Scognet * before pmap_devmap_bootstrap() is called. 4836135641Scognet */ 4837135641Scognetvoid 4838135641Scognetpmap_devmap_register(const struct pmap_devmap *table) 4839135641Scognet{ 4840135641Scognet 4841135641Scognet pmap_devmap_table = table; 4842135641Scognet} 4843135641Scognet 4844135641Scognet/* 4845135641Scognet * Map all of the static regions in the devmap table, and remember 4846135641Scognet * the devmap table so other parts of the kernel can look up entries 4847135641Scognet * later. 4848135641Scognet */ 4849135641Scognetvoid 4850135641Scognetpmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4851135641Scognet{ 4852135641Scognet int i; 4853135641Scognet 4854135641Scognet pmap_devmap_table = table; 4855135641Scognet 4856135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4857135641Scognet#ifdef VERBOSE_INIT_ARM 4858159322Scognet printf("devmap: %08x -> %08x @ %08x\n", 4859135641Scognet pmap_devmap_table[i].pd_pa, 4860135641Scognet pmap_devmap_table[i].pd_pa + 4861135641Scognet pmap_devmap_table[i].pd_size - 1, 4862135641Scognet pmap_devmap_table[i].pd_va); 4863135641Scognet#endif 4864135641Scognet pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4865135641Scognet pmap_devmap_table[i].pd_pa, 4866135641Scognet pmap_devmap_table[i].pd_size, 4867135641Scognet pmap_devmap_table[i].pd_prot, 4868135641Scognet pmap_devmap_table[i].pd_cache); 4869135641Scognet } 4870135641Scognet} 4871135641Scognet 4872135641Scognetconst struct pmap_devmap * 4873135641Scognetpmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4874135641Scognet{ 4875135641Scognet int i; 4876135641Scognet 4877135641Scognet if (pmap_devmap_table == NULL) 4878135641Scognet return (NULL); 4879135641Scognet 4880135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4881135641Scognet if (pa >= pmap_devmap_table[i].pd_pa && 4882135641Scognet pa + size <= pmap_devmap_table[i].pd_pa + 4883135641Scognet pmap_devmap_table[i].pd_size) 4884135641Scognet return (&pmap_devmap_table[i]); 4885135641Scognet } 4886135641Scognet 4887135641Scognet return (NULL); 4888135641Scognet} 4889135641Scognet 4890135641Scognetconst struct pmap_devmap * 4891135641Scognetpmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4892135641Scognet{ 4893135641Scognet int i; 4894135641Scognet 4895135641Scognet if (pmap_devmap_table == NULL) 4896135641Scognet return (NULL); 4897135641Scognet 4898135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4899135641Scognet if (va >= pmap_devmap_table[i].pd_va && 4900135641Scognet va + size <= pmap_devmap_table[i].pd_va + 4901135641Scognet pmap_devmap_table[i].pd_size) 4902135641Scognet return (&pmap_devmap_table[i]); 4903135641Scognet } 4904135641Scognet 4905135641Scognet return (NULL); 4906135641Scognet} 4907135641Scognet 4908