pmap-v4.c revision 169763
1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 3. All advertising materials mentioning features or use of this software 81129198Scognet * must display the following acknowledgement: 82129198Scognet * This product includes software developed by the NetBSD 83129198Scognet * Foundation, Inc. and its contributors. 84129198Scognet * 4. Neither the name of The NetBSD Foundation nor the names of its 85129198Scognet * contributors may be used to endorse or promote products derived 86129198Scognet * from this software without specific prior written permission. 87129198Scognet * 88129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 89129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 90129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 91129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 92129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 93129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 94129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 95129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 96129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 97129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98129198Scognet * POSSIBILITY OF SUCH DAMAGE. 99129198Scognet */ 100129198Scognet 101139735Simp/*- 102129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 103129198Scognet * Copyright (c) 1994 Brini. 104129198Scognet * All rights reserved. 105139735Simp * 106129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 107129198Scognet * 108129198Scognet * Redistribution and use in source and binary forms, with or without 109129198Scognet * modification, are permitted provided that the following conditions 110129198Scognet * are met: 111129198Scognet * 1. Redistributions of source code must retain the above copyright 112129198Scognet * notice, this list of conditions and the following disclaimer. 113129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 114129198Scognet * notice, this list of conditions and the following disclaimer in the 115129198Scognet * documentation and/or other materials provided with the distribution. 116129198Scognet * 3. All advertising materials mentioning features or use of this software 117129198Scognet * must display the following acknowledgement: 118129198Scognet * This product includes software developed by Mark Brinicombe. 119129198Scognet * 4. The name of the author may not be used to endorse or promote products 120129198Scognet * derived from this software without specific prior written permission. 121129198Scognet * 122129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 123129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 124129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 125129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 126129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 127129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 128129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 129129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 130129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 131129198Scognet * 132129198Scognet * RiscBSD kernel project 133129198Scognet * 134129198Scognet * pmap.c 135129198Scognet * 136129198Scognet * Machine dependant vm stuff 137129198Scognet * 138129198Scognet * Created : 20/09/94 139129198Scognet */ 140129198Scognet 141129198Scognet/* 142129198Scognet * Special compilation symbols 143129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 144129198Scognet */ 145129198Scognet/* Include header files */ 146135641Scognet 147137552Scognet#include "opt_vm.h" 148137552Scognet 149129198Scognet#include <sys/cdefs.h> 150129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 169763 2007-05-19 13:21:41Z cognet $"); 151129198Scognet#include <sys/param.h> 152129198Scognet#include <sys/systm.h> 153129198Scognet#include <sys/kernel.h> 154129198Scognet#include <sys/proc.h> 155129198Scognet#include <sys/malloc.h> 156129198Scognet#include <sys/msgbuf.h> 157129198Scognet#include <sys/vmmeter.h> 158129198Scognet#include <sys/mman.h> 159129198Scognet#include <sys/smp.h> 160129198Scognet#include <sys/sched.h> 161129198Scognet 162129198Scognet#include <vm/vm.h> 163129198Scognet#include <vm/uma.h> 164129198Scognet#include <vm/pmap.h> 165129198Scognet#include <vm/vm_kern.h> 166129198Scognet#include <vm/vm_object.h> 167129198Scognet#include <vm/vm_map.h> 168129198Scognet#include <vm/vm_page.h> 169129198Scognet#include <vm/vm_pageout.h> 170129198Scognet#include <vm/vm_extern.h> 171129198Scognet#include <sys/lock.h> 172129198Scognet#include <sys/mutex.h> 173129198Scognet#include <machine/md_var.h> 174129198Scognet#include <machine/vmparam.h> 175129198Scognet#include <machine/cpu.h> 176129198Scognet#include <machine/cpufunc.h> 177129198Scognet#include <machine/pcb.h> 178129198Scognet 179129198Scognet#ifdef PMAP_DEBUG 180129198Scognet#define PDEBUG(_lev_,_stat_) \ 181129198Scognet if (pmap_debug_level >= (_lev_)) \ 182129198Scognet ((_stat_)) 183129198Scognet#define dprintf printf 184129198Scognet 185129198Scognetint pmap_debug_level = 0; 186135641Scognet#define PMAP_INLINE 187129198Scognet#else /* PMAP_DEBUG */ 188129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 189129198Scognet#define dprintf(x, arg...) 190135641Scognet#define PMAP_INLINE __inline 191129198Scognet#endif /* PMAP_DEBUG */ 192129198Scognet 193129198Scognetextern struct pv_addr systempage; 194129198Scognet/* 195129198Scognet * Internal function prototypes 196129198Scognet */ 197135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 198129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 199129198Scognet 200159127Salcstatic void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 201160260Scognet vm_prot_t, boolean_t, int); 202129198Scognetstatic void pmap_vac_me_harder(struct vm_page *, pmap_t, 203129198Scognet vm_offset_t); 204129198Scognetstatic void pmap_vac_me_kpmap(struct vm_page *, pmap_t, 205129198Scognet vm_offset_t); 206129198Scognetstatic void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t); 207129198Scognetstatic void pmap_alloc_l1(pmap_t); 208129198Scognetstatic void pmap_free_l1(pmap_t); 209129198Scognetstatic void pmap_use_l1(pmap_t); 210129198Scognet 211135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 212129198Scognet 213129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 214129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 215129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 216129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 217129198Scognet 218129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 219129198Scognet 220129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 221129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 222135641Scognetvm_offset_t pmap_curmaxkvaddr; 223150865Scognetvm_paddr_t kernel_l1pa; 224129198Scognet 225129198Scognetextern void *end; 226129198Scognetvm_offset_t kernel_vm_end = 0; 227129198Scognet 228129198Scognetstruct pmap kernel_pmap_store; 229129198Scognetpmap_t kernel_pmap; 230129198Scognet 231129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 232129198Scognetstatic vm_offset_t csrcp, cdstp; 233159088Scognetstatic struct mtx cmtx; 234159088Scognet 235129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 236129198Scognet/* 237129198Scognet * These routines are called when the CPU type is identified to set up 238129198Scognet * the PTE prototypes, cache modes, etc. 239129198Scognet * 240129198Scognet * The variables are always here, just in case LKMs need to reference 241129198Scognet * them (though, they shouldn't). 242129198Scognet */ 243129198Scognet 244129198Scognetpt_entry_t pte_l1_s_cache_mode; 245129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 246129198Scognetpt_entry_t pte_l1_s_cache_mask; 247129198Scognet 248129198Scognetpt_entry_t pte_l2_l_cache_mode; 249129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 250129198Scognetpt_entry_t pte_l2_l_cache_mask; 251129198Scognet 252129198Scognetpt_entry_t pte_l2_s_cache_mode; 253129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 254129198Scognetpt_entry_t pte_l2_s_cache_mask; 255129198Scognet 256129198Scognetpt_entry_t pte_l2_s_prot_u; 257129198Scognetpt_entry_t pte_l2_s_prot_w; 258129198Scognetpt_entry_t pte_l2_s_prot_mask; 259129198Scognet 260129198Scognetpt_entry_t pte_l1_s_proto; 261129198Scognetpt_entry_t pte_l1_c_proto; 262129198Scognetpt_entry_t pte_l2_s_proto; 263129198Scognet 264129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 265129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 266129198Scognet/* 267129198Scognet * Which pmap is currently 'live' in the cache 268129198Scognet * 269129198Scognet * XXXSCW: Fix for SMP ... 270129198Scognet */ 271129198Scognetunion pmap_cache_state *pmap_cache_state; 272129198Scognet 273129198Scognet/* static pt_entry_t *msgbufmap;*/ 274129198Scognetstruct msgbuf *msgbufp = 0; 275129198Scognet 276129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 277129198Scognetextern void bzero_page(vm_offset_t); 278137362Scognet 279164079Scognetextern vm_offset_t alloc_firstaddr; 280164079Scognet 281137362Scognetchar *_tmppt; 282137362Scognet 283129198Scognet/* 284129198Scognet * Metadata for L1 translation tables. 285129198Scognet */ 286129198Scognetstruct l1_ttable { 287129198Scognet /* Entry on the L1 Table list */ 288129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 289129198Scognet 290129198Scognet /* Entry on the L1 Least Recently Used list */ 291129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 292129198Scognet 293129198Scognet /* Track how many domains are allocated from this L1 */ 294129198Scognet volatile u_int l1_domain_use_count; 295129198Scognet 296129198Scognet /* 297129198Scognet * A free-list of domain numbers for this L1. 298129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 299129198Scognet * is slow on ARM. 300129198Scognet */ 301129198Scognet u_int8_t l1_domain_first; 302129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 303129198Scognet 304129198Scognet /* Physical address of this L1 page table */ 305129198Scognet vm_paddr_t l1_physaddr; 306129198Scognet 307129198Scognet /* KVA of this L1 page table */ 308129198Scognet pd_entry_t *l1_kva; 309129198Scognet}; 310129198Scognet 311129198Scognet/* 312129198Scognet * Convert a virtual address into its L1 table index. That is, the 313129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 314129198Scognet * This is basically used to index l1->l1_kva[]. 315129198Scognet * 316129198Scognet * Each L2 descriptor table represents 1MB of VA space. 317129198Scognet */ 318129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 319129198Scognet 320129198Scognet/* 321129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 322129198Scognet * - New L1s are allocated from the HEAD. 323129198Scognet * - Freed L1s are added to the TAIl. 324129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 325129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 326129198Scognet */ 327129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 328135641Scognet/* 329135641Scognet * A list of all L1 tables 330135641Scognet */ 331135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 332129198Scognetstatic struct mtx l1_lru_lock; 333129198Scognet 334129198Scognet/* 335129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 336129198Scognet * 337129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 338129198Scognet * Reference counts are maintained for L2 descriptors so they can be 339129198Scognet * freed when empty. 340129198Scognet */ 341129198Scognetstruct l2_dtable { 342129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 343129198Scognet u_int l2_occupancy; 344129198Scognet 345129198Scognet /* List of L2 page descriptors */ 346129198Scognet struct l2_bucket { 347129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 348129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 349129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 350129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 351129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 352129198Scognet}; 353129198Scognet 354135641Scognet/* pmap_kenter_internal flags */ 355135641Scognet#define KENTER_CACHE 0x1 356142570Scognet#define KENTER_USER 0x2 357135641Scognet 358129198Scognet/* 359129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 360129198Scognet * and bucket index within the l2_dtable. 361129198Scognet */ 362129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 363129198Scognet (L2_SIZE - 1)) 364129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 365129198Scognet 366129198Scognet/* 367129198Scognet * Given a virtual address, this macro returns the 368129198Scognet * virtual address required to drop into the next L2 bucket. 369129198Scognet */ 370129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 371129198Scognet 372129198Scognet/* 373129198Scognet * L2 allocation. 374129198Scognet */ 375129198Scognet#define pmap_alloc_l2_dtable() \ 376160260Scognet (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE) 377129198Scognet#define pmap_free_l2_dtable(l2) \ 378129198Scognet uma_zfree(l2table_zone, l2) 379129198Scognet 380129198Scognet/* 381129198Scognet * We try to map the page tables write-through, if possible. However, not 382129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 383129198Scognet * the cache when we frob page tables. 384129198Scognet * 385129198Scognet * We try to evaluate this at compile time, if possible. However, it's 386129198Scognet * not always possible to do that, hence this run-time var. 387129198Scognet */ 388129198Scognetint pmap_needs_pte_sync; 389129198Scognet 390129198Scognet/* 391129198Scognet * Macro to determine if a mapping might be resident in the 392129198Scognet * instruction cache and/or TLB 393129198Scognet */ 394129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 395129198Scognet 396129198Scognet/* 397129198Scognet * Macro to determine if a mapping might be resident in the 398129198Scognet * data cache and/or TLB 399129198Scognet */ 400129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 401129198Scognet 402129198Scognet#ifndef PMAP_SHPGPERPROC 403129198Scognet#define PMAP_SHPGPERPROC 200 404129198Scognet#endif 405129198Scognet 406135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 407135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 408129198Scognetstatic uma_zone_t pvzone; 409147114Scognetuma_zone_t l2zone; 410129198Scognetstatic uma_zone_t l2table_zone; 411135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 412135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 413135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 414129198Scognetstatic struct vm_object pvzone_obj; 415129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 416129198Scognet 417129198Scognet/* 418129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 419129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 420129198Scognet * find them as necessary. 421129198Scognet * 422129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 423129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 424129198Scognet */ 425129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 426129198Scognet 427129198Scognetstatic void 428129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 429129198Scognet{ 430129198Scognet int i; 431129198Scognet 432129198Scognet l1->l1_kva = l1pt; 433129198Scognet l1->l1_domain_use_count = 0; 434169756Scognet l1->l1_domain_first = 1; 435129198Scognet 436129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 437169756Scognet l1->l1_domain_free[i] = i + 2; 438129198Scognet 439129198Scognet /* 440129198Scognet * Copy the kernel's L1 entries to each new L1. 441129198Scognet */ 442147249Scognet if (l1pt != pmap_kernel()->pm_l1->l1_kva) 443129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 444129198Scognet 445129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 446129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 447135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 448129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 449129198Scognet} 450129198Scognet 451129198Scognetstatic vm_offset_t 452129198Scognetkernel_pt_lookup(vm_paddr_t pa) 453129198Scognet{ 454129198Scognet struct pv_addr *pv; 455129198Scognet 456129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 457129198Scognet if (pv->pv_pa == pa) 458129198Scognet return (pv->pv_va); 459129198Scognet } 460129198Scognet return (0); 461129198Scognet} 462129198Scognet 463129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 464129198Scognetvoid 465129198Scognetpmap_pte_init_generic(void) 466129198Scognet{ 467129198Scognet 468129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 469129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 470129198Scognet 471129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 472129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 473129198Scognet 474129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 475129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 476129198Scognet 477129198Scognet /* 478129198Scognet * If we have a write-through cache, set B and C. If 479129198Scognet * we have a write-back cache, then we assume setting 480129198Scognet * only C will make those pages write-through. 481129198Scognet */ 482129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 483129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 484129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 485129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 486129198Scognet } else { 487129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 488129198Scognet pte_l2_l_cache_mode_pt = L2_C; 489129198Scognet pte_l2_s_cache_mode_pt = L2_C; 490129198Scognet } 491129198Scognet 492129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 493129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 494129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 495129198Scognet 496129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 497129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 498129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 499129198Scognet 500129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 501129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 502129198Scognet} 503129198Scognet 504129198Scognet#if defined(CPU_ARM8) 505129198Scognetvoid 506129198Scognetpmap_pte_init_arm8(void) 507129198Scognet{ 508129198Scognet 509129198Scognet /* 510129198Scognet * ARM8 is compatible with generic, but we need to use 511129198Scognet * the page tables uncached. 512129198Scognet */ 513129198Scognet pmap_pte_init_generic(); 514129198Scognet 515129198Scognet pte_l1_s_cache_mode_pt = 0; 516129198Scognet pte_l2_l_cache_mode_pt = 0; 517129198Scognet pte_l2_s_cache_mode_pt = 0; 518129198Scognet} 519129198Scognet#endif /* CPU_ARM8 */ 520129198Scognet 521129198Scognet#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 522129198Scognetvoid 523129198Scognetpmap_pte_init_arm9(void) 524129198Scognet{ 525129198Scognet 526129198Scognet /* 527129198Scognet * ARM9 is compatible with generic, but we want to use 528129198Scognet * write-through caching for now. 529129198Scognet */ 530129198Scognet pmap_pte_init_generic(); 531129198Scognet 532129198Scognet pte_l1_s_cache_mode = L1_S_C; 533129198Scognet pte_l2_l_cache_mode = L2_C; 534129198Scognet pte_l2_s_cache_mode = L2_C; 535129198Scognet 536129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 537129198Scognet pte_l2_l_cache_mode_pt = L2_C; 538129198Scognet pte_l2_s_cache_mode_pt = L2_C; 539129198Scognet} 540129198Scognet#endif /* CPU_ARM9 */ 541129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 542129198Scognet 543129198Scognet#if defined(CPU_ARM10) 544129198Scognetvoid 545129198Scognetpmap_pte_init_arm10(void) 546129198Scognet{ 547129198Scognet 548129198Scognet /* 549129198Scognet * ARM10 is compatible with generic, but we want to use 550129198Scognet * write-through caching for now. 551129198Scognet */ 552129198Scognet pmap_pte_init_generic(); 553129198Scognet 554129198Scognet pte_l1_s_cache_mode = L1_S_B | L1_S_C; 555129198Scognet pte_l2_l_cache_mode = L2_B | L2_C; 556129198Scognet pte_l2_s_cache_mode = L2_B | L2_C; 557129198Scognet 558129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 559129198Scognet pte_l2_l_cache_mode_pt = L2_C; 560129198Scognet pte_l2_s_cache_mode_pt = L2_C; 561129198Scognet 562129198Scognet} 563129198Scognet#endif /* CPU_ARM10 */ 564129198Scognet 565129198Scognet#if ARM_MMU_SA1 == 1 566129198Scognetvoid 567129198Scognetpmap_pte_init_sa1(void) 568129198Scognet{ 569129198Scognet 570129198Scognet /* 571129198Scognet * The StrongARM SA-1 cache does not have a write-through 572129198Scognet * mode. So, do the generic initialization, then reset 573129198Scognet * the page table cache mode to B=1,C=1, and note that 574129198Scognet * the PTEs need to be sync'd. 575129198Scognet */ 576129198Scognet pmap_pte_init_generic(); 577129198Scognet 578129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 579129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 580129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 581129198Scognet 582129198Scognet pmap_needs_pte_sync = 1; 583129198Scognet} 584129198Scognet#endif /* ARM_MMU_SA1 == 1*/ 585129198Scognet 586129198Scognet#if ARM_MMU_XSCALE == 1 587164778Scognet#if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) 588129198Scognetstatic u_int xscale_use_minidata; 589129198Scognet#endif 590129198Scognet 591129198Scognetvoid 592129198Scognetpmap_pte_init_xscale(void) 593129198Scognet{ 594129198Scognet uint32_t auxctl; 595129198Scognet int write_through = 0; 596129198Scognet 597135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 598129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 599129198Scognet 600129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 601129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 602129198Scognet 603129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 604129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 605129198Scognet 606129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 607129198Scognet pte_l2_l_cache_mode_pt = L2_C; 608129198Scognet pte_l2_s_cache_mode_pt = L2_C; 609129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 610129198Scognet /* 611129198Scognet * The XScale core has an enhanced mode where writes that 612129198Scognet * miss the cache cause a cache line to be allocated. This 613129198Scognet * is significantly faster than the traditional, write-through 614129198Scognet * behavior of this case. 615129198Scognet */ 616164778Scognet#ifndef CPU_XSCALE_CORE3 617129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 618129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 619129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 620164778Scognet#endif 621129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 622129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 623129198Scognet /* 624129198Scognet * Some versions of the XScale core have various bugs in 625129198Scognet * their cache units, the work-around for which is to run 626129198Scognet * the cache in write-through mode. Unfortunately, this 627129198Scognet * has a major (negative) impact on performance. So, we 628129198Scognet * go ahead and run fast-and-loose, in the hopes that we 629129198Scognet * don't line up the planets in a way that will trip the 630129198Scognet * bugs. 631129198Scognet * 632129198Scognet * However, we give you the option to be slow-but-correct. 633129198Scognet */ 634129198Scognet write_through = 1; 635129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 636129198Scognet /* force write back cache mode */ 637129198Scognet write_through = 0; 638129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 639129198Scognet /* 640129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 641129198Scognet * write-back cache on revision 4 and earlier (stepping 642129198Scognet * A[01] and B[012]). Fixed for C0 and later. 643129198Scognet */ 644129198Scognet { 645129198Scognet uint32_t id, type; 646129198Scognet 647129198Scognet id = cpufunc_id(); 648129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 649129198Scognet 650129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 651129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 652129198Scognet /* write through for stepping A0-1 and B0-2 */ 653129198Scognet write_through = 1; 654129198Scognet } 655129198Scognet } 656129198Scognet } 657129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 658129198Scognet 659129198Scognet if (write_through) { 660129198Scognet pte_l1_s_cache_mode = L1_S_C; 661129198Scognet pte_l2_l_cache_mode = L2_C; 662129198Scognet pte_l2_s_cache_mode = L2_C; 663129198Scognet } 664129198Scognet 665129198Scognet#if (ARM_NMMUS > 1) 666129198Scognet xscale_use_minidata = 1; 667129198Scognet#endif 668129198Scognet 669129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 670129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 671129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 672129198Scognet 673129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 674129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 675129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 676129198Scognet 677164778Scognet#ifdef CPU_XSCALE_CORE3 678164778Scognet pmap_copy_page_func = pmap_copy_page_generic; 679164778Scognet pmap_zero_page_func = pmap_zero_page_generic; 680164778Scognet xscale_use_minidata = 0; 681164778Scognet pte_l1_s_cache_mode_pt = pte_l2_l_cache_mode_pt = 682164778Scognet pte_l2_s_cache_mode_pt = 0; 683164778Scognet#else 684129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 685129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 686164778Scognet#endif 687129198Scognet 688129198Scognet /* 689129198Scognet * Disable ECC protection of page table access, for now. 690129198Scognet */ 691129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 692129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 693129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 694129198Scognet} 695129198Scognet 696129198Scognet/* 697129198Scognet * xscale_setup_minidata: 698129198Scognet * 699129198Scognet * Set up the mini-data cache clean area. We require the 700129198Scognet * caller to allocate the right amount of physically and 701129198Scognet * virtually contiguous space. 702129198Scognet */ 703129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 704129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 705129198Scognetvoid 706129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 707129198Scognet{ 708129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 709129198Scognet pt_entry_t *pte; 710129198Scognet vm_size_t size; 711129198Scognet uint32_t auxctl; 712129198Scognet 713129198Scognet xscale_minidata_clean_addr = va; 714129198Scognet 715129198Scognet /* Round it to page size. */ 716129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 717129198Scognet 718129198Scognet for (; size != 0; 719129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 720129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 721129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 722129198Scognet if (pte == NULL) 723129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 724129198Scognet "VA 0x%08x", (u_int32_t) va); 725129198Scognet pte[l2pte_index(va)] = 726129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 727129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 728129198Scognet } 729129198Scognet 730129198Scognet /* 731129198Scognet * Configure the mini-data cache for write-back with 732129198Scognet * read/write-allocate. 733129198Scognet * 734129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 735129198Scognet * make sure it contains no valid data! In order to do that, 736129198Scognet * we must issue a global data cache invalidate command! 737129198Scognet * 738129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 739129198Scognet * THIS IS VERY IMPORTANT! 740129198Scognet */ 741129198Scognet 742129198Scognet /* Invalidate data and mini-data. */ 743129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 744129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 745129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 746129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 747129198Scognet} 748129198Scognet#endif 749129198Scognet 750129198Scognet/* 751129198Scognet * Allocate an L1 translation table for the specified pmap. 752129198Scognet * This is called at pmap creation time. 753129198Scognet */ 754129198Scognetstatic void 755129198Scognetpmap_alloc_l1(pmap_t pm) 756129198Scognet{ 757129198Scognet struct l1_ttable *l1; 758129198Scognet u_int8_t domain; 759129198Scognet 760129198Scognet /* 761129198Scognet * Remove the L1 at the head of the LRU list 762129198Scognet */ 763129198Scognet mtx_lock(&l1_lru_lock); 764129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 765129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 766129198Scognet 767129198Scognet /* 768129198Scognet * Pick the first available domain number, and update 769129198Scognet * the link to the next number. 770129198Scognet */ 771129198Scognet domain = l1->l1_domain_first; 772129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 773129198Scognet 774129198Scognet /* 775129198Scognet * If there are still free domain numbers in this L1, 776129198Scognet * put it back on the TAIL of the LRU list. 777129198Scognet */ 778129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 779129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 780129198Scognet 781129198Scognet mtx_unlock(&l1_lru_lock); 782129198Scognet 783129198Scognet /* 784129198Scognet * Fix up the relevant bits in the pmap structure 785129198Scognet */ 786129198Scognet pm->pm_l1 = l1; 787129198Scognet pm->pm_domain = domain; 788129198Scognet} 789129198Scognet 790129198Scognet/* 791129198Scognet * Free an L1 translation table. 792129198Scognet * This is called at pmap destruction time. 793129198Scognet */ 794129198Scognetstatic void 795129198Scognetpmap_free_l1(pmap_t pm) 796129198Scognet{ 797129198Scognet struct l1_ttable *l1 = pm->pm_l1; 798129198Scognet 799129198Scognet mtx_lock(&l1_lru_lock); 800129198Scognet 801129198Scognet /* 802129198Scognet * If this L1 is currently on the LRU list, remove it. 803129198Scognet */ 804129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 805129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 806129198Scognet 807129198Scognet /* 808129198Scognet * Free up the domain number which was allocated to the pmap 809129198Scognet */ 810129198Scognet l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 811129198Scognet l1->l1_domain_first = pm->pm_domain; 812129198Scognet l1->l1_domain_use_count--; 813129198Scognet 814129198Scognet /* 815129198Scognet * The L1 now must have at least 1 free domain, so add 816129198Scognet * it back to the LRU list. If the use count is zero, 817129198Scognet * put it at the head of the list, otherwise it goes 818129198Scognet * to the tail. 819129198Scognet */ 820129198Scognet if (l1->l1_domain_use_count == 0) { 821129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 822129198Scognet } else 823129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 824129198Scognet 825129198Scognet mtx_unlock(&l1_lru_lock); 826129198Scognet} 827129198Scognet 828129198Scognetstatic PMAP_INLINE void 829129198Scognetpmap_use_l1(pmap_t pm) 830129198Scognet{ 831129198Scognet struct l1_ttable *l1; 832129198Scognet 833129198Scognet /* 834129198Scognet * Do nothing if we're in interrupt context. 835129198Scognet * Access to an L1 by the kernel pmap must not affect 836129198Scognet * the LRU list. 837129198Scognet */ 838129198Scognet if (pm == pmap_kernel()) 839129198Scognet return; 840129198Scognet 841129198Scognet l1 = pm->pm_l1; 842129198Scognet 843129198Scognet /* 844129198Scognet * If the L1 is not currently on the LRU list, just return 845129198Scognet */ 846129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) 847129198Scognet return; 848129198Scognet 849129198Scognet mtx_lock(&l1_lru_lock); 850129198Scognet 851129198Scognet /* 852129198Scognet * Check the use count again, now that we've acquired the lock 853129198Scognet */ 854129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) { 855129198Scognet mtx_unlock(&l1_lru_lock); 856129198Scognet return; 857129198Scognet } 858129198Scognet 859129198Scognet /* 860129198Scognet * Move the L1 to the back of the LRU list 861129198Scognet */ 862129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 863129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 864129198Scognet 865129198Scognet mtx_unlock(&l1_lru_lock); 866129198Scognet} 867129198Scognet 868129198Scognet 869129198Scognet/* 870129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 871129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 872129198Scognet */ 873129198Scognetstatic PMAP_INLINE struct l2_bucket * 874129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 875129198Scognet{ 876129198Scognet struct l2_dtable *l2; 877129198Scognet struct l2_bucket *l2b; 878129198Scognet u_short l1idx; 879129198Scognet 880129198Scognet l1idx = L1_IDX(va); 881129198Scognet 882129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 883129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 884129198Scognet return (NULL); 885129198Scognet 886129198Scognet return (l2b); 887129198Scognet} 888129198Scognet 889129198Scognet/* 890129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 891129198Scognet * and VA. 892129198Scognet * 893129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 894129198Scognet * bucket/page table in place. 895129198Scognet * 896129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 897129198Scognet * increment the bucket occupancy counter appropriately *before* 898129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 899129198Scognet * the bucket/page in the meantime. 900129198Scognet */ 901129198Scognetstatic struct l2_bucket * 902129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 903129198Scognet{ 904129198Scognet struct l2_dtable *l2; 905129198Scognet struct l2_bucket *l2b; 906129198Scognet u_short l1idx; 907129198Scognet 908129198Scognet l1idx = L1_IDX(va); 909129198Scognet 910159352Salc PMAP_ASSERT_LOCKED(pm); 911159108Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 912129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 913129198Scognet /* 914129198Scognet * No mapping at this address, as there is 915129198Scognet * no entry in the L1 table. 916129198Scognet * Need to allocate a new l2_dtable. 917129198Scognet */ 918159108Scognetagain_l2table: 919159352Salc PMAP_UNLOCK(pm); 920159108Scognet vm_page_unlock_queues(); 921129198Scognet if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 922159108Scognet vm_page_lock_queues(); 923159352Salc PMAP_LOCK(pm); 924129198Scognet return (NULL); 925129198Scognet } 926159108Scognet vm_page_lock_queues(); 927159352Salc PMAP_LOCK(pm); 928159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 929159352Salc PMAP_UNLOCK(pm); 930159108Scognet vm_page_unlock_queues(); 931159108Scognet uma_zfree(l2table_zone, l2); 932159108Scognet vm_page_lock_queues(); 933159352Salc PMAP_LOCK(pm); 934159108Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 935159108Scognet if (l2 == NULL) 936159108Scognet goto again_l2table; 937159108Scognet /* 938159108Scognet * Someone already allocated the l2_dtable while 939159108Scognet * we were doing the same. 940159108Scognet */ 941159108Scognet } else { 942159108Scognet bzero(l2, sizeof(*l2)); 943159108Scognet /* 944159108Scognet * Link it into the parent pmap 945159108Scognet */ 946159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 947159108Scognet } 948129198Scognet } 949129198Scognet 950129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 951129198Scognet 952129198Scognet /* 953129198Scognet * Fetch pointer to the L2 page table associated with the address. 954129198Scognet */ 955129198Scognet if (l2b->l2b_kva == NULL) { 956129198Scognet pt_entry_t *ptep; 957129198Scognet 958129198Scognet /* 959129198Scognet * No L2 page table has been allocated. Chances are, this 960129198Scognet * is because we just allocated the l2_dtable, above. 961129198Scognet */ 962159108Scognetagain_ptep: 963159352Salc PMAP_UNLOCK(pm); 964159108Scognet vm_page_unlock_queues(); 965160260Scognet ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE); 966159108Scognet vm_page_lock_queues(); 967159352Salc PMAP_LOCK(pm); 968159108Scognet if (l2b->l2b_kva != 0) { 969159108Scognet /* We lost the race. */ 970159352Salc PMAP_UNLOCK(pm); 971159108Scognet vm_page_unlock_queues(); 972159108Scognet uma_zfree(l2zone, ptep); 973159108Scognet vm_page_lock_queues(); 974159352Salc PMAP_LOCK(pm); 975159108Scognet if (l2b->l2b_kva == 0) 976159108Scognet goto again_ptep; 977159108Scognet return (l2b); 978159108Scognet } 979129198Scognet l2b->l2b_phys = vtophys(ptep); 980129198Scognet if (ptep == NULL) { 981129198Scognet /* 982129198Scognet * Oops, no more L2 page tables available at this 983129198Scognet * time. We may need to deallocate the l2_dtable 984129198Scognet * if we allocated a new one above. 985129198Scognet */ 986129198Scognet if (l2->l2_occupancy == 0) { 987129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 988129198Scognet pmap_free_l2_dtable(l2); 989129198Scognet } 990129198Scognet return (NULL); 991129198Scognet } 992129198Scognet 993129198Scognet l2->l2_occupancy++; 994129198Scognet l2b->l2b_kva = ptep; 995129198Scognet l2b->l2b_l1idx = l1idx; 996129198Scognet } 997129198Scognet 998129198Scognet return (l2b); 999129198Scognet} 1000129198Scognet 1001129198Scognetstatic PMAP_INLINE void 1002129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1003129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 1004129198Scognet#else 1005129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 1006129198Scognet#endif 1007129198Scognet{ 1008129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1009129198Scognet /* 1010129198Scognet * Note: With a write-back cache, we may need to sync this 1011129198Scognet * L2 table before re-using it. 1012129198Scognet * This is because it may have belonged to a non-current 1013129198Scognet * pmap, in which case the cache syncs would have been 1014129198Scognet * skipped when the pages were being unmapped. If the 1015129198Scognet * L2 table were then to be immediately re-allocated to 1016129198Scognet * the *current* pmap, it may well contain stale mappings 1017129198Scognet * which have not yet been cleared by a cache write-back 1018129198Scognet * and so would still be visible to the mmu. 1019129198Scognet */ 1020129198Scognet if (need_sync) 1021129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1022129198Scognet#endif 1023129198Scognet uma_zfree(l2zone, l2); 1024129198Scognet} 1025129198Scognet/* 1026129198Scognet * One or more mappings in the specified L2 descriptor table have just been 1027129198Scognet * invalidated. 1028129198Scognet * 1029129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 1030129198Scognet * 1031129198Scognet * The pmap lock must be acquired when this is called (not necessary 1032129198Scognet * for the kernel pmap). 1033129198Scognet */ 1034129198Scognetstatic void 1035129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1036129198Scognet{ 1037129198Scognet struct l2_dtable *l2; 1038129198Scognet pd_entry_t *pl1pd, l1pd; 1039129198Scognet pt_entry_t *ptep; 1040129198Scognet u_short l1idx; 1041129198Scognet 1042129198Scognet 1043129198Scognet /* 1044129198Scognet * Update the bucket's reference count according to how many 1045129198Scognet * PTEs the caller has just invalidated. 1046129198Scognet */ 1047129198Scognet l2b->l2b_occupancy -= count; 1048129198Scognet 1049129198Scognet /* 1050129198Scognet * Note: 1051129198Scognet * 1052129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 1053129198Scognet * as that would require checking all Level 1 page tables and 1054129198Scognet * removing any references to the Level 2 page table. See also the 1055129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 1056129198Scognet * 1057129198Scognet * We make do with just invalidating the mapping in the L2 table. 1058129198Scognet * 1059129198Scognet * This isn't really a big deal in practice and, in fact, leads 1060129198Scognet * to a performance win over time as we don't need to continually 1061129198Scognet * alloc/free. 1062129198Scognet */ 1063129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1064129198Scognet return; 1065129198Scognet 1066129198Scognet /* 1067129198Scognet * There are no more valid mappings in this level 2 page table. 1068129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 1069129198Scognet * free the page table. 1070129198Scognet */ 1071129198Scognet l1idx = l2b->l2b_l1idx; 1072129198Scognet ptep = l2b->l2b_kva; 1073129198Scognet l2b->l2b_kva = NULL; 1074129198Scognet 1075129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1076129198Scognet 1077129198Scognet /* 1078129198Scognet * If the L1 slot matches the pmap's domain 1079129198Scognet * number, then invalidate it. 1080129198Scognet */ 1081129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1082129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1083129198Scognet *pl1pd = 0; 1084129198Scognet PTE_SYNC(pl1pd); 1085129198Scognet } 1086129198Scognet 1087129198Scognet /* 1088129198Scognet * Release the L2 descriptor table back to the pool cache. 1089129198Scognet */ 1090129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1091129198Scognet pmap_free_l2_ptp(ptep); 1092129198Scognet#else 1093135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1094129198Scognet#endif 1095129198Scognet 1096129198Scognet /* 1097129198Scognet * Update the reference count in the associated l2_dtable 1098129198Scognet */ 1099129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1100129198Scognet if (--l2->l2_occupancy > 0) 1101129198Scognet return; 1102129198Scognet 1103129198Scognet /* 1104129198Scognet * There are no more valid mappings in any of the Level 1 1105129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 1106129198Scognet * the pointer in the parent pmap and free the l2_dtable. 1107129198Scognet */ 1108129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 1109129198Scognet pmap_free_l2_dtable(l2); 1110129198Scognet} 1111129198Scognet 1112129198Scognet/* 1113129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 1114129198Scognet * structures. 1115129198Scognet */ 1116133237Scognetstatic int 1117133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1118129198Scognet{ 1119129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1120129198Scognet struct l2_bucket *l2b; 1121129198Scognet pt_entry_t *ptep, pte; 1122147417Scognet#ifdef ARM_USE_SMALL_ALLOC 1123147417Scognet pd_entry_t *pde; 1124147417Scognet#endif 1125129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1126129198Scognet 1127129198Scognet /* 1128129198Scognet * The mappings for these page tables were initially made using 1129135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1130129198Scognet * mode will not be right for page table mappings. To avoid 1131135641Scognet * polluting the pmap_kenter() code with a special case for 1132129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1133129198Scognet * correct. 1134129198Scognet */ 1135147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1136147417Scognet pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)]; 1137147417Scognet if (!l1pte_section_p(*pde)) { 1138147114Scognet#endif 1139147114Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1140147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1141147114Scognet pte = *ptep; 1142161105Scognet 1143147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1144147114Scognet /* 1145147114Scognet * Page tables must have the cache-mode set to 1146147114Scognet * Write-Thru. 1147147114Scognet */ 1148147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1149147114Scognet PTE_SYNC(ptep); 1150147114Scognet cpu_tlb_flushD_SE(va); 1151147114Scognet cpu_cpwait(); 1152147114Scognet } 1153147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1154129198Scognet } 1155129198Scognet#endif 1156147114Scognet#endif 1157129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1158129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1159133237Scognet return (0); 1160129198Scognet} 1161129198Scognet 1162129198Scognet/* 1163129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1164129198Scognet * on whether the specified pmap actually needs to be flushed at any 1165129198Scognet * given time. 1166129198Scognet */ 1167129198Scognetstatic PMAP_INLINE void 1168129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1169129198Scognet{ 1170129198Scognet 1171135641Scognet if (pmap_is_current(pm)) 1172129198Scognet cpu_tlb_flushID_SE(va); 1173129198Scognet} 1174129198Scognet 1175129198Scognetstatic PMAP_INLINE void 1176129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1177129198Scognet{ 1178129198Scognet 1179135641Scognet if (pmap_is_current(pm)) 1180129198Scognet cpu_tlb_flushD_SE(va); 1181129198Scognet} 1182129198Scognet 1183129198Scognetstatic PMAP_INLINE void 1184129198Scognetpmap_tlb_flushID(pmap_t pm) 1185129198Scognet{ 1186129198Scognet 1187135641Scognet if (pmap_is_current(pm)) 1188129198Scognet cpu_tlb_flushID(); 1189129198Scognet} 1190129198Scognetstatic PMAP_INLINE void 1191129198Scognetpmap_tlb_flushD(pmap_t pm) 1192129198Scognet{ 1193129198Scognet 1194135641Scognet if (pmap_is_current(pm)) 1195129198Scognet cpu_tlb_flushD(); 1196129198Scognet} 1197129198Scognet 1198129198Scognetstatic PMAP_INLINE void 1199129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1200129198Scognet{ 1201129198Scognet 1202135641Scognet if (pmap_is_current(pm)) 1203129198Scognet cpu_idcache_wbinv_range(va, len); 1204129198Scognet} 1205129198Scognet 1206129198Scognetstatic PMAP_INLINE void 1207129198Scognetpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, 1208129198Scognet boolean_t do_inv, boolean_t rd_only) 1209129198Scognet{ 1210129198Scognet 1211135641Scognet if (pmap_is_current(pm)) { 1212129198Scognet if (do_inv) { 1213129198Scognet if (rd_only) 1214129198Scognet cpu_dcache_inv_range(va, len); 1215129198Scognet else 1216129198Scognet cpu_dcache_wbinv_range(va, len); 1217129198Scognet } else 1218129198Scognet if (!rd_only) 1219129198Scognet cpu_dcache_wb_range(va, len); 1220129198Scognet } 1221129198Scognet} 1222129198Scognet 1223129198Scognetstatic PMAP_INLINE void 1224129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1225129198Scognet{ 1226129198Scognet 1227135641Scognet if (pmap_is_current(pm)) 1228129198Scognet cpu_idcache_wbinv_all(); 1229129198Scognet} 1230129198Scognet 1231129198Scognetstatic PMAP_INLINE void 1232129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1233129198Scognet{ 1234129198Scognet 1235135641Scognet if (pmap_is_current(pm)) 1236129198Scognet cpu_dcache_wbinv_all(); 1237129198Scognet} 1238129198Scognet 1239129198Scognet/* 1240129198Scognet * PTE_SYNC_CURRENT: 1241129198Scognet * 1242129198Scognet * Make sure the pte is written out to RAM. 1243129198Scognet * We need to do this for one of two cases: 1244129198Scognet * - We're dealing with the kernel pmap 1245129198Scognet * - There is no pmap active in the cache/tlb. 1246129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1247129198Scognet */ 1248129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1249129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1250129198Scognetdo { \ 1251129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1252135641Scognet pmap_is_current(pm)) \ 1253129198Scognet PTE_SYNC(ptep); \ 1254129198Scognet} while (/*CONSTCOND*/0) 1255129198Scognet#else 1256129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1257129198Scognet#endif 1258129198Scognet 1259129198Scognet/* 1260129198Scognet * Since we have a virtually indexed cache, we may need to inhibit caching if 1261129198Scognet * there is more than one mapping and at least one of them is writable. 1262129198Scognet * Since we purge the cache on every context switch, we only need to check for 1263129198Scognet * other mappings within the same pmap, or kernel_pmap. 1264129198Scognet * This function is also called when a page is unmapped, to possibly reenable 1265129198Scognet * caching on any remaining mappings. 1266129198Scognet * 1267129198Scognet * The code implements the following logic, where: 1268129198Scognet * 1269129198Scognet * KW = # of kernel read/write pages 1270129198Scognet * KR = # of kernel read only pages 1271129198Scognet * UW = # of user read/write pages 1272129198Scognet * UR = # of user read only pages 1273129198Scognet * 1274129198Scognet * KC = kernel mapping is cacheable 1275129198Scognet * UC = user mapping is cacheable 1276129198Scognet * 1277129198Scognet * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1278129198Scognet * +--------------------------------------------- 1279129198Scognet * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1280129198Scognet * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1281129198Scognet * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1282129198Scognet * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1283129198Scognet */ 1284129198Scognet 1285129198Scognetstatic const int pmap_vac_flags[4][4] = { 1286129198Scognet {-1, 0, 0, PVF_KNC}, 1287129198Scognet {0, 0, PVF_NC, PVF_NC}, 1288129198Scognet {0, PVF_NC, PVF_NC, PVF_NC}, 1289129198Scognet {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1290129198Scognet}; 1291129198Scognet 1292129198Scognetstatic PMAP_INLINE int 1293129198Scognetpmap_get_vac_flags(const struct vm_page *pg) 1294129198Scognet{ 1295129198Scognet int kidx, uidx; 1296129198Scognet 1297129198Scognet kidx = 0; 1298129198Scognet if (pg->md.kro_mappings || pg->md.krw_mappings > 1) 1299129198Scognet kidx |= 1; 1300129198Scognet if (pg->md.krw_mappings) 1301129198Scognet kidx |= 2; 1302129198Scognet 1303129198Scognet uidx = 0; 1304129198Scognet if (pg->md.uro_mappings || pg->md.urw_mappings > 1) 1305129198Scognet uidx |= 1; 1306129198Scognet if (pg->md.urw_mappings) 1307129198Scognet uidx |= 2; 1308129198Scognet 1309129198Scognet return (pmap_vac_flags[uidx][kidx]); 1310129198Scognet} 1311129198Scognet 1312129198Scognetstatic __inline void 1313129198Scognetpmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1314129198Scognet{ 1315129198Scognet int nattr; 1316129198Scognet 1317159384Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1318129198Scognet nattr = pmap_get_vac_flags(pg); 1319129198Scognet 1320129198Scognet if (nattr < 0) { 1321129198Scognet pg->md.pvh_attrs &= ~PVF_NC; 1322129198Scognet return; 1323129198Scognet } 1324129198Scognet 1325129198Scognet if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) { 1326129198Scognet return; 1327129198Scognet } 1328129198Scognet 1329129198Scognet if (pm == pmap_kernel()) 1330129198Scognet pmap_vac_me_kpmap(pg, pm, va); 1331129198Scognet else 1332129198Scognet pmap_vac_me_user(pg, pm, va); 1333129198Scognet 1334129198Scognet pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr; 1335129198Scognet} 1336129198Scognet 1337129198Scognetstatic void 1338129198Scognetpmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1339129198Scognet{ 1340129198Scognet u_int u_cacheable, u_entries; 1341129198Scognet struct pv_entry *pv; 1342129198Scognet pmap_t last_pmap = pm; 1343129198Scognet 1344129198Scognet /* 1345129198Scognet * Pass one, see if there are both kernel and user pmaps for 1346129198Scognet * this page. Calculate whether there are user-writable or 1347129198Scognet * kernel-writable pages. 1348129198Scognet */ 1349129198Scognet u_cacheable = 0; 1350129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1351129198Scognet if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1352129198Scognet u_cacheable++; 1353129198Scognet } 1354129198Scognet 1355129198Scognet u_entries = pg->md.urw_mappings + pg->md.uro_mappings; 1356129198Scognet 1357129198Scognet /* 1358129198Scognet * We know we have just been updating a kernel entry, so if 1359129198Scognet * all user pages are already cacheable, then there is nothing 1360129198Scognet * further to do. 1361129198Scognet */ 1362129198Scognet if (pg->md.k_mappings == 0 && u_cacheable == u_entries) 1363129198Scognet return; 1364129198Scognet 1365129198Scognet if (u_entries) { 1366129198Scognet /* 1367129198Scognet * Scan over the list again, for each entry, if it 1368129198Scognet * might not be set correctly, call pmap_vac_me_user 1369129198Scognet * to recalculate the settings. 1370129198Scognet */ 1371129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1372129198Scognet /* 1373129198Scognet * We know kernel mappings will get set 1374129198Scognet * correctly in other calls. We also know 1375129198Scognet * that if the pmap is the same as last_pmap 1376129198Scognet * then we've just handled this entry. 1377129198Scognet */ 1378129198Scognet if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1379129198Scognet continue; 1380129198Scognet 1381129198Scognet /* 1382129198Scognet * If there are kernel entries and this page 1383129198Scognet * is writable but non-cacheable, then we can 1384129198Scognet * skip this entry also. 1385129198Scognet */ 1386129198Scognet if (pg->md.k_mappings && 1387129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1388129198Scognet (PVF_NC | PVF_WRITE)) 1389129198Scognet continue; 1390129198Scognet 1391129198Scognet /* 1392129198Scognet * Similarly if there are no kernel-writable 1393129198Scognet * entries and the page is already 1394129198Scognet * read-only/cacheable. 1395129198Scognet */ 1396129198Scognet if (pg->md.krw_mappings == 0 && 1397129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1398129198Scognet continue; 1399129198Scognet 1400129198Scognet /* 1401129198Scognet * For some of the remaining cases, we know 1402129198Scognet * that we must recalculate, but for others we 1403129198Scognet * can't tell if they are correct or not, so 1404129198Scognet * we recalculate anyway. 1405129198Scognet */ 1406129198Scognet pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1407129198Scognet } 1408129198Scognet 1409129198Scognet if (pg->md.k_mappings == 0) 1410129198Scognet return; 1411129198Scognet } 1412129198Scognet 1413129198Scognet pmap_vac_me_user(pg, pm, va); 1414129198Scognet} 1415129198Scognet 1416129198Scognetstatic void 1417129198Scognetpmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1418129198Scognet{ 1419129198Scognet pmap_t kpmap = pmap_kernel(); 1420129198Scognet struct pv_entry *pv, *npv; 1421129198Scognet struct l2_bucket *l2b; 1422129198Scognet pt_entry_t *ptep, pte; 1423129198Scognet u_int entries = 0; 1424129198Scognet u_int writable = 0; 1425129198Scognet u_int cacheable_entries = 0; 1426129198Scognet u_int kern_cacheable = 0; 1427129198Scognet u_int other_writable = 0; 1428129198Scognet 1429129198Scognet /* 1430129198Scognet * Count mappings and writable mappings in this pmap. 1431129198Scognet * Include kernel mappings as part of our own. 1432129198Scognet * Keep a pointer to the first one. 1433129198Scognet */ 1434129198Scognet npv = TAILQ_FIRST(&pg->md.pv_list); 1435129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1436129198Scognet /* Count mappings in the same pmap */ 1437129198Scognet if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1438129198Scognet if (entries++ == 0) 1439129198Scognet npv = pv; 1440129198Scognet 1441129198Scognet /* Cacheable mappings */ 1442129198Scognet if ((pv->pv_flags & PVF_NC) == 0) { 1443129198Scognet cacheable_entries++; 1444129198Scognet if (kpmap == pv->pv_pmap) 1445129198Scognet kern_cacheable++; 1446129198Scognet } 1447129198Scognet 1448129198Scognet /* Writable mappings */ 1449129198Scognet if (pv->pv_flags & PVF_WRITE) 1450129198Scognet ++writable; 1451129198Scognet } else 1452129198Scognet if (pv->pv_flags & PVF_WRITE) 1453129198Scognet other_writable = 1; 1454129198Scognet } 1455129198Scognet 1456129198Scognet /* 1457129198Scognet * Enable or disable caching as necessary. 1458129198Scognet * Note: the first entry might be part of the kernel pmap, 1459129198Scognet * so we can't assume this is indicative of the state of the 1460129198Scognet * other (maybe non-kpmap) entries. 1461129198Scognet */ 1462129198Scognet if ((entries > 1 && writable) || 1463129198Scognet (entries > 0 && pm == kpmap && other_writable)) { 1464129198Scognet if (cacheable_entries == 0) 1465129198Scognet return; 1466129198Scognet 1467129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1468129198Scognet if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1469129198Scognet (pv->pv_flags & PVF_NC)) 1470129198Scognet continue; 1471129198Scognet 1472129198Scognet pv->pv_flags |= PVF_NC; 1473129198Scognet 1474129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1475129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1476129198Scognet pte = *ptep & ~L2_S_CACHE_MASK; 1477129198Scognet 1478129198Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1479129198Scognet l2pte_valid(pte)) { 1480129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1481129198Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1482129198Scognet pv->pv_va, PAGE_SIZE); 1483129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1484129198Scognet pv->pv_va); 1485129198Scognet } else 1486129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1487129198Scognet pmap_dcache_wb_range(pv->pv_pmap, 1488129198Scognet pv->pv_va, PAGE_SIZE, TRUE, 1489129198Scognet (pv->pv_flags & PVF_WRITE) == 0); 1490129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1491129198Scognet pv->pv_va); 1492129198Scognet } 1493129198Scognet } 1494129198Scognet 1495129198Scognet *ptep = pte; 1496129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1497129198Scognet } 1498129198Scognet cpu_cpwait(); 1499129198Scognet } else 1500129198Scognet if (entries > cacheable_entries) { 1501129198Scognet /* 1502129198Scognet * Turn cacheing back on for some pages. If it is a kernel 1503129198Scognet * page, only do so if there are no other writable pages. 1504129198Scognet */ 1505129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1506129198Scognet if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1507129198Scognet (kpmap != pv->pv_pmap || other_writable))) 1508129198Scognet continue; 1509129198Scognet 1510129198Scognet pv->pv_flags &= ~PVF_NC; 1511129198Scognet 1512129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1513129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1514129198Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1515129198Scognet 1516129198Scognet if (l2pte_valid(pte)) { 1517129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1518129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1519129198Scognet pv->pv_va); 1520129198Scognet } else 1521129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1522129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1523129198Scognet pv->pv_va); 1524129198Scognet } 1525129198Scognet } 1526129198Scognet 1527129198Scognet *ptep = pte; 1528129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1529129198Scognet } 1530129198Scognet } 1531129198Scognet} 1532129198Scognet 1533129198Scognet/* 1534129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1535129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1536129198Scognet * constants and the latter would require an extra inversion at run-time. 1537129198Scognet */ 1538135641Scognetstatic int 1539129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1540129198Scognet{ 1541129198Scognet struct l2_bucket *l2b; 1542129198Scognet struct pv_entry *pv; 1543129198Scognet pt_entry_t *ptep, npte, opte; 1544129198Scognet pmap_t pm; 1545129198Scognet vm_offset_t va; 1546129198Scognet u_int oflags; 1547135641Scognet int count = 0; 1548129198Scognet 1549159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1550159352Salc 1551129198Scognet /* 1552129198Scognet * Clear saved attributes (modify, reference) 1553129198Scognet */ 1554129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1555129198Scognet 1556129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1557135641Scognet return (0); 1558129198Scognet } 1559129198Scognet 1560129198Scognet /* 1561129198Scognet * Loop over all current mappings setting/clearing as appropos 1562129198Scognet */ 1563129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1564129198Scognet va = pv->pv_va; 1565129198Scognet pm = pv->pv_pmap; 1566129198Scognet oflags = pv->pv_flags; 1567129198Scognet pv->pv_flags &= ~maskbits; 1568129198Scognet 1569159352Salc PMAP_LOCK(pm); 1570129198Scognet 1571129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1572129198Scognet 1573129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1574129198Scognet npte = opte = *ptep; 1575129198Scognet 1576157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1577129198Scognet if ((pv->pv_flags & PVF_NC)) { 1578129198Scognet /* 1579129198Scognet * Entry is not cacheable: 1580129198Scognet * 1581129198Scognet * Don't turn caching on again if this is a 1582129198Scognet * modified emulation. This would be 1583129198Scognet * inconsitent with the settings created by 1584129198Scognet * pmap_vac_me_harder(). Otherwise, it's safe 1585129198Scognet * to re-enable cacheing. 1586129198Scognet * 1587129198Scognet * There's no need to call pmap_vac_me_harder() 1588129198Scognet * here: all pages are losing their write 1589129198Scognet * permission. 1590129198Scognet */ 1591129198Scognet if (maskbits & PVF_WRITE) { 1592129198Scognet npte |= pte_l2_s_cache_mode; 1593129198Scognet pv->pv_flags &= ~PVF_NC; 1594129198Scognet } 1595129198Scognet } else 1596129198Scognet if (opte & L2_S_PROT_W) { 1597144760Scognet vm_page_dirty(pg); 1598129198Scognet /* 1599129198Scognet * Entry is writable/cacheable: check if pmap 1600129198Scognet * is current if it is flush it, otherwise it 1601129198Scognet * won't be in the cache 1602129198Scognet */ 1603129198Scognet if (PV_BEEN_EXECD(oflags)) 1604129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1605129198Scognet PAGE_SIZE); 1606129198Scognet else 1607129198Scognet if (PV_BEEN_REFD(oflags)) 1608129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1609129198Scognet PAGE_SIZE, 1610129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1611129198Scognet FALSE); 1612129198Scognet } 1613129198Scognet 1614129198Scognet /* make the pte read only */ 1615129198Scognet npte &= ~L2_S_PROT_W; 1616129198Scognet 1617129198Scognet if (maskbits & PVF_WRITE) { 1618129198Scognet /* 1619129198Scognet * Keep alias accounting up to date 1620129198Scognet */ 1621129198Scognet if (pv->pv_pmap == pmap_kernel()) { 1622129198Scognet if (oflags & PVF_WRITE) { 1623129198Scognet pg->md.krw_mappings--; 1624129198Scognet pg->md.kro_mappings++; 1625129198Scognet } 1626129198Scognet } else 1627129198Scognet if (oflags & PVF_WRITE) { 1628129198Scognet pg->md.urw_mappings--; 1629129198Scognet pg->md.uro_mappings++; 1630129198Scognet } 1631129198Scognet } 1632129198Scognet } 1633129198Scognet 1634157970Scognet if (maskbits & PVF_REF) { 1635129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1636129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1637129198Scognet /* 1638129198Scognet * Check npte here; we may have already 1639129198Scognet * done the wbinv above, and the validity 1640129198Scognet * of the PTE is the same for opte and 1641129198Scognet * npte. 1642129198Scognet */ 1643129198Scognet if (npte & L2_S_PROT_W) { 1644129198Scognet if (PV_BEEN_EXECD(oflags)) 1645129198Scognet pmap_idcache_wbinv_range(pm, 1646129198Scognet pv->pv_va, PAGE_SIZE); 1647129198Scognet else 1648129198Scognet if (PV_BEEN_REFD(oflags)) 1649129198Scognet pmap_dcache_wb_range(pm, 1650129198Scognet pv->pv_va, PAGE_SIZE, 1651129198Scognet TRUE, FALSE); 1652129198Scognet } else 1653129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1654129198Scognet /* XXXJRT need idcache_inv_range */ 1655129198Scognet if (PV_BEEN_EXECD(oflags)) 1656129198Scognet pmap_idcache_wbinv_range(pm, 1657129198Scognet pv->pv_va, PAGE_SIZE); 1658129198Scognet else 1659129198Scognet if (PV_BEEN_REFD(oflags)) 1660129198Scognet pmap_dcache_wb_range(pm, 1661129198Scognet pv->pv_va, PAGE_SIZE, 1662129198Scognet TRUE, TRUE); 1663129198Scognet } 1664129198Scognet } 1665129198Scognet 1666129198Scognet /* 1667129198Scognet * Make the PTE invalid so that we will take a 1668129198Scognet * page fault the next time the mapping is 1669129198Scognet * referenced. 1670129198Scognet */ 1671129198Scognet npte &= ~L2_TYPE_MASK; 1672129198Scognet npte |= L2_TYPE_INV; 1673129198Scognet } 1674129198Scognet 1675129198Scognet if (npte != opte) { 1676135641Scognet count++; 1677129198Scognet *ptep = npte; 1678129198Scognet PTE_SYNC(ptep); 1679129198Scognet /* Flush the TLB entry if a current pmap. */ 1680129198Scognet if (PV_BEEN_EXECD(oflags)) 1681129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1682129198Scognet else 1683129198Scognet if (PV_BEEN_REFD(oflags)) 1684129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1685129198Scognet } 1686129198Scognet 1687159352Salc PMAP_UNLOCK(pm); 1688129198Scognet 1689129198Scognet } 1690129198Scognet 1691137664Scognet if (maskbits & PVF_WRITE) 1692137664Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1693135641Scognet return (count); 1694129198Scognet} 1695129198Scognet 1696129198Scognet/* 1697129198Scognet * main pv_entry manipulation functions: 1698129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1699129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1700129198Scognet * 1701129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1702129198Scognet * pmap_remove_pv expects te caller to lock the pvh before calling 1703129198Scognet */ 1704129198Scognet 1705129198Scognet/* 1706129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page lst 1707129198Scognet * 1708129198Scognet * => caller should hold the proper lock on pmap_main_lock 1709129198Scognet * => caller should have pmap locked 1710129198Scognet * => we will gain the lock on the vm_page and allocate the new pv_entry 1711129198Scognet * => caller should adjust ptp's wire_count before calling 1712129198Scognet * => caller should not adjust pmap's wire_count 1713129198Scognet */ 1714129198Scognetstatic void 1715129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1716129198Scognet vm_offset_t va, u_int flags) 1717129198Scognet{ 1718129198Scognet 1719159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1720159352Salc PMAP_ASSERT_LOCKED(pm); 1721129198Scognet pve->pv_pmap = pm; 1722129198Scognet pve->pv_va = va; 1723129198Scognet pve->pv_flags = flags; 1724129198Scognet 1725129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1726144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1727129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1728129198Scognet if (pm == pmap_kernel()) { 1729129198Scognet if (flags & PVF_WRITE) 1730129198Scognet pg->md.krw_mappings++; 1731129198Scognet else 1732129198Scognet pg->md.kro_mappings++; 1733129198Scognet } 1734129198Scognet if (flags & PVF_WRITE) 1735129198Scognet pg->md.urw_mappings++; 1736129198Scognet else 1737129198Scognet pg->md.uro_mappings++; 1738135641Scognet pg->md.pv_list_count++; 1739129198Scognet if (pve->pv_flags & PVF_WIRED) 1740129198Scognet ++pm->pm_stats.wired_count; 1741144760Scognet vm_page_flag_set(pg, PG_REFERENCED); 1742129198Scognet} 1743129198Scognet 1744129198Scognet/* 1745129198Scognet * 1746129198Scognet * pmap_find_pv: Find a pv entry 1747129198Scognet * 1748129198Scognet * => caller should hold lock on vm_page 1749129198Scognet */ 1750129198Scognetstatic PMAP_INLINE struct pv_entry * 1751129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1752129198Scognet{ 1753129198Scognet struct pv_entry *pv; 1754129198Scognet 1755159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1756129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1757129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1758129198Scognet break; 1759129198Scognet return (pv); 1760129198Scognet} 1761129198Scognet 1762129198Scognet/* 1763129198Scognet * vector_page_setprot: 1764129198Scognet * 1765129198Scognet * Manipulate the protection of the vector page. 1766129198Scognet */ 1767129198Scognetvoid 1768129198Scognetvector_page_setprot(int prot) 1769129198Scognet{ 1770129198Scognet struct l2_bucket *l2b; 1771129198Scognet pt_entry_t *ptep; 1772129198Scognet 1773129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1774129198Scognet 1775129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1776129198Scognet 1777129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1778129198Scognet PTE_SYNC(ptep); 1779129198Scognet cpu_tlb_flushD_SE(vector_page); 1780129198Scognet cpu_cpwait(); 1781129198Scognet} 1782129198Scognet 1783129198Scognet/* 1784129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1785129198Scognet * 1786129198Scognet * => caller should hold proper lock on pmap_main_lock 1787129198Scognet * => pmap should be locked 1788129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1789129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1790129198Scognet * => caller should NOT adjust pmap's wire_count 1791129198Scognet * => we return the removed pve 1792129198Scognet */ 1793135641Scognet 1794135641Scognetstatic void 1795135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1796135641Scognet{ 1797135641Scognet 1798159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1799159352Salc PMAP_ASSERT_LOCKED(pm); 1800135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1801144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1802135641Scognet if (pve->pv_flags & PVF_WIRED) 1803135641Scognet --pm->pm_stats.wired_count; 1804135641Scognet pg->md.pv_list_count--; 1805144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1806144760Scognet vm_page_dirty(pg); 1807135641Scognet if (pm == pmap_kernel()) { 1808135641Scognet if (pve->pv_flags & PVF_WRITE) 1809135641Scognet pg->md.krw_mappings--; 1810135641Scognet else 1811135641Scognet pg->md.kro_mappings--; 1812135641Scognet } else 1813135641Scognet if (pve->pv_flags & PVF_WRITE) 1814135641Scognet pg->md.urw_mappings--; 1815135641Scognet else 1816135641Scognet pg->md.uro_mappings--; 1817144760Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL || 1818144760Scognet (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) { 1819144760Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1820144760Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1821144760Scognet pg->md.pvh_attrs &= ~PVF_REF; 1822137664Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1823146647Scognet } 1824144760Scognet if (TAILQ_FIRST(&pg->md.pv_list)) 1825144760Scognet vm_page_flag_set(pg, PG_REFERENCED); 1826144760Scognet if (pve->pv_flags & PVF_WRITE) 1827144760Scognet pmap_vac_me_harder(pg, pm, 0); 1828135641Scognet} 1829135641Scognet 1830129198Scognetstatic struct pv_entry * 1831129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1832129198Scognet{ 1833135641Scognet struct pv_entry *pve; 1834129198Scognet 1835159474Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1836135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1837129198Scognet 1838129198Scognet while (pve) { 1839129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1840135641Scognet pmap_nuke_pv(pg, pm, pve); 1841129198Scognet break; 1842129198Scognet } 1843129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1844129198Scognet } 1845129198Scognet 1846129198Scognet return(pve); /* return removed pve */ 1847129198Scognet} 1848129198Scognet/* 1849129198Scognet * 1850129198Scognet * pmap_modify_pv: Update pv flags 1851129198Scognet * 1852129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1853129198Scognet * => caller should NOT adjust pmap's wire_count 1854129198Scognet * => caller must call pmap_vac_me_harder() if writable status of a page 1855129198Scognet * may have changed. 1856129198Scognet * => we return the old flags 1857129198Scognet * 1858129198Scognet * Modify a physical-virtual mapping in the pv table 1859129198Scognet */ 1860129198Scognetstatic u_int 1861129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1862129198Scognet u_int clr_mask, u_int set_mask) 1863129198Scognet{ 1864129198Scognet struct pv_entry *npv; 1865129198Scognet u_int flags, oflags; 1866129198Scognet 1867159352Salc PMAP_ASSERT_LOCKED(pm); 1868159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1869129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1870129198Scognet return (0); 1871129198Scognet 1872129198Scognet /* 1873129198Scognet * There is at least one VA mapping this page. 1874129198Scognet */ 1875129198Scognet 1876129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1877129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1878129198Scognet 1879129198Scognet oflags = npv->pv_flags; 1880129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1881129198Scognet 1882129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1883129198Scognet if (flags & PVF_WIRED) 1884129198Scognet ++pm->pm_stats.wired_count; 1885129198Scognet else 1886129198Scognet --pm->pm_stats.wired_count; 1887129198Scognet } 1888129198Scognet 1889129198Scognet if ((flags ^ oflags) & PVF_WRITE) { 1890129198Scognet if (pm == pmap_kernel()) { 1891129198Scognet if (flags & PVF_WRITE) { 1892129198Scognet pg->md.krw_mappings++; 1893129198Scognet pg->md.kro_mappings--; 1894129198Scognet } else { 1895129198Scognet pg->md.kro_mappings++; 1896129198Scognet pg->md.krw_mappings--; 1897129198Scognet } 1898129198Scognet } else 1899129198Scognet if (flags & PVF_WRITE) { 1900129198Scognet pg->md.urw_mappings++; 1901129198Scognet pg->md.uro_mappings--; 1902129198Scognet } else { 1903129198Scognet pg->md.uro_mappings++; 1904129198Scognet pg->md.urw_mappings--; 1905129198Scognet } 1906144760Scognet if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) { 1907144760Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1908144760Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1909144760Scognet } 1910144760Scognet pmap_vac_me_harder(pg, pm, 0); 1911129198Scognet } 1912129198Scognet 1913129198Scognet return (oflags); 1914129198Scognet} 1915129198Scognet 1916129198Scognet/* Function to set the debug level of the pmap code */ 1917129198Scognet#ifdef PMAP_DEBUG 1918129198Scognetvoid 1919129198Scognetpmap_debug(int level) 1920129198Scognet{ 1921129198Scognet pmap_debug_level = level; 1922129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1923129198Scognet} 1924129198Scognet#endif /* PMAP_DEBUG */ 1925129198Scognet 1926129198Scognetvoid 1927129198Scognetpmap_pinit0(struct pmap *pmap) 1928129198Scognet{ 1929129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1930129198Scognet 1931129198Scognet dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1932129198Scognet (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1933135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1934159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1935159325Salc PMAP_LOCK_INIT(pmap); 1936129198Scognet} 1937129198Scognet 1938147217Salc/* 1939147217Salc * Initialize a vm_page's machine-dependent fields. 1940147217Salc */ 1941147217Salcvoid 1942147217Salcpmap_page_init(vm_page_t m) 1943147217Salc{ 1944129198Scognet 1945147217Salc TAILQ_INIT(&m->md.pv_list); 1946147217Salc m->md.pv_list_count = 0; 1947147217Salc} 1948147217Salc 1949129198Scognet/* 1950129198Scognet * Initialize the pmap module. 1951129198Scognet * Called by vm_init, to initialize any structures that the pmap 1952129198Scognet * system needs to map virtual memory. 1953129198Scognet */ 1954129198Scognetvoid 1955129198Scognetpmap_init(void) 1956129198Scognet{ 1957152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1958129198Scognet 1959129198Scognet PDEBUG(1, printf("pmap_init: phys_start = %08x\n")); 1960147114Scognet 1961129198Scognet /* 1962129198Scognet * init the pv free list 1963129198Scognet */ 1964129198Scognet pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1965129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1966129198Scognet /* 1967129198Scognet * Now it is safe to enable pv_table recording. 1968129198Scognet */ 1969129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1970147114Scognet 1971152128Scognet TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1972152128Scognet 1973169667Sjeff pv_entry_max = shpgperproc * maxproc + VMCNT_GET(page_count); 1974152128Scognet pv_entry_high_water = 9 * (pv_entry_max / 10); 1975152128Scognet l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1976152128Scognet NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1977152128Scognet l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 1978152128Scognet NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1979152128Scognet UMA_ZONE_VM | UMA_ZONE_NOFREE); 1980152128Scognet 1981152128Scognet uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1982152128Scognet 1983129198Scognet} 1984129198Scognet 1985129198Scognetint 1986129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1987129198Scognet{ 1988129198Scognet struct l2_dtable *l2; 1989129198Scognet struct l2_bucket *l2b; 1990129198Scognet pd_entry_t *pl1pd, l1pd; 1991129198Scognet pt_entry_t *ptep, pte; 1992129198Scognet vm_paddr_t pa; 1993129198Scognet u_int l1idx; 1994129198Scognet int rv = 0; 1995129198Scognet 1996129198Scognet l1idx = L1_IDX(va); 1997159384Salc vm_page_lock_queues(); 1998159384Salc PMAP_LOCK(pm); 1999129198Scognet 2000129198Scognet /* 2001129198Scognet * If there is no l2_dtable for this address, then the process 2002129198Scognet * has no business accessing it. 2003129198Scognet * 2004129198Scognet * Note: This will catch userland processes trying to access 2005129198Scognet * kernel addresses. 2006129198Scognet */ 2007129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 2008129198Scognet if (l2 == NULL) 2009129198Scognet goto out; 2010129198Scognet 2011129198Scognet /* 2012129198Scognet * Likewise if there is no L2 descriptor table 2013129198Scognet */ 2014129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2015129198Scognet if (l2b->l2b_kva == NULL) 2016129198Scognet goto out; 2017129198Scognet 2018129198Scognet /* 2019129198Scognet * Check the PTE itself. 2020129198Scognet */ 2021129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2022129198Scognet pte = *ptep; 2023129198Scognet if (pte == 0) 2024129198Scognet goto out; 2025129198Scognet 2026129198Scognet /* 2027129198Scognet * Catch a userland access to the vector page mapped at 0x0 2028129198Scognet */ 2029129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 2030129198Scognet goto out; 2031157027Scognet if (va == vector_page) 2032157027Scognet goto out; 2033129198Scognet 2034129198Scognet pa = l2pte_pa(pte); 2035129198Scognet 2036129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2037129198Scognet /* 2038129198Scognet * This looks like a good candidate for "page modified" 2039129198Scognet * emulation... 2040129198Scognet */ 2041129198Scognet struct pv_entry *pv; 2042129198Scognet struct vm_page *pg; 2043129198Scognet 2044129198Scognet /* Extract the physical address of the page */ 2045129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 2046129198Scognet goto out; 2047129198Scognet } 2048129198Scognet /* Get the current flags for this page. */ 2049129198Scognet 2050129198Scognet pv = pmap_find_pv(pg, pm, va); 2051129198Scognet if (pv == NULL) { 2052129198Scognet goto out; 2053129198Scognet } 2054129198Scognet 2055129198Scognet /* 2056129198Scognet * Do the flags say this page is writable? If not then it 2057129198Scognet * is a genuine write fault. If yes then the write fault is 2058129198Scognet * our fault as we did not reflect the write access in the 2059129198Scognet * PTE. Now we know a write has occurred we can correct this 2060129198Scognet * and also set the modified bit 2061129198Scognet */ 2062129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 2063129198Scognet goto out; 2064129198Scognet } 2065129198Scognet 2066157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 2067157970Scognet vm_page_dirty(pg); 2068129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 2069129198Scognet 2070129198Scognet /* 2071129198Scognet * Re-enable write permissions for the page. No need to call 2072129198Scognet * pmap_vac_me_harder(), since this is just a 2073129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 2074129198Scognet * changing. We've already set the cacheable bits based on 2075129198Scognet * the assumption that we can write to this page. 2076129198Scognet */ 2077147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2078129198Scognet PTE_SYNC(ptep); 2079129198Scognet rv = 1; 2080129198Scognet } else 2081129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2082129198Scognet /* 2083129198Scognet * This looks like a good candidate for "page referenced" 2084129198Scognet * emulation. 2085129198Scognet */ 2086129198Scognet struct pv_entry *pv; 2087129198Scognet struct vm_page *pg; 2088129198Scognet 2089129198Scognet /* Extract the physical address of the page */ 2090159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2091129198Scognet goto out; 2092129198Scognet /* Get the current flags for this page. */ 2093129198Scognet 2094129198Scognet pv = pmap_find_pv(pg, pm, va); 2095159384Salc if (pv == NULL) 2096129198Scognet goto out; 2097129198Scognet 2098129198Scognet pg->md.pvh_attrs |= PVF_REF; 2099129198Scognet pv->pv_flags |= PVF_REF; 2100129198Scognet 2101129198Scognet 2102129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2103129198Scognet PTE_SYNC(ptep); 2104129198Scognet rv = 1; 2105129198Scognet } 2106129198Scognet 2107129198Scognet /* 2108129198Scognet * We know there is a valid mapping here, so simply 2109129198Scognet * fix up the L1 if necessary. 2110129198Scognet */ 2111129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2112129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2113129198Scognet if (*pl1pd != l1pd) { 2114129198Scognet *pl1pd = l1pd; 2115129198Scognet PTE_SYNC(pl1pd); 2116129198Scognet rv = 1; 2117129198Scognet } 2118129198Scognet 2119129198Scognet#ifdef CPU_SA110 2120129198Scognet /* 2121129198Scognet * There are bugs in the rev K SA110. This is a check for one 2122129198Scognet * of them. 2123129198Scognet */ 2124129198Scognet if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2125129198Scognet curcpu()->ci_arm_cpurev < 3) { 2126129198Scognet /* Always current pmap */ 2127129198Scognet if (l2pte_valid(pte)) { 2128129198Scognet extern int kernel_debug; 2129129198Scognet if (kernel_debug & 1) { 2130129198Scognet struct proc *p = curlwp->l_proc; 2131129198Scognet printf("prefetch_abort: page is already " 2132129198Scognet "mapped - pte=%p *pte=%08x\n", ptep, pte); 2133129198Scognet printf("prefetch_abort: pc=%08lx proc=%p " 2134129198Scognet "process=%s\n", va, p, p->p_comm); 2135129198Scognet printf("prefetch_abort: far=%08x fs=%x\n", 2136129198Scognet cpu_faultaddress(), cpu_faultstatus()); 2137129198Scognet } 2138129198Scognet#ifdef DDB 2139129198Scognet if (kernel_debug & 2) 2140129198Scognet Debugger(); 2141129198Scognet#endif 2142129198Scognet rv = 1; 2143129198Scognet } 2144129198Scognet } 2145129198Scognet#endif /* CPU_SA110 */ 2146129198Scognet 2147129198Scognet#ifdef DEBUG 2148129198Scognet /* 2149129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 2150129198Scognet * stale TLB entry for the faulting address. This happens when two or 2151129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 2152129198Scognet * a context switch between such processes, we can take domain faults 2153129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 2154129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2155129198Scognet * example. 2156129198Scognet * 2157129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 2158129198Scognet * entry for a recently entered mapping. In this case, the TLB is 2159129198Scognet * flushed for the new mapping, but there may still be TLB entries for 2160129198Scognet * other mappings belonging to other processes in the 1MB range 2161129198Scognet * covered by the L1 entry. 2162129198Scognet * 2163129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 2164129198Scognet * value, so the fault must be due to a stale TLB entry. 2165129198Scognet * 2166129198Scognet * Since we always need to flush the TLB anyway in the case where we 2167129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2168129198Scognet * stale TLB entries dynamically. 2169129198Scognet * 2170129198Scognet * However, the above condition can ONLY happen if the current L1 is 2171129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 2172129198Scognet * that other parts of the pmap are not doing their job WRT managing 2173129198Scognet * the TLB. 2174129198Scognet */ 2175129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2176129198Scognet extern int last_fault_code; 2177129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2178129198Scognet pm, va, ftype); 2179129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2180129198Scognet l2, l2b, ptep, pl1pd); 2181129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2182129198Scognet pte, l1pd, last_fault_code); 2183129198Scognet#ifdef DDB 2184129198Scognet Debugger(); 2185129198Scognet#endif 2186129198Scognet } 2187129198Scognet#endif 2188129198Scognet 2189129198Scognet cpu_tlb_flushID_SE(va); 2190129198Scognet cpu_cpwait(); 2191129198Scognet 2192129198Scognet rv = 1; 2193129198Scognet 2194129198Scognetout: 2195159384Salc vm_page_unlock_queues(); 2196159384Salc PMAP_UNLOCK(pm); 2197129198Scognet return (rv); 2198129198Scognet} 2199129198Scognet 2200129198Scognetvoid 2201152128Scognetpmap_postinit(void) 2202152128Scognet{ 2203129198Scognet struct l2_bucket *l2b; 2204129198Scognet struct l1_ttable *l1; 2205129198Scognet pd_entry_t *pl1pt; 2206129198Scognet pt_entry_t *ptep, pte; 2207129198Scognet vm_offset_t va, eva; 2208129198Scognet u_int loop, needed; 2209129198Scognet 2210129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2211129198Scognet needed -= 1; 2212129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2213129198Scognet 2214129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 2215129198Scognet /* Allocate a L1 page table */ 2216132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2217132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 2218129198Scognet 2219129198Scognet if (va == 0) 2220129198Scognet panic("Cannot allocate L1 KVM"); 2221129198Scognet 2222129198Scognet eva = va + L1_TABLE_SIZE; 2223129198Scognet pl1pt = (pd_entry_t *)va; 2224129198Scognet 2225135641Scognet while (va < eva) { 2226129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2227129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2228129198Scognet pte = *ptep; 2229129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2230129198Scognet *ptep = pte; 2231129198Scognet PTE_SYNC(ptep); 2232129198Scognet cpu_tlb_flushD_SE(va); 2233129198Scognet 2234129198Scognet va += PAGE_SIZE; 2235129198Scognet } 2236129198Scognet pmap_init_l1(l1, pl1pt); 2237129198Scognet } 2238129198Scognet 2239129198Scognet 2240129198Scognet#ifdef DEBUG 2241129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2242129198Scognet needed); 2243129198Scognet#endif 2244129198Scognet} 2245129198Scognet 2246129198Scognet/* 2247129198Scognet * This is used to stuff certain critical values into the PCB where they 2248129198Scognet * can be accessed quickly from cpu_switch() et al. 2249129198Scognet */ 2250129198Scognetvoid 2251129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2252129198Scognet{ 2253129198Scognet struct l2_bucket *l2b; 2254129198Scognet 2255129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2256129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2257129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2258129198Scognet 2259129198Scognet if (vector_page < KERNBASE) { 2260129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2261129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2262129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2263145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2264129198Scognet } else 2265129198Scognet pcb->pcb_pl1vec = NULL; 2266129198Scognet} 2267129198Scognet 2268129198Scognetvoid 2269129198Scognetpmap_activate(struct thread *td) 2270129198Scognet{ 2271129198Scognet pmap_t pm; 2272129198Scognet struct pcb *pcb; 2273129198Scognet 2274135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2275129198Scognet pcb = td->td_pcb; 2276129198Scognet 2277129198Scognet critical_enter(); 2278129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2279129198Scognet 2280129198Scognet if (td == curthread) { 2281129198Scognet u_int cur_dacr, cur_ttb; 2282129198Scognet 2283129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2284129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2285129198Scognet 2286129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2287129198Scognet 2288129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2289129198Scognet cur_dacr == pcb->pcb_dacr) { 2290129198Scognet /* 2291129198Scognet * No need to switch address spaces. 2292129198Scognet */ 2293129198Scognet critical_exit(); 2294129198Scognet return; 2295129198Scognet } 2296129198Scognet 2297129198Scognet 2298129198Scognet /* 2299129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2300129198Scognet * to 'vector_page' in the incoming L1 table before switching 2301129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2302129198Scognet * domain faults!) will jump into hyperspace. 2303129198Scognet */ 2304129198Scognet if (pcb->pcb_pl1vec) { 2305129198Scognet 2306129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2307129198Scognet /* 2308129198Scognet * Don't need to PTE_SYNC() at this point since 2309129198Scognet * cpu_setttb() is about to flush both the cache 2310129198Scognet * and the TLB. 2311129198Scognet */ 2312129198Scognet } 2313129198Scognet 2314129198Scognet cpu_domains(pcb->pcb_dacr); 2315129198Scognet cpu_setttb(pcb->pcb_pagedir); 2316129198Scognet } 2317129198Scognet critical_exit(); 2318129198Scognet} 2319129198Scognet 2320129198Scognetstatic int 2321129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2322129198Scognet{ 2323129198Scognet pd_entry_t *pdep, pde; 2324129198Scognet pt_entry_t *ptep, pte; 2325129198Scognet vm_offset_t pa; 2326129198Scognet int rv = 0; 2327129198Scognet 2328129198Scognet /* 2329129198Scognet * Make sure the descriptor itself has the correct cache mode 2330129198Scognet */ 2331129198Scognet pdep = &kl1[L1_IDX(va)]; 2332129198Scognet pde = *pdep; 2333129198Scognet 2334129198Scognet if (l1pte_section_p(pde)) { 2335129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2336129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2337129198Scognet pte_l1_s_cache_mode_pt; 2338129198Scognet PTE_SYNC(pdep); 2339129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2340129198Scognet sizeof(*pdep)); 2341129198Scognet rv = 1; 2342129198Scognet } 2343129198Scognet } else { 2344129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2345129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2346129198Scognet if (ptep == NULL) 2347129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2348129198Scognet 2349129198Scognet ptep = &ptep[l2pte_index(va)]; 2350129198Scognet pte = *ptep; 2351129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2352129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2353129198Scognet pte_l2_s_cache_mode_pt; 2354129198Scognet PTE_SYNC(ptep); 2355129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2356129198Scognet sizeof(*ptep)); 2357129198Scognet rv = 1; 2358129198Scognet } 2359129198Scognet } 2360129198Scognet 2361129198Scognet return (rv); 2362129198Scognet} 2363129198Scognet 2364129198Scognetstatic void 2365129198Scognetpmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2366129198Scognet pt_entry_t **ptep) 2367129198Scognet{ 2368129198Scognet vm_offset_t va = *availp; 2369129198Scognet struct l2_bucket *l2b; 2370129198Scognet 2371129198Scognet if (ptep) { 2372129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2373129198Scognet if (l2b == NULL) 2374129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2375129198Scognet 2376129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2377129198Scognet } 2378129198Scognet 2379129198Scognet *vap = va; 2380129198Scognet *availp = va + (PAGE_SIZE * pages); 2381129198Scognet} 2382129198Scognet 2383129198Scognet/* 2384129198Scognet * Bootstrap the system enough to run with virtual memory. 2385129198Scognet * 2386129198Scognet * On the arm this is called after mapping has already been enabled 2387129198Scognet * and just syncs the pmap module with what has already been done. 2388129198Scognet * [We can't call it easily with mapping off since the kernel is not 2389129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2390129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2391129198Scognet * (physical) address starting relative to 0] 2392129198Scognet */ 2393129198Scognet#define PMAP_STATIC_L2_SIZE 16 2394147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2395147114Scognetextern struct mtx smallalloc_mtx; 2396147114Scognet#endif 2397147114Scognet 2398129198Scognetvoid 2399129198Scognetpmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2400129198Scognet{ 2401129198Scognet static struct l1_ttable static_l1; 2402129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2403129198Scognet struct l1_ttable *l1 = &static_l1; 2404129198Scognet struct l2_dtable *l2; 2405129198Scognet struct l2_bucket *l2b; 2406129198Scognet pd_entry_t pde; 2407129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2408129198Scognet pt_entry_t *ptep; 2409129198Scognet vm_paddr_t pa; 2410129198Scognet vm_offset_t va; 2411135641Scognet vm_size_t size; 2412129198Scognet int l1idx, l2idx, l2next = 0; 2413129198Scognet 2414129198Scognet PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n", 2415129198Scognet firstaddr, loadaddr)); 2416129198Scognet 2417129198Scognet virtual_avail = firstaddr; 2418129198Scognet kernel_pmap = &kernel_pmap_store; 2419129198Scognet kernel_pmap->pm_l1 = l1; 2420150865Scognet kernel_l1pa = l1pt->pv_pa; 2421143192Scognet 2422143192Scognet /* 2423129198Scognet * Scan the L1 translation table created by initarm() and create 2424129198Scognet * the required metadata for all valid mappings found in it. 2425129198Scognet */ 2426129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2427129198Scognet pde = kernel_l1pt[l1idx]; 2428129198Scognet 2429129198Scognet /* 2430129198Scognet * We're only interested in Coarse mappings. 2431129198Scognet * pmap_extract() can deal with section mappings without 2432129198Scognet * recourse to checking L2 metadata. 2433129198Scognet */ 2434129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2435129198Scognet continue; 2436129198Scognet 2437129198Scognet /* 2438129198Scognet * Lookup the KVA of this L2 descriptor table 2439129198Scognet */ 2440129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2441129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2442129198Scognet 2443129198Scognet if (ptep == NULL) { 2444129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2445129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2446129198Scognet } 2447129198Scognet 2448129198Scognet /* 2449129198Scognet * Fetch the associated L2 metadata structure. 2450129198Scognet * Allocate a new one if necessary. 2451129198Scognet */ 2452129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2453129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2454129198Scognet panic("pmap_bootstrap: out of static L2s"); 2455129198Scognet kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2456129198Scognet &static_l2[l2next++]; 2457129198Scognet } 2458129198Scognet 2459129198Scognet /* 2460129198Scognet * One more L1 slot tracked... 2461129198Scognet */ 2462129198Scognet l2->l2_occupancy++; 2463129198Scognet 2464129198Scognet /* 2465129198Scognet * Fill in the details of the L2 descriptor in the 2466129198Scognet * appropriate bucket. 2467129198Scognet */ 2468129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2469129198Scognet l2b->l2b_kva = ptep; 2470129198Scognet l2b->l2b_phys = pa; 2471129198Scognet l2b->l2b_l1idx = l1idx; 2472129198Scognet 2473129198Scognet /* 2474129198Scognet * Establish an initial occupancy count for this descriptor 2475129198Scognet */ 2476129198Scognet for (l2idx = 0; 2477129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2478129198Scognet l2idx++) { 2479129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2480129198Scognet l2b->l2b_occupancy++; 2481129198Scognet } 2482129198Scognet } 2483129198Scognet 2484129198Scognet /* 2485129198Scognet * Make sure the descriptor itself has the correct cache mode. 2486129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2487129198Scognet * should consider this a clue to fix up their initarm() 2488129198Scognet * function. :) 2489129198Scognet */ 2490129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2491129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2492129198Scognet "L2 pte @ %p\n", ptep); 2493129198Scognet } 2494129198Scognet } 2495129198Scognet 2496129198Scognet 2497129198Scognet /* 2498129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2499129198Scognet * a page table. Bitch if it is not correctly set. 2500129198Scognet */ 2501129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2502129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2503129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2504129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2505129198Scognet "primary L1 @ 0x%x\n", va); 2506129198Scognet } 2507129198Scognet 2508129198Scognet cpu_dcache_wbinv_all(); 2509129198Scognet cpu_tlb_flushID(); 2510129198Scognet cpu_cpwait(); 2511129198Scognet 2512159325Salc PMAP_LOCK_INIT(kernel_pmap); 2513129198Scognet kernel_pmap->pm_active = -1; 2514129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2515144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2516129198Scognet 2517129198Scognet /* 2518129198Scognet * Reserve some special page table entries/VA space for temporary 2519129198Scognet * mapping of pages. 2520129198Scognet */ 2521129198Scognet#define SYSMAP(c, p, v, n) \ 2522129198Scognet v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2523129198Scognet 2524129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2525129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2526129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2527129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2528135641Scognet size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2529135641Scognet pmap_alloc_specials(&virtual_avail, 2530135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2531135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2532135641Scognet 2533135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2534135641Scognet pmap_alloc_specials(&virtual_avail, 2535135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2536135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2537135641Scognet 2538137362Scognet pmap_alloc_specials(&virtual_avail, 2539137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2540135641Scognet SLIST_INIT(&l1_list); 2541129198Scognet TAILQ_INIT(&l1_lru_list); 2542129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2543129198Scognet pmap_init_l1(l1, kernel_l1pt); 2544129198Scognet cpu_dcache_wbinv_all(); 2545129198Scognet 2546129198Scognet virtual_avail = round_page(virtual_avail); 2547129198Scognet virtual_end = lastaddr; 2548135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2549156191Scognet arm_nocache_startaddr = lastaddr; 2550159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2551156191Scognet 2552147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2553147114Scognet mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF); 2554161105Scognet arm_init_smallalloc(); 2555147114Scognet#endif 2556161105Scognet pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 2557129198Scognet} 2558129198Scognet 2559129198Scognet/*************************************************** 2560129198Scognet * Pmap allocation/deallocation routines. 2561129198Scognet ***************************************************/ 2562129198Scognet 2563129198Scognet/* 2564129198Scognet * Release any resources held by the given physical map. 2565129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2566129198Scognet * Should only be called if the map contains no valid mappings. 2567129198Scognet */ 2568129198Scognetvoid 2569129198Scognetpmap_release(pmap_t pmap) 2570129198Scognet{ 2571135641Scognet struct pcb *pcb; 2572135641Scognet 2573135641Scognet pmap_idcache_wbinv_all(pmap); 2574135641Scognet pmap_tlb_flushID(pmap); 2575135641Scognet cpu_cpwait(); 2576135641Scognet if (vector_page < KERNBASE) { 2577135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2578135641Scognet pcb = thread0.td_pcb; 2579135641Scognet if (pmap_is_current(pmap)) { 2580135641Scognet /* 2581135641Scognet * Frob the L1 entry corresponding to the vector 2582135641Scognet * page so that it contains the kernel pmap's domain 2583135641Scognet * number. This will ensure pmap_remove() does not 2584135641Scognet * pull the current vector page out from under us. 2585135641Scognet */ 2586135641Scognet critical_enter(); 2587135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2588135641Scognet cpu_domains(pcb->pcb_dacr); 2589135641Scognet cpu_setttb(pcb->pcb_pagedir); 2590135641Scognet critical_exit(); 2591135641Scognet } 2592135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2593135641Scognet /* 2594135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2595135641Scognet * since this process has no remaining mappings of its own. 2596135641Scognet */ 2597135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2598135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2599135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2600135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2601135641Scognet 2602135641Scognet } 2603129198Scognet pmap_free_l1(pmap); 2604159325Salc PMAP_LOCK_DESTROY(pmap); 2605135641Scognet 2606129198Scognet dprintf("pmap_release()\n"); 2607129198Scognet} 2608129198Scognet 2609129198Scognet 2610135641Scognet 2611129198Scognet/* 2612135641Scognet * Helper function for pmap_grow_l2_bucket() 2613135641Scognet */ 2614135641Scognetstatic __inline int 2615135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2616135641Scognet{ 2617135641Scognet struct l2_bucket *l2b; 2618135641Scognet pt_entry_t *ptep; 2619135641Scognet vm_paddr_t pa; 2620135641Scognet struct vm_page *pg; 2621135641Scognet 2622150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2623135641Scognet if (pg == NULL) 2624135641Scognet return (1); 2625135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2626135641Scognet 2627135641Scognet if (pap) 2628135641Scognet *pap = pa; 2629135641Scognet 2630135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2631135641Scognet 2632135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2633135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2634135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2635135641Scognet PTE_SYNC(ptep); 2636135641Scognet return (0); 2637135641Scognet} 2638135641Scognet 2639135641Scognet/* 2640135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2641135641Scognet * used by pmap_growkernel(). 2642135641Scognet */ 2643135641Scognetstatic __inline struct l2_bucket * 2644135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2645135641Scognet{ 2646135641Scognet struct l2_dtable *l2; 2647135641Scognet struct l2_bucket *l2b; 2648135641Scognet struct l1_ttable *l1; 2649135641Scognet pd_entry_t *pl1pd; 2650135641Scognet u_short l1idx; 2651135641Scognet vm_offset_t nva; 2652135641Scognet 2653135641Scognet l1idx = L1_IDX(va); 2654135641Scognet 2655135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2656135641Scognet /* 2657135641Scognet * No mapping at this address, as there is 2658135641Scognet * no entry in the L1 table. 2659135641Scognet * Need to allocate a new l2_dtable. 2660135641Scognet */ 2661135641Scognet nva = pmap_kernel_l2dtable_kva; 2662135641Scognet if ((nva & PAGE_MASK) == 0) { 2663135641Scognet /* 2664135641Scognet * Need to allocate a backing page 2665135641Scognet */ 2666135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2667135641Scognet return (NULL); 2668135641Scognet } 2669135641Scognet 2670135641Scognet l2 = (struct l2_dtable *)nva; 2671135641Scognet nva += sizeof(struct l2_dtable); 2672135641Scognet 2673135641Scognet if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2674135641Scognet PAGE_MASK)) { 2675135641Scognet /* 2676135641Scognet * The new l2_dtable straddles a page boundary. 2677135641Scognet * Map in another page to cover it. 2678135641Scognet */ 2679135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2680135641Scognet return (NULL); 2681135641Scognet } 2682135641Scognet 2683135641Scognet pmap_kernel_l2dtable_kva = nva; 2684135641Scognet 2685135641Scognet /* 2686135641Scognet * Link it into the parent pmap 2687135641Scognet */ 2688135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2689150865Scognet memset(l2, 0, sizeof(*l2)); 2690135641Scognet } 2691135641Scognet 2692135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2693135641Scognet 2694135641Scognet /* 2695135641Scognet * Fetch pointer to the L2 page table associated with the address. 2696135641Scognet */ 2697135641Scognet if (l2b->l2b_kva == NULL) { 2698135641Scognet pt_entry_t *ptep; 2699135641Scognet 2700135641Scognet /* 2701135641Scognet * No L2 page table has been allocated. Chances are, this 2702135641Scognet * is because we just allocated the l2_dtable, above. 2703135641Scognet */ 2704135641Scognet nva = pmap_kernel_l2ptp_kva; 2705135641Scognet ptep = (pt_entry_t *)nva; 2706135641Scognet if ((nva & PAGE_MASK) == 0) { 2707135641Scognet /* 2708135641Scognet * Need to allocate a backing page 2709135641Scognet */ 2710135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2711135641Scognet &pmap_kernel_l2ptp_phys)) 2712135641Scognet return (NULL); 2713135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2714135641Scognet } 2715150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2716135641Scognet l2->l2_occupancy++; 2717135641Scognet l2b->l2b_kva = ptep; 2718135641Scognet l2b->l2b_l1idx = l1idx; 2719135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2720135641Scognet 2721135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2722135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2723135641Scognet } 2724135641Scognet 2725135641Scognet /* Distribute new L1 entry to all other L1s */ 2726135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2727145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2728135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2729135641Scognet L1_C_PROTO; 2730135641Scognet PTE_SYNC(pl1pd); 2731135641Scognet } 2732135641Scognet 2733135641Scognet return (l2b); 2734135641Scognet} 2735135641Scognet 2736135641Scognet 2737135641Scognet/* 2738129198Scognet * grow the number of kernel page table entries, if needed 2739129198Scognet */ 2740129198Scognetvoid 2741129198Scognetpmap_growkernel(vm_offset_t addr) 2742129198Scognet{ 2743135641Scognet pmap_t kpm = pmap_kernel(); 2744129198Scognet 2745135641Scognet if (addr <= pmap_curmaxkvaddr) 2746135641Scognet return; /* we are OK */ 2747135641Scognet 2748135641Scognet /* 2749135641Scognet * whoops! we need to add kernel PTPs 2750135641Scognet */ 2751135641Scognet 2752135641Scognet /* Map 1MB at a time */ 2753135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2754135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2755135641Scognet 2756135641Scognet /* 2757135641Scognet * flush out the cache, expensive but growkernel will happen so 2758135641Scognet * rarely 2759135641Scognet */ 2760135641Scognet cpu_dcache_wbinv_all(); 2761135641Scognet cpu_tlb_flushD(); 2762135641Scognet cpu_cpwait(); 2763135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2764135641Scognet 2765129198Scognet} 2766129198Scognet 2767129198Scognet 2768129198Scognet/* 2769129198Scognet * Remove all pages from specified address space 2770129198Scognet * this aids process exit speeds. Also, this code 2771129198Scognet * is special cased for current process only, but 2772129198Scognet * can have the more generic (and slightly slower) 2773129198Scognet * mode enabled. This is much faster than pmap_remove 2774129198Scognet * in the case of running down an entire address space. 2775129198Scognet */ 2776129198Scognetvoid 2777157443Speterpmap_remove_pages(pmap_t pmap) 2778129198Scognet{ 2779144760Scognet struct pv_entry *pv, *npv; 2780144760Scognet struct l2_bucket *l2b = NULL; 2781144760Scognet vm_page_t m; 2782144760Scognet pt_entry_t *pt; 2783144760Scognet 2784144760Scognet vm_page_lock_queues(); 2785159352Salc PMAP_LOCK(pmap); 2786144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2787144760Scognet if (pv->pv_flags & PVF_WIRED) { 2788144760Scognet /* The page is wired, cannot remove it now. */ 2789144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2790144760Scognet continue; 2791144760Scognet } 2792144760Scognet pmap->pm_stats.resident_count--; 2793144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2794144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2795144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2796144760Scognet m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2797164079Scognet#ifdef ARM_USE_SMALL_ALLOC 2798164079Scognet KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2799164079Scognet#else 2800164079Scognet KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2801164079Scognet#endif 2802144760Scognet *pt = 0; 2803144760Scognet PTE_SYNC(pt); 2804144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2805144760Scognet pmap_nuke_pv(m, pmap, pv); 2806150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2807150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 2808144760Scognet pmap_free_pv_entry(pv); 2809164874Scognet pmap_free_l2_bucket(pmap, l2b, 1); 2810144760Scognet } 2811144760Scognet vm_page_unlock_queues(); 2812135641Scognet cpu_idcache_wbinv_all(); 2813135641Scognet cpu_tlb_flushID(); 2814135641Scognet cpu_cpwait(); 2815159352Salc PMAP_UNLOCK(pmap); 2816129198Scognet} 2817129198Scognet 2818129198Scognet 2819129198Scognet/*************************************************** 2820129198Scognet * Low level mapping routines..... 2821129198Scognet ***************************************************/ 2822129198Scognet 2823147114Scognet/* Map a section into the KVA. */ 2824147114Scognet 2825147114Scognetvoid 2826147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2827147114Scognet{ 2828147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2829147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2830147114Scognet struct l1_ttable *l1; 2831147114Scognet 2832147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2833147114Scognet ("Not a valid section mapping")); 2834147114Scognet if (flags & SECTION_CACHE) 2835147114Scognet pd |= pte_l1_s_cache_mode; 2836147114Scognet else if (flags & SECTION_PT) 2837147114Scognet pd |= pte_l1_s_cache_mode_pt; 2838147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2839147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2840147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2841147114Scognet } 2842147114Scognet} 2843147114Scognet 2844129198Scognet/* 2845129198Scognet * add a wired page to the kva 2846129198Scognet * note that in order for the mapping to take effect -- you 2847129198Scognet * should do a invltlb after doing the pmap_kenter... 2848129198Scognet */ 2849135641Scognetstatic PMAP_INLINE void 2850135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2851129198Scognet{ 2852129198Scognet struct l2_bucket *l2b; 2853129198Scognet pt_entry_t *pte; 2854129198Scognet pt_entry_t opte; 2855129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2856129198Scognet (uint32_t) va, (uint32_t) pa)); 2857129198Scognet 2858129198Scognet 2859129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2860135641Scognet if (l2b == NULL) 2861135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2862129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2863129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2864129198Scognet opte = *pte; 2865129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2866129198Scognet (uint32_t) pte, opte, *pte)); 2867129198Scognet if (l2pte_valid(opte)) { 2868129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2869129198Scognet cpu_tlb_flushD_SE(va); 2870129198Scognet cpu_cpwait(); 2871135641Scognet } else { 2872129198Scognet if (opte == 0) 2873129198Scognet l2b->l2b_occupancy++; 2874135641Scognet } 2875129198Scognet *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2876135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2877135641Scognet if (flags & KENTER_CACHE) 2878135641Scognet *pte |= pte_l2_s_cache_mode; 2879142570Scognet if (flags & KENTER_USER) 2880142570Scognet *pte |= L2_S_PROT_U; 2881129198Scognet PTE_SYNC(pte); 2882135641Scognet} 2883129198Scognet 2884135641Scognetvoid 2885135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2886135641Scognet{ 2887135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2888129198Scognet} 2889129198Scognet 2890142570Scognetvoid 2891156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2892156191Scognet{ 2893156191Scognet 2894156191Scognet pmap_kenter_internal(va, pa, 0); 2895156191Scognet} 2896156191Scognet 2897156191Scognetvoid 2898142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2899142570Scognet{ 2900143192Scognet 2901142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2902143192Scognet /* 2903143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2904143192Scognet * at the first use of the new address, or bad things will happen, 2905143192Scognet * as we use one of these addresses in the exception handlers. 2906143192Scognet */ 2907143192Scognet pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2908142570Scognet} 2909129198Scognet 2910129198Scognet/* 2911135641Scognet * remove a page rom the kernel pagetables 2912129198Scognet */ 2913169763Scognetvoid 2914129198Scognetpmap_kremove(vm_offset_t va) 2915129198Scognet{ 2916135641Scognet struct l2_bucket *l2b; 2917135641Scognet pt_entry_t *pte, opte; 2918135641Scognet 2919135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2920145071Scognet if (!l2b) 2921145071Scognet return; 2922135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2923135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2924135641Scognet opte = *pte; 2925135641Scognet if (l2pte_valid(opte)) { 2926135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2927135641Scognet cpu_tlb_flushD_SE(va); 2928135641Scognet cpu_cpwait(); 2929144760Scognet *pte = 0; 2930135641Scognet } 2931129198Scognet} 2932129198Scognet 2933129198Scognet 2934129198Scognet/* 2935129198Scognet * Used to map a range of physical addresses into kernel 2936129198Scognet * virtual address space. 2937129198Scognet * 2938129198Scognet * The value passed in '*virt' is a suggested virtual address for 2939129198Scognet * the mapping. Architectures which can support a direct-mapped 2940129198Scognet * physical to virtual region can return the appropriate address 2941129198Scognet * within that region, leaving '*virt' unchanged. Other 2942129198Scognet * architectures should map the pages starting at '*virt' and 2943129198Scognet * update '*virt' with the first usable address after the mapped 2944129198Scognet * region. 2945129198Scognet */ 2946129198Scognetvm_offset_t 2947129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2948129198Scognet{ 2949161105Scognet#ifdef ARM_USE_SMALL_ALLOC 2950161105Scognet return (arm_ptovirt(start)); 2951161105Scognet#else 2952129198Scognet vm_offset_t sva = *virt; 2953129198Scognet vm_offset_t va = sva; 2954129198Scognet 2955129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2956129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2957129198Scognet prot)); 2958129198Scognet 2959129198Scognet while (start < end) { 2960129198Scognet pmap_kenter(va, start); 2961129198Scognet va += PAGE_SIZE; 2962129198Scognet start += PAGE_SIZE; 2963129198Scognet } 2964129198Scognet *virt = va; 2965129198Scognet return (sva); 2966161105Scognet#endif 2967129198Scognet} 2968129198Scognet 2969143724Scognetstatic void 2970150865Scognetpmap_wb_page(vm_page_t m) 2971143724Scognet{ 2972143724Scognet struct pv_entry *pv; 2973129198Scognet 2974143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2975150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2976144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2977143724Scognet} 2978143724Scognet 2979150865Scognetstatic void 2980150865Scognetpmap_inv_page(vm_page_t m) 2981150865Scognet{ 2982150865Scognet struct pv_entry *pv; 2983150865Scognet 2984150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2985150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2986150865Scognet} 2987129198Scognet/* 2988129198Scognet * Add a list of wired pages to the kva 2989129198Scognet * this routine is only used for temporary 2990129198Scognet * kernel mappings that do not need to have 2991129198Scognet * page modification or references recorded. 2992129198Scognet * Note that old mappings are simply written 2993129198Scognet * over. The page *must* be wired. 2994129198Scognet */ 2995129198Scognetvoid 2996129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2997129198Scognet{ 2998129198Scognet int i; 2999129198Scognet 3000129198Scognet for (i = 0; i < count; i++) { 3001150865Scognet pmap_wb_page(m[i]); 3002135641Scognet pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 3003135641Scognet KENTER_CACHE); 3004129198Scognet va += PAGE_SIZE; 3005129198Scognet } 3006129198Scognet} 3007129198Scognet 3008129198Scognet 3009129198Scognet/* 3010129198Scognet * this routine jerks page mappings from the 3011129198Scognet * kernel -- it is meant only for temporary mappings. 3012129198Scognet */ 3013129198Scognetvoid 3014129198Scognetpmap_qremove(vm_offset_t va, int count) 3015129198Scognet{ 3016146596Scognet vm_paddr_t pa; 3017129198Scognet int i; 3018129198Scognet 3019129198Scognet for (i = 0; i < count; i++) { 3020146596Scognet pa = vtophys(va); 3021146596Scognet if (pa) { 3022150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 3023146596Scognet pmap_kremove(va); 3024146596Scognet } 3025129198Scognet va += PAGE_SIZE; 3026129198Scognet } 3027129198Scognet} 3028129198Scognet 3029129198Scognet 3030129198Scognet/* 3031129198Scognet * pmap_object_init_pt preloads the ptes for a given object 3032129198Scognet * into the specified pmap. This eliminates the blast of soft 3033129198Scognet * faults on process startup and immediately after an mmap. 3034129198Scognet */ 3035129198Scognetvoid 3036129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3037129198Scognet vm_pindex_t pindex, vm_size_t size) 3038129198Scognet{ 3039157156Scognet 3040157156Scognet VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3041157156Scognet KASSERT(object->type == OBJT_DEVICE, 3042157156Scognet ("pmap_object_init_pt: non-device object")); 3043129198Scognet} 3044129198Scognet 3045129198Scognet 3046129198Scognet/* 3047129198Scognet * pmap_is_prefaultable: 3048129198Scognet * 3049129198Scognet * Return whether or not the specified virtual address is elgible 3050129198Scognet * for prefault. 3051129198Scognet */ 3052129198Scognetboolean_t 3053129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3054129198Scognet{ 3055135641Scognet pd_entry_t *pde; 3056129198Scognet pt_entry_t *pte; 3057129198Scognet 3058135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3059135641Scognet return (FALSE); 3060159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 3061135641Scognet if (*pte == 0) 3062135641Scognet return (TRUE); 3063135641Scognet return (FALSE); 3064129198Scognet} 3065129198Scognet 3066129198Scognet/* 3067129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3068129198Scognet * Returns TRUE if the mapping exists, else FALSE. 3069129198Scognet * 3070129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 3071129198Scognet * It is not safe to take any pmap locks here, since we could be right 3072129198Scognet * in the middle of debugging the pmap anyway... 3073129198Scognet * 3074129198Scognet * It is possible for this routine to return FALSE even though a valid 3075129198Scognet * mapping does exist. This is because we don't lock, so the metadata 3076129198Scognet * state may be inconsistent. 3077129198Scognet * 3078129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3079129198Scognet * a "section" mapping. 3080129198Scognet */ 3081129198Scognetboolean_t 3082129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3083129198Scognet{ 3084129198Scognet struct l2_dtable *l2; 3085129198Scognet pd_entry_t *pl1pd, l1pd; 3086129198Scognet pt_entry_t *ptep; 3087129198Scognet u_short l1idx; 3088129198Scognet 3089129198Scognet if (pm->pm_l1 == NULL) 3090129198Scognet return (FALSE); 3091129198Scognet 3092129198Scognet l1idx = L1_IDX(va); 3093129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3094129198Scognet l1pd = *pl1pd; 3095129198Scognet 3096129198Scognet if (l1pte_section_p(l1pd)) { 3097129198Scognet *ptp = NULL; 3098129198Scognet return (TRUE); 3099129198Scognet } 3100129198Scognet 3101129198Scognet if (pm->pm_l2 == NULL) 3102129198Scognet return (FALSE); 3103129198Scognet 3104129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3105129198Scognet 3106129198Scognet if (l2 == NULL || 3107129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3108129198Scognet return (FALSE); 3109129198Scognet } 3110129198Scognet 3111129198Scognet *ptp = &ptep[l2pte_index(va)]; 3112129198Scognet return (TRUE); 3113129198Scognet} 3114129198Scognet 3115129198Scognet/* 3116129198Scognet * Routine: pmap_remove_all 3117129198Scognet * Function: 3118129198Scognet * Removes this physical page from 3119129198Scognet * all physical maps in which it resides. 3120129198Scognet * Reflects back modify bits to the pager. 3121129198Scognet * 3122129198Scognet * Notes: 3123129198Scognet * Original versions of this routine were very 3124129198Scognet * inefficient because they iteratively called 3125129198Scognet * pmap_remove (slow...) 3126129198Scognet */ 3127129198Scognetvoid 3128129198Scognetpmap_remove_all(vm_page_t m) 3129129198Scognet{ 3130129198Scognet pv_entry_t pv; 3131135641Scognet pt_entry_t *ptep, pte; 3132135641Scognet struct l2_bucket *l2b; 3133135641Scognet boolean_t flush = FALSE; 3134135641Scognet pmap_t curpm; 3135135641Scognet int flags = 0; 3136129198Scognet 3137129198Scognet#if defined(PMAP_DEBUG) 3138129198Scognet /* 3139129198Scognet * XXX this makes pmap_page_protect(NONE) illegal for non-managed 3140129198Scognet * pages! 3141129198Scognet */ 3142147217Salc if (m->flags & PG_FICTITIOUS) { 3143129198Scognet panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m)); 3144129198Scognet } 3145129198Scognet#endif 3146129198Scognet 3147135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3148135641Scognet return; 3149164778Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3150135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3151129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3152135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3153135641Scognet pv->pv_pmap == pmap_kernel())) 3154135641Scognet flush = TRUE; 3155159352Salc PMAP_LOCK(pv->pv_pmap); 3156135641Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3157135641Scognet KASSERT(l2b != NULL, ("No l2 bucket")); 3158135641Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3159135641Scognet pte = *ptep; 3160135641Scognet *ptep = 0; 3161135641Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3162135641Scognet pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3163135641Scognet if (pv->pv_flags & PVF_WIRED) 3164135641Scognet pv->pv_pmap->pm_stats.wired_count--; 3165129198Scognet pv->pv_pmap->pm_stats.resident_count--; 3166135641Scognet flags |= pv->pv_flags; 3167135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3168159352Salc PMAP_UNLOCK(pv->pv_pmap); 3169129198Scognet pmap_free_pv_entry(pv); 3170129198Scognet } 3171129198Scognet 3172135641Scognet if (flush) { 3173135641Scognet if (PV_BEEN_EXECD(flags)) 3174135641Scognet pmap_tlb_flushID(curpm); 3175135641Scognet else 3176135641Scognet pmap_tlb_flushD(curpm); 3177135641Scognet } 3178150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 3179129198Scognet} 3180129198Scognet 3181129198Scognet 3182129198Scognet/* 3183129198Scognet * Set the physical protection on the 3184129198Scognet * specified range of this map as requested. 3185129198Scognet */ 3186129198Scognetvoid 3187129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3188129198Scognet{ 3189129198Scognet struct l2_bucket *l2b; 3190129198Scognet pt_entry_t *ptep, pte; 3191129198Scognet vm_offset_t next_bucket; 3192129198Scognet u_int flags; 3193129198Scognet int flush; 3194129198Scognet 3195129198Scognet if ((prot & VM_PROT_READ) == 0) { 3196129198Scognet pmap_remove(pm, sva, eva); 3197129198Scognet return; 3198129198Scognet } 3199129198Scognet 3200129198Scognet if (prot & VM_PROT_WRITE) { 3201129198Scognet /* 3202129198Scognet * If this is a read->write transition, just ignore it and let 3203135641Scognet * vm_fault() take care of it later. 3204129198Scognet */ 3205129198Scognet return; 3206129198Scognet } 3207129198Scognet 3208159352Salc vm_page_lock_queues(); 3209159352Salc PMAP_LOCK(pm); 3210129198Scognet 3211129198Scognet /* 3212129198Scognet * OK, at this point, we know we're doing write-protect operation. 3213129198Scognet * If the pmap is active, write-back the range. 3214129198Scognet */ 3215129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3216129198Scognet 3217129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3218129198Scognet flags = 0; 3219129198Scognet 3220129198Scognet while (sva < eva) { 3221129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3222129198Scognet if (next_bucket > eva) 3223129198Scognet next_bucket = eva; 3224129198Scognet 3225129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3226129198Scognet if (l2b == NULL) { 3227129198Scognet sva = next_bucket; 3228129198Scognet continue; 3229129198Scognet } 3230129198Scognet 3231129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3232129198Scognet 3233129198Scognet while (sva < next_bucket) { 3234129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3235129198Scognet struct vm_page *pg; 3236129198Scognet u_int f; 3237129198Scognet 3238129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3239129198Scognet pte &= ~L2_S_PROT_W; 3240129198Scognet *ptep = pte; 3241129198Scognet PTE_SYNC(ptep); 3242129198Scognet 3243129198Scognet if (pg != NULL) { 3244129198Scognet f = pmap_modify_pv(pg, pm, sva, 3245129198Scognet PVF_WRITE, 0); 3246129198Scognet pmap_vac_me_harder(pg, pm, sva); 3247157970Scognet vm_page_dirty(pg); 3248129198Scognet } else 3249129198Scognet f = PVF_REF | PVF_EXEC; 3250129198Scognet 3251129198Scognet if (flush >= 0) { 3252129198Scognet flush++; 3253129198Scognet flags |= f; 3254129198Scognet } else 3255129198Scognet if (PV_BEEN_EXECD(f)) 3256129198Scognet pmap_tlb_flushID_SE(pm, sva); 3257129198Scognet else 3258129198Scognet if (PV_BEEN_REFD(f)) 3259129198Scognet pmap_tlb_flushD_SE(pm, sva); 3260129198Scognet } 3261129198Scognet 3262129198Scognet sva += PAGE_SIZE; 3263129198Scognet ptep++; 3264129198Scognet } 3265129198Scognet } 3266129198Scognet 3267129198Scognet 3268129198Scognet if (flush) { 3269129198Scognet if (PV_BEEN_EXECD(flags)) 3270129198Scognet pmap_tlb_flushID(pm); 3271129198Scognet else 3272129198Scognet if (PV_BEEN_REFD(flags)) 3273129198Scognet pmap_tlb_flushD(pm); 3274129198Scognet } 3275144760Scognet vm_page_unlock_queues(); 3276129198Scognet 3277159352Salc PMAP_UNLOCK(pm); 3278129198Scognet} 3279129198Scognet 3280129198Scognet 3281129198Scognet/* 3282129198Scognet * Insert the given physical page (p) at 3283129198Scognet * the specified virtual address (v) in the 3284129198Scognet * target physical map with the protection requested. 3285129198Scognet * 3286129198Scognet * If specified, the page will be wired down, meaning 3287129198Scognet * that the related pte can not be reclaimed. 3288129198Scognet * 3289129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3290129198Scognet * or lose information. That is, this routine must actually 3291129198Scognet * insert this page into the given map NOW. 3292129198Scognet */ 3293135641Scognet 3294129198Scognetvoid 3295129198Scognetpmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3296129198Scognet boolean_t wired) 3297129198Scognet{ 3298159127Salc 3299159127Salc vm_page_lock_queues(); 3300159352Salc PMAP_LOCK(pmap); 3301160260Scognet pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK); 3302159127Salc vm_page_unlock_queues(); 3303159352Salc PMAP_UNLOCK(pmap); 3304159127Salc} 3305159127Salc 3306159127Salc/* 3307159127Salc * The page queues and pmap must be locked. 3308159127Salc */ 3309159127Salcstatic void 3310159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3311160260Scognet boolean_t wired, int flags) 3312159127Salc{ 3313135641Scognet struct l2_bucket *l2b = NULL; 3314129198Scognet struct vm_page *opg; 3315144760Scognet struct pv_entry *pve = NULL; 3316129198Scognet pt_entry_t *ptep, npte, opte; 3317129198Scognet u_int nflags; 3318129198Scognet u_int oflags; 3319129198Scognet vm_paddr_t pa; 3320129198Scognet 3321159325Salc PMAP_ASSERT_LOCKED(pmap); 3322159127Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3323129198Scognet if (va == vector_page) { 3324129198Scognet pa = systempage.pv_pa; 3325129198Scognet m = NULL; 3326129198Scognet } else 3327129198Scognet pa = VM_PAGE_TO_PHYS(m); 3328129198Scognet nflags = 0; 3329129198Scognet if (prot & VM_PROT_WRITE) 3330129198Scognet nflags |= PVF_WRITE; 3331129198Scognet if (prot & VM_PROT_EXECUTE) 3332129198Scognet nflags |= PVF_EXEC; 3333129198Scognet if (wired) 3334129198Scognet nflags |= PVF_WIRED; 3335129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3336129198Scognet "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3337129198Scognet 3338135641Scognet if (pmap == pmap_kernel()) { 3339129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3340135641Scognet if (l2b == NULL) 3341135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3342160260Scognet } else { 3343160260Scognetdo_l2b_alloc: 3344129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3345160260Scognet if (l2b == NULL) { 3346160260Scognet if (flags & M_WAITOK) { 3347160260Scognet PMAP_UNLOCK(pmap); 3348160260Scognet vm_page_unlock_queues(); 3349160260Scognet VM_WAIT; 3350160260Scognet vm_page_lock_queues(); 3351160260Scognet PMAP_LOCK(pmap); 3352160260Scognet goto do_l2b_alloc; 3353160260Scognet } 3354160260Scognet return; 3355160260Scognet } 3356160260Scognet } 3357160260Scognet 3358129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3359129198Scognet 3360135641Scognet opte = *ptep; 3361129198Scognet npte = pa; 3362129198Scognet oflags = 0; 3363129198Scognet if (opte) { 3364129198Scognet /* 3365129198Scognet * There is already a mapping at this address. 3366129198Scognet * If the physical address is different, lookup the 3367129198Scognet * vm_page. 3368129198Scognet */ 3369129198Scognet if (l2pte_pa(opte) != pa) 3370129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3371129198Scognet else 3372129198Scognet opg = m; 3373129198Scognet } else 3374129198Scognet opg = NULL; 3375129198Scognet 3376135641Scognet if ((prot & (VM_PROT_ALL)) || 3377135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3378129198Scognet /* 3379135641Scognet * - The access type indicates that we don't need 3380135641Scognet * to do referenced emulation. 3381135641Scognet * OR 3382135641Scognet * - The physical page has already been referenced 3383135641Scognet * so no need to re-do referenced emulation here. 3384129198Scognet */ 3385135641Scognet npte |= L2_S_PROTO; 3386135641Scognet 3387135641Scognet nflags |= PVF_REF; 3388135641Scognet 3389144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3390144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3391129198Scognet /* 3392135641Scognet * This is a writable mapping, and the 3393135641Scognet * page's mod state indicates it has 3394135641Scognet * already been modified. Make it 3395135641Scognet * writable from the outset. 3396129198Scognet */ 3397135641Scognet nflags |= PVF_MOD; 3398157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3399144760Scognet vm_page_dirty(m); 3400129198Scognet } 3401144760Scognet if (m && opte) 3402144760Scognet vm_page_flag_set(m, PG_REFERENCED); 3403135641Scognet } else { 3404135641Scognet /* 3405135641Scognet * Need to do page referenced emulation. 3406135641Scognet */ 3407135641Scognet npte |= L2_TYPE_INV; 3408135641Scognet } 3409135641Scognet 3410164229Salc if (prot & VM_PROT_WRITE) { 3411135641Scognet npte |= L2_S_PROT_W; 3412164229Salc if (m != NULL) 3413164229Salc vm_page_flag_set(m, PG_WRITEABLE); 3414164229Salc } 3415135641Scognet npte |= pte_l2_s_cache_mode; 3416135641Scognet if (m && m == opg) { 3417135641Scognet /* 3418135641Scognet * We're changing the attrs of an existing mapping. 3419135641Scognet */ 3420135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3421135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3422135641Scognet PVF_MOD | PVF_REF, nflags); 3423135641Scognet 3424135641Scognet /* 3425135641Scognet * We may need to flush the cache if we're 3426135641Scognet * doing rw-ro... 3427135641Scognet */ 3428135641Scognet if (pmap_is_current(pmap) && 3429135641Scognet (oflags & PVF_NC) == 0 && 3430129198Scognet (opte & L2_S_PROT_W) != 0 && 3431129198Scognet (prot & VM_PROT_WRITE) == 0) 3432135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3433129198Scognet } else { 3434129198Scognet /* 3435135641Scognet * New mapping, or changing the backing page 3436135641Scognet * of an existing mapping. 3437129198Scognet */ 3438129198Scognet if (opg) { 3439129198Scognet /* 3440135641Scognet * Replacing an existing mapping with a new one. 3441135641Scognet * It is part of our managed memory so we 3442135641Scognet * must remove it from the PV list 3443129198Scognet */ 3444129198Scognet pve = pmap_remove_pv(opg, pmap, va); 3445159088Scognet if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) && 3446159088Scognet pve) 3447135641Scognet pmap_free_pv_entry(pve); 3448159088Scognet else if (!pve && 3449159088Scognet !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3450144760Scognet pve = pmap_get_pv_entry(); 3451164790Scognet KASSERT(pve != NULL || m->flags & (PG_UNMANAGED | 3452164790Scognet PG_FICTITIOUS), ("No pv")); 3453129198Scognet oflags = pve->pv_flags; 3454135641Scognet 3455135641Scognet /* 3456135641Scognet * If the old mapping was valid (ref/mod 3457135641Scognet * emulation creates 'invalid' mappings 3458135641Scognet * initially) then make sure to frob 3459135641Scognet * the cache. 3460135641Scognet */ 3461135641Scognet if ((oflags & PVF_NC) == 0 && 3462135641Scognet l2pte_valid(opte)) { 3463135641Scognet if (PV_BEEN_EXECD(oflags)) { 3464129198Scognet pmap_idcache_wbinv_range(pmap, va, 3465129198Scognet PAGE_SIZE); 3466135641Scognet } else 3467135641Scognet if (PV_BEEN_REFD(oflags)) { 3468135641Scognet pmap_dcache_wb_range(pmap, va, 3469135641Scognet PAGE_SIZE, TRUE, 3470135641Scognet (oflags & PVF_WRITE) == 0); 3471135641Scognet } 3472129198Scognet } 3473150865Scognet } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3474135641Scognet if ((pve = pmap_get_pv_entry()) == NULL) { 3475135641Scognet panic("pmap_enter: no pv entries"); 3476135641Scognet } 3477157970Scognet if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) { 3478157970Scognet KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3479157970Scognet ("pmap_enter: managed mapping within the clean submap")); 3480135641Scognet pmap_enter_pv(m, pve, pmap, va, nflags); 3481157970Scognet } 3482129198Scognet } 3483129198Scognet /* 3484129198Scognet * Make sure userland mappings get the right permissions 3485129198Scognet */ 3486129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3487129198Scognet npte |= L2_S_PROT_U; 3488129198Scognet } 3489129198Scognet 3490129198Scognet /* 3491129198Scognet * Keep the stats up to date 3492129198Scognet */ 3493129198Scognet if (opte == 0) { 3494129198Scognet l2b->l2b_occupancy++; 3495129198Scognet pmap->pm_stats.resident_count++; 3496129198Scognet } 3497129198Scognet 3498129198Scognet 3499129198Scognet /* 3500129198Scognet * If this is just a wiring change, the two PTEs will be 3501129198Scognet * identical, so there's no need to update the page table. 3502129198Scognet */ 3503129198Scognet if (npte != opte) { 3504135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3505129198Scognet 3506129198Scognet *ptep = npte; 3507129198Scognet if (is_cached) { 3508129198Scognet /* 3509129198Scognet * We only need to frob the cache/tlb if this pmap 3510129198Scognet * is current 3511129198Scognet */ 3512129198Scognet PTE_SYNC(ptep); 3513161105Scognet if (L1_IDX(va) != L1_IDX(vector_page) && 3514129198Scognet l2pte_valid(npte)) { 3515129198Scognet /* 3516129198Scognet * This mapping is likely to be accessed as 3517129198Scognet * soon as we return to userland. Fix up the 3518129198Scognet * L1 entry to avoid taking another 3519129198Scognet * page/domain fault. 3520129198Scognet */ 3521129198Scognet pd_entry_t *pl1pd, l1pd; 3522129198Scognet 3523129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3524129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3525144760Scognet L1_C_PROTO; 3526129198Scognet if (*pl1pd != l1pd) { 3527129198Scognet *pl1pd = l1pd; 3528129198Scognet PTE_SYNC(pl1pd); 3529129198Scognet } 3530129198Scognet } 3531129198Scognet } 3532129198Scognet 3533129198Scognet if (PV_BEEN_EXECD(oflags)) 3534129198Scognet pmap_tlb_flushID_SE(pmap, va); 3535135641Scognet else if (PV_BEEN_REFD(oflags)) 3536129198Scognet pmap_tlb_flushD_SE(pmap, va); 3537129198Scognet 3538129198Scognet 3539157025Scognet if (m) 3540157025Scognet pmap_vac_me_harder(m, pmap, va); 3541129198Scognet } 3542129198Scognet} 3543129198Scognet 3544129198Scognet/* 3545159303Salc * Maps a sequence of resident pages belonging to the same object. 3546159303Salc * The sequence begins with the given page m_start. This page is 3547159303Salc * mapped at the given virtual address start. Each subsequent page is 3548159303Salc * mapped at a virtual address that is offset from start by the same 3549159303Salc * amount as the page is offset from m_start within the object. The 3550159303Salc * last page in the sequence is the page with the largest offset from 3551159303Salc * m_start that can be mapped at a virtual address less than the given 3552159303Salc * virtual address end. Not every virtual page between start and end 3553159303Salc * is mapped; only those for which a resident page exists with the 3554159303Salc * corresponding offset from m_start are mapped. 3555159303Salc */ 3556159303Salcvoid 3557159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3558159303Salc vm_page_t m_start, vm_prot_t prot) 3559159303Salc{ 3560159303Salc vm_page_t m; 3561159303Salc vm_pindex_t diff, psize; 3562159303Salc 3563159303Salc psize = atop(end - start); 3564159303Salc m = m_start; 3565159325Salc PMAP_LOCK(pmap); 3566159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3567159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3568160260Scognet (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT); 3569159303Salc m = TAILQ_NEXT(m, listq); 3570159303Salc } 3571159325Salc PMAP_UNLOCK(pmap); 3572159303Salc} 3573159303Salc 3574159303Salc/* 3575129198Scognet * this code makes some *MAJOR* assumptions: 3576129198Scognet * 1. Current pmap & pmap exists. 3577129198Scognet * 2. Not wired. 3578129198Scognet * 3. Read access. 3579129198Scognet * 4. No page table pages. 3580129198Scognet * but is *MUCH* faster than pmap_enter... 3581129198Scognet */ 3582129198Scognet 3583159627Supsvoid 3584159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3585129198Scognet{ 3586138897Salc 3587159325Salc PMAP_LOCK(pmap); 3588159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3589160260Scognet FALSE, M_NOWAIT); 3590159325Salc PMAP_UNLOCK(pmap); 3591129198Scognet} 3592129198Scognet 3593129198Scognet/* 3594129198Scognet * Routine: pmap_change_wiring 3595129198Scognet * Function: Change the wiring attribute for a map/virtual-address 3596129198Scognet * pair. 3597129198Scognet * In/out conditions: 3598129198Scognet * The mapping must already exist in the pmap. 3599129198Scognet */ 3600129198Scognetvoid 3601129198Scognetpmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3602129198Scognet{ 3603129198Scognet struct l2_bucket *l2b; 3604129198Scognet pt_entry_t *ptep, pte; 3605129198Scognet vm_page_t pg; 3606129198Scognet 3607159352Salc vm_page_lock_queues(); 3608159325Salc PMAP_LOCK(pmap); 3609129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3610129198Scognet KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3611129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3612129198Scognet pte = *ptep; 3613129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3614129198Scognet if (pg) 3615129198Scognet pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired); 3616159352Salc vm_page_unlock_queues(); 3617159325Salc PMAP_UNLOCK(pmap); 3618129198Scognet} 3619129198Scognet 3620129198Scognet 3621129198Scognet/* 3622129198Scognet * Copy the range specified by src_addr/len 3623129198Scognet * from the source map to the range dst_addr/len 3624129198Scognet * in the destination map. 3625129198Scognet * 3626129198Scognet * This routine is only advisory and need not do anything. 3627129198Scognet */ 3628129198Scognetvoid 3629129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3630129198Scognet vm_size_t len, vm_offset_t src_addr) 3631129198Scognet{ 3632129198Scognet} 3633129198Scognet 3634129198Scognet 3635129198Scognet/* 3636129198Scognet * Routine: pmap_extract 3637129198Scognet * Function: 3638129198Scognet * Extract the physical page address associated 3639129198Scognet * with the given map/virtual_address pair. 3640129198Scognet */ 3641131658Salcvm_paddr_t 3642129198Scognetpmap_extract(pmap_t pm, vm_offset_t va) 3643129198Scognet{ 3644129198Scognet struct l2_dtable *l2; 3645159450Salc pd_entry_t l1pd; 3646129198Scognet pt_entry_t *ptep, pte; 3647129198Scognet vm_paddr_t pa; 3648129198Scognet u_int l1idx; 3649129198Scognet l1idx = L1_IDX(va); 3650129198Scognet 3651159450Salc PMAP_LOCK(pm); 3652159450Salc l1pd = pm->pm_l1->l1_kva[l1idx]; 3653129198Scognet if (l1pte_section_p(l1pd)) { 3654129198Scognet /* 3655129198Scognet * These should only happen for pmap_kernel() 3656129198Scognet */ 3657129198Scognet KASSERT(pm == pmap_kernel(), ("huh")); 3658129198Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3659129198Scognet } else { 3660129198Scognet /* 3661129198Scognet * Note that we can't rely on the validity of the L1 3662129198Scognet * descriptor as an indication that a mapping exists. 3663129198Scognet * We have to look it up in the L2 dtable. 3664129198Scognet */ 3665129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3666129198Scognet 3667129198Scognet if (l2 == NULL || 3668129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3669159450Salc PMAP_UNLOCK(pm); 3670129198Scognet return (0); 3671129198Scognet } 3672129198Scognet 3673129198Scognet ptep = &ptep[l2pte_index(va)]; 3674129198Scognet pte = *ptep; 3675129198Scognet 3676159450Salc if (pte == 0) { 3677159450Salc PMAP_UNLOCK(pm); 3678129198Scognet return (0); 3679159450Salc } 3680129198Scognet 3681129198Scognet switch (pte & L2_TYPE_MASK) { 3682129198Scognet case L2_TYPE_L: 3683129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3684129198Scognet break; 3685129198Scognet 3686129198Scognet default: 3687129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3688129198Scognet break; 3689129198Scognet } 3690129198Scognet } 3691129198Scognet 3692159450Salc PMAP_UNLOCK(pm); 3693129198Scognet return (pa); 3694129198Scognet} 3695129198Scognet 3696133453Salc/* 3697133453Salc * Atomically extract and hold the physical page with the given 3698133453Salc * pmap and virtual address pair if that mapping permits the given 3699133453Salc * protection. 3700133453Salc * 3701133453Salc */ 3702129198Scognetvm_page_t 3703129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3704129198Scognet{ 3705135641Scognet struct l2_dtable *l2; 3706159378Salc pd_entry_t l1pd; 3707135641Scognet pt_entry_t *ptep, pte; 3708129198Scognet vm_paddr_t pa; 3709135641Scognet vm_page_t m = NULL; 3710135641Scognet u_int l1idx; 3711135641Scognet l1idx = L1_IDX(va); 3712129198Scognet 3713135641Scognet vm_page_lock_queues(); 3714159325Salc PMAP_LOCK(pmap); 3715159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3716135641Scognet if (l1pte_section_p(l1pd)) { 3717135641Scognet /* 3718135641Scognet * These should only happen for pmap_kernel() 3719135641Scognet */ 3720135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3721135641Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3722135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3723135641Scognet m = PHYS_TO_VM_PAGE(pa); 3724135641Scognet vm_page_hold(m); 3725135641Scognet } 3726135641Scognet 3727135641Scognet } else { 3728135641Scognet /* 3729135641Scognet * Note that we can't rely on the validity of the L1 3730135641Scognet * descriptor as an indication that a mapping exists. 3731135641Scognet * We have to look it up in the L2 dtable. 3732135641Scognet */ 3733135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3734135641Scognet 3735135641Scognet if (l2 == NULL || 3736135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3737159325Salc PMAP_UNLOCK(pmap); 3738150865Scognet vm_page_unlock_queues(); 3739135641Scognet return (NULL); 3740135641Scognet } 3741135641Scognet 3742135641Scognet ptep = &ptep[l2pte_index(va)]; 3743135641Scognet pte = *ptep; 3744135641Scognet 3745150865Scognet if (pte == 0) { 3746159325Salc PMAP_UNLOCK(pmap); 3747150865Scognet vm_page_unlock_queues(); 3748135641Scognet return (NULL); 3749150865Scognet } 3750135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3751135641Scognet switch (pte & L2_TYPE_MASK) { 3752135641Scognet case L2_TYPE_L: 3753135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3754135641Scognet break; 3755135641Scognet 3756135641Scognet default: 3757135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3758135641Scognet break; 3759135641Scognet } 3760135641Scognet m = PHYS_TO_VM_PAGE(pa); 3761135641Scognet vm_page_hold(m); 3762135641Scognet } 3763129198Scognet } 3764135641Scognet 3765159325Salc PMAP_UNLOCK(pmap); 3766135641Scognet vm_page_unlock_queues(); 3767129198Scognet return (m); 3768129198Scognet} 3769129198Scognet 3770129198Scognet/* 3771129198Scognet * Initialize a preallocated and zeroed pmap structure, 3772129198Scognet * such as one in a vmspace structure. 3773129198Scognet */ 3774129198Scognet 3775129198Scognetvoid 3776129198Scognetpmap_pinit(pmap_t pmap) 3777129198Scognet{ 3778129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3779129198Scognet 3780159325Salc PMAP_LOCK_INIT(pmap); 3781129198Scognet pmap_alloc_l1(pmap); 3782129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3783129198Scognet 3784129198Scognet pmap->pm_count = 1; 3785129198Scognet pmap->pm_active = 0; 3786129198Scognet 3787144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3788129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3789129198Scognet pmap->pm_stats.resident_count = 1; 3790129198Scognet if (vector_page < KERNBASE) { 3791129198Scognet pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3792129198Scognet VM_PROT_READ, 1); 3793129198Scognet } 3794129198Scognet} 3795129198Scognet 3796129198Scognet 3797129198Scognet/*************************************************** 3798129198Scognet * page management routines. 3799129198Scognet ***************************************************/ 3800129198Scognet 3801129198Scognet 3802135641Scognetstatic void 3803129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3804129198Scognet{ 3805129198Scognet pv_entry_count--; 3806129198Scognet uma_zfree(pvzone, pv); 3807129198Scognet} 3808129198Scognet 3809129198Scognet 3810129198Scognet/* 3811129198Scognet * get a new pv_entry, allocating a block from the system 3812129198Scognet * when needed. 3813129198Scognet * the memory allocation is performed bypassing the malloc code 3814129198Scognet * because of the possibility of allocations at interrupt time. 3815129198Scognet */ 3816129198Scognetstatic pv_entry_t 3817129198Scognetpmap_get_pv_entry(void) 3818129198Scognet{ 3819129198Scognet pv_entry_t ret_value; 3820129198Scognet 3821129198Scognet pv_entry_count++; 3822159500Salc if (pv_entry_count > pv_entry_high_water) 3823159500Salc pagedaemon_wakeup(); 3824129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3825129198Scognet return ret_value; 3826129198Scognet} 3827129198Scognet 3828129198Scognet 3829129198Scognet/* 3830129198Scognet * Remove the given range of addresses from the specified map. 3831129198Scognet * 3832129198Scognet * It is assumed that the start and end are properly 3833129198Scognet * rounded to the page size. 3834129198Scognet */ 3835129198Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3836129198Scognetvoid 3837129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3838129198Scognet{ 3839129198Scognet struct l2_bucket *l2b; 3840129198Scognet vm_offset_t next_bucket; 3841129198Scognet pt_entry_t *ptep; 3842129198Scognet u_int cleanlist_idx, total, cnt; 3843129198Scognet struct { 3844129198Scognet vm_offset_t va; 3845129198Scognet pt_entry_t *pte; 3846129198Scognet } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3847129198Scognet u_int mappings, is_exec, is_refd; 3848135641Scognet int flushall = 0; 3849129198Scognet 3850129198Scognet 3851129198Scognet /* 3852129198Scognet * we lock in the pmap => pv_head direction 3853129198Scognet */ 3854129198Scognet 3855137664Scognet vm_page_lock_queues(); 3856159352Salc PMAP_LOCK(pm); 3857135641Scognet if (!pmap_is_current(pm)) { 3858129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3859129198Scognet } else 3860129198Scognet cleanlist_idx = 0; 3861129198Scognet 3862129198Scognet total = 0; 3863129198Scognet while (sva < eva) { 3864129198Scognet /* 3865129198Scognet * Do one L2 bucket's worth at a time. 3866129198Scognet */ 3867129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3868129198Scognet if (next_bucket > eva) 3869129198Scognet next_bucket = eva; 3870129198Scognet 3871129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3872129198Scognet if (l2b == NULL) { 3873129198Scognet sva = next_bucket; 3874129198Scognet continue; 3875129198Scognet } 3876129198Scognet 3877129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3878129198Scognet mappings = 0; 3879129198Scognet 3880129198Scognet while (sva < next_bucket) { 3881129198Scognet struct vm_page *pg; 3882129198Scognet pt_entry_t pte; 3883129198Scognet vm_paddr_t pa; 3884129198Scognet 3885129198Scognet pte = *ptep; 3886129198Scognet 3887129198Scognet if (pte == 0) { 3888129198Scognet /* 3889129198Scognet * Nothing here, move along 3890129198Scognet */ 3891129198Scognet sva += PAGE_SIZE; 3892129198Scognet ptep++; 3893129198Scognet continue; 3894129198Scognet } 3895129198Scognet 3896129198Scognet pm->pm_stats.resident_count--; 3897129198Scognet pa = l2pte_pa(pte); 3898129198Scognet is_exec = 0; 3899129198Scognet is_refd = 1; 3900129198Scognet 3901129198Scognet /* 3902129198Scognet * Update flags. In a number of circumstances, 3903129198Scognet * we could cluster a lot of these and do a 3904129198Scognet * number of sequential pages in one go. 3905129198Scognet */ 3906129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3907129198Scognet struct pv_entry *pve; 3908159474Salc 3909129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3910135641Scognet if (pve) { 3911159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3912159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3913129198Scognet pmap_free_pv_entry(pve); 3914129198Scognet } 3915129198Scognet } 3916129198Scognet 3917129198Scognet if (!l2pte_valid(pte)) { 3918129198Scognet *ptep = 0; 3919129198Scognet PTE_SYNC_CURRENT(pm, ptep); 3920129198Scognet sva += PAGE_SIZE; 3921129198Scognet ptep++; 3922129198Scognet mappings++; 3923129198Scognet continue; 3924129198Scognet } 3925129198Scognet 3926129198Scognet if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3927129198Scognet /* Add to the clean list. */ 3928129198Scognet cleanlist[cleanlist_idx].pte = ptep; 3929129198Scognet cleanlist[cleanlist_idx].va = 3930129198Scognet sva | (is_exec & 1); 3931129198Scognet cleanlist_idx++; 3932129198Scognet } else 3933129198Scognet if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3934129198Scognet /* Nuke everything if needed. */ 3935129198Scognet pmap_idcache_wbinv_all(pm); 3936129198Scognet pmap_tlb_flushID(pm); 3937129198Scognet 3938129198Scognet /* 3939129198Scognet * Roll back the previous PTE list, 3940129198Scognet * and zero out the current PTE. 3941129198Scognet */ 3942129198Scognet for (cnt = 0; 3943129198Scognet cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3944129198Scognet *cleanlist[cnt].pte = 0; 3945129198Scognet } 3946129198Scognet *ptep = 0; 3947129198Scognet PTE_SYNC(ptep); 3948129198Scognet cleanlist_idx++; 3949135641Scognet flushall = 1; 3950129198Scognet } else { 3951129198Scognet *ptep = 0; 3952129198Scognet PTE_SYNC(ptep); 3953129198Scognet if (is_exec) 3954129198Scognet pmap_tlb_flushID_SE(pm, sva); 3955129198Scognet else 3956129198Scognet if (is_refd) 3957129198Scognet pmap_tlb_flushD_SE(pm, sva); 3958129198Scognet } 3959129198Scognet 3960129198Scognet sva += PAGE_SIZE; 3961129198Scognet ptep++; 3962129198Scognet mappings++; 3963129198Scognet } 3964129198Scognet 3965129198Scognet /* 3966129198Scognet * Deal with any left overs 3967129198Scognet */ 3968129198Scognet if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3969129198Scognet total += cleanlist_idx; 3970129198Scognet for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3971135641Scognet vm_offset_t clva = 3972135641Scognet cleanlist[cnt].va & ~1; 3973135641Scognet if (cleanlist[cnt].va & 1) { 3974135641Scognet pmap_idcache_wbinv_range(pm, 3975135641Scognet clva, PAGE_SIZE); 3976135641Scognet pmap_tlb_flushID_SE(pm, clva); 3977135641Scognet } else { 3978135641Scognet pmap_dcache_wb_range(pm, 3979135641Scognet clva, PAGE_SIZE, TRUE, 3980135641Scognet FALSE); 3981135641Scognet pmap_tlb_flushD_SE(pm, clva); 3982129198Scognet } 3983129198Scognet *cleanlist[cnt].pte = 0; 3984129198Scognet PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 3985129198Scognet } 3986129198Scognet 3987129198Scognet if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3988129198Scognet cleanlist_idx = 0; 3989129198Scognet else { 3990144760Scognet /* 3991144760Scognet * We are removing so much entries it's just 3992144760Scognet * easier to flush the whole cache. 3993144760Scognet */ 3994129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3995129198Scognet pmap_idcache_wbinv_all(pm); 3996135641Scognet flushall = 1; 3997129198Scognet } 3998129198Scognet } 3999129198Scognet 4000129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 4001129198Scognet } 4002129198Scognet 4003137664Scognet vm_page_unlock_queues(); 4004135641Scognet if (flushall) 4005135641Scognet cpu_tlb_flushID(); 4006159352Salc PMAP_UNLOCK(pm); 4007129198Scognet} 4008129198Scognet 4009129198Scognet 4010129198Scognet 4011129198Scognet 4012129198Scognet/* 4013129198Scognet * pmap_zero_page() 4014129198Scognet * 4015129198Scognet * Zero a given physical page by mapping it at a page hook point. 4016129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 4017129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 4018129198Scognet * _any_ bulk data very slow. 4019129198Scognet */ 4020164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) 4021129198Scognetvoid 4022129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 4023129198Scognet{ 4024161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4025161105Scognet char *dstpg; 4026161105Scognet#endif 4027161105Scognet 4028129198Scognet#ifdef DEBUG 4029129198Scognet struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4030129198Scognet 4031129198Scognet if (pg->md.pvh_list != NULL) 4032129198Scognet panic("pmap_zero_page: page has mappings"); 4033129198Scognet#endif 4034129198Scognet 4035150865Scognet if (_arm_bzero && 4036150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4037150865Scognet return; 4038129198Scognet 4039161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4040161105Scognet dstpg = (char *)arm_ptovirt(phys); 4041161105Scognet if (off || size != PAGE_SIZE) { 4042161105Scognet bzero(dstpg + off, size); 4043161105Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4044161105Scognet } else { 4045161105Scognet bzero_page((vm_offset_t)dstpg); 4046161105Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4047161105Scognet } 4048161105Scognet#else 4049150865Scognet 4050159088Scognet mtx_lock(&cmtx); 4051129198Scognet /* 4052129198Scognet * Hook in the page, zero it, and purge the cache for that 4053129198Scognet * zeroed page. Invalidate the TLB as needed. 4054129198Scognet */ 4055129198Scognet *cdst_pte = L2_S_PROTO | phys | 4056129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4057129198Scognet PTE_SYNC(cdst_pte); 4058129198Scognet cpu_tlb_flushD_SE(cdstp); 4059129198Scognet cpu_cpwait(); 4060161105Scognet if (off || size != PAGE_SIZE) { 4061129198Scognet bzero((void *)(cdstp + off), size); 4062161105Scognet cpu_dcache_wbinv_range(cdstp + off, size); 4063161105Scognet } else { 4064129198Scognet bzero_page(cdstp); 4065161105Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4066161105Scognet } 4067159088Scognet mtx_unlock(&cmtx); 4068161105Scognet#endif 4069129198Scognet} 4070129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4071129198Scognet 4072129198Scognet#if ARM_MMU_XSCALE == 1 4073129198Scognetvoid 4074129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 4075129198Scognet{ 4076150865Scognet if (_arm_bzero && 4077150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4078150865Scognet return; 4079159088Scognet mtx_lock(&cmtx); 4080129198Scognet /* 4081129198Scognet * Hook in the page, zero it, and purge the cache for that 4082129198Scognet * zeroed page. Invalidate the TLB as needed. 4083129198Scognet */ 4084129198Scognet *cdst_pte = L2_S_PROTO | phys | 4085129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4086129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4087129198Scognet PTE_SYNC(cdst_pte); 4088129198Scognet cpu_tlb_flushD_SE(cdstp); 4089129198Scognet cpu_cpwait(); 4090135641Scognet if (off || size != PAGE_SIZE) 4091129198Scognet bzero((void *)(cdstp + off), size); 4092129198Scognet else 4093129198Scognet bzero_page(cdstp); 4094159088Scognet mtx_unlock(&cmtx); 4095129198Scognet xscale_cache_clean_minidata(); 4096129198Scognet} 4097129198Scognet 4098129198Scognet/* 4099129198Scognet * Change the PTEs for the specified kernel mappings such that they 4100129198Scognet * will use the mini data cache instead of the main data cache. 4101129198Scognet */ 4102129198Scognetvoid 4103135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 4104129198Scognet{ 4105129198Scognet struct l2_bucket *l2b; 4106129198Scognet pt_entry_t *ptep, *sptep, pte; 4107129198Scognet vm_offset_t next_bucket, eva; 4108129198Scognet 4109164778Scognet#if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3) 4110129198Scognet if (xscale_use_minidata == 0) 4111129198Scognet return; 4112129198Scognet#endif 4113129198Scognet 4114135641Scognet eva = va + size; 4115129198Scognet 4116129198Scognet while (va < eva) { 4117129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4118129198Scognet if (next_bucket > eva) 4119129198Scognet next_bucket = eva; 4120129198Scognet 4121129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4122129198Scognet 4123129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4124129198Scognet 4125129198Scognet while (va < next_bucket) { 4126129198Scognet pte = *ptep; 4127129198Scognet if (!l2pte_minidata(pte)) { 4128129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4129129198Scognet cpu_tlb_flushD_SE(va); 4130129198Scognet *ptep = pte & ~L2_B; 4131129198Scognet } 4132129198Scognet ptep++; 4133129198Scognet va += PAGE_SIZE; 4134129198Scognet } 4135129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4136129198Scognet } 4137129198Scognet cpu_cpwait(); 4138129198Scognet} 4139129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4140129198Scognet 4141129198Scognet/* 4142129198Scognet * pmap_zero_page zeros the specified hardware page by mapping 4143129198Scognet * the page into KVM and using bzero to clear its contents. 4144129198Scognet */ 4145129198Scognetvoid 4146129198Scognetpmap_zero_page(vm_page_t m) 4147129198Scognet{ 4148135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4149129198Scognet} 4150129198Scognet 4151129198Scognet 4152129198Scognet/* 4153129198Scognet * pmap_zero_page_area zeros the specified hardware page by mapping 4154129198Scognet * the page into KVM and using bzero to clear its contents. 4155129198Scognet * 4156129198Scognet * off and size may not cover an area beyond a single hardware page. 4157129198Scognet */ 4158129198Scognetvoid 4159129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4160129198Scognet{ 4161129198Scognet 4162129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4163129198Scognet} 4164129198Scognet 4165129198Scognet 4166129198Scognet/* 4167129198Scognet * pmap_zero_page_idle zeros the specified hardware page by mapping 4168129198Scognet * the page into KVM and using bzero to clear its contents. This 4169129198Scognet * is intended to be called from the vm_pagezero process only and 4170129198Scognet * outside of Giant. 4171129198Scognet */ 4172129198Scognetvoid 4173129198Scognetpmap_zero_page_idle(vm_page_t m) 4174129198Scognet{ 4175129198Scognet 4176129198Scognet pmap_zero_page(m); 4177129198Scognet} 4178129198Scognet 4179150865Scognet#if 0 4180129198Scognet/* 4181129198Scognet * pmap_clean_page() 4182129198Scognet * 4183129198Scognet * This is a local function used to work out the best strategy to clean 4184129198Scognet * a single page referenced by its entry in the PV table. It's used by 4185129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4186129198Scognet * 4187129198Scognet * Its policy is effectively: 4188129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4189129198Scognet * o If there is one mapping, we clean just that page. 4190129198Scognet * o If there are multiple mappings, we clean the entire cache. 4191129198Scognet * 4192129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4193129198Scognet * clean the entire cache, or 1 if it did. 4194129198Scognet * 4195129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4196129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4197129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4198129198Scognet * it will just result in not the most efficient clean for the page. 4199129198Scognet */ 4200129198Scognetstatic int 4201129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4202129198Scognet{ 4203129198Scognet pmap_t pm, pm_to_clean = NULL; 4204129198Scognet struct pv_entry *npv; 4205129198Scognet u_int cache_needs_cleaning = 0; 4206129198Scognet u_int flags = 0; 4207129198Scognet vm_offset_t page_to_clean = 0; 4208129198Scognet 4209129198Scognet if (pv == NULL) { 4210129198Scognet /* nothing mapped in so nothing to flush */ 4211129198Scognet return (0); 4212129198Scognet } 4213129198Scognet 4214129198Scognet /* 4215129198Scognet * Since we flush the cache each time we change to a different 4216129198Scognet * user vmspace, we only need to flush the page if it is in the 4217129198Scognet * current pmap. 4218129198Scognet */ 4219135641Scognet if (curthread) 4220135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4221129198Scognet else 4222129198Scognet pm = pmap_kernel(); 4223129198Scognet 4224129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4225129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4226129198Scognet flags |= npv->pv_flags; 4227129198Scognet /* 4228129198Scognet * The page is mapped non-cacheable in 4229129198Scognet * this map. No need to flush the cache. 4230129198Scognet */ 4231129198Scognet if (npv->pv_flags & PVF_NC) { 4232129198Scognet#ifdef DIAGNOSTIC 4233129198Scognet if (cache_needs_cleaning) 4234129198Scognet panic("pmap_clean_page: " 4235129198Scognet "cache inconsistency"); 4236129198Scognet#endif 4237129198Scognet break; 4238129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4239129198Scognet continue; 4240129198Scognet if (cache_needs_cleaning) { 4241129198Scognet page_to_clean = 0; 4242129198Scognet break; 4243129198Scognet } else { 4244129198Scognet page_to_clean = npv->pv_va; 4245129198Scognet pm_to_clean = npv->pv_pmap; 4246129198Scognet } 4247129198Scognet cache_needs_cleaning = 1; 4248129198Scognet } 4249129198Scognet } 4250129198Scognet if (page_to_clean) { 4251129198Scognet if (PV_BEEN_EXECD(flags)) 4252129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4253129198Scognet PAGE_SIZE); 4254129198Scognet else 4255129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4256129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4257129198Scognet } else if (cache_needs_cleaning) { 4258129198Scognet if (PV_BEEN_EXECD(flags)) 4259129198Scognet pmap_idcache_wbinv_all(pm); 4260129198Scognet else 4261129198Scognet pmap_dcache_wbinv_all(pm); 4262129198Scognet return (1); 4263129198Scognet } 4264129198Scognet return (0); 4265129198Scognet} 4266150865Scognet#endif 4267129198Scognet 4268129198Scognet/* 4269129198Scognet * pmap_copy_page copies the specified (machine independent) 4270129198Scognet * page by mapping the page into virtual memory and using 4271129198Scognet * bcopy to copy the page, one machine dependent page at a 4272129198Scognet * time. 4273129198Scognet */ 4274129198Scognet 4275129198Scognet/* 4276129198Scognet * pmap_copy_page() 4277129198Scognet * 4278129198Scognet * Copy one physical page into another, by mapping the pages into 4279129198Scognet * hook points. The same comment regarding cachability as in 4280129198Scognet * pmap_zero_page also applies here. 4281129198Scognet */ 4282164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) 4283129198Scognetvoid 4284129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4285129198Scognet{ 4286151596Scognet#if 0 4287129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4288151596Scognet#endif 4289129198Scognet#ifdef DEBUG 4290129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4291129198Scognet 4292129198Scognet if (dst_pg->md.pvh_list != NULL) 4293129198Scognet panic("pmap_copy_page: dst page has mappings"); 4294129198Scognet#endif 4295129198Scognet 4296129198Scognet 4297129198Scognet /* 4298129198Scognet * Clean the source page. Hold the source page's lock for 4299129198Scognet * the duration of the copy so that no other mappings can 4300129198Scognet * be created while we have a potentially aliased mapping. 4301129198Scognet */ 4302129198Scognet#if 0 4303150865Scognet /* 4304150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4305150865Scognet * pmap_copy_page(). 4306150865Scognet */ 4307129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4308150865Scognet#endif 4309129198Scognet /* 4310129198Scognet * Map the pages into the page hook points, copy them, and purge 4311129198Scognet * the cache for the appropriate page. Invalidate the TLB 4312129198Scognet * as required. 4313129198Scognet */ 4314159088Scognet mtx_lock(&cmtx); 4315129198Scognet *csrc_pte = L2_S_PROTO | src | 4316129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4317129198Scognet PTE_SYNC(csrc_pte); 4318129198Scognet *cdst_pte = L2_S_PROTO | dst | 4319129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4320129198Scognet PTE_SYNC(cdst_pte); 4321129198Scognet cpu_tlb_flushD_SE(csrcp); 4322129198Scognet cpu_tlb_flushD_SE(cdstp); 4323129198Scognet cpu_cpwait(); 4324129198Scognet bcopy_page(csrcp, cdstp); 4325159088Scognet mtx_unlock(&cmtx); 4326129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4327129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4328129198Scognet} 4329129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4330129198Scognet 4331129198Scognet#if ARM_MMU_XSCALE == 1 4332129198Scognetvoid 4333129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4334129198Scognet{ 4335150865Scognet#if 0 4336150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4337129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4338150865Scognet#endif 4339129198Scognet#ifdef DEBUG 4340129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4341129198Scognet 4342129198Scognet if (dst_pg->md.pvh_list != NULL) 4343129198Scognet panic("pmap_copy_page: dst page has mappings"); 4344129198Scognet#endif 4345129198Scognet 4346129198Scognet 4347129198Scognet /* 4348129198Scognet * Clean the source page. Hold the source page's lock for 4349129198Scognet * the duration of the copy so that no other mappings can 4350129198Scognet * be created while we have a potentially aliased mapping. 4351129198Scognet */ 4352150865Scognet#if 0 4353150865Scognet /* 4354150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4355150865Scognet * pmap_copy_page(). 4356150865Scognet */ 4357130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4358150865Scognet#endif 4359129198Scognet /* 4360129198Scognet * Map the pages into the page hook points, copy them, and purge 4361129198Scognet * the cache for the appropriate page. Invalidate the TLB 4362129198Scognet * as required. 4363129198Scognet */ 4364159088Scognet mtx_lock(&cmtx); 4365129198Scognet *csrc_pte = L2_S_PROTO | src | 4366129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4367129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4368129198Scognet PTE_SYNC(csrc_pte); 4369129198Scognet *cdst_pte = L2_S_PROTO | dst | 4370129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4371129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4372129198Scognet PTE_SYNC(cdst_pte); 4373129198Scognet cpu_tlb_flushD_SE(csrcp); 4374129198Scognet cpu_tlb_flushD_SE(cdstp); 4375129198Scognet cpu_cpwait(); 4376129198Scognet bcopy_page(csrcp, cdstp); 4377159088Scognet mtx_unlock(&cmtx); 4378129198Scognet xscale_cache_clean_minidata(); 4379129198Scognet} 4380129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4381129198Scognet 4382129198Scognetvoid 4383129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4384129198Scognet{ 4385161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4386161105Scognet vm_offset_t srcpg, dstpg; 4387161105Scognet#endif 4388161105Scognet 4389146596Scognet cpu_dcache_wbinv_all(); 4390150865Scognet if (_arm_memcpy && 4391150865Scognet _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4392150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4393150865Scognet return; 4394161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4395161105Scognet srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src)); 4396161105Scognet dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst)); 4397161105Scognet bcopy_page(srcpg, dstpg); 4398161105Scognet cpu_dcache_wbinv_range(dstpg, PAGE_SIZE); 4399161105Scognet#else 4400129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4401161105Scognet#endif 4402129198Scognet} 4403129198Scognet 4404129198Scognet 4405129198Scognet 4406129198Scognet 4407129198Scognet/* 4408129198Scognet * this routine returns true if a physical page resides 4409129198Scognet * in the given pmap. 4410129198Scognet */ 4411129198Scognetboolean_t 4412129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4413129198Scognet{ 4414129198Scognet pv_entry_t pv; 4415129198Scognet int loops = 0; 4416129198Scognet 4417147217Salc if (m->flags & PG_FICTITIOUS) 4418129198Scognet return (FALSE); 4419129198Scognet 4420129198Scognet /* 4421129198Scognet * Not found, check current mappings returning immediately 4422129198Scognet */ 4423129198Scognet for (pv = TAILQ_FIRST(&m->md.pv_list); 4424129198Scognet pv; 4425129198Scognet pv = TAILQ_NEXT(pv, pv_list)) { 4426129198Scognet if (pv->pv_pmap == pmap) { 4427129198Scognet return (TRUE); 4428129198Scognet } 4429129198Scognet loops++; 4430129198Scognet if (loops >= 16) 4431129198Scognet break; 4432129198Scognet } 4433129198Scognet return (FALSE); 4434129198Scognet} 4435129198Scognet 4436129198Scognet 4437129198Scognet/* 4438129198Scognet * pmap_ts_referenced: 4439129198Scognet * 4440129198Scognet * Return the count of reference bits for a page, clearing all of them. 4441129198Scognet */ 4442129198Scognetint 4443129198Scognetpmap_ts_referenced(vm_page_t m) 4444129198Scognet{ 4445164778Scognet 4446164779Scognet if (m->flags & PG_FICTITIOUS) 4447164779Scognet return (0); 4448135641Scognet return (pmap_clearbit(m, PVF_REF)); 4449129198Scognet} 4450129198Scognet 4451129198Scognet 4452129198Scognetboolean_t 4453129198Scognetpmap_is_modified(vm_page_t m) 4454129198Scognet{ 4455135641Scognet 4456135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4457135641Scognet return (TRUE); 4458129198Scognet 4459129198Scognet return(FALSE); 4460129198Scognet} 4461129198Scognet 4462129198Scognet 4463129198Scognet/* 4464129198Scognet * Clear the modify bits on the specified physical page. 4465129198Scognet */ 4466129198Scognetvoid 4467129198Scognetpmap_clear_modify(vm_page_t m) 4468129198Scognet{ 4469129198Scognet 4470129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4471129198Scognet pmap_clearbit(m, PVF_MOD); 4472129198Scognet} 4473129198Scognet 4474129198Scognet 4475129198Scognet/* 4476129198Scognet * pmap_clear_reference: 4477129198Scognet * 4478129198Scognet * Clear the reference bit on the specified physical page. 4479129198Scognet */ 4480129198Scognetvoid 4481129198Scognetpmap_clear_reference(vm_page_t m) 4482129198Scognet{ 4483129198Scognet 4484129198Scognet if (m->md.pvh_attrs & PVF_REF) 4485129198Scognet pmap_clearbit(m, PVF_REF); 4486129198Scognet} 4487129198Scognet 4488129198Scognet 4489129198Scognet/* 4490160537Salc * Clear the write and modified bits in each of the given page's mappings. 4491160537Salc */ 4492160537Salcvoid 4493160889Salcpmap_remove_write(vm_page_t m) 4494160537Salc{ 4495160537Salc 4496161705Scognet if (m->flags & PG_WRITEABLE) 4497160537Salc pmap_clearbit(m, PVF_WRITE); 4498160537Salc} 4499160537Salc 4500160537Salc 4501160537Salc/* 4502129198Scognet * perform the pmap work for mincore 4503129198Scognet */ 4504129198Scognetint 4505129198Scognetpmap_mincore(pmap_t pmap, vm_offset_t addr) 4506129198Scognet{ 4507129198Scognet printf("pmap_mincore()\n"); 4508129198Scognet 4509129198Scognet return (0); 4510129198Scognet} 4511129198Scognet 4512129198Scognet 4513129198Scognetvm_offset_t 4514129198Scognetpmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 4515129198Scognet{ 4516129198Scognet 4517129198Scognet return(addr); 4518129198Scognet} 4519129198Scognet 4520129198Scognet 4521129198Scognet/* 4522129198Scognet * Map a set of physical memory pages into the kernel virtual 4523129198Scognet * address space. Return a pointer to where it is mapped. This 4524129198Scognet * routine is intended to be used for mapping device memory, 4525129198Scognet * NOT real memory. 4526129198Scognet */ 4527129198Scognetvoid * 4528129198Scognetpmap_mapdev(vm_offset_t pa, vm_size_t size) 4529129198Scognet{ 4530129198Scognet vm_offset_t va, tmpva, offset; 4531129198Scognet 4532129198Scognet offset = pa & PAGE_MASK; 4533135641Scognet size = roundup(size, PAGE_SIZE); 4534129198Scognet 4535129198Scognet GIANT_REQUIRED; 4536129198Scognet 4537132560Salc va = kmem_alloc_nofault(kernel_map, size); 4538129198Scognet if (!va) 4539129198Scognet panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4540129198Scognet for (tmpva = va; size > 0;) { 4541135641Scognet pmap_kenter_internal(tmpva, pa, 0); 4542129198Scognet size -= PAGE_SIZE; 4543129198Scognet tmpva += PAGE_SIZE; 4544129198Scognet pa += PAGE_SIZE; 4545129198Scognet } 4546129198Scognet 4547159068Sbenno return ((void *)(va + offset)); 4548129198Scognet} 4549129198Scognet 4550129198Scognet#define BOOTSTRAP_DEBUG 4551129198Scognet 4552129198Scognet/* 4553129198Scognet * pmap_map_section: 4554129198Scognet * 4555129198Scognet * Create a single section mapping. 4556129198Scognet */ 4557129198Scognetvoid 4558129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4559129198Scognet int prot, int cache) 4560129198Scognet{ 4561129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4562129198Scognet pd_entry_t fl; 4563129198Scognet 4564129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4565129198Scognet 4566129198Scognet switch (cache) { 4567129198Scognet case PTE_NOCACHE: 4568129198Scognet default: 4569129198Scognet fl = 0; 4570129198Scognet break; 4571129198Scognet 4572129198Scognet case PTE_CACHE: 4573129198Scognet fl = pte_l1_s_cache_mode; 4574129198Scognet break; 4575129198Scognet 4576129198Scognet case PTE_PAGETABLE: 4577129198Scognet fl = pte_l1_s_cache_mode_pt; 4578129198Scognet break; 4579129198Scognet } 4580129198Scognet 4581129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4582129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4583129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4584129198Scognet 4585129198Scognet} 4586129198Scognet 4587129198Scognet/* 4588129198Scognet * pmap_link_l2pt: 4589129198Scognet * 4590164079Scognet * Link the L2 page table specified by l2pv.pv_pa into the L1 4591129198Scognet * page table at the slot for "va". 4592129198Scognet */ 4593129198Scognetvoid 4594129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4595129198Scognet{ 4596129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4597129198Scognet u_int slot = va >> L1_S_SHIFT; 4598129198Scognet 4599129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4600129198Scognet 4601164079Scognet#ifdef VERBOSE_INIT_ARM 4602164079Scognet printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 4603164079Scognet#endif 4604164079Scognet 4605129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4606164079Scognet 4607129198Scognet PTE_SYNC(&pde[slot]); 4608129198Scognet 4609129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4610129198Scognet 4611129198Scognet 4612129198Scognet} 4613129198Scognet 4614129198Scognet/* 4615129198Scognet * pmap_map_entry 4616129198Scognet * 4617129198Scognet * Create a single page mapping. 4618129198Scognet */ 4619129198Scognetvoid 4620129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4621129198Scognet int cache) 4622129198Scognet{ 4623129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4624129198Scognet pt_entry_t fl; 4625129198Scognet pt_entry_t *pte; 4626129198Scognet 4627129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4628129198Scognet 4629129198Scognet switch (cache) { 4630129198Scognet case PTE_NOCACHE: 4631129198Scognet default: 4632129198Scognet fl = 0; 4633129198Scognet break; 4634129198Scognet 4635129198Scognet case PTE_CACHE: 4636129198Scognet fl = pte_l2_s_cache_mode; 4637129198Scognet break; 4638129198Scognet 4639129198Scognet case PTE_PAGETABLE: 4640129198Scognet fl = pte_l2_s_cache_mode_pt; 4641129198Scognet break; 4642129198Scognet } 4643129198Scognet 4644129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4645129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4646129198Scognet 4647129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4648129198Scognet 4649129198Scognet if (pte == NULL) 4650129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4651129198Scognet 4652129198Scognet pte[l2pte_index(va)] = 4653129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4654129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4655129198Scognet} 4656129198Scognet 4657129198Scognet/* 4658129198Scognet * pmap_map_chunk: 4659129198Scognet * 4660129198Scognet * Map a chunk of memory using the most efficient mappings 4661129198Scognet * possible (section. large page, small page) into the 4662129198Scognet * provided L1 and L2 tables at the specified virtual address. 4663129198Scognet */ 4664129198Scognetvm_size_t 4665129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4666129198Scognet vm_size_t size, int prot, int cache) 4667129198Scognet{ 4668129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4669129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4670129198Scognet vm_size_t resid; 4671129198Scognet int i; 4672129198Scognet 4673129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4674129198Scognet 4675129198Scognet if (l1pt == 0) 4676129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4677129198Scognet 4678129198Scognet#ifdef VERBOSE_INIT_ARM 4679159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4680129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4681129198Scognet#endif 4682129198Scognet 4683129198Scognet switch (cache) { 4684129198Scognet case PTE_NOCACHE: 4685129198Scognet default: 4686129198Scognet f1 = 0; 4687129198Scognet f2l = 0; 4688129198Scognet f2s = 0; 4689129198Scognet break; 4690129198Scognet 4691129198Scognet case PTE_CACHE: 4692129198Scognet f1 = pte_l1_s_cache_mode; 4693129198Scognet f2l = pte_l2_l_cache_mode; 4694129198Scognet f2s = pte_l2_s_cache_mode; 4695129198Scognet break; 4696129198Scognet 4697129198Scognet case PTE_PAGETABLE: 4698129198Scognet f1 = pte_l1_s_cache_mode_pt; 4699129198Scognet f2l = pte_l2_l_cache_mode_pt; 4700129198Scognet f2s = pte_l2_s_cache_mode_pt; 4701129198Scognet break; 4702129198Scognet } 4703129198Scognet 4704129198Scognet size = resid; 4705129198Scognet 4706129198Scognet while (resid > 0) { 4707129198Scognet /* See if we can use a section mapping. */ 4708129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4709129198Scognet#ifdef VERBOSE_INIT_ARM 4710129198Scognet printf("S"); 4711129198Scognet#endif 4712129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4713129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4714129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4715129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4716129198Scognet va += L1_S_SIZE; 4717129198Scognet pa += L1_S_SIZE; 4718129198Scognet resid -= L1_S_SIZE; 4719129198Scognet continue; 4720129198Scognet } 4721129198Scognet 4722129198Scognet /* 4723129198Scognet * Ok, we're going to use an L2 table. Make sure 4724129198Scognet * one is actually in the corresponding L1 slot 4725129198Scognet * for the current VA. 4726129198Scognet */ 4727129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4728129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4729129198Scognet 4730129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4731129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4732129198Scognet if (pte == NULL) 4733129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4734129198Scognet "0x%08x", va); 4735129198Scognet /* See if we can use a L2 large page mapping. */ 4736129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4737129198Scognet#ifdef VERBOSE_INIT_ARM 4738129198Scognet printf("L"); 4739129198Scognet#endif 4740129198Scognet for (i = 0; i < 16; i++) { 4741129198Scognet pte[l2pte_index(va) + i] = 4742129198Scognet L2_L_PROTO | pa | 4743129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4744129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4745129198Scognet } 4746129198Scognet va += L2_L_SIZE; 4747129198Scognet pa += L2_L_SIZE; 4748129198Scognet resid -= L2_L_SIZE; 4749129198Scognet continue; 4750129198Scognet } 4751129198Scognet 4752129198Scognet /* Use a small page mapping. */ 4753129198Scognet#ifdef VERBOSE_INIT_ARM 4754129198Scognet printf("P"); 4755129198Scognet#endif 4756129198Scognet pte[l2pte_index(va)] = 4757129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4758129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4759129198Scognet va += PAGE_SIZE; 4760129198Scognet pa += PAGE_SIZE; 4761129198Scognet resid -= PAGE_SIZE; 4762129198Scognet } 4763129198Scognet#ifdef VERBOSE_INIT_ARM 4764129198Scognet printf("\n"); 4765129198Scognet#endif 4766129198Scognet return (size); 4767129198Scognet 4768129198Scognet} 4769129198Scognet 4770135641Scognet/********************** Static device map routines ***************************/ 4771135641Scognet 4772135641Scognetstatic const struct pmap_devmap *pmap_devmap_table; 4773135641Scognet 4774135641Scognet/* 4775135641Scognet * Register the devmap table. This is provided in case early console 4776135641Scognet * initialization needs to register mappings created by bootstrap code 4777135641Scognet * before pmap_devmap_bootstrap() is called. 4778135641Scognet */ 4779135641Scognetvoid 4780135641Scognetpmap_devmap_register(const struct pmap_devmap *table) 4781135641Scognet{ 4782135641Scognet 4783135641Scognet pmap_devmap_table = table; 4784135641Scognet} 4785135641Scognet 4786135641Scognet/* 4787135641Scognet * Map all of the static regions in the devmap table, and remember 4788135641Scognet * the devmap table so other parts of the kernel can look up entries 4789135641Scognet * later. 4790135641Scognet */ 4791135641Scognetvoid 4792135641Scognetpmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4793135641Scognet{ 4794135641Scognet int i; 4795135641Scognet 4796135641Scognet pmap_devmap_table = table; 4797135641Scognet 4798135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4799135641Scognet#ifdef VERBOSE_INIT_ARM 4800159322Scognet printf("devmap: %08x -> %08x @ %08x\n", 4801135641Scognet pmap_devmap_table[i].pd_pa, 4802135641Scognet pmap_devmap_table[i].pd_pa + 4803135641Scognet pmap_devmap_table[i].pd_size - 1, 4804135641Scognet pmap_devmap_table[i].pd_va); 4805135641Scognet#endif 4806135641Scognet pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4807135641Scognet pmap_devmap_table[i].pd_pa, 4808135641Scognet pmap_devmap_table[i].pd_size, 4809135641Scognet pmap_devmap_table[i].pd_prot, 4810135641Scognet pmap_devmap_table[i].pd_cache); 4811135641Scognet } 4812135641Scognet} 4813135641Scognet 4814135641Scognetconst struct pmap_devmap * 4815135641Scognetpmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4816135641Scognet{ 4817135641Scognet int i; 4818135641Scognet 4819135641Scognet if (pmap_devmap_table == NULL) 4820135641Scognet return (NULL); 4821135641Scognet 4822135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4823135641Scognet if (pa >= pmap_devmap_table[i].pd_pa && 4824135641Scognet pa + size <= pmap_devmap_table[i].pd_pa + 4825135641Scognet pmap_devmap_table[i].pd_size) 4826135641Scognet return (&pmap_devmap_table[i]); 4827135641Scognet } 4828135641Scognet 4829135641Scognet return (NULL); 4830135641Scognet} 4831135641Scognet 4832135641Scognetconst struct pmap_devmap * 4833135641Scognetpmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4834135641Scognet{ 4835135641Scognet int i; 4836135641Scognet 4837135641Scognet if (pmap_devmap_table == NULL) 4838135641Scognet return (NULL); 4839135641Scognet 4840135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4841135641Scognet if (va >= pmap_devmap_table[i].pd_va && 4842135641Scognet va + size <= pmap_devmap_table[i].pd_va + 4843135641Scognet pmap_devmap_table[i].pd_size) 4844135641Scognet return (&pmap_devmap_table[i]); 4845135641Scognet } 4846135641Scognet 4847135641Scognet return (NULL); 4848135641Scognet} 4849135641Scognet 4850