pmap-v4.c revision 164779
1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 3. All advertising materials mentioning features or use of this software 81129198Scognet * must display the following acknowledgement: 82129198Scognet * This product includes software developed by the NetBSD 83129198Scognet * Foundation, Inc. and its contributors. 84129198Scognet * 4. Neither the name of The NetBSD Foundation nor the names of its 85129198Scognet * contributors may be used to endorse or promote products derived 86129198Scognet * from this software without specific prior written permission. 87129198Scognet * 88129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 89129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 90129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 91129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 92129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 93129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 94129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 95129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 96129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 97129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98129198Scognet * POSSIBILITY OF SUCH DAMAGE. 99129198Scognet */ 100129198Scognet 101139735Simp/*- 102129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 103129198Scognet * Copyright (c) 1994 Brini. 104129198Scognet * All rights reserved. 105139735Simp * 106129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 107129198Scognet * 108129198Scognet * Redistribution and use in source and binary forms, with or without 109129198Scognet * modification, are permitted provided that the following conditions 110129198Scognet * are met: 111129198Scognet * 1. Redistributions of source code must retain the above copyright 112129198Scognet * notice, this list of conditions and the following disclaimer. 113129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 114129198Scognet * notice, this list of conditions and the following disclaimer in the 115129198Scognet * documentation and/or other materials provided with the distribution. 116129198Scognet * 3. All advertising materials mentioning features or use of this software 117129198Scognet * must display the following acknowledgement: 118129198Scognet * This product includes software developed by Mark Brinicombe. 119129198Scognet * 4. The name of the author may not be used to endorse or promote products 120129198Scognet * derived from this software without specific prior written permission. 121129198Scognet * 122129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 123129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 124129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 125129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 126129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 127129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 128129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 129129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 130129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 131129198Scognet * 132129198Scognet * RiscBSD kernel project 133129198Scognet * 134129198Scognet * pmap.c 135129198Scognet * 136129198Scognet * Machine dependant vm stuff 137129198Scognet * 138129198Scognet * Created : 20/09/94 139129198Scognet */ 140129198Scognet 141129198Scognet/* 142129198Scognet * Special compilation symbols 143129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 144129198Scognet */ 145129198Scognet/* Include header files */ 146135641Scognet 147137552Scognet#include "opt_vm.h" 148137552Scognet 149129198Scognet#include <sys/cdefs.h> 150129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 164779 2006-11-30 23:35:34Z cognet $"); 151129198Scognet#include <sys/param.h> 152129198Scognet#include <sys/systm.h> 153129198Scognet#include <sys/kernel.h> 154129198Scognet#include <sys/proc.h> 155129198Scognet#include <sys/malloc.h> 156129198Scognet#include <sys/msgbuf.h> 157129198Scognet#include <sys/vmmeter.h> 158129198Scognet#include <sys/mman.h> 159129198Scognet#include <sys/smp.h> 160129198Scognet#include <sys/sx.h> 161129198Scognet#include <sys/sched.h> 162129198Scognet 163129198Scognet#include <vm/vm.h> 164129198Scognet#include <vm/uma.h> 165129198Scognet#include <vm/pmap.h> 166129198Scognet#include <vm/vm_kern.h> 167129198Scognet#include <vm/vm_object.h> 168129198Scognet#include <vm/vm_map.h> 169129198Scognet#include <vm/vm_page.h> 170129198Scognet#include <vm/vm_pageout.h> 171129198Scognet#include <vm/vm_extern.h> 172129198Scognet#include <sys/lock.h> 173129198Scognet#include <sys/mutex.h> 174129198Scognet#include <machine/md_var.h> 175129198Scognet#include <machine/vmparam.h> 176129198Scognet#include <machine/cpu.h> 177129198Scognet#include <machine/cpufunc.h> 178129198Scognet#include <machine/pcb.h> 179129198Scognet 180129198Scognet#ifdef PMAP_DEBUG 181129198Scognet#define PDEBUG(_lev_,_stat_) \ 182129198Scognet if (pmap_debug_level >= (_lev_)) \ 183129198Scognet ((_stat_)) 184129198Scognet#define dprintf printf 185129198Scognet 186129198Scognetint pmap_debug_level = 0; 187135641Scognet#define PMAP_INLINE 188129198Scognet#else /* PMAP_DEBUG */ 189129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 190129198Scognet#define dprintf(x, arg...) 191135641Scognet#define PMAP_INLINE __inline 192129198Scognet#endif /* PMAP_DEBUG */ 193129198Scognet 194129198Scognetextern struct pv_addr systempage; 195129198Scognet/* 196129198Scognet * Internal function prototypes 197129198Scognet */ 198135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 199129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 200129198Scognet 201159127Salcstatic void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 202160260Scognet vm_prot_t, boolean_t, int); 203129198Scognetstatic void pmap_vac_me_harder(struct vm_page *, pmap_t, 204129198Scognet vm_offset_t); 205129198Scognetstatic void pmap_vac_me_kpmap(struct vm_page *, pmap_t, 206129198Scognet vm_offset_t); 207129198Scognetstatic void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t); 208129198Scognetstatic void pmap_alloc_l1(pmap_t); 209129198Scognetstatic void pmap_free_l1(pmap_t); 210129198Scognetstatic void pmap_use_l1(pmap_t); 211129198Scognet 212135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 213129198Scognet 214129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 215129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 216129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 217129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 218129198Scognet 219129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 220129198Scognet 221129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 222129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 223135641Scognetvm_offset_t pmap_curmaxkvaddr; 224150865Scognetvm_paddr_t kernel_l1pa; 225129198Scognet 226129198Scognetextern void *end; 227129198Scognetvm_offset_t kernel_vm_end = 0; 228129198Scognet 229129198Scognetstruct pmap kernel_pmap_store; 230129198Scognetpmap_t kernel_pmap; 231129198Scognet 232129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 233129198Scognetstatic vm_offset_t csrcp, cdstp; 234159088Scognetstatic struct mtx cmtx; 235159088Scognet 236129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 237129198Scognet/* 238129198Scognet * These routines are called when the CPU type is identified to set up 239129198Scognet * the PTE prototypes, cache modes, etc. 240129198Scognet * 241129198Scognet * The variables are always here, just in case LKMs need to reference 242129198Scognet * them (though, they shouldn't). 243129198Scognet */ 244129198Scognet 245129198Scognetpt_entry_t pte_l1_s_cache_mode; 246129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 247129198Scognetpt_entry_t pte_l1_s_cache_mask; 248129198Scognet 249129198Scognetpt_entry_t pte_l2_l_cache_mode; 250129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 251129198Scognetpt_entry_t pte_l2_l_cache_mask; 252129198Scognet 253129198Scognetpt_entry_t pte_l2_s_cache_mode; 254129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 255129198Scognetpt_entry_t pte_l2_s_cache_mask; 256129198Scognet 257129198Scognetpt_entry_t pte_l2_s_prot_u; 258129198Scognetpt_entry_t pte_l2_s_prot_w; 259129198Scognetpt_entry_t pte_l2_s_prot_mask; 260129198Scognet 261129198Scognetpt_entry_t pte_l1_s_proto; 262129198Scognetpt_entry_t pte_l1_c_proto; 263129198Scognetpt_entry_t pte_l2_s_proto; 264129198Scognet 265129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 266129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 267129198Scognet/* 268129198Scognet * Which pmap is currently 'live' in the cache 269129198Scognet * 270129198Scognet * XXXSCW: Fix for SMP ... 271129198Scognet */ 272129198Scognetunion pmap_cache_state *pmap_cache_state; 273129198Scognet 274129198Scognet/* static pt_entry_t *msgbufmap;*/ 275129198Scognetstruct msgbuf *msgbufp = 0; 276129198Scognet 277129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 278129198Scognetextern void bzero_page(vm_offset_t); 279137362Scognet 280164079Scognetextern vm_offset_t alloc_firstaddr; 281164079Scognet 282137362Scognetchar *_tmppt; 283137362Scognet 284129198Scognet/* 285129198Scognet * Metadata for L1 translation tables. 286129198Scognet */ 287129198Scognetstruct l1_ttable { 288129198Scognet /* Entry on the L1 Table list */ 289129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 290129198Scognet 291129198Scognet /* Entry on the L1 Least Recently Used list */ 292129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 293129198Scognet 294129198Scognet /* Track how many domains are allocated from this L1 */ 295129198Scognet volatile u_int l1_domain_use_count; 296129198Scognet 297129198Scognet /* 298129198Scognet * A free-list of domain numbers for this L1. 299129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 300129198Scognet * is slow on ARM. 301129198Scognet */ 302129198Scognet u_int8_t l1_domain_first; 303129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 304129198Scognet 305129198Scognet /* Physical address of this L1 page table */ 306129198Scognet vm_paddr_t l1_physaddr; 307129198Scognet 308129198Scognet /* KVA of this L1 page table */ 309129198Scognet pd_entry_t *l1_kva; 310129198Scognet}; 311129198Scognet 312129198Scognet/* 313129198Scognet * Convert a virtual address into its L1 table index. That is, the 314129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 315129198Scognet * This is basically used to index l1->l1_kva[]. 316129198Scognet * 317129198Scognet * Each L2 descriptor table represents 1MB of VA space. 318129198Scognet */ 319129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 320129198Scognet 321129198Scognet/* 322129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 323129198Scognet * - New L1s are allocated from the HEAD. 324129198Scognet * - Freed L1s are added to the TAIl. 325129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 326129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 327129198Scognet */ 328129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 329135641Scognet/* 330135641Scognet * A list of all L1 tables 331135641Scognet */ 332135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 333129198Scognetstatic struct mtx l1_lru_lock; 334129198Scognet 335129198Scognet/* 336129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 337129198Scognet * 338129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 339129198Scognet * Reference counts are maintained for L2 descriptors so they can be 340129198Scognet * freed when empty. 341129198Scognet */ 342129198Scognetstruct l2_dtable { 343129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 344129198Scognet u_int l2_occupancy; 345129198Scognet 346129198Scognet /* List of L2 page descriptors */ 347129198Scognet struct l2_bucket { 348129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 349129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 350129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 351129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 352129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 353129198Scognet}; 354129198Scognet 355135641Scognet/* pmap_kenter_internal flags */ 356135641Scognet#define KENTER_CACHE 0x1 357142570Scognet#define KENTER_USER 0x2 358135641Scognet 359129198Scognet/* 360129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 361129198Scognet * and bucket index within the l2_dtable. 362129198Scognet */ 363129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 364129198Scognet (L2_SIZE - 1)) 365129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 366129198Scognet 367129198Scognet/* 368129198Scognet * Given a virtual address, this macro returns the 369129198Scognet * virtual address required to drop into the next L2 bucket. 370129198Scognet */ 371129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 372129198Scognet 373129198Scognet/* 374129198Scognet * L2 allocation. 375129198Scognet */ 376129198Scognet#define pmap_alloc_l2_dtable() \ 377160260Scognet (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE) 378129198Scognet#define pmap_free_l2_dtable(l2) \ 379129198Scognet uma_zfree(l2table_zone, l2) 380129198Scognet 381129198Scognet/* 382129198Scognet * We try to map the page tables write-through, if possible. However, not 383129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 384129198Scognet * the cache when we frob page tables. 385129198Scognet * 386129198Scognet * We try to evaluate this at compile time, if possible. However, it's 387129198Scognet * not always possible to do that, hence this run-time var. 388129198Scognet */ 389129198Scognetint pmap_needs_pte_sync; 390129198Scognet 391129198Scognet/* 392129198Scognet * Macro to determine if a mapping might be resident in the 393129198Scognet * instruction cache and/or TLB 394129198Scognet */ 395129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 396129198Scognet 397129198Scognet/* 398129198Scognet * Macro to determine if a mapping might be resident in the 399129198Scognet * data cache and/or TLB 400129198Scognet */ 401129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 402129198Scognet 403129198Scognet#ifndef PMAP_SHPGPERPROC 404129198Scognet#define PMAP_SHPGPERPROC 200 405129198Scognet#endif 406129198Scognet 407135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 408135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 409129198Scognetstatic uma_zone_t pvzone; 410147114Scognetuma_zone_t l2zone; 411129198Scognetstatic uma_zone_t l2table_zone; 412135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 413135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 414135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 415129198Scognetstatic struct vm_object pvzone_obj; 416129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 417129198Scognet 418129198Scognet/* 419129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 420129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 421129198Scognet * find them as necessary. 422129198Scognet * 423129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 424129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 425129198Scognet */ 426129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 427129198Scognet 428129198Scognetstatic void 429129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 430129198Scognet{ 431129198Scognet int i; 432129198Scognet 433129198Scognet l1->l1_kva = l1pt; 434129198Scognet l1->l1_domain_use_count = 0; 435129198Scognet l1->l1_domain_first = 0; 436129198Scognet 437129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 438129198Scognet l1->l1_domain_free[i] = i + 1; 439129198Scognet 440129198Scognet /* 441129198Scognet * Copy the kernel's L1 entries to each new L1. 442129198Scognet */ 443147249Scognet if (l1pt != pmap_kernel()->pm_l1->l1_kva) 444129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 445129198Scognet 446129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 447129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 448135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 449129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 450129198Scognet} 451129198Scognet 452129198Scognetstatic vm_offset_t 453129198Scognetkernel_pt_lookup(vm_paddr_t pa) 454129198Scognet{ 455129198Scognet struct pv_addr *pv; 456129198Scognet 457129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 458129198Scognet if (pv->pv_pa == pa) 459129198Scognet return (pv->pv_va); 460129198Scognet } 461129198Scognet return (0); 462129198Scognet} 463129198Scognet 464129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 465129198Scognetvoid 466129198Scognetpmap_pte_init_generic(void) 467129198Scognet{ 468129198Scognet 469129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 470129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 471129198Scognet 472129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 473129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 474129198Scognet 475129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 476129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 477129198Scognet 478129198Scognet /* 479129198Scognet * If we have a write-through cache, set B and C. If 480129198Scognet * we have a write-back cache, then we assume setting 481129198Scognet * only C will make those pages write-through. 482129198Scognet */ 483129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 484129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 485129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 486129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 487129198Scognet } else { 488129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 489129198Scognet pte_l2_l_cache_mode_pt = L2_C; 490129198Scognet pte_l2_s_cache_mode_pt = L2_C; 491129198Scognet } 492129198Scognet 493129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 494129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 495129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 496129198Scognet 497129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 498129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 499129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 500129198Scognet 501129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 502129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 503129198Scognet} 504129198Scognet 505129198Scognet#if defined(CPU_ARM8) 506129198Scognetvoid 507129198Scognetpmap_pte_init_arm8(void) 508129198Scognet{ 509129198Scognet 510129198Scognet /* 511129198Scognet * ARM8 is compatible with generic, but we need to use 512129198Scognet * the page tables uncached. 513129198Scognet */ 514129198Scognet pmap_pte_init_generic(); 515129198Scognet 516129198Scognet pte_l1_s_cache_mode_pt = 0; 517129198Scognet pte_l2_l_cache_mode_pt = 0; 518129198Scognet pte_l2_s_cache_mode_pt = 0; 519129198Scognet} 520129198Scognet#endif /* CPU_ARM8 */ 521129198Scognet 522129198Scognet#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 523129198Scognetvoid 524129198Scognetpmap_pte_init_arm9(void) 525129198Scognet{ 526129198Scognet 527129198Scognet /* 528129198Scognet * ARM9 is compatible with generic, but we want to use 529129198Scognet * write-through caching for now. 530129198Scognet */ 531129198Scognet pmap_pte_init_generic(); 532129198Scognet 533129198Scognet pte_l1_s_cache_mode = L1_S_C; 534129198Scognet pte_l2_l_cache_mode = L2_C; 535129198Scognet pte_l2_s_cache_mode = L2_C; 536129198Scognet 537129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 538129198Scognet pte_l2_l_cache_mode_pt = L2_C; 539129198Scognet pte_l2_s_cache_mode_pt = L2_C; 540129198Scognet} 541129198Scognet#endif /* CPU_ARM9 */ 542129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 543129198Scognet 544129198Scognet#if defined(CPU_ARM10) 545129198Scognetvoid 546129198Scognetpmap_pte_init_arm10(void) 547129198Scognet{ 548129198Scognet 549129198Scognet /* 550129198Scognet * ARM10 is compatible with generic, but we want to use 551129198Scognet * write-through caching for now. 552129198Scognet */ 553129198Scognet pmap_pte_init_generic(); 554129198Scognet 555129198Scognet pte_l1_s_cache_mode = L1_S_B | L1_S_C; 556129198Scognet pte_l2_l_cache_mode = L2_B | L2_C; 557129198Scognet pte_l2_s_cache_mode = L2_B | L2_C; 558129198Scognet 559129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 560129198Scognet pte_l2_l_cache_mode_pt = L2_C; 561129198Scognet pte_l2_s_cache_mode_pt = L2_C; 562129198Scognet 563129198Scognet} 564129198Scognet#endif /* CPU_ARM10 */ 565129198Scognet 566129198Scognet#if ARM_MMU_SA1 == 1 567129198Scognetvoid 568129198Scognetpmap_pte_init_sa1(void) 569129198Scognet{ 570129198Scognet 571129198Scognet /* 572129198Scognet * The StrongARM SA-1 cache does not have a write-through 573129198Scognet * mode. So, do the generic initialization, then reset 574129198Scognet * the page table cache mode to B=1,C=1, and note that 575129198Scognet * the PTEs need to be sync'd. 576129198Scognet */ 577129198Scognet pmap_pte_init_generic(); 578129198Scognet 579129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 580129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 581129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 582129198Scognet 583129198Scognet pmap_needs_pte_sync = 1; 584129198Scognet} 585129198Scognet#endif /* ARM_MMU_SA1 == 1*/ 586129198Scognet 587129198Scognet#if ARM_MMU_XSCALE == 1 588164778Scognet#if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) 589129198Scognetstatic u_int xscale_use_minidata; 590129198Scognet#endif 591129198Scognet 592129198Scognetvoid 593129198Scognetpmap_pte_init_xscale(void) 594129198Scognet{ 595129198Scognet uint32_t auxctl; 596129198Scognet int write_through = 0; 597129198Scognet 598135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 599129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 600129198Scognet 601129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 602129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 603129198Scognet 604129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 605129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 606129198Scognet 607129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 608129198Scognet pte_l2_l_cache_mode_pt = L2_C; 609129198Scognet pte_l2_s_cache_mode_pt = L2_C; 610129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 611129198Scognet /* 612129198Scognet * The XScale core has an enhanced mode where writes that 613129198Scognet * miss the cache cause a cache line to be allocated. This 614129198Scognet * is significantly faster than the traditional, write-through 615129198Scognet * behavior of this case. 616129198Scognet */ 617164778Scognet#ifndef CPU_XSCALE_CORE3 618129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 619129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 620129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 621164778Scognet#endif 622129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 623129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 624129198Scognet /* 625129198Scognet * Some versions of the XScale core have various bugs in 626129198Scognet * their cache units, the work-around for which is to run 627129198Scognet * the cache in write-through mode. Unfortunately, this 628129198Scognet * has a major (negative) impact on performance. So, we 629129198Scognet * go ahead and run fast-and-loose, in the hopes that we 630129198Scognet * don't line up the planets in a way that will trip the 631129198Scognet * bugs. 632129198Scognet * 633129198Scognet * However, we give you the option to be slow-but-correct. 634129198Scognet */ 635129198Scognet write_through = 1; 636129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 637129198Scognet /* force write back cache mode */ 638129198Scognet write_through = 0; 639129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 640129198Scognet /* 641129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 642129198Scognet * write-back cache on revision 4 and earlier (stepping 643129198Scognet * A[01] and B[012]). Fixed for C0 and later. 644129198Scognet */ 645129198Scognet { 646129198Scognet uint32_t id, type; 647129198Scognet 648129198Scognet id = cpufunc_id(); 649129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 650129198Scognet 651129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 652129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 653129198Scognet /* write through for stepping A0-1 and B0-2 */ 654129198Scognet write_through = 1; 655129198Scognet } 656129198Scognet } 657129198Scognet } 658129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 659129198Scognet 660129198Scognet if (write_through) { 661129198Scognet pte_l1_s_cache_mode = L1_S_C; 662129198Scognet pte_l2_l_cache_mode = L2_C; 663129198Scognet pte_l2_s_cache_mode = L2_C; 664129198Scognet } 665129198Scognet 666129198Scognet#if (ARM_NMMUS > 1) 667129198Scognet xscale_use_minidata = 1; 668129198Scognet#endif 669129198Scognet 670129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 671129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 672129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 673129198Scognet 674129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 675129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 676129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 677129198Scognet 678164778Scognet#ifdef CPU_XSCALE_CORE3 679164778Scognet pmap_copy_page_func = pmap_copy_page_generic; 680164778Scognet pmap_zero_page_func = pmap_zero_page_generic; 681164778Scognet xscale_use_minidata = 0; 682164778Scognet pte_l1_s_cache_mode_pt = pte_l2_l_cache_mode_pt = 683164778Scognet pte_l2_s_cache_mode_pt = 0; 684164778Scognet#else 685129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 686129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 687164778Scognet#endif 688129198Scognet 689129198Scognet /* 690129198Scognet * Disable ECC protection of page table access, for now. 691129198Scognet */ 692129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 693129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 694129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 695129198Scognet} 696129198Scognet 697129198Scognet/* 698129198Scognet * xscale_setup_minidata: 699129198Scognet * 700129198Scognet * Set up the mini-data cache clean area. We require the 701129198Scognet * caller to allocate the right amount of physically and 702129198Scognet * virtually contiguous space. 703129198Scognet */ 704129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 705129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 706129198Scognetvoid 707129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 708129198Scognet{ 709129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 710129198Scognet pt_entry_t *pte; 711129198Scognet vm_size_t size; 712129198Scognet uint32_t auxctl; 713129198Scognet 714129198Scognet xscale_minidata_clean_addr = va; 715129198Scognet 716129198Scognet /* Round it to page size. */ 717129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 718129198Scognet 719129198Scognet for (; size != 0; 720129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 721129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 722129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 723129198Scognet if (pte == NULL) 724129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 725129198Scognet "VA 0x%08x", (u_int32_t) va); 726129198Scognet pte[l2pte_index(va)] = 727129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 728129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 729129198Scognet } 730129198Scognet 731129198Scognet /* 732129198Scognet * Configure the mini-data cache for write-back with 733129198Scognet * read/write-allocate. 734129198Scognet * 735129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 736129198Scognet * make sure it contains no valid data! In order to do that, 737129198Scognet * we must issue a global data cache invalidate command! 738129198Scognet * 739129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 740129198Scognet * THIS IS VERY IMPORTANT! 741129198Scognet */ 742129198Scognet 743129198Scognet /* Invalidate data and mini-data. */ 744129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 745129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 746129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 747129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 748129198Scognet} 749129198Scognet#endif 750129198Scognet 751129198Scognet/* 752129198Scognet * Allocate an L1 translation table for the specified pmap. 753129198Scognet * This is called at pmap creation time. 754129198Scognet */ 755129198Scognetstatic void 756129198Scognetpmap_alloc_l1(pmap_t pm) 757129198Scognet{ 758129198Scognet struct l1_ttable *l1; 759129198Scognet u_int8_t domain; 760129198Scognet 761129198Scognet /* 762129198Scognet * Remove the L1 at the head of the LRU list 763129198Scognet */ 764129198Scognet mtx_lock(&l1_lru_lock); 765129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 766129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 767129198Scognet 768129198Scognet /* 769129198Scognet * Pick the first available domain number, and update 770129198Scognet * the link to the next number. 771129198Scognet */ 772129198Scognet domain = l1->l1_domain_first; 773129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 774129198Scognet 775129198Scognet /* 776129198Scognet * If there are still free domain numbers in this L1, 777129198Scognet * put it back on the TAIL of the LRU list. 778129198Scognet */ 779129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 780129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 781129198Scognet 782129198Scognet mtx_unlock(&l1_lru_lock); 783129198Scognet 784129198Scognet /* 785129198Scognet * Fix up the relevant bits in the pmap structure 786129198Scognet */ 787129198Scognet pm->pm_l1 = l1; 788129198Scognet pm->pm_domain = domain; 789129198Scognet} 790129198Scognet 791129198Scognet/* 792129198Scognet * Free an L1 translation table. 793129198Scognet * This is called at pmap destruction time. 794129198Scognet */ 795129198Scognetstatic void 796129198Scognetpmap_free_l1(pmap_t pm) 797129198Scognet{ 798129198Scognet struct l1_ttable *l1 = pm->pm_l1; 799129198Scognet 800129198Scognet mtx_lock(&l1_lru_lock); 801129198Scognet 802129198Scognet /* 803129198Scognet * If this L1 is currently on the LRU list, remove it. 804129198Scognet */ 805129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 806129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 807129198Scognet 808129198Scognet /* 809129198Scognet * Free up the domain number which was allocated to the pmap 810129198Scognet */ 811129198Scognet l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 812129198Scognet l1->l1_domain_first = pm->pm_domain; 813129198Scognet l1->l1_domain_use_count--; 814129198Scognet 815129198Scognet /* 816129198Scognet * The L1 now must have at least 1 free domain, so add 817129198Scognet * it back to the LRU list. If the use count is zero, 818129198Scognet * put it at the head of the list, otherwise it goes 819129198Scognet * to the tail. 820129198Scognet */ 821129198Scognet if (l1->l1_domain_use_count == 0) { 822129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 823129198Scognet } else 824129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 825129198Scognet 826129198Scognet mtx_unlock(&l1_lru_lock); 827129198Scognet} 828129198Scognet 829129198Scognetstatic PMAP_INLINE void 830129198Scognetpmap_use_l1(pmap_t pm) 831129198Scognet{ 832129198Scognet struct l1_ttable *l1; 833129198Scognet 834129198Scognet /* 835129198Scognet * Do nothing if we're in interrupt context. 836129198Scognet * Access to an L1 by the kernel pmap must not affect 837129198Scognet * the LRU list. 838129198Scognet */ 839129198Scognet if (pm == pmap_kernel()) 840129198Scognet return; 841129198Scognet 842129198Scognet l1 = pm->pm_l1; 843129198Scognet 844129198Scognet /* 845129198Scognet * If the L1 is not currently on the LRU list, just return 846129198Scognet */ 847129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) 848129198Scognet return; 849129198Scognet 850129198Scognet mtx_lock(&l1_lru_lock); 851129198Scognet 852129198Scognet /* 853129198Scognet * Check the use count again, now that we've acquired the lock 854129198Scognet */ 855129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) { 856129198Scognet mtx_unlock(&l1_lru_lock); 857129198Scognet return; 858129198Scognet } 859129198Scognet 860129198Scognet /* 861129198Scognet * Move the L1 to the back of the LRU list 862129198Scognet */ 863129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 864129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 865129198Scognet 866129198Scognet mtx_unlock(&l1_lru_lock); 867129198Scognet} 868129198Scognet 869129198Scognet 870129198Scognet/* 871129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 872129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 873129198Scognet */ 874129198Scognetstatic PMAP_INLINE struct l2_bucket * 875129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 876129198Scognet{ 877129198Scognet struct l2_dtable *l2; 878129198Scognet struct l2_bucket *l2b; 879129198Scognet u_short l1idx; 880129198Scognet 881129198Scognet l1idx = L1_IDX(va); 882129198Scognet 883129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 884129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 885129198Scognet return (NULL); 886129198Scognet 887129198Scognet return (l2b); 888129198Scognet} 889129198Scognet 890129198Scognet/* 891129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 892129198Scognet * and VA. 893129198Scognet * 894129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 895129198Scognet * bucket/page table in place. 896129198Scognet * 897129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 898129198Scognet * increment the bucket occupancy counter appropriately *before* 899129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 900129198Scognet * the bucket/page in the meantime. 901129198Scognet */ 902129198Scognetstatic struct l2_bucket * 903129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 904129198Scognet{ 905129198Scognet struct l2_dtable *l2; 906129198Scognet struct l2_bucket *l2b; 907129198Scognet u_short l1idx; 908129198Scognet 909129198Scognet l1idx = L1_IDX(va); 910129198Scognet 911159352Salc PMAP_ASSERT_LOCKED(pm); 912159108Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 913129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 914129198Scognet /* 915129198Scognet * No mapping at this address, as there is 916129198Scognet * no entry in the L1 table. 917129198Scognet * Need to allocate a new l2_dtable. 918129198Scognet */ 919159108Scognetagain_l2table: 920159352Salc PMAP_UNLOCK(pm); 921159108Scognet vm_page_unlock_queues(); 922129198Scognet if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 923159108Scognet vm_page_lock_queues(); 924159352Salc PMAP_LOCK(pm); 925129198Scognet return (NULL); 926129198Scognet } 927159108Scognet vm_page_lock_queues(); 928159352Salc PMAP_LOCK(pm); 929159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 930159352Salc PMAP_UNLOCK(pm); 931159108Scognet vm_page_unlock_queues(); 932159108Scognet uma_zfree(l2table_zone, l2); 933159108Scognet vm_page_lock_queues(); 934159352Salc PMAP_LOCK(pm); 935159108Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 936159108Scognet if (l2 == NULL) 937159108Scognet goto again_l2table; 938159108Scognet /* 939159108Scognet * Someone already allocated the l2_dtable while 940159108Scognet * we were doing the same. 941159108Scognet */ 942159108Scognet } else { 943159108Scognet bzero(l2, sizeof(*l2)); 944159108Scognet /* 945159108Scognet * Link it into the parent pmap 946159108Scognet */ 947159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 948159108Scognet } 949129198Scognet } 950129198Scognet 951129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 952129198Scognet 953129198Scognet /* 954129198Scognet * Fetch pointer to the L2 page table associated with the address. 955129198Scognet */ 956129198Scognet if (l2b->l2b_kva == NULL) { 957129198Scognet pt_entry_t *ptep; 958129198Scognet 959129198Scognet /* 960129198Scognet * No L2 page table has been allocated. Chances are, this 961129198Scognet * is because we just allocated the l2_dtable, above. 962129198Scognet */ 963159108Scognetagain_ptep: 964159352Salc PMAP_UNLOCK(pm); 965159108Scognet vm_page_unlock_queues(); 966160260Scognet ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE); 967159108Scognet vm_page_lock_queues(); 968159352Salc PMAP_LOCK(pm); 969159108Scognet if (l2b->l2b_kva != 0) { 970159108Scognet /* We lost the race. */ 971159352Salc PMAP_UNLOCK(pm); 972159108Scognet vm_page_unlock_queues(); 973159108Scognet uma_zfree(l2zone, ptep); 974159108Scognet vm_page_lock_queues(); 975159352Salc PMAP_LOCK(pm); 976159108Scognet if (l2b->l2b_kva == 0) 977159108Scognet goto again_ptep; 978159108Scognet return (l2b); 979159108Scognet } 980129198Scognet l2b->l2b_phys = vtophys(ptep); 981129198Scognet if (ptep == NULL) { 982129198Scognet /* 983129198Scognet * Oops, no more L2 page tables available at this 984129198Scognet * time. We may need to deallocate the l2_dtable 985129198Scognet * if we allocated a new one above. 986129198Scognet */ 987129198Scognet if (l2->l2_occupancy == 0) { 988129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 989129198Scognet pmap_free_l2_dtable(l2); 990129198Scognet } 991129198Scognet return (NULL); 992129198Scognet } 993129198Scognet 994129198Scognet l2->l2_occupancy++; 995129198Scognet l2b->l2b_kva = ptep; 996129198Scognet l2b->l2b_l1idx = l1idx; 997129198Scognet } 998129198Scognet 999129198Scognet return (l2b); 1000129198Scognet} 1001129198Scognet 1002129198Scognetstatic PMAP_INLINE void 1003129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1004129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 1005129198Scognet#else 1006129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 1007129198Scognet#endif 1008129198Scognet{ 1009129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1010129198Scognet /* 1011129198Scognet * Note: With a write-back cache, we may need to sync this 1012129198Scognet * L2 table before re-using it. 1013129198Scognet * This is because it may have belonged to a non-current 1014129198Scognet * pmap, in which case the cache syncs would have been 1015129198Scognet * skipped when the pages were being unmapped. If the 1016129198Scognet * L2 table were then to be immediately re-allocated to 1017129198Scognet * the *current* pmap, it may well contain stale mappings 1018129198Scognet * which have not yet been cleared by a cache write-back 1019129198Scognet * and so would still be visible to the mmu. 1020129198Scognet */ 1021129198Scognet if (need_sync) 1022129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1023129198Scognet#endif 1024129198Scognet uma_zfree(l2zone, l2); 1025129198Scognet} 1026129198Scognet/* 1027129198Scognet * One or more mappings in the specified L2 descriptor table have just been 1028129198Scognet * invalidated. 1029129198Scognet * 1030129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 1031129198Scognet * 1032129198Scognet * The pmap lock must be acquired when this is called (not necessary 1033129198Scognet * for the kernel pmap). 1034129198Scognet */ 1035129198Scognetstatic void 1036129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1037129198Scognet{ 1038129198Scognet struct l2_dtable *l2; 1039129198Scognet pd_entry_t *pl1pd, l1pd; 1040129198Scognet pt_entry_t *ptep; 1041129198Scognet u_short l1idx; 1042129198Scognet 1043129198Scognet 1044129198Scognet /* 1045129198Scognet * Update the bucket's reference count according to how many 1046129198Scognet * PTEs the caller has just invalidated. 1047129198Scognet */ 1048129198Scognet l2b->l2b_occupancy -= count; 1049129198Scognet 1050129198Scognet /* 1051129198Scognet * Note: 1052129198Scognet * 1053129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 1054129198Scognet * as that would require checking all Level 1 page tables and 1055129198Scognet * removing any references to the Level 2 page table. See also the 1056129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 1057129198Scognet * 1058129198Scognet * We make do with just invalidating the mapping in the L2 table. 1059129198Scognet * 1060129198Scognet * This isn't really a big deal in practice and, in fact, leads 1061129198Scognet * to a performance win over time as we don't need to continually 1062129198Scognet * alloc/free. 1063129198Scognet */ 1064129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1065129198Scognet return; 1066129198Scognet 1067129198Scognet /* 1068129198Scognet * There are no more valid mappings in this level 2 page table. 1069129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 1070129198Scognet * free the page table. 1071129198Scognet */ 1072129198Scognet l1idx = l2b->l2b_l1idx; 1073129198Scognet ptep = l2b->l2b_kva; 1074129198Scognet l2b->l2b_kva = NULL; 1075129198Scognet 1076129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1077129198Scognet 1078129198Scognet /* 1079129198Scognet * If the L1 slot matches the pmap's domain 1080129198Scognet * number, then invalidate it. 1081129198Scognet */ 1082129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1083129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1084129198Scognet *pl1pd = 0; 1085129198Scognet PTE_SYNC(pl1pd); 1086129198Scognet } 1087129198Scognet 1088129198Scognet /* 1089129198Scognet * Release the L2 descriptor table back to the pool cache. 1090129198Scognet */ 1091129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1092129198Scognet pmap_free_l2_ptp(ptep); 1093129198Scognet#else 1094135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1095129198Scognet#endif 1096129198Scognet 1097129198Scognet /* 1098129198Scognet * Update the reference count in the associated l2_dtable 1099129198Scognet */ 1100129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1101129198Scognet if (--l2->l2_occupancy > 0) 1102129198Scognet return; 1103129198Scognet 1104129198Scognet /* 1105129198Scognet * There are no more valid mappings in any of the Level 1 1106129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 1107129198Scognet * the pointer in the parent pmap and free the l2_dtable. 1108129198Scognet */ 1109129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 1110129198Scognet pmap_free_l2_dtable(l2); 1111129198Scognet} 1112129198Scognet 1113129198Scognet/* 1114129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 1115129198Scognet * structures. 1116129198Scognet */ 1117133237Scognetstatic int 1118133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1119129198Scognet{ 1120129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1121129198Scognet struct l2_bucket *l2b; 1122129198Scognet pt_entry_t *ptep, pte; 1123147417Scognet#ifdef ARM_USE_SMALL_ALLOC 1124147417Scognet pd_entry_t *pde; 1125147417Scognet#endif 1126129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1127129198Scognet 1128129198Scognet /* 1129129198Scognet * The mappings for these page tables were initially made using 1130135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1131129198Scognet * mode will not be right for page table mappings. To avoid 1132135641Scognet * polluting the pmap_kenter() code with a special case for 1133129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1134129198Scognet * correct. 1135129198Scognet */ 1136147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1137147417Scognet pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)]; 1138147417Scognet if (!l1pte_section_p(*pde)) { 1139147114Scognet#endif 1140147114Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1141147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1142147114Scognet pte = *ptep; 1143161105Scognet 1144147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1145147114Scognet /* 1146147114Scognet * Page tables must have the cache-mode set to 1147147114Scognet * Write-Thru. 1148147114Scognet */ 1149147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1150147114Scognet PTE_SYNC(ptep); 1151147114Scognet cpu_tlb_flushD_SE(va); 1152147114Scognet cpu_cpwait(); 1153147114Scognet } 1154147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1155129198Scognet } 1156129198Scognet#endif 1157147114Scognet#endif 1158129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1159129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1160133237Scognet return (0); 1161129198Scognet} 1162129198Scognet 1163129198Scognet/* 1164129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1165129198Scognet * on whether the specified pmap actually needs to be flushed at any 1166129198Scognet * given time. 1167129198Scognet */ 1168129198Scognetstatic PMAP_INLINE void 1169129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1170129198Scognet{ 1171129198Scognet 1172135641Scognet if (pmap_is_current(pm)) 1173129198Scognet cpu_tlb_flushID_SE(va); 1174129198Scognet} 1175129198Scognet 1176129198Scognetstatic PMAP_INLINE void 1177129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1178129198Scognet{ 1179129198Scognet 1180135641Scognet if (pmap_is_current(pm)) 1181129198Scognet cpu_tlb_flushD_SE(va); 1182129198Scognet} 1183129198Scognet 1184129198Scognetstatic PMAP_INLINE void 1185129198Scognetpmap_tlb_flushID(pmap_t pm) 1186129198Scognet{ 1187129198Scognet 1188135641Scognet if (pmap_is_current(pm)) 1189129198Scognet cpu_tlb_flushID(); 1190129198Scognet} 1191129198Scognetstatic PMAP_INLINE void 1192129198Scognetpmap_tlb_flushD(pmap_t pm) 1193129198Scognet{ 1194129198Scognet 1195135641Scognet if (pmap_is_current(pm)) 1196129198Scognet cpu_tlb_flushD(); 1197129198Scognet} 1198129198Scognet 1199129198Scognetstatic PMAP_INLINE void 1200129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1201129198Scognet{ 1202129198Scognet 1203135641Scognet if (pmap_is_current(pm)) 1204129198Scognet cpu_idcache_wbinv_range(va, len); 1205129198Scognet} 1206129198Scognet 1207129198Scognetstatic PMAP_INLINE void 1208129198Scognetpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, 1209129198Scognet boolean_t do_inv, boolean_t rd_only) 1210129198Scognet{ 1211129198Scognet 1212135641Scognet if (pmap_is_current(pm)) { 1213129198Scognet if (do_inv) { 1214129198Scognet if (rd_only) 1215129198Scognet cpu_dcache_inv_range(va, len); 1216129198Scognet else 1217129198Scognet cpu_dcache_wbinv_range(va, len); 1218129198Scognet } else 1219129198Scognet if (!rd_only) 1220129198Scognet cpu_dcache_wb_range(va, len); 1221129198Scognet } 1222129198Scognet} 1223129198Scognet 1224129198Scognetstatic PMAP_INLINE void 1225129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1226129198Scognet{ 1227129198Scognet 1228135641Scognet if (pmap_is_current(pm)) 1229129198Scognet cpu_idcache_wbinv_all(); 1230129198Scognet} 1231129198Scognet 1232129198Scognetstatic PMAP_INLINE void 1233129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1234129198Scognet{ 1235129198Scognet 1236135641Scognet if (pmap_is_current(pm)) 1237129198Scognet cpu_dcache_wbinv_all(); 1238129198Scognet} 1239129198Scognet 1240129198Scognet/* 1241129198Scognet * PTE_SYNC_CURRENT: 1242129198Scognet * 1243129198Scognet * Make sure the pte is written out to RAM. 1244129198Scognet * We need to do this for one of two cases: 1245129198Scognet * - We're dealing with the kernel pmap 1246129198Scognet * - There is no pmap active in the cache/tlb. 1247129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1248129198Scognet */ 1249129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1250129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1251129198Scognetdo { \ 1252129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1253135641Scognet pmap_is_current(pm)) \ 1254129198Scognet PTE_SYNC(ptep); \ 1255129198Scognet} while (/*CONSTCOND*/0) 1256129198Scognet#else 1257129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1258129198Scognet#endif 1259129198Scognet 1260129198Scognet/* 1261129198Scognet * Since we have a virtually indexed cache, we may need to inhibit caching if 1262129198Scognet * there is more than one mapping and at least one of them is writable. 1263129198Scognet * Since we purge the cache on every context switch, we only need to check for 1264129198Scognet * other mappings within the same pmap, or kernel_pmap. 1265129198Scognet * This function is also called when a page is unmapped, to possibly reenable 1266129198Scognet * caching on any remaining mappings. 1267129198Scognet * 1268129198Scognet * The code implements the following logic, where: 1269129198Scognet * 1270129198Scognet * KW = # of kernel read/write pages 1271129198Scognet * KR = # of kernel read only pages 1272129198Scognet * UW = # of user read/write pages 1273129198Scognet * UR = # of user read only pages 1274129198Scognet * 1275129198Scognet * KC = kernel mapping is cacheable 1276129198Scognet * UC = user mapping is cacheable 1277129198Scognet * 1278129198Scognet * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1279129198Scognet * +--------------------------------------------- 1280129198Scognet * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1281129198Scognet * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1282129198Scognet * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1283129198Scognet * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1284129198Scognet */ 1285129198Scognet 1286129198Scognetstatic const int pmap_vac_flags[4][4] = { 1287129198Scognet {-1, 0, 0, PVF_KNC}, 1288129198Scognet {0, 0, PVF_NC, PVF_NC}, 1289129198Scognet {0, PVF_NC, PVF_NC, PVF_NC}, 1290129198Scognet {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1291129198Scognet}; 1292129198Scognet 1293129198Scognetstatic PMAP_INLINE int 1294129198Scognetpmap_get_vac_flags(const struct vm_page *pg) 1295129198Scognet{ 1296129198Scognet int kidx, uidx; 1297129198Scognet 1298129198Scognet kidx = 0; 1299129198Scognet if (pg->md.kro_mappings || pg->md.krw_mappings > 1) 1300129198Scognet kidx |= 1; 1301129198Scognet if (pg->md.krw_mappings) 1302129198Scognet kidx |= 2; 1303129198Scognet 1304129198Scognet uidx = 0; 1305129198Scognet if (pg->md.uro_mappings || pg->md.urw_mappings > 1) 1306129198Scognet uidx |= 1; 1307129198Scognet if (pg->md.urw_mappings) 1308129198Scognet uidx |= 2; 1309129198Scognet 1310129198Scognet return (pmap_vac_flags[uidx][kidx]); 1311129198Scognet} 1312129198Scognet 1313129198Scognetstatic __inline void 1314129198Scognetpmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1315129198Scognet{ 1316129198Scognet int nattr; 1317129198Scognet 1318159384Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1319129198Scognet nattr = pmap_get_vac_flags(pg); 1320129198Scognet 1321129198Scognet if (nattr < 0) { 1322129198Scognet pg->md.pvh_attrs &= ~PVF_NC; 1323129198Scognet return; 1324129198Scognet } 1325129198Scognet 1326129198Scognet if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) { 1327129198Scognet return; 1328129198Scognet } 1329129198Scognet 1330129198Scognet if (pm == pmap_kernel()) 1331129198Scognet pmap_vac_me_kpmap(pg, pm, va); 1332129198Scognet else 1333129198Scognet pmap_vac_me_user(pg, pm, va); 1334129198Scognet 1335129198Scognet pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr; 1336129198Scognet} 1337129198Scognet 1338129198Scognetstatic void 1339129198Scognetpmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1340129198Scognet{ 1341129198Scognet u_int u_cacheable, u_entries; 1342129198Scognet struct pv_entry *pv; 1343129198Scognet pmap_t last_pmap = pm; 1344129198Scognet 1345129198Scognet /* 1346129198Scognet * Pass one, see if there are both kernel and user pmaps for 1347129198Scognet * this page. Calculate whether there are user-writable or 1348129198Scognet * kernel-writable pages. 1349129198Scognet */ 1350129198Scognet u_cacheable = 0; 1351129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1352129198Scognet if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1353129198Scognet u_cacheable++; 1354129198Scognet } 1355129198Scognet 1356129198Scognet u_entries = pg->md.urw_mappings + pg->md.uro_mappings; 1357129198Scognet 1358129198Scognet /* 1359129198Scognet * We know we have just been updating a kernel entry, so if 1360129198Scognet * all user pages are already cacheable, then there is nothing 1361129198Scognet * further to do. 1362129198Scognet */ 1363129198Scognet if (pg->md.k_mappings == 0 && u_cacheable == u_entries) 1364129198Scognet return; 1365129198Scognet 1366129198Scognet if (u_entries) { 1367129198Scognet /* 1368129198Scognet * Scan over the list again, for each entry, if it 1369129198Scognet * might not be set correctly, call pmap_vac_me_user 1370129198Scognet * to recalculate the settings. 1371129198Scognet */ 1372129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1373129198Scognet /* 1374129198Scognet * We know kernel mappings will get set 1375129198Scognet * correctly in other calls. We also know 1376129198Scognet * that if the pmap is the same as last_pmap 1377129198Scognet * then we've just handled this entry. 1378129198Scognet */ 1379129198Scognet if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1380129198Scognet continue; 1381129198Scognet 1382129198Scognet /* 1383129198Scognet * If there are kernel entries and this page 1384129198Scognet * is writable but non-cacheable, then we can 1385129198Scognet * skip this entry also. 1386129198Scognet */ 1387129198Scognet if (pg->md.k_mappings && 1388129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1389129198Scognet (PVF_NC | PVF_WRITE)) 1390129198Scognet continue; 1391129198Scognet 1392129198Scognet /* 1393129198Scognet * Similarly if there are no kernel-writable 1394129198Scognet * entries and the page is already 1395129198Scognet * read-only/cacheable. 1396129198Scognet */ 1397129198Scognet if (pg->md.krw_mappings == 0 && 1398129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1399129198Scognet continue; 1400129198Scognet 1401129198Scognet /* 1402129198Scognet * For some of the remaining cases, we know 1403129198Scognet * that we must recalculate, but for others we 1404129198Scognet * can't tell if they are correct or not, so 1405129198Scognet * we recalculate anyway. 1406129198Scognet */ 1407129198Scognet pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1408129198Scognet } 1409129198Scognet 1410129198Scognet if (pg->md.k_mappings == 0) 1411129198Scognet return; 1412129198Scognet } 1413129198Scognet 1414129198Scognet pmap_vac_me_user(pg, pm, va); 1415129198Scognet} 1416129198Scognet 1417129198Scognetstatic void 1418129198Scognetpmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1419129198Scognet{ 1420129198Scognet pmap_t kpmap = pmap_kernel(); 1421129198Scognet struct pv_entry *pv, *npv; 1422129198Scognet struct l2_bucket *l2b; 1423129198Scognet pt_entry_t *ptep, pte; 1424129198Scognet u_int entries = 0; 1425129198Scognet u_int writable = 0; 1426129198Scognet u_int cacheable_entries = 0; 1427129198Scognet u_int kern_cacheable = 0; 1428129198Scognet u_int other_writable = 0; 1429129198Scognet 1430129198Scognet /* 1431129198Scognet * Count mappings and writable mappings in this pmap. 1432129198Scognet * Include kernel mappings as part of our own. 1433129198Scognet * Keep a pointer to the first one. 1434129198Scognet */ 1435129198Scognet npv = TAILQ_FIRST(&pg->md.pv_list); 1436129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1437129198Scognet /* Count mappings in the same pmap */ 1438129198Scognet if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1439129198Scognet if (entries++ == 0) 1440129198Scognet npv = pv; 1441129198Scognet 1442129198Scognet /* Cacheable mappings */ 1443129198Scognet if ((pv->pv_flags & PVF_NC) == 0) { 1444129198Scognet cacheable_entries++; 1445129198Scognet if (kpmap == pv->pv_pmap) 1446129198Scognet kern_cacheable++; 1447129198Scognet } 1448129198Scognet 1449129198Scognet /* Writable mappings */ 1450129198Scognet if (pv->pv_flags & PVF_WRITE) 1451129198Scognet ++writable; 1452129198Scognet } else 1453129198Scognet if (pv->pv_flags & PVF_WRITE) 1454129198Scognet other_writable = 1; 1455129198Scognet } 1456129198Scognet 1457129198Scognet /* 1458129198Scognet * Enable or disable caching as necessary. 1459129198Scognet * Note: the first entry might be part of the kernel pmap, 1460129198Scognet * so we can't assume this is indicative of the state of the 1461129198Scognet * other (maybe non-kpmap) entries. 1462129198Scognet */ 1463129198Scognet if ((entries > 1 && writable) || 1464129198Scognet (entries > 0 && pm == kpmap && other_writable)) { 1465129198Scognet if (cacheable_entries == 0) 1466129198Scognet return; 1467129198Scognet 1468129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1469129198Scognet if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1470129198Scognet (pv->pv_flags & PVF_NC)) 1471129198Scognet continue; 1472129198Scognet 1473129198Scognet pv->pv_flags |= PVF_NC; 1474129198Scognet 1475129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1476129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1477129198Scognet pte = *ptep & ~L2_S_CACHE_MASK; 1478129198Scognet 1479129198Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1480129198Scognet l2pte_valid(pte)) { 1481129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1482129198Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1483129198Scognet pv->pv_va, PAGE_SIZE); 1484129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1485129198Scognet pv->pv_va); 1486129198Scognet } else 1487129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1488129198Scognet pmap_dcache_wb_range(pv->pv_pmap, 1489129198Scognet pv->pv_va, PAGE_SIZE, TRUE, 1490129198Scognet (pv->pv_flags & PVF_WRITE) == 0); 1491129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1492129198Scognet pv->pv_va); 1493129198Scognet } 1494129198Scognet } 1495129198Scognet 1496129198Scognet *ptep = pte; 1497129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1498129198Scognet } 1499129198Scognet cpu_cpwait(); 1500129198Scognet } else 1501129198Scognet if (entries > cacheable_entries) { 1502129198Scognet /* 1503129198Scognet * Turn cacheing back on for some pages. If it is a kernel 1504129198Scognet * page, only do so if there are no other writable pages. 1505129198Scognet */ 1506129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1507129198Scognet if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1508129198Scognet (kpmap != pv->pv_pmap || other_writable))) 1509129198Scognet continue; 1510129198Scognet 1511129198Scognet pv->pv_flags &= ~PVF_NC; 1512129198Scognet 1513129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1514129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1515129198Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1516129198Scognet 1517129198Scognet if (l2pte_valid(pte)) { 1518129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1519129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1520129198Scognet pv->pv_va); 1521129198Scognet } else 1522129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1523129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1524129198Scognet pv->pv_va); 1525129198Scognet } 1526129198Scognet } 1527129198Scognet 1528129198Scognet *ptep = pte; 1529129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1530129198Scognet } 1531129198Scognet } 1532129198Scognet} 1533129198Scognet 1534129198Scognet/* 1535129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1536129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1537129198Scognet * constants and the latter would require an extra inversion at run-time. 1538129198Scognet */ 1539135641Scognetstatic int 1540129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1541129198Scognet{ 1542129198Scognet struct l2_bucket *l2b; 1543129198Scognet struct pv_entry *pv; 1544129198Scognet pt_entry_t *ptep, npte, opte; 1545129198Scognet pmap_t pm; 1546129198Scognet vm_offset_t va; 1547129198Scognet u_int oflags; 1548135641Scognet int count = 0; 1549129198Scognet 1550159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1551159352Salc 1552129198Scognet /* 1553129198Scognet * Clear saved attributes (modify, reference) 1554129198Scognet */ 1555129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1556129198Scognet 1557129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1558135641Scognet return (0); 1559129198Scognet } 1560129198Scognet 1561129198Scognet /* 1562129198Scognet * Loop over all current mappings setting/clearing as appropos 1563129198Scognet */ 1564129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1565129198Scognet va = pv->pv_va; 1566129198Scognet pm = pv->pv_pmap; 1567129198Scognet oflags = pv->pv_flags; 1568129198Scognet pv->pv_flags &= ~maskbits; 1569129198Scognet 1570159352Salc PMAP_LOCK(pm); 1571129198Scognet 1572129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1573129198Scognet 1574129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1575129198Scognet npte = opte = *ptep; 1576129198Scognet 1577157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1578129198Scognet if ((pv->pv_flags & PVF_NC)) { 1579129198Scognet /* 1580129198Scognet * Entry is not cacheable: 1581129198Scognet * 1582129198Scognet * Don't turn caching on again if this is a 1583129198Scognet * modified emulation. This would be 1584129198Scognet * inconsitent with the settings created by 1585129198Scognet * pmap_vac_me_harder(). Otherwise, it's safe 1586129198Scognet * to re-enable cacheing. 1587129198Scognet * 1588129198Scognet * There's no need to call pmap_vac_me_harder() 1589129198Scognet * here: all pages are losing their write 1590129198Scognet * permission. 1591129198Scognet */ 1592129198Scognet if (maskbits & PVF_WRITE) { 1593129198Scognet npte |= pte_l2_s_cache_mode; 1594129198Scognet pv->pv_flags &= ~PVF_NC; 1595129198Scognet } 1596129198Scognet } else 1597129198Scognet if (opte & L2_S_PROT_W) { 1598144760Scognet vm_page_dirty(pg); 1599129198Scognet /* 1600129198Scognet * Entry is writable/cacheable: check if pmap 1601129198Scognet * is current if it is flush it, otherwise it 1602129198Scognet * won't be in the cache 1603129198Scognet */ 1604129198Scognet if (PV_BEEN_EXECD(oflags)) 1605129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1606129198Scognet PAGE_SIZE); 1607129198Scognet else 1608129198Scognet if (PV_BEEN_REFD(oflags)) 1609129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1610129198Scognet PAGE_SIZE, 1611129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1612129198Scognet FALSE); 1613129198Scognet } 1614129198Scognet 1615129198Scognet /* make the pte read only */ 1616129198Scognet npte &= ~L2_S_PROT_W; 1617129198Scognet 1618129198Scognet if (maskbits & PVF_WRITE) { 1619129198Scognet /* 1620129198Scognet * Keep alias accounting up to date 1621129198Scognet */ 1622129198Scognet if (pv->pv_pmap == pmap_kernel()) { 1623129198Scognet if (oflags & PVF_WRITE) { 1624129198Scognet pg->md.krw_mappings--; 1625129198Scognet pg->md.kro_mappings++; 1626129198Scognet } 1627129198Scognet } else 1628129198Scognet if (oflags & PVF_WRITE) { 1629129198Scognet pg->md.urw_mappings--; 1630129198Scognet pg->md.uro_mappings++; 1631129198Scognet } 1632129198Scognet } 1633129198Scognet } 1634129198Scognet 1635157970Scognet if (maskbits & PVF_REF) { 1636129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1637129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1638129198Scognet /* 1639129198Scognet * Check npte here; we may have already 1640129198Scognet * done the wbinv above, and the validity 1641129198Scognet * of the PTE is the same for opte and 1642129198Scognet * npte. 1643129198Scognet */ 1644129198Scognet if (npte & L2_S_PROT_W) { 1645129198Scognet if (PV_BEEN_EXECD(oflags)) 1646129198Scognet pmap_idcache_wbinv_range(pm, 1647129198Scognet pv->pv_va, PAGE_SIZE); 1648129198Scognet else 1649129198Scognet if (PV_BEEN_REFD(oflags)) 1650129198Scognet pmap_dcache_wb_range(pm, 1651129198Scognet pv->pv_va, PAGE_SIZE, 1652129198Scognet TRUE, FALSE); 1653129198Scognet } else 1654129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1655129198Scognet /* XXXJRT need idcache_inv_range */ 1656129198Scognet if (PV_BEEN_EXECD(oflags)) 1657129198Scognet pmap_idcache_wbinv_range(pm, 1658129198Scognet pv->pv_va, PAGE_SIZE); 1659129198Scognet else 1660129198Scognet if (PV_BEEN_REFD(oflags)) 1661129198Scognet pmap_dcache_wb_range(pm, 1662129198Scognet pv->pv_va, PAGE_SIZE, 1663129198Scognet TRUE, TRUE); 1664129198Scognet } 1665129198Scognet } 1666129198Scognet 1667129198Scognet /* 1668129198Scognet * Make the PTE invalid so that we will take a 1669129198Scognet * page fault the next time the mapping is 1670129198Scognet * referenced. 1671129198Scognet */ 1672129198Scognet npte &= ~L2_TYPE_MASK; 1673129198Scognet npte |= L2_TYPE_INV; 1674129198Scognet } 1675129198Scognet 1676129198Scognet if (npte != opte) { 1677135641Scognet count++; 1678129198Scognet *ptep = npte; 1679129198Scognet PTE_SYNC(ptep); 1680129198Scognet /* Flush the TLB entry if a current pmap. */ 1681129198Scognet if (PV_BEEN_EXECD(oflags)) 1682129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1683129198Scognet else 1684129198Scognet if (PV_BEEN_REFD(oflags)) 1685129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1686129198Scognet } 1687129198Scognet 1688159352Salc PMAP_UNLOCK(pm); 1689129198Scognet 1690129198Scognet } 1691129198Scognet 1692137664Scognet if (maskbits & PVF_WRITE) 1693137664Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1694135641Scognet return (count); 1695129198Scognet} 1696129198Scognet 1697129198Scognet/* 1698129198Scognet * main pv_entry manipulation functions: 1699129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1700129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1701129198Scognet * 1702129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1703129198Scognet * pmap_remove_pv expects te caller to lock the pvh before calling 1704129198Scognet */ 1705129198Scognet 1706129198Scognet/* 1707129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page lst 1708129198Scognet * 1709129198Scognet * => caller should hold the proper lock on pmap_main_lock 1710129198Scognet * => caller should have pmap locked 1711129198Scognet * => we will gain the lock on the vm_page and allocate the new pv_entry 1712129198Scognet * => caller should adjust ptp's wire_count before calling 1713129198Scognet * => caller should not adjust pmap's wire_count 1714129198Scognet */ 1715129198Scognetstatic void 1716129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1717129198Scognet vm_offset_t va, u_int flags) 1718129198Scognet{ 1719129198Scognet 1720159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1721159352Salc PMAP_ASSERT_LOCKED(pm); 1722129198Scognet pve->pv_pmap = pm; 1723129198Scognet pve->pv_va = va; 1724129198Scognet pve->pv_flags = flags; 1725129198Scognet 1726129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1727144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1728129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1729129198Scognet if (pm == pmap_kernel()) { 1730129198Scognet if (flags & PVF_WRITE) 1731129198Scognet pg->md.krw_mappings++; 1732129198Scognet else 1733129198Scognet pg->md.kro_mappings++; 1734129198Scognet } 1735129198Scognet if (flags & PVF_WRITE) 1736129198Scognet pg->md.urw_mappings++; 1737129198Scognet else 1738129198Scognet pg->md.uro_mappings++; 1739135641Scognet pg->md.pv_list_count++; 1740129198Scognet if (pve->pv_flags & PVF_WIRED) 1741129198Scognet ++pm->pm_stats.wired_count; 1742144760Scognet vm_page_flag_set(pg, PG_REFERENCED); 1743129198Scognet} 1744129198Scognet 1745129198Scognet/* 1746129198Scognet * 1747129198Scognet * pmap_find_pv: Find a pv entry 1748129198Scognet * 1749129198Scognet * => caller should hold lock on vm_page 1750129198Scognet */ 1751129198Scognetstatic PMAP_INLINE struct pv_entry * 1752129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1753129198Scognet{ 1754129198Scognet struct pv_entry *pv; 1755129198Scognet 1756159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1757129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1758129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1759129198Scognet break; 1760129198Scognet return (pv); 1761129198Scognet} 1762129198Scognet 1763129198Scognet/* 1764129198Scognet * vector_page_setprot: 1765129198Scognet * 1766129198Scognet * Manipulate the protection of the vector page. 1767129198Scognet */ 1768129198Scognetvoid 1769129198Scognetvector_page_setprot(int prot) 1770129198Scognet{ 1771129198Scognet struct l2_bucket *l2b; 1772129198Scognet pt_entry_t *ptep; 1773129198Scognet 1774129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1775129198Scognet 1776129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1777129198Scognet 1778129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1779129198Scognet PTE_SYNC(ptep); 1780129198Scognet cpu_tlb_flushD_SE(vector_page); 1781129198Scognet cpu_cpwait(); 1782129198Scognet} 1783129198Scognet 1784129198Scognet/* 1785129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1786129198Scognet * 1787129198Scognet * => caller should hold proper lock on pmap_main_lock 1788129198Scognet * => pmap should be locked 1789129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1790129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1791129198Scognet * => caller should NOT adjust pmap's wire_count 1792129198Scognet * => we return the removed pve 1793129198Scognet */ 1794135641Scognet 1795135641Scognetstatic void 1796135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1797135641Scognet{ 1798135641Scognet 1799159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1800159352Salc PMAP_ASSERT_LOCKED(pm); 1801135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1802144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1803135641Scognet if (pve->pv_flags & PVF_WIRED) 1804135641Scognet --pm->pm_stats.wired_count; 1805135641Scognet pg->md.pv_list_count--; 1806144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1807144760Scognet vm_page_dirty(pg); 1808135641Scognet if (pm == pmap_kernel()) { 1809135641Scognet if (pve->pv_flags & PVF_WRITE) 1810135641Scognet pg->md.krw_mappings--; 1811135641Scognet else 1812135641Scognet pg->md.kro_mappings--; 1813135641Scognet } else 1814135641Scognet if (pve->pv_flags & PVF_WRITE) 1815135641Scognet pg->md.urw_mappings--; 1816135641Scognet else 1817135641Scognet pg->md.uro_mappings--; 1818144760Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL || 1819144760Scognet (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) { 1820144760Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1821144760Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1822144760Scognet pg->md.pvh_attrs &= ~PVF_REF; 1823137664Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1824146647Scognet } 1825144760Scognet if (TAILQ_FIRST(&pg->md.pv_list)) 1826144760Scognet vm_page_flag_set(pg, PG_REFERENCED); 1827144760Scognet if (pve->pv_flags & PVF_WRITE) 1828144760Scognet pmap_vac_me_harder(pg, pm, 0); 1829135641Scognet} 1830135641Scognet 1831129198Scognetstatic struct pv_entry * 1832129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1833129198Scognet{ 1834135641Scognet struct pv_entry *pve; 1835129198Scognet 1836159474Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1837135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1838129198Scognet 1839129198Scognet while (pve) { 1840129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1841135641Scognet pmap_nuke_pv(pg, pm, pve); 1842129198Scognet break; 1843129198Scognet } 1844129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1845129198Scognet } 1846129198Scognet 1847129198Scognet return(pve); /* return removed pve */ 1848129198Scognet} 1849129198Scognet/* 1850129198Scognet * 1851129198Scognet * pmap_modify_pv: Update pv flags 1852129198Scognet * 1853129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1854129198Scognet * => caller should NOT adjust pmap's wire_count 1855129198Scognet * => caller must call pmap_vac_me_harder() if writable status of a page 1856129198Scognet * may have changed. 1857129198Scognet * => we return the old flags 1858129198Scognet * 1859129198Scognet * Modify a physical-virtual mapping in the pv table 1860129198Scognet */ 1861129198Scognetstatic u_int 1862129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1863129198Scognet u_int clr_mask, u_int set_mask) 1864129198Scognet{ 1865129198Scognet struct pv_entry *npv; 1866129198Scognet u_int flags, oflags; 1867129198Scognet 1868159352Salc PMAP_ASSERT_LOCKED(pm); 1869159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1870129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1871129198Scognet return (0); 1872129198Scognet 1873129198Scognet /* 1874129198Scognet * There is at least one VA mapping this page. 1875129198Scognet */ 1876129198Scognet 1877129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1878129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1879129198Scognet 1880129198Scognet oflags = npv->pv_flags; 1881129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1882129198Scognet 1883129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1884129198Scognet if (flags & PVF_WIRED) 1885129198Scognet ++pm->pm_stats.wired_count; 1886129198Scognet else 1887129198Scognet --pm->pm_stats.wired_count; 1888129198Scognet } 1889129198Scognet 1890129198Scognet if ((flags ^ oflags) & PVF_WRITE) { 1891129198Scognet if (pm == pmap_kernel()) { 1892129198Scognet if (flags & PVF_WRITE) { 1893129198Scognet pg->md.krw_mappings++; 1894129198Scognet pg->md.kro_mappings--; 1895129198Scognet } else { 1896129198Scognet pg->md.kro_mappings++; 1897129198Scognet pg->md.krw_mappings--; 1898129198Scognet } 1899129198Scognet } else 1900129198Scognet if (flags & PVF_WRITE) { 1901129198Scognet pg->md.urw_mappings++; 1902129198Scognet pg->md.uro_mappings--; 1903129198Scognet } else { 1904129198Scognet pg->md.uro_mappings++; 1905129198Scognet pg->md.urw_mappings--; 1906129198Scognet } 1907144760Scognet if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) { 1908144760Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1909144760Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1910144760Scognet } 1911144760Scognet pmap_vac_me_harder(pg, pm, 0); 1912129198Scognet } 1913129198Scognet 1914129198Scognet return (oflags); 1915129198Scognet} 1916129198Scognet 1917129198Scognet/* Function to set the debug level of the pmap code */ 1918129198Scognet#ifdef PMAP_DEBUG 1919129198Scognetvoid 1920129198Scognetpmap_debug(int level) 1921129198Scognet{ 1922129198Scognet pmap_debug_level = level; 1923129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1924129198Scognet} 1925129198Scognet#endif /* PMAP_DEBUG */ 1926129198Scognet 1927129198Scognetvoid 1928129198Scognetpmap_pinit0(struct pmap *pmap) 1929129198Scognet{ 1930129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1931129198Scognet 1932129198Scognet dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1933129198Scognet (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1934135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1935159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1936159325Salc PMAP_LOCK_INIT(pmap); 1937129198Scognet} 1938129198Scognet 1939147217Salc/* 1940147217Salc * Initialize a vm_page's machine-dependent fields. 1941147217Salc */ 1942147217Salcvoid 1943147217Salcpmap_page_init(vm_page_t m) 1944147217Salc{ 1945129198Scognet 1946147217Salc TAILQ_INIT(&m->md.pv_list); 1947147217Salc m->md.pv_list_count = 0; 1948147217Salc} 1949147217Salc 1950129198Scognet/* 1951129198Scognet * Initialize the pmap module. 1952129198Scognet * Called by vm_init, to initialize any structures that the pmap 1953129198Scognet * system needs to map virtual memory. 1954129198Scognet */ 1955129198Scognetvoid 1956129198Scognetpmap_init(void) 1957129198Scognet{ 1958152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1959129198Scognet 1960129198Scognet PDEBUG(1, printf("pmap_init: phys_start = %08x\n")); 1961147114Scognet 1962129198Scognet /* 1963129198Scognet * init the pv free list 1964129198Scognet */ 1965129198Scognet pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1966129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1967129198Scognet /* 1968129198Scognet * Now it is safe to enable pv_table recording. 1969129198Scognet */ 1970129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1971147114Scognet 1972152128Scognet TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1973152128Scognet 1974164090Salc pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1975152128Scognet pv_entry_high_water = 9 * (pv_entry_max / 10); 1976152128Scognet l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1977152128Scognet NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1978152128Scognet l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 1979152128Scognet NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1980152128Scognet UMA_ZONE_VM | UMA_ZONE_NOFREE); 1981152128Scognet 1982152128Scognet uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1983152128Scognet 1984129198Scognet} 1985129198Scognet 1986129198Scognetint 1987129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1988129198Scognet{ 1989129198Scognet struct l2_dtable *l2; 1990129198Scognet struct l2_bucket *l2b; 1991129198Scognet pd_entry_t *pl1pd, l1pd; 1992129198Scognet pt_entry_t *ptep, pte; 1993129198Scognet vm_paddr_t pa; 1994129198Scognet u_int l1idx; 1995129198Scognet int rv = 0; 1996129198Scognet 1997129198Scognet l1idx = L1_IDX(va); 1998159384Salc vm_page_lock_queues(); 1999159384Salc PMAP_LOCK(pm); 2000129198Scognet 2001129198Scognet /* 2002129198Scognet * If there is no l2_dtable for this address, then the process 2003129198Scognet * has no business accessing it. 2004129198Scognet * 2005129198Scognet * Note: This will catch userland processes trying to access 2006129198Scognet * kernel addresses. 2007129198Scognet */ 2008129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 2009129198Scognet if (l2 == NULL) 2010129198Scognet goto out; 2011129198Scognet 2012129198Scognet /* 2013129198Scognet * Likewise if there is no L2 descriptor table 2014129198Scognet */ 2015129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2016129198Scognet if (l2b->l2b_kva == NULL) 2017129198Scognet goto out; 2018129198Scognet 2019129198Scognet /* 2020129198Scognet * Check the PTE itself. 2021129198Scognet */ 2022129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2023129198Scognet pte = *ptep; 2024129198Scognet if (pte == 0) 2025129198Scognet goto out; 2026129198Scognet 2027129198Scognet /* 2028129198Scognet * Catch a userland access to the vector page mapped at 0x0 2029129198Scognet */ 2030129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 2031129198Scognet goto out; 2032157027Scognet if (va == vector_page) 2033157027Scognet goto out; 2034129198Scognet 2035129198Scognet pa = l2pte_pa(pte); 2036129198Scognet 2037129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2038129198Scognet /* 2039129198Scognet * This looks like a good candidate for "page modified" 2040129198Scognet * emulation... 2041129198Scognet */ 2042129198Scognet struct pv_entry *pv; 2043129198Scognet struct vm_page *pg; 2044129198Scognet 2045129198Scognet /* Extract the physical address of the page */ 2046129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 2047129198Scognet goto out; 2048129198Scognet } 2049129198Scognet /* Get the current flags for this page. */ 2050129198Scognet 2051129198Scognet pv = pmap_find_pv(pg, pm, va); 2052129198Scognet if (pv == NULL) { 2053129198Scognet goto out; 2054129198Scognet } 2055129198Scognet 2056129198Scognet /* 2057129198Scognet * Do the flags say this page is writable? If not then it 2058129198Scognet * is a genuine write fault. If yes then the write fault is 2059129198Scognet * our fault as we did not reflect the write access in the 2060129198Scognet * PTE. Now we know a write has occurred we can correct this 2061129198Scognet * and also set the modified bit 2062129198Scognet */ 2063129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 2064129198Scognet goto out; 2065129198Scognet } 2066129198Scognet 2067157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 2068157970Scognet vm_page_dirty(pg); 2069129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 2070129198Scognet 2071129198Scognet /* 2072129198Scognet * Re-enable write permissions for the page. No need to call 2073129198Scognet * pmap_vac_me_harder(), since this is just a 2074129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 2075129198Scognet * changing. We've already set the cacheable bits based on 2076129198Scognet * the assumption that we can write to this page. 2077129198Scognet */ 2078147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2079129198Scognet PTE_SYNC(ptep); 2080129198Scognet rv = 1; 2081129198Scognet } else 2082129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2083129198Scognet /* 2084129198Scognet * This looks like a good candidate for "page referenced" 2085129198Scognet * emulation. 2086129198Scognet */ 2087129198Scognet struct pv_entry *pv; 2088129198Scognet struct vm_page *pg; 2089129198Scognet 2090129198Scognet /* Extract the physical address of the page */ 2091159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2092129198Scognet goto out; 2093129198Scognet /* Get the current flags for this page. */ 2094129198Scognet 2095129198Scognet pv = pmap_find_pv(pg, pm, va); 2096159384Salc if (pv == NULL) 2097129198Scognet goto out; 2098129198Scognet 2099129198Scognet pg->md.pvh_attrs |= PVF_REF; 2100129198Scognet pv->pv_flags |= PVF_REF; 2101129198Scognet 2102129198Scognet 2103129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2104129198Scognet PTE_SYNC(ptep); 2105129198Scognet rv = 1; 2106129198Scognet } 2107129198Scognet 2108129198Scognet /* 2109129198Scognet * We know there is a valid mapping here, so simply 2110129198Scognet * fix up the L1 if necessary. 2111129198Scognet */ 2112129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2113129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2114129198Scognet if (*pl1pd != l1pd) { 2115129198Scognet *pl1pd = l1pd; 2116129198Scognet PTE_SYNC(pl1pd); 2117129198Scognet rv = 1; 2118129198Scognet } 2119129198Scognet 2120129198Scognet#ifdef CPU_SA110 2121129198Scognet /* 2122129198Scognet * There are bugs in the rev K SA110. This is a check for one 2123129198Scognet * of them. 2124129198Scognet */ 2125129198Scognet if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2126129198Scognet curcpu()->ci_arm_cpurev < 3) { 2127129198Scognet /* Always current pmap */ 2128129198Scognet if (l2pte_valid(pte)) { 2129129198Scognet extern int kernel_debug; 2130129198Scognet if (kernel_debug & 1) { 2131129198Scognet struct proc *p = curlwp->l_proc; 2132129198Scognet printf("prefetch_abort: page is already " 2133129198Scognet "mapped - pte=%p *pte=%08x\n", ptep, pte); 2134129198Scognet printf("prefetch_abort: pc=%08lx proc=%p " 2135129198Scognet "process=%s\n", va, p, p->p_comm); 2136129198Scognet printf("prefetch_abort: far=%08x fs=%x\n", 2137129198Scognet cpu_faultaddress(), cpu_faultstatus()); 2138129198Scognet } 2139129198Scognet#ifdef DDB 2140129198Scognet if (kernel_debug & 2) 2141129198Scognet Debugger(); 2142129198Scognet#endif 2143129198Scognet rv = 1; 2144129198Scognet } 2145129198Scognet } 2146129198Scognet#endif /* CPU_SA110 */ 2147129198Scognet 2148129198Scognet#ifdef DEBUG 2149129198Scognet /* 2150129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 2151129198Scognet * stale TLB entry for the faulting address. This happens when two or 2152129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 2153129198Scognet * a context switch between such processes, we can take domain faults 2154129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 2155129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2156129198Scognet * example. 2157129198Scognet * 2158129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 2159129198Scognet * entry for a recently entered mapping. In this case, the TLB is 2160129198Scognet * flushed for the new mapping, but there may still be TLB entries for 2161129198Scognet * other mappings belonging to other processes in the 1MB range 2162129198Scognet * covered by the L1 entry. 2163129198Scognet * 2164129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 2165129198Scognet * value, so the fault must be due to a stale TLB entry. 2166129198Scognet * 2167129198Scognet * Since we always need to flush the TLB anyway in the case where we 2168129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2169129198Scognet * stale TLB entries dynamically. 2170129198Scognet * 2171129198Scognet * However, the above condition can ONLY happen if the current L1 is 2172129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 2173129198Scognet * that other parts of the pmap are not doing their job WRT managing 2174129198Scognet * the TLB. 2175129198Scognet */ 2176129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2177129198Scognet extern int last_fault_code; 2178129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2179129198Scognet pm, va, ftype); 2180129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2181129198Scognet l2, l2b, ptep, pl1pd); 2182129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2183129198Scognet pte, l1pd, last_fault_code); 2184129198Scognet#ifdef DDB 2185129198Scognet Debugger(); 2186129198Scognet#endif 2187129198Scognet } 2188129198Scognet#endif 2189129198Scognet 2190129198Scognet cpu_tlb_flushID_SE(va); 2191129198Scognet cpu_cpwait(); 2192129198Scognet 2193129198Scognet rv = 1; 2194129198Scognet 2195129198Scognetout: 2196159384Salc vm_page_unlock_queues(); 2197159384Salc PMAP_UNLOCK(pm); 2198129198Scognet return (rv); 2199129198Scognet} 2200129198Scognet 2201129198Scognetvoid 2202152128Scognetpmap_postinit(void) 2203152128Scognet{ 2204129198Scognet struct l2_bucket *l2b; 2205129198Scognet struct l1_ttable *l1; 2206129198Scognet pd_entry_t *pl1pt; 2207129198Scognet pt_entry_t *ptep, pte; 2208129198Scognet vm_offset_t va, eva; 2209129198Scognet u_int loop, needed; 2210129198Scognet 2211129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2212129198Scognet needed -= 1; 2213129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2214129198Scognet 2215129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 2216129198Scognet /* Allocate a L1 page table */ 2217132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2218132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 2219129198Scognet 2220129198Scognet if (va == 0) 2221129198Scognet panic("Cannot allocate L1 KVM"); 2222129198Scognet 2223129198Scognet eva = va + L1_TABLE_SIZE; 2224129198Scognet pl1pt = (pd_entry_t *)va; 2225129198Scognet 2226135641Scognet while (va < eva) { 2227129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2228129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2229129198Scognet pte = *ptep; 2230129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2231129198Scognet *ptep = pte; 2232129198Scognet PTE_SYNC(ptep); 2233129198Scognet cpu_tlb_flushD_SE(va); 2234129198Scognet 2235129198Scognet va += PAGE_SIZE; 2236129198Scognet } 2237129198Scognet pmap_init_l1(l1, pl1pt); 2238129198Scognet } 2239129198Scognet 2240129198Scognet 2241129198Scognet#ifdef DEBUG 2242129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2243129198Scognet needed); 2244129198Scognet#endif 2245129198Scognet} 2246129198Scognet 2247129198Scognet/* 2248129198Scognet * This is used to stuff certain critical values into the PCB where they 2249129198Scognet * can be accessed quickly from cpu_switch() et al. 2250129198Scognet */ 2251129198Scognetvoid 2252129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2253129198Scognet{ 2254129198Scognet struct l2_bucket *l2b; 2255129198Scognet 2256129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2257129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2258129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2259129198Scognet 2260129198Scognet if (vector_page < KERNBASE) { 2261129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2262129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2263129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2264145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2265129198Scognet } else 2266129198Scognet pcb->pcb_pl1vec = NULL; 2267129198Scognet} 2268129198Scognet 2269129198Scognetvoid 2270129198Scognetpmap_activate(struct thread *td) 2271129198Scognet{ 2272129198Scognet pmap_t pm; 2273129198Scognet struct pcb *pcb; 2274129198Scognet 2275135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2276129198Scognet pcb = td->td_pcb; 2277129198Scognet 2278129198Scognet critical_enter(); 2279129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2280129198Scognet 2281129198Scognet if (td == curthread) { 2282129198Scognet u_int cur_dacr, cur_ttb; 2283129198Scognet 2284129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2285129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2286129198Scognet 2287129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2288129198Scognet 2289129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2290129198Scognet cur_dacr == pcb->pcb_dacr) { 2291129198Scognet /* 2292129198Scognet * No need to switch address spaces. 2293129198Scognet */ 2294129198Scognet critical_exit(); 2295129198Scognet return; 2296129198Scognet } 2297129198Scognet 2298129198Scognet 2299129198Scognet /* 2300129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2301129198Scognet * to 'vector_page' in the incoming L1 table before switching 2302129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2303129198Scognet * domain faults!) will jump into hyperspace. 2304129198Scognet */ 2305129198Scognet if (pcb->pcb_pl1vec) { 2306129198Scognet 2307129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2308129198Scognet /* 2309129198Scognet * Don't need to PTE_SYNC() at this point since 2310129198Scognet * cpu_setttb() is about to flush both the cache 2311129198Scognet * and the TLB. 2312129198Scognet */ 2313129198Scognet } 2314129198Scognet 2315129198Scognet cpu_domains(pcb->pcb_dacr); 2316129198Scognet cpu_setttb(pcb->pcb_pagedir); 2317129198Scognet } 2318129198Scognet critical_exit(); 2319129198Scognet} 2320129198Scognet 2321129198Scognetstatic int 2322129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2323129198Scognet{ 2324129198Scognet pd_entry_t *pdep, pde; 2325129198Scognet pt_entry_t *ptep, pte; 2326129198Scognet vm_offset_t pa; 2327129198Scognet int rv = 0; 2328129198Scognet 2329129198Scognet /* 2330129198Scognet * Make sure the descriptor itself has the correct cache mode 2331129198Scognet */ 2332129198Scognet pdep = &kl1[L1_IDX(va)]; 2333129198Scognet pde = *pdep; 2334129198Scognet 2335129198Scognet if (l1pte_section_p(pde)) { 2336129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2337129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2338129198Scognet pte_l1_s_cache_mode_pt; 2339129198Scognet PTE_SYNC(pdep); 2340129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2341129198Scognet sizeof(*pdep)); 2342129198Scognet rv = 1; 2343129198Scognet } 2344129198Scognet } else { 2345129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2346129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2347129198Scognet if (ptep == NULL) 2348129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2349129198Scognet 2350129198Scognet ptep = &ptep[l2pte_index(va)]; 2351129198Scognet pte = *ptep; 2352129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2353129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2354129198Scognet pte_l2_s_cache_mode_pt; 2355129198Scognet PTE_SYNC(ptep); 2356129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2357129198Scognet sizeof(*ptep)); 2358129198Scognet rv = 1; 2359129198Scognet } 2360129198Scognet } 2361129198Scognet 2362129198Scognet return (rv); 2363129198Scognet} 2364129198Scognet 2365129198Scognetstatic void 2366129198Scognetpmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2367129198Scognet pt_entry_t **ptep) 2368129198Scognet{ 2369129198Scognet vm_offset_t va = *availp; 2370129198Scognet struct l2_bucket *l2b; 2371129198Scognet 2372129198Scognet if (ptep) { 2373129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2374129198Scognet if (l2b == NULL) 2375129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2376129198Scognet 2377129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2378129198Scognet } 2379129198Scognet 2380129198Scognet *vap = va; 2381129198Scognet *availp = va + (PAGE_SIZE * pages); 2382129198Scognet} 2383129198Scognet 2384129198Scognet/* 2385129198Scognet * Bootstrap the system enough to run with virtual memory. 2386129198Scognet * 2387129198Scognet * On the arm this is called after mapping has already been enabled 2388129198Scognet * and just syncs the pmap module with what has already been done. 2389129198Scognet * [We can't call it easily with mapping off since the kernel is not 2390129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2391129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2392129198Scognet * (physical) address starting relative to 0] 2393129198Scognet */ 2394129198Scognet#define PMAP_STATIC_L2_SIZE 16 2395147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2396147114Scognetextern struct mtx smallalloc_mtx; 2397147114Scognet#endif 2398147114Scognet 2399129198Scognetvoid 2400129198Scognetpmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2401129198Scognet{ 2402129198Scognet static struct l1_ttable static_l1; 2403129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2404129198Scognet struct l1_ttable *l1 = &static_l1; 2405129198Scognet struct l2_dtable *l2; 2406129198Scognet struct l2_bucket *l2b; 2407129198Scognet pd_entry_t pde; 2408129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2409129198Scognet pt_entry_t *ptep; 2410129198Scognet vm_paddr_t pa; 2411129198Scognet vm_offset_t va; 2412135641Scognet vm_size_t size; 2413129198Scognet int l1idx, l2idx, l2next = 0; 2414129198Scognet 2415129198Scognet PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n", 2416129198Scognet firstaddr, loadaddr)); 2417129198Scognet 2418129198Scognet virtual_avail = firstaddr; 2419129198Scognet kernel_pmap = &kernel_pmap_store; 2420129198Scognet kernel_pmap->pm_l1 = l1; 2421150865Scognet kernel_l1pa = l1pt->pv_pa; 2422143192Scognet 2423143192Scognet /* 2424129198Scognet * Scan the L1 translation table created by initarm() and create 2425129198Scognet * the required metadata for all valid mappings found in it. 2426129198Scognet */ 2427129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2428129198Scognet pde = kernel_l1pt[l1idx]; 2429129198Scognet 2430129198Scognet /* 2431129198Scognet * We're only interested in Coarse mappings. 2432129198Scognet * pmap_extract() can deal with section mappings without 2433129198Scognet * recourse to checking L2 metadata. 2434129198Scognet */ 2435129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2436129198Scognet continue; 2437129198Scognet 2438129198Scognet /* 2439129198Scognet * Lookup the KVA of this L2 descriptor table 2440129198Scognet */ 2441129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2442129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2443129198Scognet 2444129198Scognet if (ptep == NULL) { 2445129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2446129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2447129198Scognet } 2448129198Scognet 2449129198Scognet /* 2450129198Scognet * Fetch the associated L2 metadata structure. 2451129198Scognet * Allocate a new one if necessary. 2452129198Scognet */ 2453129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2454129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2455129198Scognet panic("pmap_bootstrap: out of static L2s"); 2456129198Scognet kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2457129198Scognet &static_l2[l2next++]; 2458129198Scognet } 2459129198Scognet 2460129198Scognet /* 2461129198Scognet * One more L1 slot tracked... 2462129198Scognet */ 2463129198Scognet l2->l2_occupancy++; 2464129198Scognet 2465129198Scognet /* 2466129198Scognet * Fill in the details of the L2 descriptor in the 2467129198Scognet * appropriate bucket. 2468129198Scognet */ 2469129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2470129198Scognet l2b->l2b_kva = ptep; 2471129198Scognet l2b->l2b_phys = pa; 2472129198Scognet l2b->l2b_l1idx = l1idx; 2473129198Scognet 2474129198Scognet /* 2475129198Scognet * Establish an initial occupancy count for this descriptor 2476129198Scognet */ 2477129198Scognet for (l2idx = 0; 2478129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2479129198Scognet l2idx++) { 2480129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2481129198Scognet l2b->l2b_occupancy++; 2482129198Scognet } 2483129198Scognet } 2484129198Scognet 2485129198Scognet /* 2486129198Scognet * Make sure the descriptor itself has the correct cache mode. 2487129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2488129198Scognet * should consider this a clue to fix up their initarm() 2489129198Scognet * function. :) 2490129198Scognet */ 2491129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2492129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2493129198Scognet "L2 pte @ %p\n", ptep); 2494129198Scognet } 2495129198Scognet } 2496129198Scognet 2497129198Scognet 2498129198Scognet /* 2499129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2500129198Scognet * a page table. Bitch if it is not correctly set. 2501129198Scognet */ 2502129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2503129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2504129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2505129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2506129198Scognet "primary L1 @ 0x%x\n", va); 2507129198Scognet } 2508129198Scognet 2509129198Scognet cpu_dcache_wbinv_all(); 2510129198Scognet cpu_tlb_flushID(); 2511129198Scognet cpu_cpwait(); 2512129198Scognet 2513159325Salc PMAP_LOCK_INIT(kernel_pmap); 2514129198Scognet kernel_pmap->pm_active = -1; 2515129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2516144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2517129198Scognet 2518129198Scognet /* 2519129198Scognet * Reserve some special page table entries/VA space for temporary 2520129198Scognet * mapping of pages. 2521129198Scognet */ 2522129198Scognet#define SYSMAP(c, p, v, n) \ 2523129198Scognet v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2524129198Scognet 2525129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2526129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2527129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2528129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2529135641Scognet size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2530135641Scognet pmap_alloc_specials(&virtual_avail, 2531135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2532135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2533135641Scognet 2534135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2535135641Scognet pmap_alloc_specials(&virtual_avail, 2536135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2537135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2538135641Scognet 2539137362Scognet pmap_alloc_specials(&virtual_avail, 2540137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2541135641Scognet SLIST_INIT(&l1_list); 2542129198Scognet TAILQ_INIT(&l1_lru_list); 2543129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2544129198Scognet pmap_init_l1(l1, kernel_l1pt); 2545129198Scognet cpu_dcache_wbinv_all(); 2546129198Scognet 2547129198Scognet virtual_avail = round_page(virtual_avail); 2548129198Scognet virtual_end = lastaddr; 2549135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2550156191Scognet arm_nocache_startaddr = lastaddr; 2551159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2552156191Scognet 2553147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2554147114Scognet mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF); 2555161105Scognet arm_init_smallalloc(); 2556147114Scognet#endif 2557161105Scognet pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 2558129198Scognet} 2559129198Scognet 2560129198Scognet/*************************************************** 2561129198Scognet * Pmap allocation/deallocation routines. 2562129198Scognet ***************************************************/ 2563129198Scognet 2564129198Scognet/* 2565129198Scognet * Release any resources held by the given physical map. 2566129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2567129198Scognet * Should only be called if the map contains no valid mappings. 2568129198Scognet */ 2569129198Scognetvoid 2570129198Scognetpmap_release(pmap_t pmap) 2571129198Scognet{ 2572135641Scognet struct pcb *pcb; 2573135641Scognet 2574135641Scognet pmap_idcache_wbinv_all(pmap); 2575135641Scognet pmap_tlb_flushID(pmap); 2576135641Scognet cpu_cpwait(); 2577135641Scognet if (vector_page < KERNBASE) { 2578135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2579135641Scognet pcb = thread0.td_pcb; 2580135641Scognet if (pmap_is_current(pmap)) { 2581135641Scognet /* 2582135641Scognet * Frob the L1 entry corresponding to the vector 2583135641Scognet * page so that it contains the kernel pmap's domain 2584135641Scognet * number. This will ensure pmap_remove() does not 2585135641Scognet * pull the current vector page out from under us. 2586135641Scognet */ 2587135641Scognet critical_enter(); 2588135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2589135641Scognet cpu_domains(pcb->pcb_dacr); 2590135641Scognet cpu_setttb(pcb->pcb_pagedir); 2591135641Scognet critical_exit(); 2592135641Scognet } 2593135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2594135641Scognet /* 2595135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2596135641Scognet * since this process has no remaining mappings of its own. 2597135641Scognet */ 2598135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2599135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2600135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2601135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2602135641Scognet 2603135641Scognet } 2604129198Scognet pmap_free_l1(pmap); 2605159325Salc PMAP_LOCK_DESTROY(pmap); 2606135641Scognet 2607129198Scognet dprintf("pmap_release()\n"); 2608129198Scognet} 2609129198Scognet 2610129198Scognet 2611135641Scognet 2612129198Scognet/* 2613135641Scognet * Helper function for pmap_grow_l2_bucket() 2614135641Scognet */ 2615135641Scognetstatic __inline int 2616135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2617135641Scognet{ 2618135641Scognet struct l2_bucket *l2b; 2619135641Scognet pt_entry_t *ptep; 2620135641Scognet vm_paddr_t pa; 2621135641Scognet struct vm_page *pg; 2622135641Scognet 2623150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2624135641Scognet if (pg == NULL) 2625135641Scognet return (1); 2626135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2627135641Scognet 2628135641Scognet if (pap) 2629135641Scognet *pap = pa; 2630135641Scognet 2631135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2632135641Scognet 2633135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2634135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2635135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2636135641Scognet PTE_SYNC(ptep); 2637135641Scognet return (0); 2638135641Scognet} 2639135641Scognet 2640135641Scognet/* 2641135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2642135641Scognet * used by pmap_growkernel(). 2643135641Scognet */ 2644135641Scognetstatic __inline struct l2_bucket * 2645135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2646135641Scognet{ 2647135641Scognet struct l2_dtable *l2; 2648135641Scognet struct l2_bucket *l2b; 2649135641Scognet struct l1_ttable *l1; 2650135641Scognet pd_entry_t *pl1pd; 2651135641Scognet u_short l1idx; 2652135641Scognet vm_offset_t nva; 2653135641Scognet 2654135641Scognet l1idx = L1_IDX(va); 2655135641Scognet 2656135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2657135641Scognet /* 2658135641Scognet * No mapping at this address, as there is 2659135641Scognet * no entry in the L1 table. 2660135641Scognet * Need to allocate a new l2_dtable. 2661135641Scognet */ 2662135641Scognet nva = pmap_kernel_l2dtable_kva; 2663135641Scognet if ((nva & PAGE_MASK) == 0) { 2664135641Scognet /* 2665135641Scognet * Need to allocate a backing page 2666135641Scognet */ 2667135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2668135641Scognet return (NULL); 2669135641Scognet } 2670135641Scognet 2671135641Scognet l2 = (struct l2_dtable *)nva; 2672135641Scognet nva += sizeof(struct l2_dtable); 2673135641Scognet 2674135641Scognet if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2675135641Scognet PAGE_MASK)) { 2676135641Scognet /* 2677135641Scognet * The new l2_dtable straddles a page boundary. 2678135641Scognet * Map in another page to cover it. 2679135641Scognet */ 2680135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2681135641Scognet return (NULL); 2682135641Scognet } 2683135641Scognet 2684135641Scognet pmap_kernel_l2dtable_kva = nva; 2685135641Scognet 2686135641Scognet /* 2687135641Scognet * Link it into the parent pmap 2688135641Scognet */ 2689135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2690150865Scognet memset(l2, 0, sizeof(*l2)); 2691135641Scognet } 2692135641Scognet 2693135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2694135641Scognet 2695135641Scognet /* 2696135641Scognet * Fetch pointer to the L2 page table associated with the address. 2697135641Scognet */ 2698135641Scognet if (l2b->l2b_kva == NULL) { 2699135641Scognet pt_entry_t *ptep; 2700135641Scognet 2701135641Scognet /* 2702135641Scognet * No L2 page table has been allocated. Chances are, this 2703135641Scognet * is because we just allocated the l2_dtable, above. 2704135641Scognet */ 2705135641Scognet nva = pmap_kernel_l2ptp_kva; 2706135641Scognet ptep = (pt_entry_t *)nva; 2707135641Scognet if ((nva & PAGE_MASK) == 0) { 2708135641Scognet /* 2709135641Scognet * Need to allocate a backing page 2710135641Scognet */ 2711135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2712135641Scognet &pmap_kernel_l2ptp_phys)) 2713135641Scognet return (NULL); 2714135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2715135641Scognet } 2716150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2717135641Scognet l2->l2_occupancy++; 2718135641Scognet l2b->l2b_kva = ptep; 2719135641Scognet l2b->l2b_l1idx = l1idx; 2720135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2721135641Scognet 2722135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2723135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2724135641Scognet } 2725135641Scognet 2726135641Scognet /* Distribute new L1 entry to all other L1s */ 2727135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2728145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2729135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2730135641Scognet L1_C_PROTO; 2731135641Scognet PTE_SYNC(pl1pd); 2732135641Scognet } 2733135641Scognet 2734135641Scognet return (l2b); 2735135641Scognet} 2736135641Scognet 2737135641Scognet 2738135641Scognet/* 2739129198Scognet * grow the number of kernel page table entries, if needed 2740129198Scognet */ 2741129198Scognetvoid 2742129198Scognetpmap_growkernel(vm_offset_t addr) 2743129198Scognet{ 2744135641Scognet pmap_t kpm = pmap_kernel(); 2745129198Scognet 2746135641Scognet if (addr <= pmap_curmaxkvaddr) 2747135641Scognet return; /* we are OK */ 2748135641Scognet 2749135641Scognet /* 2750135641Scognet * whoops! we need to add kernel PTPs 2751135641Scognet */ 2752135641Scognet 2753135641Scognet /* Map 1MB at a time */ 2754135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2755135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2756135641Scognet 2757135641Scognet /* 2758135641Scognet * flush out the cache, expensive but growkernel will happen so 2759135641Scognet * rarely 2760135641Scognet */ 2761135641Scognet cpu_dcache_wbinv_all(); 2762135641Scognet cpu_tlb_flushD(); 2763135641Scognet cpu_cpwait(); 2764135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2765135641Scognet 2766129198Scognet} 2767129198Scognet 2768129198Scognet 2769129198Scognet/* 2770129198Scognet * Remove all pages from specified address space 2771129198Scognet * this aids process exit speeds. Also, this code 2772129198Scognet * is special cased for current process only, but 2773129198Scognet * can have the more generic (and slightly slower) 2774129198Scognet * mode enabled. This is much faster than pmap_remove 2775129198Scognet * in the case of running down an entire address space. 2776129198Scognet */ 2777129198Scognetvoid 2778157443Speterpmap_remove_pages(pmap_t pmap) 2779129198Scognet{ 2780144760Scognet struct pv_entry *pv, *npv; 2781144760Scognet struct l2_bucket *l2b = NULL; 2782144760Scognet vm_page_t m; 2783144760Scognet pt_entry_t *pt; 2784144760Scognet 2785144760Scognet vm_page_lock_queues(); 2786159352Salc PMAP_LOCK(pmap); 2787144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2788144760Scognet if (pv->pv_flags & PVF_WIRED) { 2789144760Scognet /* The page is wired, cannot remove it now. */ 2790144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2791144760Scognet continue; 2792144760Scognet } 2793144760Scognet pmap->pm_stats.resident_count--; 2794144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2795144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2796144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2797144760Scognet m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2798164079Scognet#ifdef ARM_USE_SMALL_ALLOC 2799164079Scognet KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2800164079Scognet#else 2801164079Scognet KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2802164079Scognet#endif 2803144760Scognet *pt = 0; 2804144760Scognet PTE_SYNC(pt); 2805144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2806144760Scognet pmap_nuke_pv(m, pmap, pv); 2807150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2808150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 2809144760Scognet pmap_free_pv_entry(pv); 2810144760Scognet } 2811144760Scognet vm_page_unlock_queues(); 2812135641Scognet cpu_idcache_wbinv_all(); 2813135641Scognet cpu_tlb_flushID(); 2814135641Scognet cpu_cpwait(); 2815159352Salc PMAP_UNLOCK(pmap); 2816129198Scognet} 2817129198Scognet 2818129198Scognet 2819129198Scognet/*************************************************** 2820129198Scognet * Low level mapping routines..... 2821129198Scognet ***************************************************/ 2822129198Scognet 2823147114Scognet/* Map a section into the KVA. */ 2824147114Scognet 2825147114Scognetvoid 2826147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2827147114Scognet{ 2828147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2829147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2830147114Scognet struct l1_ttable *l1; 2831147114Scognet 2832147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2833147114Scognet ("Not a valid section mapping")); 2834147114Scognet if (flags & SECTION_CACHE) 2835147114Scognet pd |= pte_l1_s_cache_mode; 2836147114Scognet else if (flags & SECTION_PT) 2837147114Scognet pd |= pte_l1_s_cache_mode_pt; 2838147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2839147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2840147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2841147114Scognet } 2842147114Scognet} 2843147114Scognet 2844129198Scognet/* 2845129198Scognet * add a wired page to the kva 2846129198Scognet * note that in order for the mapping to take effect -- you 2847129198Scognet * should do a invltlb after doing the pmap_kenter... 2848129198Scognet */ 2849135641Scognetstatic PMAP_INLINE void 2850135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2851129198Scognet{ 2852129198Scognet struct l2_bucket *l2b; 2853129198Scognet pt_entry_t *pte; 2854129198Scognet pt_entry_t opte; 2855129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2856129198Scognet (uint32_t) va, (uint32_t) pa)); 2857129198Scognet 2858129198Scognet 2859129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2860135641Scognet if (l2b == NULL) 2861135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2862129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2863129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2864129198Scognet opte = *pte; 2865129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2866129198Scognet (uint32_t) pte, opte, *pte)); 2867129198Scognet if (l2pte_valid(opte)) { 2868129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2869129198Scognet cpu_tlb_flushD_SE(va); 2870129198Scognet cpu_cpwait(); 2871135641Scognet } else { 2872129198Scognet if (opte == 0) 2873129198Scognet l2b->l2b_occupancy++; 2874135641Scognet } 2875129198Scognet *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2876135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2877135641Scognet if (flags & KENTER_CACHE) 2878135641Scognet *pte |= pte_l2_s_cache_mode; 2879142570Scognet if (flags & KENTER_USER) 2880142570Scognet *pte |= L2_S_PROT_U; 2881129198Scognet PTE_SYNC(pte); 2882135641Scognet} 2883129198Scognet 2884135641Scognetvoid 2885135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2886135641Scognet{ 2887135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2888129198Scognet} 2889129198Scognet 2890142570Scognetvoid 2891156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2892156191Scognet{ 2893156191Scognet 2894156191Scognet pmap_kenter_internal(va, pa, 0); 2895156191Scognet} 2896156191Scognet 2897156191Scognetvoid 2898142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2899142570Scognet{ 2900143192Scognet 2901142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2902143192Scognet /* 2903143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2904143192Scognet * at the first use of the new address, or bad things will happen, 2905143192Scognet * as we use one of these addresses in the exception handlers. 2906143192Scognet */ 2907143192Scognet pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2908142570Scognet} 2909129198Scognet 2910129198Scognet/* 2911135641Scognet * remove a page rom the kernel pagetables 2912129198Scognet */ 2913129198ScognetPMAP_INLINE void 2914129198Scognetpmap_kremove(vm_offset_t va) 2915129198Scognet{ 2916135641Scognet struct l2_bucket *l2b; 2917135641Scognet pt_entry_t *pte, opte; 2918135641Scognet 2919135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2920145071Scognet if (!l2b) 2921145071Scognet return; 2922135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2923135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2924135641Scognet opte = *pte; 2925135641Scognet if (l2pte_valid(opte)) { 2926135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2927135641Scognet cpu_tlb_flushD_SE(va); 2928135641Scognet cpu_cpwait(); 2929144760Scognet *pte = 0; 2930135641Scognet } 2931129198Scognet} 2932129198Scognet 2933129198Scognet 2934129198Scognet/* 2935129198Scognet * Used to map a range of physical addresses into kernel 2936129198Scognet * virtual address space. 2937129198Scognet * 2938129198Scognet * The value passed in '*virt' is a suggested virtual address for 2939129198Scognet * the mapping. Architectures which can support a direct-mapped 2940129198Scognet * physical to virtual region can return the appropriate address 2941129198Scognet * within that region, leaving '*virt' unchanged. Other 2942129198Scognet * architectures should map the pages starting at '*virt' and 2943129198Scognet * update '*virt' with the first usable address after the mapped 2944129198Scognet * region. 2945129198Scognet */ 2946129198Scognetvm_offset_t 2947129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2948129198Scognet{ 2949161105Scognet#ifdef ARM_USE_SMALL_ALLOC 2950161105Scognet return (arm_ptovirt(start)); 2951161105Scognet#else 2952129198Scognet vm_offset_t sva = *virt; 2953129198Scognet vm_offset_t va = sva; 2954129198Scognet 2955129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2956129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2957129198Scognet prot)); 2958129198Scognet 2959129198Scognet while (start < end) { 2960129198Scognet pmap_kenter(va, start); 2961129198Scognet va += PAGE_SIZE; 2962129198Scognet start += PAGE_SIZE; 2963129198Scognet } 2964129198Scognet *virt = va; 2965129198Scognet return (sva); 2966161105Scognet#endif 2967129198Scognet} 2968129198Scognet 2969143724Scognetstatic void 2970150865Scognetpmap_wb_page(vm_page_t m) 2971143724Scognet{ 2972143724Scognet struct pv_entry *pv; 2973129198Scognet 2974143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2975150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2976144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2977143724Scognet} 2978143724Scognet 2979150865Scognetstatic void 2980150865Scognetpmap_inv_page(vm_page_t m) 2981150865Scognet{ 2982150865Scognet struct pv_entry *pv; 2983150865Scognet 2984150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2985150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2986150865Scognet} 2987129198Scognet/* 2988129198Scognet * Add a list of wired pages to the kva 2989129198Scognet * this routine is only used for temporary 2990129198Scognet * kernel mappings that do not need to have 2991129198Scognet * page modification or references recorded. 2992129198Scognet * Note that old mappings are simply written 2993129198Scognet * over. The page *must* be wired. 2994129198Scognet */ 2995129198Scognetvoid 2996129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2997129198Scognet{ 2998129198Scognet int i; 2999129198Scognet 3000129198Scognet for (i = 0; i < count; i++) { 3001150865Scognet pmap_wb_page(m[i]); 3002135641Scognet pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 3003135641Scognet KENTER_CACHE); 3004129198Scognet va += PAGE_SIZE; 3005129198Scognet } 3006129198Scognet} 3007129198Scognet 3008129198Scognet 3009129198Scognet/* 3010129198Scognet * this routine jerks page mappings from the 3011129198Scognet * kernel -- it is meant only for temporary mappings. 3012129198Scognet */ 3013129198Scognetvoid 3014129198Scognetpmap_qremove(vm_offset_t va, int count) 3015129198Scognet{ 3016146596Scognet vm_paddr_t pa; 3017129198Scognet int i; 3018129198Scognet 3019129198Scognet for (i = 0; i < count; i++) { 3020146596Scognet pa = vtophys(va); 3021146596Scognet if (pa) { 3022150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 3023146596Scognet pmap_kremove(va); 3024146596Scognet } 3025129198Scognet va += PAGE_SIZE; 3026129198Scognet } 3027129198Scognet} 3028129198Scognet 3029129198Scognet 3030129198Scognet/* 3031129198Scognet * pmap_object_init_pt preloads the ptes for a given object 3032129198Scognet * into the specified pmap. This eliminates the blast of soft 3033129198Scognet * faults on process startup and immediately after an mmap. 3034129198Scognet */ 3035129198Scognetvoid 3036129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3037129198Scognet vm_pindex_t pindex, vm_size_t size) 3038129198Scognet{ 3039157156Scognet 3040157156Scognet VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3041157156Scognet KASSERT(object->type == OBJT_DEVICE, 3042157156Scognet ("pmap_object_init_pt: non-device object")); 3043129198Scognet} 3044129198Scognet 3045129198Scognet 3046129198Scognet/* 3047129198Scognet * pmap_is_prefaultable: 3048129198Scognet * 3049129198Scognet * Return whether or not the specified virtual address is elgible 3050129198Scognet * for prefault. 3051129198Scognet */ 3052129198Scognetboolean_t 3053129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3054129198Scognet{ 3055135641Scognet pd_entry_t *pde; 3056129198Scognet pt_entry_t *pte; 3057129198Scognet 3058135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3059135641Scognet return (FALSE); 3060159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 3061135641Scognet if (*pte == 0) 3062135641Scognet return (TRUE); 3063135641Scognet return (FALSE); 3064129198Scognet} 3065129198Scognet 3066129198Scognet/* 3067129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3068129198Scognet * Returns TRUE if the mapping exists, else FALSE. 3069129198Scognet * 3070129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 3071129198Scognet * It is not safe to take any pmap locks here, since we could be right 3072129198Scognet * in the middle of debugging the pmap anyway... 3073129198Scognet * 3074129198Scognet * It is possible for this routine to return FALSE even though a valid 3075129198Scognet * mapping does exist. This is because we don't lock, so the metadata 3076129198Scognet * state may be inconsistent. 3077129198Scognet * 3078129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3079129198Scognet * a "section" mapping. 3080129198Scognet */ 3081129198Scognetboolean_t 3082129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3083129198Scognet{ 3084129198Scognet struct l2_dtable *l2; 3085129198Scognet pd_entry_t *pl1pd, l1pd; 3086129198Scognet pt_entry_t *ptep; 3087129198Scognet u_short l1idx; 3088129198Scognet 3089129198Scognet if (pm->pm_l1 == NULL) 3090129198Scognet return (FALSE); 3091129198Scognet 3092129198Scognet l1idx = L1_IDX(va); 3093129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3094129198Scognet l1pd = *pl1pd; 3095129198Scognet 3096129198Scognet if (l1pte_section_p(l1pd)) { 3097129198Scognet *ptp = NULL; 3098129198Scognet return (TRUE); 3099129198Scognet } 3100129198Scognet 3101129198Scognet if (pm->pm_l2 == NULL) 3102129198Scognet return (FALSE); 3103129198Scognet 3104129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3105129198Scognet 3106129198Scognet if (l2 == NULL || 3107129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3108129198Scognet return (FALSE); 3109129198Scognet } 3110129198Scognet 3111129198Scognet *ptp = &ptep[l2pte_index(va)]; 3112129198Scognet return (TRUE); 3113129198Scognet} 3114129198Scognet 3115129198Scognet/* 3116129198Scognet * Routine: pmap_remove_all 3117129198Scognet * Function: 3118129198Scognet * Removes this physical page from 3119129198Scognet * all physical maps in which it resides. 3120129198Scognet * Reflects back modify bits to the pager. 3121129198Scognet * 3122129198Scognet * Notes: 3123129198Scognet * Original versions of this routine were very 3124129198Scognet * inefficient because they iteratively called 3125129198Scognet * pmap_remove (slow...) 3126129198Scognet */ 3127129198Scognetvoid 3128129198Scognetpmap_remove_all(vm_page_t m) 3129129198Scognet{ 3130129198Scognet pv_entry_t pv; 3131135641Scognet pt_entry_t *ptep, pte; 3132135641Scognet struct l2_bucket *l2b; 3133135641Scognet boolean_t flush = FALSE; 3134135641Scognet pmap_t curpm; 3135135641Scognet int flags = 0; 3136129198Scognet 3137129198Scognet#if defined(PMAP_DEBUG) 3138129198Scognet /* 3139129198Scognet * XXX this makes pmap_page_protect(NONE) illegal for non-managed 3140129198Scognet * pages! 3141129198Scognet */ 3142147217Salc if (m->flags & PG_FICTITIOUS) { 3143129198Scognet panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m)); 3144129198Scognet } 3145129198Scognet#endif 3146129198Scognet 3147135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3148135641Scognet return; 3149164778Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3150135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3151129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3152135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3153135641Scognet pv->pv_pmap == pmap_kernel())) 3154135641Scognet flush = TRUE; 3155159352Salc PMAP_LOCK(pv->pv_pmap); 3156135641Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3157135641Scognet KASSERT(l2b != NULL, ("No l2 bucket")); 3158135641Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3159135641Scognet pte = *ptep; 3160135641Scognet *ptep = 0; 3161135641Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3162135641Scognet pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3163135641Scognet if (pv->pv_flags & PVF_WIRED) 3164135641Scognet pv->pv_pmap->pm_stats.wired_count--; 3165129198Scognet pv->pv_pmap->pm_stats.resident_count--; 3166135641Scognet flags |= pv->pv_flags; 3167135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3168159352Salc PMAP_UNLOCK(pv->pv_pmap); 3169129198Scognet pmap_free_pv_entry(pv); 3170129198Scognet } 3171129198Scognet 3172135641Scognet if (flush) { 3173135641Scognet if (PV_BEEN_EXECD(flags)) 3174135641Scognet pmap_tlb_flushID(curpm); 3175135641Scognet else 3176135641Scognet pmap_tlb_flushD(curpm); 3177135641Scognet } 3178150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 3179129198Scognet} 3180129198Scognet 3181129198Scognet 3182129198Scognet/* 3183129198Scognet * Set the physical protection on the 3184129198Scognet * specified range of this map as requested. 3185129198Scognet */ 3186129198Scognetvoid 3187129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3188129198Scognet{ 3189129198Scognet struct l2_bucket *l2b; 3190129198Scognet pt_entry_t *ptep, pte; 3191129198Scognet vm_offset_t next_bucket; 3192129198Scognet u_int flags; 3193129198Scognet int flush; 3194129198Scognet 3195129198Scognet if ((prot & VM_PROT_READ) == 0) { 3196129198Scognet pmap_remove(pm, sva, eva); 3197129198Scognet return; 3198129198Scognet } 3199129198Scognet 3200129198Scognet if (prot & VM_PROT_WRITE) { 3201129198Scognet /* 3202129198Scognet * If this is a read->write transition, just ignore it and let 3203135641Scognet * vm_fault() take care of it later. 3204129198Scognet */ 3205129198Scognet return; 3206129198Scognet } 3207129198Scognet 3208159352Salc vm_page_lock_queues(); 3209159352Salc PMAP_LOCK(pm); 3210129198Scognet 3211129198Scognet /* 3212129198Scognet * OK, at this point, we know we're doing write-protect operation. 3213129198Scognet * If the pmap is active, write-back the range. 3214129198Scognet */ 3215129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3216129198Scognet 3217129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3218129198Scognet flags = 0; 3219129198Scognet 3220129198Scognet while (sva < eva) { 3221129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3222129198Scognet if (next_bucket > eva) 3223129198Scognet next_bucket = eva; 3224129198Scognet 3225129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3226129198Scognet if (l2b == NULL) { 3227129198Scognet sva = next_bucket; 3228129198Scognet continue; 3229129198Scognet } 3230129198Scognet 3231129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3232129198Scognet 3233129198Scognet while (sva < next_bucket) { 3234129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3235129198Scognet struct vm_page *pg; 3236129198Scognet u_int f; 3237129198Scognet 3238129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3239129198Scognet pte &= ~L2_S_PROT_W; 3240129198Scognet *ptep = pte; 3241129198Scognet PTE_SYNC(ptep); 3242129198Scognet 3243129198Scognet if (pg != NULL) { 3244129198Scognet f = pmap_modify_pv(pg, pm, sva, 3245129198Scognet PVF_WRITE, 0); 3246129198Scognet pmap_vac_me_harder(pg, pm, sva); 3247157970Scognet vm_page_dirty(pg); 3248129198Scognet } else 3249129198Scognet f = PVF_REF | PVF_EXEC; 3250129198Scognet 3251129198Scognet if (flush >= 0) { 3252129198Scognet flush++; 3253129198Scognet flags |= f; 3254129198Scognet } else 3255129198Scognet if (PV_BEEN_EXECD(f)) 3256129198Scognet pmap_tlb_flushID_SE(pm, sva); 3257129198Scognet else 3258129198Scognet if (PV_BEEN_REFD(f)) 3259129198Scognet pmap_tlb_flushD_SE(pm, sva); 3260129198Scognet } 3261129198Scognet 3262129198Scognet sva += PAGE_SIZE; 3263129198Scognet ptep++; 3264129198Scognet } 3265129198Scognet } 3266129198Scognet 3267129198Scognet 3268129198Scognet if (flush) { 3269129198Scognet if (PV_BEEN_EXECD(flags)) 3270129198Scognet pmap_tlb_flushID(pm); 3271129198Scognet else 3272129198Scognet if (PV_BEEN_REFD(flags)) 3273129198Scognet pmap_tlb_flushD(pm); 3274129198Scognet } 3275144760Scognet vm_page_unlock_queues(); 3276129198Scognet 3277159352Salc PMAP_UNLOCK(pm); 3278129198Scognet} 3279129198Scognet 3280129198Scognet 3281129198Scognet/* 3282129198Scognet * Insert the given physical page (p) at 3283129198Scognet * the specified virtual address (v) in the 3284129198Scognet * target physical map with the protection requested. 3285129198Scognet * 3286129198Scognet * If specified, the page will be wired down, meaning 3287129198Scognet * that the related pte can not be reclaimed. 3288129198Scognet * 3289129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3290129198Scognet * or lose information. That is, this routine must actually 3291129198Scognet * insert this page into the given map NOW. 3292129198Scognet */ 3293135641Scognet 3294129198Scognetvoid 3295129198Scognetpmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3296129198Scognet boolean_t wired) 3297129198Scognet{ 3298159127Salc 3299159127Salc vm_page_lock_queues(); 3300159352Salc PMAP_LOCK(pmap); 3301160260Scognet pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK); 3302159127Salc vm_page_unlock_queues(); 3303159352Salc PMAP_UNLOCK(pmap); 3304159127Salc} 3305159127Salc 3306159127Salc/* 3307159127Salc * The page queues and pmap must be locked. 3308159127Salc */ 3309159127Salcstatic void 3310159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3311160260Scognet boolean_t wired, int flags) 3312159127Salc{ 3313135641Scognet struct l2_bucket *l2b = NULL; 3314129198Scognet struct vm_page *opg; 3315144760Scognet struct pv_entry *pve = NULL; 3316129198Scognet pt_entry_t *ptep, npte, opte; 3317129198Scognet u_int nflags; 3318129198Scognet u_int oflags; 3319129198Scognet vm_paddr_t pa; 3320129198Scognet 3321159325Salc PMAP_ASSERT_LOCKED(pmap); 3322159127Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3323129198Scognet if (va == vector_page) { 3324129198Scognet pa = systempage.pv_pa; 3325129198Scognet m = NULL; 3326129198Scognet } else 3327129198Scognet pa = VM_PAGE_TO_PHYS(m); 3328129198Scognet nflags = 0; 3329129198Scognet if (prot & VM_PROT_WRITE) 3330129198Scognet nflags |= PVF_WRITE; 3331129198Scognet if (prot & VM_PROT_EXECUTE) 3332129198Scognet nflags |= PVF_EXEC; 3333129198Scognet if (wired) 3334129198Scognet nflags |= PVF_WIRED; 3335129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3336129198Scognet "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3337129198Scognet 3338135641Scognet if (pmap == pmap_kernel()) { 3339129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3340135641Scognet if (l2b == NULL) 3341135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3342160260Scognet } else { 3343160260Scognetdo_l2b_alloc: 3344129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3345160260Scognet if (l2b == NULL) { 3346160260Scognet if (flags & M_WAITOK) { 3347160260Scognet PMAP_UNLOCK(pmap); 3348160260Scognet vm_page_unlock_queues(); 3349160260Scognet VM_WAIT; 3350160260Scognet vm_page_lock_queues(); 3351160260Scognet PMAP_LOCK(pmap); 3352160260Scognet goto do_l2b_alloc; 3353160260Scognet } 3354160260Scognet return; 3355160260Scognet } 3356160260Scognet } 3357160260Scognet 3358129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3359129198Scognet 3360135641Scognet opte = *ptep; 3361129198Scognet npte = pa; 3362129198Scognet oflags = 0; 3363129198Scognet if (opte) { 3364129198Scognet /* 3365129198Scognet * There is already a mapping at this address. 3366129198Scognet * If the physical address is different, lookup the 3367129198Scognet * vm_page. 3368129198Scognet */ 3369129198Scognet if (l2pte_pa(opte) != pa) 3370129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3371129198Scognet else 3372129198Scognet opg = m; 3373129198Scognet } else 3374129198Scognet opg = NULL; 3375129198Scognet 3376135641Scognet if ((prot & (VM_PROT_ALL)) || 3377135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3378129198Scognet /* 3379135641Scognet * - The access type indicates that we don't need 3380135641Scognet * to do referenced emulation. 3381135641Scognet * OR 3382135641Scognet * - The physical page has already been referenced 3383135641Scognet * so no need to re-do referenced emulation here. 3384129198Scognet */ 3385135641Scognet npte |= L2_S_PROTO; 3386135641Scognet 3387135641Scognet nflags |= PVF_REF; 3388135641Scognet 3389144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3390144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3391129198Scognet /* 3392135641Scognet * This is a writable mapping, and the 3393135641Scognet * page's mod state indicates it has 3394135641Scognet * already been modified. Make it 3395135641Scognet * writable from the outset. 3396129198Scognet */ 3397135641Scognet nflags |= PVF_MOD; 3398157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3399144760Scognet vm_page_dirty(m); 3400129198Scognet } 3401144760Scognet if (m && opte) 3402144760Scognet vm_page_flag_set(m, PG_REFERENCED); 3403135641Scognet } else { 3404135641Scognet /* 3405135641Scognet * Need to do page referenced emulation. 3406135641Scognet */ 3407135641Scognet npte |= L2_TYPE_INV; 3408135641Scognet } 3409135641Scognet 3410164229Salc if (prot & VM_PROT_WRITE) { 3411135641Scognet npte |= L2_S_PROT_W; 3412164229Salc if (m != NULL) 3413164229Salc vm_page_flag_set(m, PG_WRITEABLE); 3414164229Salc } 3415135641Scognet npte |= pte_l2_s_cache_mode; 3416135641Scognet if (m && m == opg) { 3417135641Scognet /* 3418135641Scognet * We're changing the attrs of an existing mapping. 3419135641Scognet */ 3420135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3421135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3422135641Scognet PVF_MOD | PVF_REF, nflags); 3423135641Scognet 3424135641Scognet /* 3425135641Scognet * We may need to flush the cache if we're 3426135641Scognet * doing rw-ro... 3427135641Scognet */ 3428135641Scognet if (pmap_is_current(pmap) && 3429135641Scognet (oflags & PVF_NC) == 0 && 3430129198Scognet (opte & L2_S_PROT_W) != 0 && 3431129198Scognet (prot & VM_PROT_WRITE) == 0) 3432135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3433129198Scognet } else { 3434129198Scognet /* 3435135641Scognet * New mapping, or changing the backing page 3436135641Scognet * of an existing mapping. 3437129198Scognet */ 3438129198Scognet if (opg) { 3439129198Scognet /* 3440135641Scognet * Replacing an existing mapping with a new one. 3441135641Scognet * It is part of our managed memory so we 3442135641Scognet * must remove it from the PV list 3443129198Scognet */ 3444129198Scognet pve = pmap_remove_pv(opg, pmap, va); 3445159088Scognet if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) && 3446159088Scognet pve) 3447135641Scognet pmap_free_pv_entry(pve); 3448159088Scognet else if (!pve && 3449159088Scognet !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3450144760Scognet pve = pmap_get_pv_entry(); 3451135641Scognet KASSERT(pve != NULL, ("No pv")); 3452129198Scognet oflags = pve->pv_flags; 3453135641Scognet 3454135641Scognet /* 3455135641Scognet * If the old mapping was valid (ref/mod 3456135641Scognet * emulation creates 'invalid' mappings 3457135641Scognet * initially) then make sure to frob 3458135641Scognet * the cache. 3459135641Scognet */ 3460135641Scognet if ((oflags & PVF_NC) == 0 && 3461135641Scognet l2pte_valid(opte)) { 3462135641Scognet if (PV_BEEN_EXECD(oflags)) { 3463129198Scognet pmap_idcache_wbinv_range(pmap, va, 3464129198Scognet PAGE_SIZE); 3465135641Scognet } else 3466135641Scognet if (PV_BEEN_REFD(oflags)) { 3467135641Scognet pmap_dcache_wb_range(pmap, va, 3468135641Scognet PAGE_SIZE, TRUE, 3469135641Scognet (oflags & PVF_WRITE) == 0); 3470135641Scognet } 3471129198Scognet } 3472150865Scognet } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3473135641Scognet if ((pve = pmap_get_pv_entry()) == NULL) { 3474135641Scognet panic("pmap_enter: no pv entries"); 3475135641Scognet } 3476157970Scognet if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) { 3477157970Scognet KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3478157970Scognet ("pmap_enter: managed mapping within the clean submap")); 3479135641Scognet pmap_enter_pv(m, pve, pmap, va, nflags); 3480157970Scognet } 3481129198Scognet } 3482129198Scognet /* 3483129198Scognet * Make sure userland mappings get the right permissions 3484129198Scognet */ 3485129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3486129198Scognet npte |= L2_S_PROT_U; 3487129198Scognet } 3488129198Scognet 3489129198Scognet /* 3490129198Scognet * Keep the stats up to date 3491129198Scognet */ 3492129198Scognet if (opte == 0) { 3493129198Scognet l2b->l2b_occupancy++; 3494129198Scognet pmap->pm_stats.resident_count++; 3495129198Scognet } 3496129198Scognet 3497129198Scognet 3498129198Scognet /* 3499129198Scognet * If this is just a wiring change, the two PTEs will be 3500129198Scognet * identical, so there's no need to update the page table. 3501129198Scognet */ 3502129198Scognet if (npte != opte) { 3503135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3504129198Scognet 3505129198Scognet *ptep = npte; 3506129198Scognet if (is_cached) { 3507129198Scognet /* 3508129198Scognet * We only need to frob the cache/tlb if this pmap 3509129198Scognet * is current 3510129198Scognet */ 3511129198Scognet PTE_SYNC(ptep); 3512161105Scognet if (L1_IDX(va) != L1_IDX(vector_page) && 3513129198Scognet l2pte_valid(npte)) { 3514129198Scognet /* 3515129198Scognet * This mapping is likely to be accessed as 3516129198Scognet * soon as we return to userland. Fix up the 3517129198Scognet * L1 entry to avoid taking another 3518129198Scognet * page/domain fault. 3519129198Scognet */ 3520129198Scognet pd_entry_t *pl1pd, l1pd; 3521129198Scognet 3522129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3523129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3524144760Scognet L1_C_PROTO; 3525129198Scognet if (*pl1pd != l1pd) { 3526129198Scognet *pl1pd = l1pd; 3527129198Scognet PTE_SYNC(pl1pd); 3528129198Scognet } 3529129198Scognet } 3530129198Scognet } 3531129198Scognet 3532129198Scognet if (PV_BEEN_EXECD(oflags)) 3533129198Scognet pmap_tlb_flushID_SE(pmap, va); 3534135641Scognet else if (PV_BEEN_REFD(oflags)) 3535129198Scognet pmap_tlb_flushD_SE(pmap, va); 3536129198Scognet 3537129198Scognet 3538157025Scognet if (m) 3539157025Scognet pmap_vac_me_harder(m, pmap, va); 3540129198Scognet } 3541129198Scognet} 3542129198Scognet 3543129198Scognet/* 3544159303Salc * Maps a sequence of resident pages belonging to the same object. 3545159303Salc * The sequence begins with the given page m_start. This page is 3546159303Salc * mapped at the given virtual address start. Each subsequent page is 3547159303Salc * mapped at a virtual address that is offset from start by the same 3548159303Salc * amount as the page is offset from m_start within the object. The 3549159303Salc * last page in the sequence is the page with the largest offset from 3550159303Salc * m_start that can be mapped at a virtual address less than the given 3551159303Salc * virtual address end. Not every virtual page between start and end 3552159303Salc * is mapped; only those for which a resident page exists with the 3553159303Salc * corresponding offset from m_start are mapped. 3554159303Salc */ 3555159303Salcvoid 3556159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3557159303Salc vm_page_t m_start, vm_prot_t prot) 3558159303Salc{ 3559159303Salc vm_page_t m; 3560159303Salc vm_pindex_t diff, psize; 3561159303Salc 3562159303Salc psize = atop(end - start); 3563159303Salc m = m_start; 3564159325Salc PMAP_LOCK(pmap); 3565159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3566159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3567160260Scognet (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT); 3568159303Salc m = TAILQ_NEXT(m, listq); 3569159303Salc } 3570159325Salc PMAP_UNLOCK(pmap); 3571159303Salc} 3572159303Salc 3573159303Salc/* 3574129198Scognet * this code makes some *MAJOR* assumptions: 3575129198Scognet * 1. Current pmap & pmap exists. 3576129198Scognet * 2. Not wired. 3577129198Scognet * 3. Read access. 3578129198Scognet * 4. No page table pages. 3579129198Scognet * but is *MUCH* faster than pmap_enter... 3580129198Scognet */ 3581129198Scognet 3582159627Supsvoid 3583159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3584129198Scognet{ 3585138897Salc 3586159325Salc PMAP_LOCK(pmap); 3587159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3588160260Scognet FALSE, M_NOWAIT); 3589159325Salc PMAP_UNLOCK(pmap); 3590129198Scognet} 3591129198Scognet 3592129198Scognet/* 3593129198Scognet * Routine: pmap_change_wiring 3594129198Scognet * Function: Change the wiring attribute for a map/virtual-address 3595129198Scognet * pair. 3596129198Scognet * In/out conditions: 3597129198Scognet * The mapping must already exist in the pmap. 3598129198Scognet */ 3599129198Scognetvoid 3600129198Scognetpmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3601129198Scognet{ 3602129198Scognet struct l2_bucket *l2b; 3603129198Scognet pt_entry_t *ptep, pte; 3604129198Scognet vm_page_t pg; 3605129198Scognet 3606159352Salc vm_page_lock_queues(); 3607159325Salc PMAP_LOCK(pmap); 3608129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3609129198Scognet KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3610129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3611129198Scognet pte = *ptep; 3612129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3613129198Scognet if (pg) 3614129198Scognet pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired); 3615159352Salc vm_page_unlock_queues(); 3616159325Salc PMAP_UNLOCK(pmap); 3617129198Scognet} 3618129198Scognet 3619129198Scognet 3620129198Scognet/* 3621129198Scognet * Copy the range specified by src_addr/len 3622129198Scognet * from the source map to the range dst_addr/len 3623129198Scognet * in the destination map. 3624129198Scognet * 3625129198Scognet * This routine is only advisory and need not do anything. 3626129198Scognet */ 3627129198Scognetvoid 3628129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3629129198Scognet vm_size_t len, vm_offset_t src_addr) 3630129198Scognet{ 3631129198Scognet} 3632129198Scognet 3633129198Scognet 3634129198Scognet/* 3635129198Scognet * Routine: pmap_extract 3636129198Scognet * Function: 3637129198Scognet * Extract the physical page address associated 3638129198Scognet * with the given map/virtual_address pair. 3639129198Scognet */ 3640131658Salcvm_paddr_t 3641129198Scognetpmap_extract(pmap_t pm, vm_offset_t va) 3642129198Scognet{ 3643129198Scognet struct l2_dtable *l2; 3644159450Salc pd_entry_t l1pd; 3645129198Scognet pt_entry_t *ptep, pte; 3646129198Scognet vm_paddr_t pa; 3647129198Scognet u_int l1idx; 3648129198Scognet l1idx = L1_IDX(va); 3649129198Scognet 3650159450Salc PMAP_LOCK(pm); 3651159450Salc l1pd = pm->pm_l1->l1_kva[l1idx]; 3652129198Scognet if (l1pte_section_p(l1pd)) { 3653129198Scognet /* 3654129198Scognet * These should only happen for pmap_kernel() 3655129198Scognet */ 3656129198Scognet KASSERT(pm == pmap_kernel(), ("huh")); 3657129198Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3658129198Scognet } else { 3659129198Scognet /* 3660129198Scognet * Note that we can't rely on the validity of the L1 3661129198Scognet * descriptor as an indication that a mapping exists. 3662129198Scognet * We have to look it up in the L2 dtable. 3663129198Scognet */ 3664129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3665129198Scognet 3666129198Scognet if (l2 == NULL || 3667129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3668159450Salc PMAP_UNLOCK(pm); 3669129198Scognet return (0); 3670129198Scognet } 3671129198Scognet 3672129198Scognet ptep = &ptep[l2pte_index(va)]; 3673129198Scognet pte = *ptep; 3674129198Scognet 3675159450Salc if (pte == 0) { 3676159450Salc PMAP_UNLOCK(pm); 3677129198Scognet return (0); 3678159450Salc } 3679129198Scognet 3680129198Scognet switch (pte & L2_TYPE_MASK) { 3681129198Scognet case L2_TYPE_L: 3682129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3683129198Scognet break; 3684129198Scognet 3685129198Scognet default: 3686129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3687129198Scognet break; 3688129198Scognet } 3689129198Scognet } 3690129198Scognet 3691159450Salc PMAP_UNLOCK(pm); 3692129198Scognet return (pa); 3693129198Scognet} 3694129198Scognet 3695133453Salc/* 3696133453Salc * Atomically extract and hold the physical page with the given 3697133453Salc * pmap and virtual address pair if that mapping permits the given 3698133453Salc * protection. 3699133453Salc * 3700133453Salc */ 3701129198Scognetvm_page_t 3702129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3703129198Scognet{ 3704135641Scognet struct l2_dtable *l2; 3705159378Salc pd_entry_t l1pd; 3706135641Scognet pt_entry_t *ptep, pte; 3707129198Scognet vm_paddr_t pa; 3708135641Scognet vm_page_t m = NULL; 3709135641Scognet u_int l1idx; 3710135641Scognet l1idx = L1_IDX(va); 3711129198Scognet 3712135641Scognet vm_page_lock_queues(); 3713159325Salc PMAP_LOCK(pmap); 3714159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3715135641Scognet if (l1pte_section_p(l1pd)) { 3716135641Scognet /* 3717135641Scognet * These should only happen for pmap_kernel() 3718135641Scognet */ 3719135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3720135641Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3721135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3722135641Scognet m = PHYS_TO_VM_PAGE(pa); 3723135641Scognet vm_page_hold(m); 3724135641Scognet } 3725135641Scognet 3726135641Scognet } else { 3727135641Scognet /* 3728135641Scognet * Note that we can't rely on the validity of the L1 3729135641Scognet * descriptor as an indication that a mapping exists. 3730135641Scognet * We have to look it up in the L2 dtable. 3731135641Scognet */ 3732135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3733135641Scognet 3734135641Scognet if (l2 == NULL || 3735135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3736159325Salc PMAP_UNLOCK(pmap); 3737150865Scognet vm_page_unlock_queues(); 3738135641Scognet return (NULL); 3739135641Scognet } 3740135641Scognet 3741135641Scognet ptep = &ptep[l2pte_index(va)]; 3742135641Scognet pte = *ptep; 3743135641Scognet 3744150865Scognet if (pte == 0) { 3745159325Salc PMAP_UNLOCK(pmap); 3746150865Scognet vm_page_unlock_queues(); 3747135641Scognet return (NULL); 3748150865Scognet } 3749135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3750135641Scognet switch (pte & L2_TYPE_MASK) { 3751135641Scognet case L2_TYPE_L: 3752135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3753135641Scognet break; 3754135641Scognet 3755135641Scognet default: 3756135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3757135641Scognet break; 3758135641Scognet } 3759135641Scognet m = PHYS_TO_VM_PAGE(pa); 3760135641Scognet vm_page_hold(m); 3761135641Scognet } 3762129198Scognet } 3763135641Scognet 3764159325Salc PMAP_UNLOCK(pmap); 3765135641Scognet vm_page_unlock_queues(); 3766129198Scognet return (m); 3767129198Scognet} 3768129198Scognet 3769129198Scognet/* 3770129198Scognet * Initialize a preallocated and zeroed pmap structure, 3771129198Scognet * such as one in a vmspace structure. 3772129198Scognet */ 3773129198Scognet 3774129198Scognetvoid 3775129198Scognetpmap_pinit(pmap_t pmap) 3776129198Scognet{ 3777129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3778129198Scognet 3779159325Salc PMAP_LOCK_INIT(pmap); 3780129198Scognet pmap_alloc_l1(pmap); 3781129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3782129198Scognet 3783129198Scognet pmap->pm_count = 1; 3784129198Scognet pmap->pm_active = 0; 3785129198Scognet 3786144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3787129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3788129198Scognet pmap->pm_stats.resident_count = 1; 3789129198Scognet if (vector_page < KERNBASE) { 3790129198Scognet pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3791129198Scognet VM_PROT_READ, 1); 3792129198Scognet } 3793129198Scognet} 3794129198Scognet 3795129198Scognet 3796129198Scognet/*************************************************** 3797129198Scognet * page management routines. 3798129198Scognet ***************************************************/ 3799129198Scognet 3800129198Scognet 3801135641Scognetstatic void 3802129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3803129198Scognet{ 3804129198Scognet pv_entry_count--; 3805129198Scognet uma_zfree(pvzone, pv); 3806129198Scognet} 3807129198Scognet 3808129198Scognet 3809129198Scognet/* 3810129198Scognet * get a new pv_entry, allocating a block from the system 3811129198Scognet * when needed. 3812129198Scognet * the memory allocation is performed bypassing the malloc code 3813129198Scognet * because of the possibility of allocations at interrupt time. 3814129198Scognet */ 3815129198Scognetstatic pv_entry_t 3816129198Scognetpmap_get_pv_entry(void) 3817129198Scognet{ 3818129198Scognet pv_entry_t ret_value; 3819129198Scognet 3820129198Scognet pv_entry_count++; 3821159500Salc if (pv_entry_count > pv_entry_high_water) 3822159500Salc pagedaemon_wakeup(); 3823129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3824129198Scognet return ret_value; 3825129198Scognet} 3826129198Scognet 3827129198Scognet 3828129198Scognet/* 3829129198Scognet * Remove the given range of addresses from the specified map. 3830129198Scognet * 3831129198Scognet * It is assumed that the start and end are properly 3832129198Scognet * rounded to the page size. 3833129198Scognet */ 3834129198Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3835129198Scognetvoid 3836129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3837129198Scognet{ 3838129198Scognet struct l2_bucket *l2b; 3839129198Scognet vm_offset_t next_bucket; 3840129198Scognet pt_entry_t *ptep; 3841129198Scognet u_int cleanlist_idx, total, cnt; 3842129198Scognet struct { 3843129198Scognet vm_offset_t va; 3844129198Scognet pt_entry_t *pte; 3845129198Scognet } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3846129198Scognet u_int mappings, is_exec, is_refd; 3847135641Scognet int flushall = 0; 3848129198Scognet 3849129198Scognet 3850129198Scognet /* 3851129198Scognet * we lock in the pmap => pv_head direction 3852129198Scognet */ 3853129198Scognet 3854137664Scognet vm_page_lock_queues(); 3855159352Salc PMAP_LOCK(pm); 3856135641Scognet if (!pmap_is_current(pm)) { 3857129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3858129198Scognet } else 3859129198Scognet cleanlist_idx = 0; 3860129198Scognet 3861129198Scognet total = 0; 3862129198Scognet while (sva < eva) { 3863129198Scognet /* 3864129198Scognet * Do one L2 bucket's worth at a time. 3865129198Scognet */ 3866129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3867129198Scognet if (next_bucket > eva) 3868129198Scognet next_bucket = eva; 3869129198Scognet 3870129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3871129198Scognet if (l2b == NULL) { 3872129198Scognet sva = next_bucket; 3873129198Scognet continue; 3874129198Scognet } 3875129198Scognet 3876129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3877129198Scognet mappings = 0; 3878129198Scognet 3879129198Scognet while (sva < next_bucket) { 3880129198Scognet struct vm_page *pg; 3881129198Scognet pt_entry_t pte; 3882129198Scognet vm_paddr_t pa; 3883129198Scognet 3884129198Scognet pte = *ptep; 3885129198Scognet 3886129198Scognet if (pte == 0) { 3887129198Scognet /* 3888129198Scognet * Nothing here, move along 3889129198Scognet */ 3890129198Scognet sva += PAGE_SIZE; 3891129198Scognet ptep++; 3892129198Scognet continue; 3893129198Scognet } 3894129198Scognet 3895129198Scognet pm->pm_stats.resident_count--; 3896129198Scognet pa = l2pte_pa(pte); 3897129198Scognet is_exec = 0; 3898129198Scognet is_refd = 1; 3899129198Scognet 3900129198Scognet /* 3901129198Scognet * Update flags. In a number of circumstances, 3902129198Scognet * we could cluster a lot of these and do a 3903129198Scognet * number of sequential pages in one go. 3904129198Scognet */ 3905129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3906129198Scognet struct pv_entry *pve; 3907159474Salc 3908129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3909135641Scognet if (pve) { 3910159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3911159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3912129198Scognet pmap_free_pv_entry(pve); 3913129198Scognet } 3914129198Scognet } 3915129198Scognet 3916129198Scognet if (!l2pte_valid(pte)) { 3917129198Scognet *ptep = 0; 3918129198Scognet PTE_SYNC_CURRENT(pm, ptep); 3919129198Scognet sva += PAGE_SIZE; 3920129198Scognet ptep++; 3921129198Scognet mappings++; 3922129198Scognet continue; 3923129198Scognet } 3924129198Scognet 3925129198Scognet if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3926129198Scognet /* Add to the clean list. */ 3927129198Scognet cleanlist[cleanlist_idx].pte = ptep; 3928129198Scognet cleanlist[cleanlist_idx].va = 3929129198Scognet sva | (is_exec & 1); 3930129198Scognet cleanlist_idx++; 3931129198Scognet } else 3932129198Scognet if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3933129198Scognet /* Nuke everything if needed. */ 3934129198Scognet pmap_idcache_wbinv_all(pm); 3935129198Scognet pmap_tlb_flushID(pm); 3936129198Scognet 3937129198Scognet /* 3938129198Scognet * Roll back the previous PTE list, 3939129198Scognet * and zero out the current PTE. 3940129198Scognet */ 3941129198Scognet for (cnt = 0; 3942129198Scognet cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3943129198Scognet *cleanlist[cnt].pte = 0; 3944129198Scognet } 3945129198Scognet *ptep = 0; 3946129198Scognet PTE_SYNC(ptep); 3947129198Scognet cleanlist_idx++; 3948135641Scognet flushall = 1; 3949129198Scognet } else { 3950129198Scognet *ptep = 0; 3951129198Scognet PTE_SYNC(ptep); 3952129198Scognet if (is_exec) 3953129198Scognet pmap_tlb_flushID_SE(pm, sva); 3954129198Scognet else 3955129198Scognet if (is_refd) 3956129198Scognet pmap_tlb_flushD_SE(pm, sva); 3957129198Scognet } 3958129198Scognet 3959129198Scognet sva += PAGE_SIZE; 3960129198Scognet ptep++; 3961129198Scognet mappings++; 3962129198Scognet } 3963129198Scognet 3964129198Scognet /* 3965129198Scognet * Deal with any left overs 3966129198Scognet */ 3967129198Scognet if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3968129198Scognet total += cleanlist_idx; 3969129198Scognet for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3970135641Scognet vm_offset_t clva = 3971135641Scognet cleanlist[cnt].va & ~1; 3972135641Scognet if (cleanlist[cnt].va & 1) { 3973135641Scognet pmap_idcache_wbinv_range(pm, 3974135641Scognet clva, PAGE_SIZE); 3975135641Scognet pmap_tlb_flushID_SE(pm, clva); 3976135641Scognet } else { 3977135641Scognet pmap_dcache_wb_range(pm, 3978135641Scognet clva, PAGE_SIZE, TRUE, 3979135641Scognet FALSE); 3980135641Scognet pmap_tlb_flushD_SE(pm, clva); 3981129198Scognet } 3982129198Scognet *cleanlist[cnt].pte = 0; 3983129198Scognet PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 3984129198Scognet } 3985129198Scognet 3986129198Scognet if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3987129198Scognet cleanlist_idx = 0; 3988129198Scognet else { 3989144760Scognet /* 3990144760Scognet * We are removing so much entries it's just 3991144760Scognet * easier to flush the whole cache. 3992144760Scognet */ 3993129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3994129198Scognet pmap_idcache_wbinv_all(pm); 3995135641Scognet flushall = 1; 3996129198Scognet } 3997129198Scognet } 3998129198Scognet 3999129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 4000129198Scognet } 4001129198Scognet 4002137664Scognet vm_page_unlock_queues(); 4003135641Scognet if (flushall) 4004135641Scognet cpu_tlb_flushID(); 4005159352Salc PMAP_UNLOCK(pm); 4006129198Scognet} 4007129198Scognet 4008129198Scognet 4009129198Scognet 4010129198Scognet 4011129198Scognet/* 4012129198Scognet * pmap_zero_page() 4013129198Scognet * 4014129198Scognet * Zero a given physical page by mapping it at a page hook point. 4015129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 4016129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 4017129198Scognet * _any_ bulk data very slow. 4018129198Scognet */ 4019164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3) 4020129198Scognetvoid 4021129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 4022129198Scognet{ 4023161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4024161105Scognet char *dstpg; 4025161105Scognet#endif 4026161105Scognet 4027129198Scognet#ifdef DEBUG 4028129198Scognet struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4029129198Scognet 4030129198Scognet if (pg->md.pvh_list != NULL) 4031129198Scognet panic("pmap_zero_page: page has mappings"); 4032129198Scognet#endif 4033129198Scognet 4034150865Scognet if (_arm_bzero && 4035150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4036150865Scognet return; 4037129198Scognet 4038161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4039161105Scognet dstpg = (char *)arm_ptovirt(phys); 4040161105Scognet if (off || size != PAGE_SIZE) { 4041161105Scognet bzero(dstpg + off, size); 4042161105Scognet cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); 4043161105Scognet } else { 4044161105Scognet bzero_page((vm_offset_t)dstpg); 4045161105Scognet cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); 4046161105Scognet } 4047161105Scognet#else 4048150865Scognet 4049159088Scognet mtx_lock(&cmtx); 4050129198Scognet /* 4051129198Scognet * Hook in the page, zero it, and purge the cache for that 4052129198Scognet * zeroed page. Invalidate the TLB as needed. 4053129198Scognet */ 4054129198Scognet *cdst_pte = L2_S_PROTO | phys | 4055129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4056129198Scognet PTE_SYNC(cdst_pte); 4057129198Scognet cpu_tlb_flushD_SE(cdstp); 4058129198Scognet cpu_cpwait(); 4059161105Scognet if (off || size != PAGE_SIZE) { 4060129198Scognet bzero((void *)(cdstp + off), size); 4061161105Scognet cpu_dcache_wbinv_range(cdstp + off, size); 4062161105Scognet } else { 4063129198Scognet bzero_page(cdstp); 4064161105Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4065161105Scognet } 4066159088Scognet mtx_unlock(&cmtx); 4067161105Scognet#endif 4068129198Scognet} 4069129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4070129198Scognet 4071129198Scognet#if ARM_MMU_XSCALE == 1 4072129198Scognetvoid 4073129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 4074129198Scognet{ 4075150865Scognet if (_arm_bzero && 4076150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4077150865Scognet return; 4078159088Scognet mtx_lock(&cmtx); 4079129198Scognet /* 4080129198Scognet * Hook in the page, zero it, and purge the cache for that 4081129198Scognet * zeroed page. Invalidate the TLB as needed. 4082129198Scognet */ 4083129198Scognet *cdst_pte = L2_S_PROTO | phys | 4084129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4085129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4086129198Scognet PTE_SYNC(cdst_pte); 4087129198Scognet cpu_tlb_flushD_SE(cdstp); 4088129198Scognet cpu_cpwait(); 4089135641Scognet if (off || size != PAGE_SIZE) 4090129198Scognet bzero((void *)(cdstp + off), size); 4091129198Scognet else 4092129198Scognet bzero_page(cdstp); 4093159088Scognet mtx_unlock(&cmtx); 4094129198Scognet xscale_cache_clean_minidata(); 4095129198Scognet} 4096129198Scognet 4097129198Scognet/* 4098129198Scognet * Change the PTEs for the specified kernel mappings such that they 4099129198Scognet * will use the mini data cache instead of the main data cache. 4100129198Scognet */ 4101129198Scognetvoid 4102135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 4103129198Scognet{ 4104129198Scognet struct l2_bucket *l2b; 4105129198Scognet pt_entry_t *ptep, *sptep, pte; 4106129198Scognet vm_offset_t next_bucket, eva; 4107129198Scognet 4108164778Scognet#if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3) 4109129198Scognet if (xscale_use_minidata == 0) 4110129198Scognet return; 4111129198Scognet#endif 4112129198Scognet 4113135641Scognet eva = va + size; 4114129198Scognet 4115129198Scognet while (va < eva) { 4116129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4117129198Scognet if (next_bucket > eva) 4118129198Scognet next_bucket = eva; 4119129198Scognet 4120129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4121129198Scognet 4122129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4123129198Scognet 4124129198Scognet while (va < next_bucket) { 4125129198Scognet pte = *ptep; 4126129198Scognet if (!l2pte_minidata(pte)) { 4127129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4128129198Scognet cpu_tlb_flushD_SE(va); 4129129198Scognet *ptep = pte & ~L2_B; 4130129198Scognet } 4131129198Scognet ptep++; 4132129198Scognet va += PAGE_SIZE; 4133129198Scognet } 4134129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4135129198Scognet } 4136129198Scognet cpu_cpwait(); 4137129198Scognet} 4138129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4139129198Scognet 4140129198Scognet/* 4141129198Scognet * pmap_zero_page zeros the specified hardware page by mapping 4142129198Scognet * the page into KVM and using bzero to clear its contents. 4143129198Scognet */ 4144129198Scognetvoid 4145129198Scognetpmap_zero_page(vm_page_t m) 4146129198Scognet{ 4147135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4148129198Scognet} 4149129198Scognet 4150129198Scognet 4151129198Scognet/* 4152129198Scognet * pmap_zero_page_area zeros the specified hardware page by mapping 4153129198Scognet * the page into KVM and using bzero to clear its contents. 4154129198Scognet * 4155129198Scognet * off and size may not cover an area beyond a single hardware page. 4156129198Scognet */ 4157129198Scognetvoid 4158129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4159129198Scognet{ 4160129198Scognet 4161129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4162129198Scognet} 4163129198Scognet 4164129198Scognet 4165129198Scognet/* 4166129198Scognet * pmap_zero_page_idle zeros the specified hardware page by mapping 4167129198Scognet * the page into KVM and using bzero to clear its contents. This 4168129198Scognet * is intended to be called from the vm_pagezero process only and 4169129198Scognet * outside of Giant. 4170129198Scognet */ 4171129198Scognetvoid 4172129198Scognetpmap_zero_page_idle(vm_page_t m) 4173129198Scognet{ 4174129198Scognet 4175129198Scognet pmap_zero_page(m); 4176129198Scognet} 4177129198Scognet 4178150865Scognet#if 0 4179129198Scognet/* 4180129198Scognet * pmap_clean_page() 4181129198Scognet * 4182129198Scognet * This is a local function used to work out the best strategy to clean 4183129198Scognet * a single page referenced by its entry in the PV table. It's used by 4184129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4185129198Scognet * 4186129198Scognet * Its policy is effectively: 4187129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4188129198Scognet * o If there is one mapping, we clean just that page. 4189129198Scognet * o If there are multiple mappings, we clean the entire cache. 4190129198Scognet * 4191129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4192129198Scognet * clean the entire cache, or 1 if it did. 4193129198Scognet * 4194129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4195129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4196129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4197129198Scognet * it will just result in not the most efficient clean for the page. 4198129198Scognet */ 4199129198Scognetstatic int 4200129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4201129198Scognet{ 4202129198Scognet pmap_t pm, pm_to_clean = NULL; 4203129198Scognet struct pv_entry *npv; 4204129198Scognet u_int cache_needs_cleaning = 0; 4205129198Scognet u_int flags = 0; 4206129198Scognet vm_offset_t page_to_clean = 0; 4207129198Scognet 4208129198Scognet if (pv == NULL) { 4209129198Scognet /* nothing mapped in so nothing to flush */ 4210129198Scognet return (0); 4211129198Scognet } 4212129198Scognet 4213129198Scognet /* 4214129198Scognet * Since we flush the cache each time we change to a different 4215129198Scognet * user vmspace, we only need to flush the page if it is in the 4216129198Scognet * current pmap. 4217129198Scognet */ 4218135641Scognet if (curthread) 4219135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4220129198Scognet else 4221129198Scognet pm = pmap_kernel(); 4222129198Scognet 4223129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4224129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4225129198Scognet flags |= npv->pv_flags; 4226129198Scognet /* 4227129198Scognet * The page is mapped non-cacheable in 4228129198Scognet * this map. No need to flush the cache. 4229129198Scognet */ 4230129198Scognet if (npv->pv_flags & PVF_NC) { 4231129198Scognet#ifdef DIAGNOSTIC 4232129198Scognet if (cache_needs_cleaning) 4233129198Scognet panic("pmap_clean_page: " 4234129198Scognet "cache inconsistency"); 4235129198Scognet#endif 4236129198Scognet break; 4237129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4238129198Scognet continue; 4239129198Scognet if (cache_needs_cleaning) { 4240129198Scognet page_to_clean = 0; 4241129198Scognet break; 4242129198Scognet } else { 4243129198Scognet page_to_clean = npv->pv_va; 4244129198Scognet pm_to_clean = npv->pv_pmap; 4245129198Scognet } 4246129198Scognet cache_needs_cleaning = 1; 4247129198Scognet } 4248129198Scognet } 4249129198Scognet if (page_to_clean) { 4250129198Scognet if (PV_BEEN_EXECD(flags)) 4251129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4252129198Scognet PAGE_SIZE); 4253129198Scognet else 4254129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4255129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4256129198Scognet } else if (cache_needs_cleaning) { 4257129198Scognet if (PV_BEEN_EXECD(flags)) 4258129198Scognet pmap_idcache_wbinv_all(pm); 4259129198Scognet else 4260129198Scognet pmap_dcache_wbinv_all(pm); 4261129198Scognet return (1); 4262129198Scognet } 4263129198Scognet return (0); 4264129198Scognet} 4265150865Scognet#endif 4266129198Scognet 4267129198Scognet/* 4268129198Scognet * pmap_copy_page copies the specified (machine independent) 4269129198Scognet * page by mapping the page into virtual memory and using 4270129198Scognet * bcopy to copy the page, one machine dependent page at a 4271129198Scognet * time. 4272129198Scognet */ 4273129198Scognet 4274129198Scognet/* 4275129198Scognet * pmap_copy_page() 4276129198Scognet * 4277129198Scognet * Copy one physical page into another, by mapping the pages into 4278129198Scognet * hook points. The same comment regarding cachability as in 4279129198Scognet * pmap_zero_page also applies here. 4280129198Scognet */ 4281164778Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3) 4282129198Scognetvoid 4283129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4284129198Scognet{ 4285151596Scognet#if 0 4286129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4287151596Scognet#endif 4288129198Scognet#ifdef DEBUG 4289129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4290129198Scognet 4291129198Scognet if (dst_pg->md.pvh_list != NULL) 4292129198Scognet panic("pmap_copy_page: dst page has mappings"); 4293129198Scognet#endif 4294129198Scognet 4295129198Scognet 4296129198Scognet /* 4297129198Scognet * Clean the source page. Hold the source page's lock for 4298129198Scognet * the duration of the copy so that no other mappings can 4299129198Scognet * be created while we have a potentially aliased mapping. 4300129198Scognet */ 4301129198Scognet#if 0 4302150865Scognet /* 4303150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4304150865Scognet * pmap_copy_page(). 4305150865Scognet */ 4306129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4307150865Scognet#endif 4308129198Scognet /* 4309129198Scognet * Map the pages into the page hook points, copy them, and purge 4310129198Scognet * the cache for the appropriate page. Invalidate the TLB 4311129198Scognet * as required. 4312129198Scognet */ 4313159088Scognet mtx_lock(&cmtx); 4314129198Scognet *csrc_pte = L2_S_PROTO | src | 4315129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4316129198Scognet PTE_SYNC(csrc_pte); 4317129198Scognet *cdst_pte = L2_S_PROTO | dst | 4318129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4319129198Scognet PTE_SYNC(cdst_pte); 4320129198Scognet cpu_tlb_flushD_SE(csrcp); 4321129198Scognet cpu_tlb_flushD_SE(cdstp); 4322129198Scognet cpu_cpwait(); 4323129198Scognet bcopy_page(csrcp, cdstp); 4324159088Scognet mtx_unlock(&cmtx); 4325129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4326129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4327129198Scognet} 4328129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4329129198Scognet 4330129198Scognet#if ARM_MMU_XSCALE == 1 4331129198Scognetvoid 4332129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4333129198Scognet{ 4334150865Scognet#if 0 4335150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4336129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4337150865Scognet#endif 4338129198Scognet#ifdef DEBUG 4339129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4340129198Scognet 4341129198Scognet if (dst_pg->md.pvh_list != NULL) 4342129198Scognet panic("pmap_copy_page: dst page has mappings"); 4343129198Scognet#endif 4344129198Scognet 4345129198Scognet 4346129198Scognet /* 4347129198Scognet * Clean the source page. Hold the source page's lock for 4348129198Scognet * the duration of the copy so that no other mappings can 4349129198Scognet * be created while we have a potentially aliased mapping. 4350129198Scognet */ 4351150865Scognet#if 0 4352150865Scognet /* 4353150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4354150865Scognet * pmap_copy_page(). 4355150865Scognet */ 4356130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4357150865Scognet#endif 4358129198Scognet /* 4359129198Scognet * Map the pages into the page hook points, copy them, and purge 4360129198Scognet * the cache for the appropriate page. Invalidate the TLB 4361129198Scognet * as required. 4362129198Scognet */ 4363159088Scognet mtx_lock(&cmtx); 4364129198Scognet *csrc_pte = L2_S_PROTO | src | 4365129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4366129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4367129198Scognet PTE_SYNC(csrc_pte); 4368129198Scognet *cdst_pte = L2_S_PROTO | dst | 4369129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4370129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4371129198Scognet PTE_SYNC(cdst_pte); 4372129198Scognet cpu_tlb_flushD_SE(csrcp); 4373129198Scognet cpu_tlb_flushD_SE(cdstp); 4374129198Scognet cpu_cpwait(); 4375129198Scognet bcopy_page(csrcp, cdstp); 4376159088Scognet mtx_unlock(&cmtx); 4377129198Scognet xscale_cache_clean_minidata(); 4378129198Scognet} 4379129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4380129198Scognet 4381129198Scognetvoid 4382129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4383129198Scognet{ 4384161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4385161105Scognet vm_offset_t srcpg, dstpg; 4386161105Scognet#endif 4387161105Scognet 4388146596Scognet cpu_dcache_wbinv_all(); 4389150865Scognet if (_arm_memcpy && 4390150865Scognet _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4391150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4392150865Scognet return; 4393161105Scognet#ifdef ARM_USE_SMALL_ALLOC 4394161105Scognet srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src)); 4395161105Scognet dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst)); 4396161105Scognet bcopy_page(srcpg, dstpg); 4397161105Scognet cpu_dcache_wbinv_range(dstpg, PAGE_SIZE); 4398161105Scognet#else 4399129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4400161105Scognet#endif 4401129198Scognet} 4402129198Scognet 4403129198Scognet 4404129198Scognet 4405129198Scognet 4406129198Scognet/* 4407129198Scognet * this routine returns true if a physical page resides 4408129198Scognet * in the given pmap. 4409129198Scognet */ 4410129198Scognetboolean_t 4411129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4412129198Scognet{ 4413129198Scognet pv_entry_t pv; 4414129198Scognet int loops = 0; 4415129198Scognet 4416147217Salc if (m->flags & PG_FICTITIOUS) 4417129198Scognet return (FALSE); 4418129198Scognet 4419129198Scognet /* 4420129198Scognet * Not found, check current mappings returning immediately 4421129198Scognet */ 4422129198Scognet for (pv = TAILQ_FIRST(&m->md.pv_list); 4423129198Scognet pv; 4424129198Scognet pv = TAILQ_NEXT(pv, pv_list)) { 4425129198Scognet if (pv->pv_pmap == pmap) { 4426129198Scognet return (TRUE); 4427129198Scognet } 4428129198Scognet loops++; 4429129198Scognet if (loops >= 16) 4430129198Scognet break; 4431129198Scognet } 4432129198Scognet return (FALSE); 4433129198Scognet} 4434129198Scognet 4435129198Scognet 4436129198Scognet/* 4437129198Scognet * pmap_ts_referenced: 4438129198Scognet * 4439129198Scognet * Return the count of reference bits for a page, clearing all of them. 4440129198Scognet */ 4441129198Scognetint 4442129198Scognetpmap_ts_referenced(vm_page_t m) 4443129198Scognet{ 4444164778Scognet 4445164779Scognet if (m->flags & PG_FICTITIOUS) 4446164779Scognet return (0); 4447135641Scognet return (pmap_clearbit(m, PVF_REF)); 4448129198Scognet} 4449129198Scognet 4450129198Scognet 4451129198Scognetboolean_t 4452129198Scognetpmap_is_modified(vm_page_t m) 4453129198Scognet{ 4454135641Scognet 4455135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4456135641Scognet return (TRUE); 4457129198Scognet 4458129198Scognet return(FALSE); 4459129198Scognet} 4460129198Scognet 4461129198Scognet 4462129198Scognet/* 4463129198Scognet * Clear the modify bits on the specified physical page. 4464129198Scognet */ 4465129198Scognetvoid 4466129198Scognetpmap_clear_modify(vm_page_t m) 4467129198Scognet{ 4468129198Scognet 4469129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4470129198Scognet pmap_clearbit(m, PVF_MOD); 4471129198Scognet} 4472129198Scognet 4473129198Scognet 4474129198Scognet/* 4475129198Scognet * pmap_clear_reference: 4476129198Scognet * 4477129198Scognet * Clear the reference bit on the specified physical page. 4478129198Scognet */ 4479129198Scognetvoid 4480129198Scognetpmap_clear_reference(vm_page_t m) 4481129198Scognet{ 4482129198Scognet 4483129198Scognet if (m->md.pvh_attrs & PVF_REF) 4484129198Scognet pmap_clearbit(m, PVF_REF); 4485129198Scognet} 4486129198Scognet 4487129198Scognet 4488129198Scognet/* 4489160537Salc * Clear the write and modified bits in each of the given page's mappings. 4490160537Salc */ 4491160537Salcvoid 4492160889Salcpmap_remove_write(vm_page_t m) 4493160537Salc{ 4494160537Salc 4495161705Scognet if (m->flags & PG_WRITEABLE) 4496160537Salc pmap_clearbit(m, PVF_WRITE); 4497160537Salc} 4498160537Salc 4499160537Salc 4500160537Salc/* 4501129198Scognet * perform the pmap work for mincore 4502129198Scognet */ 4503129198Scognetint 4504129198Scognetpmap_mincore(pmap_t pmap, vm_offset_t addr) 4505129198Scognet{ 4506129198Scognet printf("pmap_mincore()\n"); 4507129198Scognet 4508129198Scognet return (0); 4509129198Scognet} 4510129198Scognet 4511129198Scognet 4512129198Scognetvm_offset_t 4513129198Scognetpmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 4514129198Scognet{ 4515129198Scognet 4516129198Scognet return(addr); 4517129198Scognet} 4518129198Scognet 4519129198Scognet 4520129198Scognet/* 4521129198Scognet * Map a set of physical memory pages into the kernel virtual 4522129198Scognet * address space. Return a pointer to where it is mapped. This 4523129198Scognet * routine is intended to be used for mapping device memory, 4524129198Scognet * NOT real memory. 4525129198Scognet */ 4526129198Scognetvoid * 4527129198Scognetpmap_mapdev(vm_offset_t pa, vm_size_t size) 4528129198Scognet{ 4529129198Scognet vm_offset_t va, tmpva, offset; 4530129198Scognet 4531129198Scognet offset = pa & PAGE_MASK; 4532135641Scognet size = roundup(size, PAGE_SIZE); 4533129198Scognet 4534129198Scognet GIANT_REQUIRED; 4535129198Scognet 4536132560Salc va = kmem_alloc_nofault(kernel_map, size); 4537129198Scognet if (!va) 4538129198Scognet panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4539129198Scognet for (tmpva = va; size > 0;) { 4540135641Scognet pmap_kenter_internal(tmpva, pa, 0); 4541129198Scognet size -= PAGE_SIZE; 4542129198Scognet tmpva += PAGE_SIZE; 4543129198Scognet pa += PAGE_SIZE; 4544129198Scognet } 4545129198Scognet 4546159068Sbenno return ((void *)(va + offset)); 4547129198Scognet} 4548129198Scognet 4549129198Scognet#define BOOTSTRAP_DEBUG 4550129198Scognet 4551129198Scognet/* 4552129198Scognet * pmap_map_section: 4553129198Scognet * 4554129198Scognet * Create a single section mapping. 4555129198Scognet */ 4556129198Scognetvoid 4557129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4558129198Scognet int prot, int cache) 4559129198Scognet{ 4560129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4561129198Scognet pd_entry_t fl; 4562129198Scognet 4563129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4564129198Scognet 4565129198Scognet switch (cache) { 4566129198Scognet case PTE_NOCACHE: 4567129198Scognet default: 4568129198Scognet fl = 0; 4569129198Scognet break; 4570129198Scognet 4571129198Scognet case PTE_CACHE: 4572129198Scognet fl = pte_l1_s_cache_mode; 4573129198Scognet break; 4574129198Scognet 4575129198Scognet case PTE_PAGETABLE: 4576129198Scognet fl = pte_l1_s_cache_mode_pt; 4577129198Scognet break; 4578129198Scognet } 4579129198Scognet 4580129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4581129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4582129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4583129198Scognet 4584129198Scognet} 4585129198Scognet 4586129198Scognet/* 4587129198Scognet * pmap_link_l2pt: 4588129198Scognet * 4589164079Scognet * Link the L2 page table specified by l2pv.pv_pa into the L1 4590129198Scognet * page table at the slot for "va". 4591129198Scognet */ 4592129198Scognetvoid 4593129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4594129198Scognet{ 4595129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4596129198Scognet u_int slot = va >> L1_S_SHIFT; 4597129198Scognet 4598129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4599129198Scognet 4600164079Scognet#ifdef VERBOSE_INIT_ARM 4601164079Scognet printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 4602164079Scognet#endif 4603164079Scognet 4604129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4605164079Scognet 4606129198Scognet PTE_SYNC(&pde[slot]); 4607129198Scognet 4608129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4609129198Scognet 4610129198Scognet 4611129198Scognet} 4612129198Scognet 4613129198Scognet/* 4614129198Scognet * pmap_map_entry 4615129198Scognet * 4616129198Scognet * Create a single page mapping. 4617129198Scognet */ 4618129198Scognetvoid 4619129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4620129198Scognet int cache) 4621129198Scognet{ 4622129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4623129198Scognet pt_entry_t fl; 4624129198Scognet pt_entry_t *pte; 4625129198Scognet 4626129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4627129198Scognet 4628129198Scognet switch (cache) { 4629129198Scognet case PTE_NOCACHE: 4630129198Scognet default: 4631129198Scognet fl = 0; 4632129198Scognet break; 4633129198Scognet 4634129198Scognet case PTE_CACHE: 4635129198Scognet fl = pte_l2_s_cache_mode; 4636129198Scognet break; 4637129198Scognet 4638129198Scognet case PTE_PAGETABLE: 4639129198Scognet fl = pte_l2_s_cache_mode_pt; 4640129198Scognet break; 4641129198Scognet } 4642129198Scognet 4643129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4644129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4645129198Scognet 4646129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4647129198Scognet 4648129198Scognet if (pte == NULL) 4649129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4650129198Scognet 4651129198Scognet pte[l2pte_index(va)] = 4652129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4653129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4654129198Scognet} 4655129198Scognet 4656129198Scognet/* 4657129198Scognet * pmap_map_chunk: 4658129198Scognet * 4659129198Scognet * Map a chunk of memory using the most efficient mappings 4660129198Scognet * possible (section. large page, small page) into the 4661129198Scognet * provided L1 and L2 tables at the specified virtual address. 4662129198Scognet */ 4663129198Scognetvm_size_t 4664129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4665129198Scognet vm_size_t size, int prot, int cache) 4666129198Scognet{ 4667129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4668129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4669129198Scognet vm_size_t resid; 4670129198Scognet int i; 4671129198Scognet 4672129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4673129198Scognet 4674129198Scognet if (l1pt == 0) 4675129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4676129198Scognet 4677129198Scognet#ifdef VERBOSE_INIT_ARM 4678159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4679129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4680129198Scognet#endif 4681129198Scognet 4682129198Scognet switch (cache) { 4683129198Scognet case PTE_NOCACHE: 4684129198Scognet default: 4685129198Scognet f1 = 0; 4686129198Scognet f2l = 0; 4687129198Scognet f2s = 0; 4688129198Scognet break; 4689129198Scognet 4690129198Scognet case PTE_CACHE: 4691129198Scognet f1 = pte_l1_s_cache_mode; 4692129198Scognet f2l = pte_l2_l_cache_mode; 4693129198Scognet f2s = pte_l2_s_cache_mode; 4694129198Scognet break; 4695129198Scognet 4696129198Scognet case PTE_PAGETABLE: 4697129198Scognet f1 = pte_l1_s_cache_mode_pt; 4698129198Scognet f2l = pte_l2_l_cache_mode_pt; 4699129198Scognet f2s = pte_l2_s_cache_mode_pt; 4700129198Scognet break; 4701129198Scognet } 4702129198Scognet 4703129198Scognet size = resid; 4704129198Scognet 4705129198Scognet while (resid > 0) { 4706129198Scognet /* See if we can use a section mapping. */ 4707129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4708129198Scognet#ifdef VERBOSE_INIT_ARM 4709129198Scognet printf("S"); 4710129198Scognet#endif 4711129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4712129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4713129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4714129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4715129198Scognet va += L1_S_SIZE; 4716129198Scognet pa += L1_S_SIZE; 4717129198Scognet resid -= L1_S_SIZE; 4718129198Scognet continue; 4719129198Scognet } 4720129198Scognet 4721129198Scognet /* 4722129198Scognet * Ok, we're going to use an L2 table. Make sure 4723129198Scognet * one is actually in the corresponding L1 slot 4724129198Scognet * for the current VA. 4725129198Scognet */ 4726129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4727129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4728129198Scognet 4729129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4730129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4731129198Scognet if (pte == NULL) 4732129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4733129198Scognet "0x%08x", va); 4734129198Scognet /* See if we can use a L2 large page mapping. */ 4735129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4736129198Scognet#ifdef VERBOSE_INIT_ARM 4737129198Scognet printf("L"); 4738129198Scognet#endif 4739129198Scognet for (i = 0; i < 16; i++) { 4740129198Scognet pte[l2pte_index(va) + i] = 4741129198Scognet L2_L_PROTO | pa | 4742129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4743129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4744129198Scognet } 4745129198Scognet va += L2_L_SIZE; 4746129198Scognet pa += L2_L_SIZE; 4747129198Scognet resid -= L2_L_SIZE; 4748129198Scognet continue; 4749129198Scognet } 4750129198Scognet 4751129198Scognet /* Use a small page mapping. */ 4752129198Scognet#ifdef VERBOSE_INIT_ARM 4753129198Scognet printf("P"); 4754129198Scognet#endif 4755129198Scognet pte[l2pte_index(va)] = 4756129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4757129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4758129198Scognet va += PAGE_SIZE; 4759129198Scognet pa += PAGE_SIZE; 4760129198Scognet resid -= PAGE_SIZE; 4761129198Scognet } 4762129198Scognet#ifdef VERBOSE_INIT_ARM 4763129198Scognet printf("\n"); 4764129198Scognet#endif 4765129198Scognet return (size); 4766129198Scognet 4767129198Scognet} 4768129198Scognet 4769135641Scognet/********************** Static device map routines ***************************/ 4770135641Scognet 4771135641Scognetstatic const struct pmap_devmap *pmap_devmap_table; 4772135641Scognet 4773135641Scognet/* 4774135641Scognet * Register the devmap table. This is provided in case early console 4775135641Scognet * initialization needs to register mappings created by bootstrap code 4776135641Scognet * before pmap_devmap_bootstrap() is called. 4777135641Scognet */ 4778135641Scognetvoid 4779135641Scognetpmap_devmap_register(const struct pmap_devmap *table) 4780135641Scognet{ 4781135641Scognet 4782135641Scognet pmap_devmap_table = table; 4783135641Scognet} 4784135641Scognet 4785135641Scognet/* 4786135641Scognet * Map all of the static regions in the devmap table, and remember 4787135641Scognet * the devmap table so other parts of the kernel can look up entries 4788135641Scognet * later. 4789135641Scognet */ 4790135641Scognetvoid 4791135641Scognetpmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4792135641Scognet{ 4793135641Scognet int i; 4794135641Scognet 4795135641Scognet pmap_devmap_table = table; 4796135641Scognet 4797135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4798135641Scognet#ifdef VERBOSE_INIT_ARM 4799159322Scognet printf("devmap: %08x -> %08x @ %08x\n", 4800135641Scognet pmap_devmap_table[i].pd_pa, 4801135641Scognet pmap_devmap_table[i].pd_pa + 4802135641Scognet pmap_devmap_table[i].pd_size - 1, 4803135641Scognet pmap_devmap_table[i].pd_va); 4804135641Scognet#endif 4805135641Scognet pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4806135641Scognet pmap_devmap_table[i].pd_pa, 4807135641Scognet pmap_devmap_table[i].pd_size, 4808135641Scognet pmap_devmap_table[i].pd_prot, 4809135641Scognet pmap_devmap_table[i].pd_cache); 4810135641Scognet } 4811135641Scognet} 4812135641Scognet 4813135641Scognetconst struct pmap_devmap * 4814135641Scognetpmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4815135641Scognet{ 4816135641Scognet int i; 4817135641Scognet 4818135641Scognet if (pmap_devmap_table == NULL) 4819135641Scognet return (NULL); 4820135641Scognet 4821135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4822135641Scognet if (pa >= pmap_devmap_table[i].pd_pa && 4823135641Scognet pa + size <= pmap_devmap_table[i].pd_pa + 4824135641Scognet pmap_devmap_table[i].pd_size) 4825135641Scognet return (&pmap_devmap_table[i]); 4826135641Scognet } 4827135641Scognet 4828135641Scognet return (NULL); 4829135641Scognet} 4830135641Scognet 4831135641Scognetconst struct pmap_devmap * 4832135641Scognetpmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4833135641Scognet{ 4834135641Scognet int i; 4835135641Scognet 4836135641Scognet if (pmap_devmap_table == NULL) 4837135641Scognet return (NULL); 4838135641Scognet 4839135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4840135641Scognet if (va >= pmap_devmap_table[i].pd_va && 4841135641Scognet va + size <= pmap_devmap_table[i].pd_va + 4842135641Scognet pmap_devmap_table[i].pd_size) 4843135641Scognet return (&pmap_devmap_table[i]); 4844135641Scognet } 4845135641Scognet 4846135641Scognet return (NULL); 4847135641Scognet} 4848135641Scognet 4849