pmap-v4.c revision 160537
1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 3. All advertising materials mentioning features or use of this software 81129198Scognet * must display the following acknowledgement: 82129198Scognet * This product includes software developed by the NetBSD 83129198Scognet * Foundation, Inc. and its contributors. 84129198Scognet * 4. Neither the name of The NetBSD Foundation nor the names of its 85129198Scognet * contributors may be used to endorse or promote products derived 86129198Scognet * from this software without specific prior written permission. 87129198Scognet * 88129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 89129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 90129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 91129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 92129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 93129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 94129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 95129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 96129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 97129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98129198Scognet * POSSIBILITY OF SUCH DAMAGE. 99129198Scognet */ 100129198Scognet 101139735Simp/*- 102129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 103129198Scognet * Copyright (c) 1994 Brini. 104129198Scognet * All rights reserved. 105139735Simp * 106129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 107129198Scognet * 108129198Scognet * Redistribution and use in source and binary forms, with or without 109129198Scognet * modification, are permitted provided that the following conditions 110129198Scognet * are met: 111129198Scognet * 1. Redistributions of source code must retain the above copyright 112129198Scognet * notice, this list of conditions and the following disclaimer. 113129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 114129198Scognet * notice, this list of conditions and the following disclaimer in the 115129198Scognet * documentation and/or other materials provided with the distribution. 116129198Scognet * 3. All advertising materials mentioning features or use of this software 117129198Scognet * must display the following acknowledgement: 118129198Scognet * This product includes software developed by Mark Brinicombe. 119129198Scognet * 4. The name of the author may not be used to endorse or promote products 120129198Scognet * derived from this software without specific prior written permission. 121129198Scognet * 122129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 123129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 124129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 125129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 126129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 127129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 128129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 129129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 130129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 131129198Scognet * 132129198Scognet * RiscBSD kernel project 133129198Scognet * 134129198Scognet * pmap.c 135129198Scognet * 136129198Scognet * Machine dependant vm stuff 137129198Scognet * 138129198Scognet * Created : 20/09/94 139129198Scognet */ 140129198Scognet 141129198Scognet/* 142129198Scognet * Special compilation symbols 143129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 144129198Scognet */ 145129198Scognet/* Include header files */ 146135641Scognet 147137552Scognet#include "opt_vm.h" 148137552Scognet 149129198Scognet#include <sys/cdefs.h> 150129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 160537 2006-07-20 23:26:22Z alc $"); 151129198Scognet#include <sys/param.h> 152129198Scognet#include <sys/systm.h> 153129198Scognet#include <sys/kernel.h> 154129198Scognet#include <sys/proc.h> 155129198Scognet#include <sys/malloc.h> 156129198Scognet#include <sys/msgbuf.h> 157129198Scognet#include <sys/vmmeter.h> 158129198Scognet#include <sys/mman.h> 159129198Scognet#include <sys/smp.h> 160129198Scognet#include <sys/sx.h> 161129198Scognet#include <sys/sched.h> 162129198Scognet 163129198Scognet#include <vm/vm.h> 164129198Scognet#include <vm/uma.h> 165129198Scognet#include <vm/pmap.h> 166129198Scognet#include <vm/vm_kern.h> 167129198Scognet#include <vm/vm_object.h> 168129198Scognet#include <vm/vm_map.h> 169129198Scognet#include <vm/vm_page.h> 170129198Scognet#include <vm/vm_pageout.h> 171129198Scognet#include <vm/vm_extern.h> 172129198Scognet#include <sys/lock.h> 173129198Scognet#include <sys/mutex.h> 174129198Scognet#include <machine/md_var.h> 175129198Scognet#include <machine/vmparam.h> 176129198Scognet#include <machine/cpu.h> 177129198Scognet#include <machine/cpufunc.h> 178129198Scognet#include <machine/pcb.h> 179129198Scognet 180129198Scognet#ifdef PMAP_DEBUG 181129198Scognet#define PDEBUG(_lev_,_stat_) \ 182129198Scognet if (pmap_debug_level >= (_lev_)) \ 183129198Scognet ((_stat_)) 184129198Scognet#define dprintf printf 185129198Scognet 186129198Scognetint pmap_debug_level = 0; 187135641Scognet#define PMAP_INLINE 188129198Scognet#else /* PMAP_DEBUG */ 189129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 190129198Scognet#define dprintf(x, arg...) 191135641Scognet#define PMAP_INLINE __inline 192129198Scognet#endif /* PMAP_DEBUG */ 193129198Scognet 194129198Scognetextern struct pv_addr systempage; 195129198Scognet/* 196129198Scognet * Internal function prototypes 197129198Scognet */ 198135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 199129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 200129198Scognet 201159127Salcstatic void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 202160260Scognet vm_prot_t, boolean_t, int); 203129198Scognetstatic void pmap_vac_me_harder(struct vm_page *, pmap_t, 204129198Scognet vm_offset_t); 205129198Scognetstatic void pmap_vac_me_kpmap(struct vm_page *, pmap_t, 206129198Scognet vm_offset_t); 207129198Scognetstatic void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t); 208129198Scognetstatic void pmap_alloc_l1(pmap_t); 209129198Scognetstatic void pmap_free_l1(pmap_t); 210129198Scognetstatic void pmap_use_l1(pmap_t); 211129198Scognet 212135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 213129198Scognet 214129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 215129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 216129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 217129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 218129198Scognet 219129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 220129198Scognet 221129198Scognetvm_offset_t avail_end; /* PA of last available physical page */ 222129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 223129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 224135641Scognetvm_offset_t pmap_curmaxkvaddr; 225150865Scognetvm_paddr_t kernel_l1pa; 226129198Scognet 227129198Scognetextern void *end; 228129198Scognetvm_offset_t kernel_vm_end = 0; 229129198Scognet 230129198Scognetstruct pmap kernel_pmap_store; 231129198Scognetpmap_t kernel_pmap; 232129198Scognet 233129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 234129198Scognetstatic vm_offset_t csrcp, cdstp; 235159088Scognetstatic struct mtx cmtx; 236159088Scognet 237129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 238129198Scognet/* 239129198Scognet * These routines are called when the CPU type is identified to set up 240129198Scognet * the PTE prototypes, cache modes, etc. 241129198Scognet * 242129198Scognet * The variables are always here, just in case LKMs need to reference 243129198Scognet * them (though, they shouldn't). 244129198Scognet */ 245129198Scognet 246129198Scognetpt_entry_t pte_l1_s_cache_mode; 247129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 248129198Scognetpt_entry_t pte_l1_s_cache_mask; 249129198Scognet 250129198Scognetpt_entry_t pte_l2_l_cache_mode; 251129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 252129198Scognetpt_entry_t pte_l2_l_cache_mask; 253129198Scognet 254129198Scognetpt_entry_t pte_l2_s_cache_mode; 255129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 256129198Scognetpt_entry_t pte_l2_s_cache_mask; 257129198Scognet 258129198Scognetpt_entry_t pte_l2_s_prot_u; 259129198Scognetpt_entry_t pte_l2_s_prot_w; 260129198Scognetpt_entry_t pte_l2_s_prot_mask; 261129198Scognet 262129198Scognetpt_entry_t pte_l1_s_proto; 263129198Scognetpt_entry_t pte_l1_c_proto; 264129198Scognetpt_entry_t pte_l2_s_proto; 265129198Scognet 266129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 267129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 268129198Scognet/* 269129198Scognet * Which pmap is currently 'live' in the cache 270129198Scognet * 271129198Scognet * XXXSCW: Fix for SMP ... 272129198Scognet */ 273129198Scognetunion pmap_cache_state *pmap_cache_state; 274129198Scognet 275129198Scognet/* static pt_entry_t *msgbufmap;*/ 276129198Scognetstruct msgbuf *msgbufp = 0; 277129198Scognet 278129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 279129198Scognetextern void bzero_page(vm_offset_t); 280137362Scognet 281137362Scognetchar *_tmppt; 282137362Scognet 283129198Scognet/* 284129198Scognet * Metadata for L1 translation tables. 285129198Scognet */ 286129198Scognetstruct l1_ttable { 287129198Scognet /* Entry on the L1 Table list */ 288129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 289129198Scognet 290129198Scognet /* Entry on the L1 Least Recently Used list */ 291129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 292129198Scognet 293129198Scognet /* Track how many domains are allocated from this L1 */ 294129198Scognet volatile u_int l1_domain_use_count; 295129198Scognet 296129198Scognet /* 297129198Scognet * A free-list of domain numbers for this L1. 298129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 299129198Scognet * is slow on ARM. 300129198Scognet */ 301129198Scognet u_int8_t l1_domain_first; 302129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 303129198Scognet 304129198Scognet /* Physical address of this L1 page table */ 305129198Scognet vm_paddr_t l1_physaddr; 306129198Scognet 307129198Scognet /* KVA of this L1 page table */ 308129198Scognet pd_entry_t *l1_kva; 309129198Scognet}; 310129198Scognet 311129198Scognet/* 312129198Scognet * Convert a virtual address into its L1 table index. That is, the 313129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 314129198Scognet * This is basically used to index l1->l1_kva[]. 315129198Scognet * 316129198Scognet * Each L2 descriptor table represents 1MB of VA space. 317129198Scognet */ 318129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 319129198Scognet 320129198Scognet/* 321129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 322129198Scognet * - New L1s are allocated from the HEAD. 323129198Scognet * - Freed L1s are added to the TAIl. 324129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 325129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 326129198Scognet */ 327129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 328135641Scognet/* 329135641Scognet * A list of all L1 tables 330135641Scognet */ 331135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 332129198Scognetstatic struct mtx l1_lru_lock; 333129198Scognet 334129198Scognet/* 335129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 336129198Scognet * 337129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 338129198Scognet * Reference counts are maintained for L2 descriptors so they can be 339129198Scognet * freed when empty. 340129198Scognet */ 341129198Scognetstruct l2_dtable { 342129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 343129198Scognet u_int l2_occupancy; 344129198Scognet 345129198Scognet /* List of L2 page descriptors */ 346129198Scognet struct l2_bucket { 347129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 348129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 349129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 350129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 351129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 352129198Scognet}; 353129198Scognet 354135641Scognet/* pmap_kenter_internal flags */ 355135641Scognet#define KENTER_CACHE 0x1 356142570Scognet#define KENTER_USER 0x2 357135641Scognet 358129198Scognet/* 359129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 360129198Scognet * and bucket index within the l2_dtable. 361129198Scognet */ 362129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 363129198Scognet (L2_SIZE - 1)) 364129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 365129198Scognet 366129198Scognet/* 367129198Scognet * Given a virtual address, this macro returns the 368129198Scognet * virtual address required to drop into the next L2 bucket. 369129198Scognet */ 370129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 371129198Scognet 372129198Scognet/* 373129198Scognet * L2 allocation. 374129198Scognet */ 375129198Scognet#define pmap_alloc_l2_dtable() \ 376160260Scognet (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE) 377129198Scognet#define pmap_free_l2_dtable(l2) \ 378129198Scognet uma_zfree(l2table_zone, l2) 379129198Scognet 380129198Scognet/* 381129198Scognet * We try to map the page tables write-through, if possible. However, not 382129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 383129198Scognet * the cache when we frob page tables. 384129198Scognet * 385129198Scognet * We try to evaluate this at compile time, if possible. However, it's 386129198Scognet * not always possible to do that, hence this run-time var. 387129198Scognet */ 388129198Scognetint pmap_needs_pte_sync; 389129198Scognet 390129198Scognet/* 391129198Scognet * Macro to determine if a mapping might be resident in the 392129198Scognet * instruction cache and/or TLB 393129198Scognet */ 394129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 395129198Scognet 396129198Scognet/* 397129198Scognet * Macro to determine if a mapping might be resident in the 398129198Scognet * data cache and/or TLB 399129198Scognet */ 400129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 401129198Scognet 402129198Scognet#ifndef PMAP_SHPGPERPROC 403129198Scognet#define PMAP_SHPGPERPROC 200 404129198Scognet#endif 405129198Scognet 406135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 407135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 408129198Scognetstatic uma_zone_t pvzone; 409147114Scognetuma_zone_t l2zone; 410129198Scognetstatic uma_zone_t l2table_zone; 411135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 412135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 413135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 414129198Scognetstatic struct vm_object pvzone_obj; 415129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 416129198Scognet 417129198Scognet/* 418129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 419129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 420129198Scognet * find them as necessary. 421129198Scognet * 422129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 423129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 424129198Scognet */ 425129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 426129198Scognet 427129198Scognetstatic void 428129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 429129198Scognet{ 430129198Scognet int i; 431129198Scognet 432129198Scognet l1->l1_kva = l1pt; 433129198Scognet l1->l1_domain_use_count = 0; 434129198Scognet l1->l1_domain_first = 0; 435129198Scognet 436129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 437129198Scognet l1->l1_domain_free[i] = i + 1; 438129198Scognet 439129198Scognet /* 440129198Scognet * Copy the kernel's L1 entries to each new L1. 441129198Scognet */ 442147249Scognet if (l1pt != pmap_kernel()->pm_l1->l1_kva) 443129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 444129198Scognet 445129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 446129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 447135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 448129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 449129198Scognet} 450129198Scognet 451129198Scognetstatic vm_offset_t 452129198Scognetkernel_pt_lookup(vm_paddr_t pa) 453129198Scognet{ 454129198Scognet struct pv_addr *pv; 455129198Scognet 456129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 457129198Scognet if (pv->pv_pa == pa) 458129198Scognet return (pv->pv_va); 459129198Scognet } 460129198Scognet return (0); 461129198Scognet} 462129198Scognet 463129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 464129198Scognetvoid 465129198Scognetpmap_pte_init_generic(void) 466129198Scognet{ 467129198Scognet 468129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 469129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 470129198Scognet 471129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 472129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 473129198Scognet 474129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 475129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 476129198Scognet 477129198Scognet /* 478129198Scognet * If we have a write-through cache, set B and C. If 479129198Scognet * we have a write-back cache, then we assume setting 480129198Scognet * only C will make those pages write-through. 481129198Scognet */ 482129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 483129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 484129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 485129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 486129198Scognet } else { 487129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 488129198Scognet pte_l2_l_cache_mode_pt = L2_C; 489129198Scognet pte_l2_s_cache_mode_pt = L2_C; 490129198Scognet } 491129198Scognet 492129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 493129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 494129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 495129198Scognet 496129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 497129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 498129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 499129198Scognet 500129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 501129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 502129198Scognet} 503129198Scognet 504129198Scognet#if defined(CPU_ARM8) 505129198Scognetvoid 506129198Scognetpmap_pte_init_arm8(void) 507129198Scognet{ 508129198Scognet 509129198Scognet /* 510129198Scognet * ARM8 is compatible with generic, but we need to use 511129198Scognet * the page tables uncached. 512129198Scognet */ 513129198Scognet pmap_pte_init_generic(); 514129198Scognet 515129198Scognet pte_l1_s_cache_mode_pt = 0; 516129198Scognet pte_l2_l_cache_mode_pt = 0; 517129198Scognet pte_l2_s_cache_mode_pt = 0; 518129198Scognet} 519129198Scognet#endif /* CPU_ARM8 */ 520129198Scognet 521129198Scognet#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 522129198Scognetvoid 523129198Scognetpmap_pte_init_arm9(void) 524129198Scognet{ 525129198Scognet 526129198Scognet /* 527129198Scognet * ARM9 is compatible with generic, but we want to use 528129198Scognet * write-through caching for now. 529129198Scognet */ 530129198Scognet pmap_pte_init_generic(); 531129198Scognet 532129198Scognet pte_l1_s_cache_mode = L1_S_C; 533129198Scognet pte_l2_l_cache_mode = L2_C; 534129198Scognet pte_l2_s_cache_mode = L2_C; 535129198Scognet 536129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 537129198Scognet pte_l2_l_cache_mode_pt = L2_C; 538129198Scognet pte_l2_s_cache_mode_pt = L2_C; 539129198Scognet} 540129198Scognet#endif /* CPU_ARM9 */ 541129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 542129198Scognet 543129198Scognet#if defined(CPU_ARM10) 544129198Scognetvoid 545129198Scognetpmap_pte_init_arm10(void) 546129198Scognet{ 547129198Scognet 548129198Scognet /* 549129198Scognet * ARM10 is compatible with generic, but we want to use 550129198Scognet * write-through caching for now. 551129198Scognet */ 552129198Scognet pmap_pte_init_generic(); 553129198Scognet 554129198Scognet pte_l1_s_cache_mode = L1_S_B | L1_S_C; 555129198Scognet pte_l2_l_cache_mode = L2_B | L2_C; 556129198Scognet pte_l2_s_cache_mode = L2_B | L2_C; 557129198Scognet 558129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 559129198Scognet pte_l2_l_cache_mode_pt = L2_C; 560129198Scognet pte_l2_s_cache_mode_pt = L2_C; 561129198Scognet 562129198Scognet} 563129198Scognet#endif /* CPU_ARM10 */ 564129198Scognet 565129198Scognet#if ARM_MMU_SA1 == 1 566129198Scognetvoid 567129198Scognetpmap_pte_init_sa1(void) 568129198Scognet{ 569129198Scognet 570129198Scognet /* 571129198Scognet * The StrongARM SA-1 cache does not have a write-through 572129198Scognet * mode. So, do the generic initialization, then reset 573129198Scognet * the page table cache mode to B=1,C=1, and note that 574129198Scognet * the PTEs need to be sync'd. 575129198Scognet */ 576129198Scognet pmap_pte_init_generic(); 577129198Scognet 578129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 579129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 580129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 581129198Scognet 582129198Scognet pmap_needs_pte_sync = 1; 583129198Scognet} 584129198Scognet#endif /* ARM_MMU_SA1 == 1*/ 585129198Scognet 586129198Scognet#if ARM_MMU_XSCALE == 1 587129198Scognet#if (ARM_NMMUS > 1) 588129198Scognetstatic u_int xscale_use_minidata; 589129198Scognet#endif 590129198Scognet 591129198Scognetvoid 592129198Scognetpmap_pte_init_xscale(void) 593129198Scognet{ 594129198Scognet uint32_t auxctl; 595129198Scognet int write_through = 0; 596129198Scognet 597135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 598129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 599129198Scognet 600129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 601129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 602129198Scognet 603129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 604129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 605129198Scognet 606129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 607129198Scognet pte_l2_l_cache_mode_pt = L2_C; 608129198Scognet pte_l2_s_cache_mode_pt = L2_C; 609129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 610129198Scognet /* 611129198Scognet * The XScale core has an enhanced mode where writes that 612129198Scognet * miss the cache cause a cache line to be allocated. This 613129198Scognet * is significantly faster than the traditional, write-through 614129198Scognet * behavior of this case. 615129198Scognet */ 616129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 617129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 618129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 619129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 620129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 621129198Scognet /* 622129198Scognet * Some versions of the XScale core have various bugs in 623129198Scognet * their cache units, the work-around for which is to run 624129198Scognet * the cache in write-through mode. Unfortunately, this 625129198Scognet * has a major (negative) impact on performance. So, we 626129198Scognet * go ahead and run fast-and-loose, in the hopes that we 627129198Scognet * don't line up the planets in a way that will trip the 628129198Scognet * bugs. 629129198Scognet * 630129198Scognet * However, we give you the option to be slow-but-correct. 631129198Scognet */ 632129198Scognet write_through = 1; 633129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 634129198Scognet /* force write back cache mode */ 635129198Scognet write_through = 0; 636129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 637129198Scognet /* 638129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 639129198Scognet * write-back cache on revision 4 and earlier (stepping 640129198Scognet * A[01] and B[012]). Fixed for C0 and later. 641129198Scognet */ 642129198Scognet { 643129198Scognet uint32_t id, type; 644129198Scognet 645129198Scognet id = cpufunc_id(); 646129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 647129198Scognet 648129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 649129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 650129198Scognet /* write through for stepping A0-1 and B0-2 */ 651129198Scognet write_through = 1; 652129198Scognet } 653129198Scognet } 654129198Scognet } 655129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 656129198Scognet 657129198Scognet if (write_through) { 658129198Scognet pte_l1_s_cache_mode = L1_S_C; 659129198Scognet pte_l2_l_cache_mode = L2_C; 660129198Scognet pte_l2_s_cache_mode = L2_C; 661129198Scognet } 662129198Scognet 663129198Scognet#if (ARM_NMMUS > 1) 664129198Scognet xscale_use_minidata = 1; 665129198Scognet#endif 666129198Scognet 667129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 668129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 669129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 670129198Scognet 671129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 672129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 673129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 674129198Scognet 675129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 676129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 677129198Scognet 678129198Scognet /* 679129198Scognet * Disable ECC protection of page table access, for now. 680129198Scognet */ 681129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 682129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 683129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 684129198Scognet} 685129198Scognet 686129198Scognet/* 687129198Scognet * xscale_setup_minidata: 688129198Scognet * 689129198Scognet * Set up the mini-data cache clean area. We require the 690129198Scognet * caller to allocate the right amount of physically and 691129198Scognet * virtually contiguous space. 692129198Scognet */ 693129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 694129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 695129198Scognetvoid 696129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 697129198Scognet{ 698129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 699129198Scognet pt_entry_t *pte; 700129198Scognet vm_size_t size; 701129198Scognet uint32_t auxctl; 702129198Scognet 703129198Scognet xscale_minidata_clean_addr = va; 704129198Scognet 705129198Scognet /* Round it to page size. */ 706129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 707129198Scognet 708129198Scognet for (; size != 0; 709129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 710129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 711129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 712129198Scognet if (pte == NULL) 713129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 714129198Scognet "VA 0x%08x", (u_int32_t) va); 715129198Scognet pte[l2pte_index(va)] = 716129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 717129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 718129198Scognet } 719129198Scognet 720129198Scognet /* 721129198Scognet * Configure the mini-data cache for write-back with 722129198Scognet * read/write-allocate. 723129198Scognet * 724129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 725129198Scognet * make sure it contains no valid data! In order to do that, 726129198Scognet * we must issue a global data cache invalidate command! 727129198Scognet * 728129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 729129198Scognet * THIS IS VERY IMPORTANT! 730129198Scognet */ 731129198Scognet 732129198Scognet /* Invalidate data and mini-data. */ 733129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 734129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 735129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 736129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 737129198Scognet} 738129198Scognet#endif 739129198Scognet 740129198Scognet/* 741129198Scognet * Allocate an L1 translation table for the specified pmap. 742129198Scognet * This is called at pmap creation time. 743129198Scognet */ 744129198Scognetstatic void 745129198Scognetpmap_alloc_l1(pmap_t pm) 746129198Scognet{ 747129198Scognet struct l1_ttable *l1; 748129198Scognet u_int8_t domain; 749129198Scognet 750129198Scognet /* 751129198Scognet * Remove the L1 at the head of the LRU list 752129198Scognet */ 753129198Scognet mtx_lock(&l1_lru_lock); 754129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 755129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 756129198Scognet 757129198Scognet /* 758129198Scognet * Pick the first available domain number, and update 759129198Scognet * the link to the next number. 760129198Scognet */ 761129198Scognet domain = l1->l1_domain_first; 762129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 763129198Scognet 764129198Scognet /* 765129198Scognet * If there are still free domain numbers in this L1, 766129198Scognet * put it back on the TAIL of the LRU list. 767129198Scognet */ 768129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 769129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 770129198Scognet 771129198Scognet mtx_unlock(&l1_lru_lock); 772129198Scognet 773129198Scognet /* 774129198Scognet * Fix up the relevant bits in the pmap structure 775129198Scognet */ 776129198Scognet pm->pm_l1 = l1; 777129198Scognet pm->pm_domain = domain; 778129198Scognet} 779129198Scognet 780129198Scognet/* 781129198Scognet * Free an L1 translation table. 782129198Scognet * This is called at pmap destruction time. 783129198Scognet */ 784129198Scognetstatic void 785129198Scognetpmap_free_l1(pmap_t pm) 786129198Scognet{ 787129198Scognet struct l1_ttable *l1 = pm->pm_l1; 788129198Scognet 789129198Scognet mtx_lock(&l1_lru_lock); 790129198Scognet 791129198Scognet /* 792129198Scognet * If this L1 is currently on the LRU list, remove it. 793129198Scognet */ 794129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 795129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 796129198Scognet 797129198Scognet /* 798129198Scognet * Free up the domain number which was allocated to the pmap 799129198Scognet */ 800129198Scognet l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 801129198Scognet l1->l1_domain_first = pm->pm_domain; 802129198Scognet l1->l1_domain_use_count--; 803129198Scognet 804129198Scognet /* 805129198Scognet * The L1 now must have at least 1 free domain, so add 806129198Scognet * it back to the LRU list. If the use count is zero, 807129198Scognet * put it at the head of the list, otherwise it goes 808129198Scognet * to the tail. 809129198Scognet */ 810129198Scognet if (l1->l1_domain_use_count == 0) { 811129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 812129198Scognet } else 813129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 814129198Scognet 815129198Scognet mtx_unlock(&l1_lru_lock); 816129198Scognet} 817129198Scognet 818129198Scognetstatic PMAP_INLINE void 819129198Scognetpmap_use_l1(pmap_t pm) 820129198Scognet{ 821129198Scognet struct l1_ttable *l1; 822129198Scognet 823129198Scognet /* 824129198Scognet * Do nothing if we're in interrupt context. 825129198Scognet * Access to an L1 by the kernel pmap must not affect 826129198Scognet * the LRU list. 827129198Scognet */ 828129198Scognet if (pm == pmap_kernel()) 829129198Scognet return; 830129198Scognet 831129198Scognet l1 = pm->pm_l1; 832129198Scognet 833129198Scognet /* 834129198Scognet * If the L1 is not currently on the LRU list, just return 835129198Scognet */ 836129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) 837129198Scognet return; 838129198Scognet 839129198Scognet mtx_lock(&l1_lru_lock); 840129198Scognet 841129198Scognet /* 842129198Scognet * Check the use count again, now that we've acquired the lock 843129198Scognet */ 844129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) { 845129198Scognet mtx_unlock(&l1_lru_lock); 846129198Scognet return; 847129198Scognet } 848129198Scognet 849129198Scognet /* 850129198Scognet * Move the L1 to the back of the LRU list 851129198Scognet */ 852129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 853129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 854129198Scognet 855129198Scognet mtx_unlock(&l1_lru_lock); 856129198Scognet} 857129198Scognet 858129198Scognet 859129198Scognet/* 860129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 861129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 862129198Scognet */ 863129198Scognetstatic PMAP_INLINE struct l2_bucket * 864129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 865129198Scognet{ 866129198Scognet struct l2_dtable *l2; 867129198Scognet struct l2_bucket *l2b; 868129198Scognet u_short l1idx; 869129198Scognet 870129198Scognet l1idx = L1_IDX(va); 871129198Scognet 872129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 873129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 874129198Scognet return (NULL); 875129198Scognet 876129198Scognet return (l2b); 877129198Scognet} 878129198Scognet 879129198Scognet/* 880129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 881129198Scognet * and VA. 882129198Scognet * 883129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 884129198Scognet * bucket/page table in place. 885129198Scognet * 886129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 887129198Scognet * increment the bucket occupancy counter appropriately *before* 888129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 889129198Scognet * the bucket/page in the meantime. 890129198Scognet */ 891129198Scognetstatic struct l2_bucket * 892129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 893129198Scognet{ 894129198Scognet struct l2_dtable *l2; 895129198Scognet struct l2_bucket *l2b; 896129198Scognet u_short l1idx; 897129198Scognet 898129198Scognet l1idx = L1_IDX(va); 899129198Scognet 900159352Salc PMAP_ASSERT_LOCKED(pm); 901159108Scognet mtx_assert(&vm_page_queue_mtx, MA_OWNED); 902129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 903129198Scognet /* 904129198Scognet * No mapping at this address, as there is 905129198Scognet * no entry in the L1 table. 906129198Scognet * Need to allocate a new l2_dtable. 907129198Scognet */ 908159108Scognetagain_l2table: 909159352Salc PMAP_UNLOCK(pm); 910159108Scognet vm_page_unlock_queues(); 911129198Scognet if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 912159108Scognet vm_page_lock_queues(); 913159352Salc PMAP_LOCK(pm); 914129198Scognet return (NULL); 915129198Scognet } 916159108Scognet vm_page_lock_queues(); 917159352Salc PMAP_LOCK(pm); 918159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 919159352Salc PMAP_UNLOCK(pm); 920159108Scognet vm_page_unlock_queues(); 921159108Scognet uma_zfree(l2table_zone, l2); 922159108Scognet vm_page_lock_queues(); 923159352Salc PMAP_LOCK(pm); 924159108Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 925159108Scognet if (l2 == NULL) 926159108Scognet goto again_l2table; 927159108Scognet /* 928159108Scognet * Someone already allocated the l2_dtable while 929159108Scognet * we were doing the same. 930159108Scognet */ 931159108Scognet } else { 932159108Scognet bzero(l2, sizeof(*l2)); 933159108Scognet /* 934159108Scognet * Link it into the parent pmap 935159108Scognet */ 936159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 937159108Scognet } 938129198Scognet } 939129198Scognet 940129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 941129198Scognet 942129198Scognet /* 943129198Scognet * Fetch pointer to the L2 page table associated with the address. 944129198Scognet */ 945129198Scognet if (l2b->l2b_kva == NULL) { 946129198Scognet pt_entry_t *ptep; 947129198Scognet 948129198Scognet /* 949129198Scognet * No L2 page table has been allocated. Chances are, this 950129198Scognet * is because we just allocated the l2_dtable, above. 951129198Scognet */ 952159108Scognetagain_ptep: 953159352Salc PMAP_UNLOCK(pm); 954159108Scognet vm_page_unlock_queues(); 955160260Scognet ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE); 956159108Scognet vm_page_lock_queues(); 957159352Salc PMAP_LOCK(pm); 958159108Scognet if (l2b->l2b_kva != 0) { 959159108Scognet /* We lost the race. */ 960159352Salc PMAP_UNLOCK(pm); 961159108Scognet vm_page_unlock_queues(); 962159108Scognet uma_zfree(l2zone, ptep); 963159108Scognet vm_page_lock_queues(); 964159352Salc PMAP_LOCK(pm); 965159108Scognet if (l2b->l2b_kva == 0) 966159108Scognet goto again_ptep; 967159108Scognet return (l2b); 968159108Scognet } 969129198Scognet l2b->l2b_phys = vtophys(ptep); 970129198Scognet if (ptep == NULL) { 971129198Scognet /* 972129198Scognet * Oops, no more L2 page tables available at this 973129198Scognet * time. We may need to deallocate the l2_dtable 974129198Scognet * if we allocated a new one above. 975129198Scognet */ 976129198Scognet if (l2->l2_occupancy == 0) { 977129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 978129198Scognet pmap_free_l2_dtable(l2); 979129198Scognet } 980129198Scognet return (NULL); 981129198Scognet } 982129198Scognet 983129198Scognet l2->l2_occupancy++; 984129198Scognet l2b->l2b_kva = ptep; 985129198Scognet l2b->l2b_l1idx = l1idx; 986129198Scognet } 987129198Scognet 988129198Scognet return (l2b); 989129198Scognet} 990129198Scognet 991129198Scognetstatic PMAP_INLINE void 992129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 993129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 994129198Scognet#else 995129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 996129198Scognet#endif 997129198Scognet{ 998129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 999129198Scognet /* 1000129198Scognet * Note: With a write-back cache, we may need to sync this 1001129198Scognet * L2 table before re-using it. 1002129198Scognet * This is because it may have belonged to a non-current 1003129198Scognet * pmap, in which case the cache syncs would have been 1004129198Scognet * skipped when the pages were being unmapped. If the 1005129198Scognet * L2 table were then to be immediately re-allocated to 1006129198Scognet * the *current* pmap, it may well contain stale mappings 1007129198Scognet * which have not yet been cleared by a cache write-back 1008129198Scognet * and so would still be visible to the mmu. 1009129198Scognet */ 1010129198Scognet if (need_sync) 1011129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1012129198Scognet#endif 1013129198Scognet uma_zfree(l2zone, l2); 1014129198Scognet} 1015129198Scognet/* 1016129198Scognet * One or more mappings in the specified L2 descriptor table have just been 1017129198Scognet * invalidated. 1018129198Scognet * 1019129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 1020129198Scognet * 1021129198Scognet * The pmap lock must be acquired when this is called (not necessary 1022129198Scognet * for the kernel pmap). 1023129198Scognet */ 1024129198Scognetstatic void 1025129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1026129198Scognet{ 1027129198Scognet struct l2_dtable *l2; 1028129198Scognet pd_entry_t *pl1pd, l1pd; 1029129198Scognet pt_entry_t *ptep; 1030129198Scognet u_short l1idx; 1031129198Scognet 1032129198Scognet 1033129198Scognet /* 1034129198Scognet * Update the bucket's reference count according to how many 1035129198Scognet * PTEs the caller has just invalidated. 1036129198Scognet */ 1037129198Scognet l2b->l2b_occupancy -= count; 1038129198Scognet 1039129198Scognet /* 1040129198Scognet * Note: 1041129198Scognet * 1042129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 1043129198Scognet * as that would require checking all Level 1 page tables and 1044129198Scognet * removing any references to the Level 2 page table. See also the 1045129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 1046129198Scognet * 1047129198Scognet * We make do with just invalidating the mapping in the L2 table. 1048129198Scognet * 1049129198Scognet * This isn't really a big deal in practice and, in fact, leads 1050129198Scognet * to a performance win over time as we don't need to continually 1051129198Scognet * alloc/free. 1052129198Scognet */ 1053129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1054129198Scognet return; 1055129198Scognet 1056129198Scognet /* 1057129198Scognet * There are no more valid mappings in this level 2 page table. 1058129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 1059129198Scognet * free the page table. 1060129198Scognet */ 1061129198Scognet l1idx = l2b->l2b_l1idx; 1062129198Scognet ptep = l2b->l2b_kva; 1063129198Scognet l2b->l2b_kva = NULL; 1064129198Scognet 1065129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1066129198Scognet 1067129198Scognet /* 1068129198Scognet * If the L1 slot matches the pmap's domain 1069129198Scognet * number, then invalidate it. 1070129198Scognet */ 1071129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1072129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1073129198Scognet *pl1pd = 0; 1074129198Scognet PTE_SYNC(pl1pd); 1075129198Scognet } 1076129198Scognet 1077129198Scognet /* 1078129198Scognet * Release the L2 descriptor table back to the pool cache. 1079129198Scognet */ 1080129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1081129198Scognet pmap_free_l2_ptp(ptep); 1082129198Scognet#else 1083135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1084129198Scognet#endif 1085129198Scognet 1086129198Scognet /* 1087129198Scognet * Update the reference count in the associated l2_dtable 1088129198Scognet */ 1089129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1090129198Scognet if (--l2->l2_occupancy > 0) 1091129198Scognet return; 1092129198Scognet 1093129198Scognet /* 1094129198Scognet * There are no more valid mappings in any of the Level 1 1095129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 1096129198Scognet * the pointer in the parent pmap and free the l2_dtable. 1097129198Scognet */ 1098129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 1099129198Scognet pmap_free_l2_dtable(l2); 1100129198Scognet} 1101129198Scognet 1102129198Scognet/* 1103129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 1104129198Scognet * structures. 1105129198Scognet */ 1106133237Scognetstatic int 1107133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1108129198Scognet{ 1109129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1110129198Scognet struct l2_bucket *l2b; 1111129198Scognet pt_entry_t *ptep, pte; 1112147417Scognet#ifdef ARM_USE_SMALL_ALLOC 1113147417Scognet pd_entry_t *pde; 1114147417Scognet#endif 1115129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1116129198Scognet 1117129198Scognet /* 1118129198Scognet * The mappings for these page tables were initially made using 1119135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1120129198Scognet * mode will not be right for page table mappings. To avoid 1121135641Scognet * polluting the pmap_kenter() code with a special case for 1122129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1123129198Scognet * correct. 1124129198Scognet */ 1125147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1126147417Scognet pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)]; 1127147417Scognet if (!l1pte_section_p(*pde)) { 1128147114Scognet#endif 1129147114Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1130147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1131147114Scognet pte = *ptep; 1132129198Scognet 1133147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1134147114Scognet /* 1135147114Scognet * Page tables must have the cache-mode set to 1136147114Scognet * Write-Thru. 1137147114Scognet */ 1138147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1139147114Scognet PTE_SYNC(ptep); 1140147114Scognet cpu_tlb_flushD_SE(va); 1141147114Scognet cpu_cpwait(); 1142147114Scognet } 1143147114Scognet 1144147114Scognet#ifdef ARM_USE_SMALL_ALLOC 1145129198Scognet } 1146129198Scognet#endif 1147147114Scognet#endif 1148129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1149129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1150133237Scognet return (0); 1151129198Scognet} 1152129198Scognet 1153129198Scognet/* 1154129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1155129198Scognet * on whether the specified pmap actually needs to be flushed at any 1156129198Scognet * given time. 1157129198Scognet */ 1158129198Scognetstatic PMAP_INLINE void 1159129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1160129198Scognet{ 1161129198Scognet 1162135641Scognet if (pmap_is_current(pm)) 1163129198Scognet cpu_tlb_flushID_SE(va); 1164129198Scognet} 1165129198Scognet 1166129198Scognetstatic PMAP_INLINE void 1167129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1168129198Scognet{ 1169129198Scognet 1170135641Scognet if (pmap_is_current(pm)) 1171129198Scognet cpu_tlb_flushD_SE(va); 1172129198Scognet} 1173129198Scognet 1174129198Scognetstatic PMAP_INLINE void 1175129198Scognetpmap_tlb_flushID(pmap_t pm) 1176129198Scognet{ 1177129198Scognet 1178135641Scognet if (pmap_is_current(pm)) 1179129198Scognet cpu_tlb_flushID(); 1180129198Scognet} 1181129198Scognetstatic PMAP_INLINE void 1182129198Scognetpmap_tlb_flushD(pmap_t pm) 1183129198Scognet{ 1184129198Scognet 1185135641Scognet if (pmap_is_current(pm)) 1186129198Scognet cpu_tlb_flushD(); 1187129198Scognet} 1188129198Scognet 1189129198Scognetstatic PMAP_INLINE void 1190129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1191129198Scognet{ 1192129198Scognet 1193135641Scognet if (pmap_is_current(pm)) 1194129198Scognet cpu_idcache_wbinv_range(va, len); 1195129198Scognet} 1196129198Scognet 1197129198Scognetstatic PMAP_INLINE void 1198129198Scognetpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, 1199129198Scognet boolean_t do_inv, boolean_t rd_only) 1200129198Scognet{ 1201129198Scognet 1202135641Scognet if (pmap_is_current(pm)) { 1203129198Scognet if (do_inv) { 1204129198Scognet if (rd_only) 1205129198Scognet cpu_dcache_inv_range(va, len); 1206129198Scognet else 1207129198Scognet cpu_dcache_wbinv_range(va, len); 1208129198Scognet } else 1209129198Scognet if (!rd_only) 1210129198Scognet cpu_dcache_wb_range(va, len); 1211129198Scognet } 1212129198Scognet} 1213129198Scognet 1214129198Scognetstatic PMAP_INLINE void 1215129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1216129198Scognet{ 1217129198Scognet 1218135641Scognet if (pmap_is_current(pm)) 1219129198Scognet cpu_idcache_wbinv_all(); 1220129198Scognet} 1221129198Scognet 1222129198Scognetstatic PMAP_INLINE void 1223129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1224129198Scognet{ 1225129198Scognet 1226135641Scognet if (pmap_is_current(pm)) 1227129198Scognet cpu_dcache_wbinv_all(); 1228129198Scognet} 1229129198Scognet 1230129198Scognet/* 1231129198Scognet * PTE_SYNC_CURRENT: 1232129198Scognet * 1233129198Scognet * Make sure the pte is written out to RAM. 1234129198Scognet * We need to do this for one of two cases: 1235129198Scognet * - We're dealing with the kernel pmap 1236129198Scognet * - There is no pmap active in the cache/tlb. 1237129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1238129198Scognet */ 1239129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1240129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1241129198Scognetdo { \ 1242129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1243135641Scognet pmap_is_current(pm)) \ 1244129198Scognet PTE_SYNC(ptep); \ 1245129198Scognet} while (/*CONSTCOND*/0) 1246129198Scognet#else 1247129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1248129198Scognet#endif 1249129198Scognet 1250129198Scognet/* 1251129198Scognet * Since we have a virtually indexed cache, we may need to inhibit caching if 1252129198Scognet * there is more than one mapping and at least one of them is writable. 1253129198Scognet * Since we purge the cache on every context switch, we only need to check for 1254129198Scognet * other mappings within the same pmap, or kernel_pmap. 1255129198Scognet * This function is also called when a page is unmapped, to possibly reenable 1256129198Scognet * caching on any remaining mappings. 1257129198Scognet * 1258129198Scognet * The code implements the following logic, where: 1259129198Scognet * 1260129198Scognet * KW = # of kernel read/write pages 1261129198Scognet * KR = # of kernel read only pages 1262129198Scognet * UW = # of user read/write pages 1263129198Scognet * UR = # of user read only pages 1264129198Scognet * 1265129198Scognet * KC = kernel mapping is cacheable 1266129198Scognet * UC = user mapping is cacheable 1267129198Scognet * 1268129198Scognet * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1269129198Scognet * +--------------------------------------------- 1270129198Scognet * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1271129198Scognet * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1272129198Scognet * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1273129198Scognet * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1274129198Scognet */ 1275129198Scognet 1276129198Scognetstatic const int pmap_vac_flags[4][4] = { 1277129198Scognet {-1, 0, 0, PVF_KNC}, 1278129198Scognet {0, 0, PVF_NC, PVF_NC}, 1279129198Scognet {0, PVF_NC, PVF_NC, PVF_NC}, 1280129198Scognet {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1281129198Scognet}; 1282129198Scognet 1283129198Scognetstatic PMAP_INLINE int 1284129198Scognetpmap_get_vac_flags(const struct vm_page *pg) 1285129198Scognet{ 1286129198Scognet int kidx, uidx; 1287129198Scognet 1288129198Scognet kidx = 0; 1289129198Scognet if (pg->md.kro_mappings || pg->md.krw_mappings > 1) 1290129198Scognet kidx |= 1; 1291129198Scognet if (pg->md.krw_mappings) 1292129198Scognet kidx |= 2; 1293129198Scognet 1294129198Scognet uidx = 0; 1295129198Scognet if (pg->md.uro_mappings || pg->md.urw_mappings > 1) 1296129198Scognet uidx |= 1; 1297129198Scognet if (pg->md.urw_mappings) 1298129198Scognet uidx |= 2; 1299129198Scognet 1300129198Scognet return (pmap_vac_flags[uidx][kidx]); 1301129198Scognet} 1302129198Scognet 1303129198Scognetstatic __inline void 1304129198Scognetpmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1305129198Scognet{ 1306129198Scognet int nattr; 1307129198Scognet 1308159384Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1309129198Scognet nattr = pmap_get_vac_flags(pg); 1310129198Scognet 1311129198Scognet if (nattr < 0) { 1312129198Scognet pg->md.pvh_attrs &= ~PVF_NC; 1313129198Scognet return; 1314129198Scognet } 1315129198Scognet 1316129198Scognet if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) { 1317129198Scognet return; 1318129198Scognet } 1319129198Scognet 1320129198Scognet if (pm == pmap_kernel()) 1321129198Scognet pmap_vac_me_kpmap(pg, pm, va); 1322129198Scognet else 1323129198Scognet pmap_vac_me_user(pg, pm, va); 1324129198Scognet 1325129198Scognet pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr; 1326129198Scognet} 1327129198Scognet 1328129198Scognetstatic void 1329129198Scognetpmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1330129198Scognet{ 1331129198Scognet u_int u_cacheable, u_entries; 1332129198Scognet struct pv_entry *pv; 1333129198Scognet pmap_t last_pmap = pm; 1334129198Scognet 1335129198Scognet /* 1336129198Scognet * Pass one, see if there are both kernel and user pmaps for 1337129198Scognet * this page. Calculate whether there are user-writable or 1338129198Scognet * kernel-writable pages. 1339129198Scognet */ 1340129198Scognet u_cacheable = 0; 1341129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1342129198Scognet if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1343129198Scognet u_cacheable++; 1344129198Scognet } 1345129198Scognet 1346129198Scognet u_entries = pg->md.urw_mappings + pg->md.uro_mappings; 1347129198Scognet 1348129198Scognet /* 1349129198Scognet * We know we have just been updating a kernel entry, so if 1350129198Scognet * all user pages are already cacheable, then there is nothing 1351129198Scognet * further to do. 1352129198Scognet */ 1353129198Scognet if (pg->md.k_mappings == 0 && u_cacheable == u_entries) 1354129198Scognet return; 1355129198Scognet 1356129198Scognet if (u_entries) { 1357129198Scognet /* 1358129198Scognet * Scan over the list again, for each entry, if it 1359129198Scognet * might not be set correctly, call pmap_vac_me_user 1360129198Scognet * to recalculate the settings. 1361129198Scognet */ 1362129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1363129198Scognet /* 1364129198Scognet * We know kernel mappings will get set 1365129198Scognet * correctly in other calls. We also know 1366129198Scognet * that if the pmap is the same as last_pmap 1367129198Scognet * then we've just handled this entry. 1368129198Scognet */ 1369129198Scognet if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1370129198Scognet continue; 1371129198Scognet 1372129198Scognet /* 1373129198Scognet * If there are kernel entries and this page 1374129198Scognet * is writable but non-cacheable, then we can 1375129198Scognet * skip this entry also. 1376129198Scognet */ 1377129198Scognet if (pg->md.k_mappings && 1378129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1379129198Scognet (PVF_NC | PVF_WRITE)) 1380129198Scognet continue; 1381129198Scognet 1382129198Scognet /* 1383129198Scognet * Similarly if there are no kernel-writable 1384129198Scognet * entries and the page is already 1385129198Scognet * read-only/cacheable. 1386129198Scognet */ 1387129198Scognet if (pg->md.krw_mappings == 0 && 1388129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1389129198Scognet continue; 1390129198Scognet 1391129198Scognet /* 1392129198Scognet * For some of the remaining cases, we know 1393129198Scognet * that we must recalculate, but for others we 1394129198Scognet * can't tell if they are correct or not, so 1395129198Scognet * we recalculate anyway. 1396129198Scognet */ 1397129198Scognet pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1398129198Scognet } 1399129198Scognet 1400129198Scognet if (pg->md.k_mappings == 0) 1401129198Scognet return; 1402129198Scognet } 1403129198Scognet 1404129198Scognet pmap_vac_me_user(pg, pm, va); 1405129198Scognet} 1406129198Scognet 1407129198Scognetstatic void 1408129198Scognetpmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1409129198Scognet{ 1410129198Scognet pmap_t kpmap = pmap_kernel(); 1411129198Scognet struct pv_entry *pv, *npv; 1412129198Scognet struct l2_bucket *l2b; 1413129198Scognet pt_entry_t *ptep, pte; 1414129198Scognet u_int entries = 0; 1415129198Scognet u_int writable = 0; 1416129198Scognet u_int cacheable_entries = 0; 1417129198Scognet u_int kern_cacheable = 0; 1418129198Scognet u_int other_writable = 0; 1419129198Scognet 1420129198Scognet /* 1421129198Scognet * Count mappings and writable mappings in this pmap. 1422129198Scognet * Include kernel mappings as part of our own. 1423129198Scognet * Keep a pointer to the first one. 1424129198Scognet */ 1425129198Scognet npv = TAILQ_FIRST(&pg->md.pv_list); 1426129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1427129198Scognet /* Count mappings in the same pmap */ 1428129198Scognet if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1429129198Scognet if (entries++ == 0) 1430129198Scognet npv = pv; 1431129198Scognet 1432129198Scognet /* Cacheable mappings */ 1433129198Scognet if ((pv->pv_flags & PVF_NC) == 0) { 1434129198Scognet cacheable_entries++; 1435129198Scognet if (kpmap == pv->pv_pmap) 1436129198Scognet kern_cacheable++; 1437129198Scognet } 1438129198Scognet 1439129198Scognet /* Writable mappings */ 1440129198Scognet if (pv->pv_flags & PVF_WRITE) 1441129198Scognet ++writable; 1442129198Scognet } else 1443129198Scognet if (pv->pv_flags & PVF_WRITE) 1444129198Scognet other_writable = 1; 1445129198Scognet } 1446129198Scognet 1447129198Scognet /* 1448129198Scognet * Enable or disable caching as necessary. 1449129198Scognet * Note: the first entry might be part of the kernel pmap, 1450129198Scognet * so we can't assume this is indicative of the state of the 1451129198Scognet * other (maybe non-kpmap) entries. 1452129198Scognet */ 1453129198Scognet if ((entries > 1 && writable) || 1454129198Scognet (entries > 0 && pm == kpmap && other_writable)) { 1455129198Scognet if (cacheable_entries == 0) 1456129198Scognet return; 1457129198Scognet 1458129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1459129198Scognet if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1460129198Scognet (pv->pv_flags & PVF_NC)) 1461129198Scognet continue; 1462129198Scognet 1463129198Scognet pv->pv_flags |= PVF_NC; 1464129198Scognet 1465129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1466129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1467129198Scognet pte = *ptep & ~L2_S_CACHE_MASK; 1468129198Scognet 1469129198Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1470129198Scognet l2pte_valid(pte)) { 1471129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1472129198Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1473129198Scognet pv->pv_va, PAGE_SIZE); 1474129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1475129198Scognet pv->pv_va); 1476129198Scognet } else 1477129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1478129198Scognet pmap_dcache_wb_range(pv->pv_pmap, 1479129198Scognet pv->pv_va, PAGE_SIZE, TRUE, 1480129198Scognet (pv->pv_flags & PVF_WRITE) == 0); 1481129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1482129198Scognet pv->pv_va); 1483129198Scognet } 1484129198Scognet } 1485129198Scognet 1486129198Scognet *ptep = pte; 1487129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1488129198Scognet } 1489129198Scognet cpu_cpwait(); 1490129198Scognet } else 1491129198Scognet if (entries > cacheable_entries) { 1492129198Scognet /* 1493129198Scognet * Turn cacheing back on for some pages. If it is a kernel 1494129198Scognet * page, only do so if there are no other writable pages. 1495129198Scognet */ 1496129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1497129198Scognet if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1498129198Scognet (kpmap != pv->pv_pmap || other_writable))) 1499129198Scognet continue; 1500129198Scognet 1501129198Scognet pv->pv_flags &= ~PVF_NC; 1502129198Scognet 1503129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1504129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1505129198Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1506129198Scognet 1507129198Scognet if (l2pte_valid(pte)) { 1508129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1509129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1510129198Scognet pv->pv_va); 1511129198Scognet } else 1512129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1513129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1514129198Scognet pv->pv_va); 1515129198Scognet } 1516129198Scognet } 1517129198Scognet 1518129198Scognet *ptep = pte; 1519129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1520129198Scognet } 1521129198Scognet } 1522129198Scognet} 1523129198Scognet 1524129198Scognet/* 1525129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1526129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1527129198Scognet * constants and the latter would require an extra inversion at run-time. 1528129198Scognet */ 1529135641Scognetstatic int 1530129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1531129198Scognet{ 1532129198Scognet struct l2_bucket *l2b; 1533129198Scognet struct pv_entry *pv; 1534129198Scognet pt_entry_t *ptep, npte, opte; 1535129198Scognet pmap_t pm; 1536129198Scognet vm_offset_t va; 1537129198Scognet u_int oflags; 1538135641Scognet int count = 0; 1539129198Scognet 1540159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1541159352Salc 1542129198Scognet /* 1543129198Scognet * Clear saved attributes (modify, reference) 1544129198Scognet */ 1545129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1546129198Scognet 1547129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1548135641Scognet return (0); 1549129198Scognet } 1550129198Scognet 1551129198Scognet /* 1552129198Scognet * Loop over all current mappings setting/clearing as appropos 1553129198Scognet */ 1554129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1555129198Scognet va = pv->pv_va; 1556129198Scognet pm = pv->pv_pmap; 1557129198Scognet oflags = pv->pv_flags; 1558129198Scognet pv->pv_flags &= ~maskbits; 1559129198Scognet 1560159352Salc PMAP_LOCK(pm); 1561129198Scognet 1562129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1563129198Scognet 1564129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1565129198Scognet npte = opte = *ptep; 1566129198Scognet 1567157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1568129198Scognet if ((pv->pv_flags & PVF_NC)) { 1569129198Scognet /* 1570129198Scognet * Entry is not cacheable: 1571129198Scognet * 1572129198Scognet * Don't turn caching on again if this is a 1573129198Scognet * modified emulation. This would be 1574129198Scognet * inconsitent with the settings created by 1575129198Scognet * pmap_vac_me_harder(). Otherwise, it's safe 1576129198Scognet * to re-enable cacheing. 1577129198Scognet * 1578129198Scognet * There's no need to call pmap_vac_me_harder() 1579129198Scognet * here: all pages are losing their write 1580129198Scognet * permission. 1581129198Scognet */ 1582129198Scognet if (maskbits & PVF_WRITE) { 1583129198Scognet npte |= pte_l2_s_cache_mode; 1584129198Scognet pv->pv_flags &= ~PVF_NC; 1585129198Scognet } 1586129198Scognet } else 1587129198Scognet if (opte & L2_S_PROT_W) { 1588144760Scognet vm_page_dirty(pg); 1589129198Scognet /* 1590129198Scognet * Entry is writable/cacheable: check if pmap 1591129198Scognet * is current if it is flush it, otherwise it 1592129198Scognet * won't be in the cache 1593129198Scognet */ 1594129198Scognet if (PV_BEEN_EXECD(oflags)) 1595129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1596129198Scognet PAGE_SIZE); 1597129198Scognet else 1598129198Scognet if (PV_BEEN_REFD(oflags)) 1599129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1600129198Scognet PAGE_SIZE, 1601129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1602129198Scognet FALSE); 1603129198Scognet } 1604129198Scognet 1605129198Scognet /* make the pte read only */ 1606129198Scognet npte &= ~L2_S_PROT_W; 1607129198Scognet 1608129198Scognet if (maskbits & PVF_WRITE) { 1609129198Scognet /* 1610129198Scognet * Keep alias accounting up to date 1611129198Scognet */ 1612129198Scognet if (pv->pv_pmap == pmap_kernel()) { 1613129198Scognet if (oflags & PVF_WRITE) { 1614129198Scognet pg->md.krw_mappings--; 1615129198Scognet pg->md.kro_mappings++; 1616129198Scognet } 1617129198Scognet } else 1618129198Scognet if (oflags & PVF_WRITE) { 1619129198Scognet pg->md.urw_mappings--; 1620129198Scognet pg->md.uro_mappings++; 1621129198Scognet } 1622129198Scognet } 1623129198Scognet } 1624129198Scognet 1625157970Scognet if (maskbits & PVF_REF) { 1626129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1627129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1628129198Scognet /* 1629129198Scognet * Check npte here; we may have already 1630129198Scognet * done the wbinv above, and the validity 1631129198Scognet * of the PTE is the same for opte and 1632129198Scognet * npte. 1633129198Scognet */ 1634129198Scognet if (npte & L2_S_PROT_W) { 1635129198Scognet if (PV_BEEN_EXECD(oflags)) 1636129198Scognet pmap_idcache_wbinv_range(pm, 1637129198Scognet pv->pv_va, PAGE_SIZE); 1638129198Scognet else 1639129198Scognet if (PV_BEEN_REFD(oflags)) 1640129198Scognet pmap_dcache_wb_range(pm, 1641129198Scognet pv->pv_va, PAGE_SIZE, 1642129198Scognet TRUE, FALSE); 1643129198Scognet } else 1644129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1645129198Scognet /* XXXJRT need idcache_inv_range */ 1646129198Scognet if (PV_BEEN_EXECD(oflags)) 1647129198Scognet pmap_idcache_wbinv_range(pm, 1648129198Scognet pv->pv_va, PAGE_SIZE); 1649129198Scognet else 1650129198Scognet if (PV_BEEN_REFD(oflags)) 1651129198Scognet pmap_dcache_wb_range(pm, 1652129198Scognet pv->pv_va, PAGE_SIZE, 1653129198Scognet TRUE, TRUE); 1654129198Scognet } 1655129198Scognet } 1656129198Scognet 1657129198Scognet /* 1658129198Scognet * Make the PTE invalid so that we will take a 1659129198Scognet * page fault the next time the mapping is 1660129198Scognet * referenced. 1661129198Scognet */ 1662129198Scognet npte &= ~L2_TYPE_MASK; 1663129198Scognet npte |= L2_TYPE_INV; 1664129198Scognet } 1665129198Scognet 1666129198Scognet if (npte != opte) { 1667135641Scognet count++; 1668129198Scognet *ptep = npte; 1669129198Scognet PTE_SYNC(ptep); 1670129198Scognet /* Flush the TLB entry if a current pmap. */ 1671129198Scognet if (PV_BEEN_EXECD(oflags)) 1672129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1673129198Scognet else 1674129198Scognet if (PV_BEEN_REFD(oflags)) 1675129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1676129198Scognet } 1677129198Scognet 1678159352Salc PMAP_UNLOCK(pm); 1679129198Scognet 1680129198Scognet } 1681129198Scognet 1682137664Scognet if (maskbits & PVF_WRITE) 1683137664Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1684135641Scognet return (count); 1685129198Scognet} 1686129198Scognet 1687129198Scognet/* 1688129198Scognet * main pv_entry manipulation functions: 1689129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1690129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1691129198Scognet * 1692129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1693129198Scognet * pmap_remove_pv expects te caller to lock the pvh before calling 1694129198Scognet */ 1695129198Scognet 1696129198Scognet/* 1697129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page lst 1698129198Scognet * 1699129198Scognet * => caller should hold the proper lock on pmap_main_lock 1700129198Scognet * => caller should have pmap locked 1701129198Scognet * => we will gain the lock on the vm_page and allocate the new pv_entry 1702129198Scognet * => caller should adjust ptp's wire_count before calling 1703129198Scognet * => caller should not adjust pmap's wire_count 1704129198Scognet */ 1705129198Scognetstatic void 1706129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1707129198Scognet vm_offset_t va, u_int flags) 1708129198Scognet{ 1709129198Scognet 1710159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1711159352Salc PMAP_ASSERT_LOCKED(pm); 1712129198Scognet pve->pv_pmap = pm; 1713129198Scognet pve->pv_va = va; 1714129198Scognet pve->pv_flags = flags; 1715129198Scognet 1716129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1717144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1718129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1719129198Scognet if (pm == pmap_kernel()) { 1720129198Scognet if (flags & PVF_WRITE) 1721129198Scognet pg->md.krw_mappings++; 1722129198Scognet else 1723129198Scognet pg->md.kro_mappings++; 1724129198Scognet } 1725129198Scognet if (flags & PVF_WRITE) 1726129198Scognet pg->md.urw_mappings++; 1727129198Scognet else 1728129198Scognet pg->md.uro_mappings++; 1729135641Scognet pg->md.pv_list_count++; 1730129198Scognet if (pve->pv_flags & PVF_WIRED) 1731129198Scognet ++pm->pm_stats.wired_count; 1732144760Scognet vm_page_flag_set(pg, PG_REFERENCED); 1733129198Scognet} 1734129198Scognet 1735129198Scognet/* 1736129198Scognet * 1737129198Scognet * pmap_find_pv: Find a pv entry 1738129198Scognet * 1739129198Scognet * => caller should hold lock on vm_page 1740129198Scognet */ 1741129198Scognetstatic PMAP_INLINE struct pv_entry * 1742129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1743129198Scognet{ 1744129198Scognet struct pv_entry *pv; 1745129198Scognet 1746159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1747129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1748129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1749129198Scognet break; 1750129198Scognet return (pv); 1751129198Scognet} 1752129198Scognet 1753129198Scognet/* 1754129198Scognet * vector_page_setprot: 1755129198Scognet * 1756129198Scognet * Manipulate the protection of the vector page. 1757129198Scognet */ 1758129198Scognetvoid 1759129198Scognetvector_page_setprot(int prot) 1760129198Scognet{ 1761129198Scognet struct l2_bucket *l2b; 1762129198Scognet pt_entry_t *ptep; 1763129198Scognet 1764129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1765129198Scognet 1766129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1767129198Scognet 1768129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1769129198Scognet PTE_SYNC(ptep); 1770129198Scognet cpu_tlb_flushD_SE(vector_page); 1771129198Scognet cpu_cpwait(); 1772129198Scognet} 1773129198Scognet 1774129198Scognet/* 1775129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1776129198Scognet * 1777129198Scognet * => caller should hold proper lock on pmap_main_lock 1778129198Scognet * => pmap should be locked 1779129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1780129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1781129198Scognet * => caller should NOT adjust pmap's wire_count 1782129198Scognet * => we return the removed pve 1783129198Scognet */ 1784135641Scognet 1785135641Scognetstatic void 1786135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1787135641Scognet{ 1788135641Scognet 1789159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1790159352Salc PMAP_ASSERT_LOCKED(pm); 1791135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1792144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1793135641Scognet if (pve->pv_flags & PVF_WIRED) 1794135641Scognet --pm->pm_stats.wired_count; 1795135641Scognet pg->md.pv_list_count--; 1796144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1797144760Scognet vm_page_dirty(pg); 1798135641Scognet if (pm == pmap_kernel()) { 1799135641Scognet if (pve->pv_flags & PVF_WRITE) 1800135641Scognet pg->md.krw_mappings--; 1801135641Scognet else 1802135641Scognet pg->md.kro_mappings--; 1803135641Scognet } else 1804135641Scognet if (pve->pv_flags & PVF_WRITE) 1805135641Scognet pg->md.urw_mappings--; 1806135641Scognet else 1807135641Scognet pg->md.uro_mappings--; 1808144760Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL || 1809144760Scognet (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) { 1810144760Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1811144760Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1812144760Scognet pg->md.pvh_attrs &= ~PVF_REF; 1813137664Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1814146647Scognet } 1815144760Scognet if (TAILQ_FIRST(&pg->md.pv_list)) 1816144760Scognet vm_page_flag_set(pg, PG_REFERENCED); 1817144760Scognet if (pve->pv_flags & PVF_WRITE) 1818144760Scognet pmap_vac_me_harder(pg, pm, 0); 1819135641Scognet} 1820135641Scognet 1821129198Scognetstatic struct pv_entry * 1822129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1823129198Scognet{ 1824135641Scognet struct pv_entry *pve; 1825129198Scognet 1826159474Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1827135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1828129198Scognet 1829129198Scognet while (pve) { 1830129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1831135641Scognet pmap_nuke_pv(pg, pm, pve); 1832129198Scognet break; 1833129198Scognet } 1834129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1835129198Scognet } 1836129198Scognet 1837129198Scognet return(pve); /* return removed pve */ 1838129198Scognet} 1839129198Scognet/* 1840129198Scognet * 1841129198Scognet * pmap_modify_pv: Update pv flags 1842129198Scognet * 1843129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1844129198Scognet * => caller should NOT adjust pmap's wire_count 1845129198Scognet * => caller must call pmap_vac_me_harder() if writable status of a page 1846129198Scognet * may have changed. 1847129198Scognet * => we return the old flags 1848129198Scognet * 1849129198Scognet * Modify a physical-virtual mapping in the pv table 1850129198Scognet */ 1851129198Scognetstatic u_int 1852129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1853129198Scognet u_int clr_mask, u_int set_mask) 1854129198Scognet{ 1855129198Scognet struct pv_entry *npv; 1856129198Scognet u_int flags, oflags; 1857129198Scognet 1858159352Salc PMAP_ASSERT_LOCKED(pm); 1859159352Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1860129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1861129198Scognet return (0); 1862129198Scognet 1863129198Scognet /* 1864129198Scognet * There is at least one VA mapping this page. 1865129198Scognet */ 1866129198Scognet 1867129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1868129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1869129198Scognet 1870129198Scognet oflags = npv->pv_flags; 1871129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1872129198Scognet 1873129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1874129198Scognet if (flags & PVF_WIRED) 1875129198Scognet ++pm->pm_stats.wired_count; 1876129198Scognet else 1877129198Scognet --pm->pm_stats.wired_count; 1878129198Scognet } 1879129198Scognet 1880129198Scognet if ((flags ^ oflags) & PVF_WRITE) { 1881129198Scognet if (pm == pmap_kernel()) { 1882129198Scognet if (flags & PVF_WRITE) { 1883129198Scognet pg->md.krw_mappings++; 1884129198Scognet pg->md.kro_mappings--; 1885129198Scognet } else { 1886129198Scognet pg->md.kro_mappings++; 1887129198Scognet pg->md.krw_mappings--; 1888129198Scognet } 1889129198Scognet } else 1890129198Scognet if (flags & PVF_WRITE) { 1891129198Scognet pg->md.urw_mappings++; 1892129198Scognet pg->md.uro_mappings--; 1893129198Scognet } else { 1894129198Scognet pg->md.uro_mappings++; 1895129198Scognet pg->md.urw_mappings--; 1896129198Scognet } 1897144760Scognet if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) { 1898144760Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1899144760Scognet vm_page_flag_clear(pg, PG_WRITEABLE); 1900144760Scognet } 1901144760Scognet pmap_vac_me_harder(pg, pm, 0); 1902129198Scognet } 1903129198Scognet 1904129198Scognet return (oflags); 1905129198Scognet} 1906129198Scognet 1907129198Scognet/* Function to set the debug level of the pmap code */ 1908129198Scognet#ifdef PMAP_DEBUG 1909129198Scognetvoid 1910129198Scognetpmap_debug(int level) 1911129198Scognet{ 1912129198Scognet pmap_debug_level = level; 1913129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1914129198Scognet} 1915129198Scognet#endif /* PMAP_DEBUG */ 1916129198Scognet 1917129198Scognetvoid 1918129198Scognetpmap_pinit0(struct pmap *pmap) 1919129198Scognet{ 1920129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1921129198Scognet 1922129198Scognet dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1923129198Scognet (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1924135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1925159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1926159325Salc PMAP_LOCK_INIT(pmap); 1927129198Scognet} 1928129198Scognet 1929147217Salc/* 1930147217Salc * Initialize a vm_page's machine-dependent fields. 1931147217Salc */ 1932147217Salcvoid 1933147217Salcpmap_page_init(vm_page_t m) 1934147217Salc{ 1935129198Scognet 1936147217Salc TAILQ_INIT(&m->md.pv_list); 1937147217Salc m->md.pv_list_count = 0; 1938147217Salc} 1939147217Salc 1940129198Scognet/* 1941129198Scognet * Initialize the pmap module. 1942129198Scognet * Called by vm_init, to initialize any structures that the pmap 1943129198Scognet * system needs to map virtual memory. 1944129198Scognet */ 1945129198Scognetvoid 1946129198Scognetpmap_init(void) 1947129198Scognet{ 1948152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1949129198Scognet 1950129198Scognet PDEBUG(1, printf("pmap_init: phys_start = %08x\n")); 1951147114Scognet 1952129198Scognet /* 1953129198Scognet * init the pv free list 1954129198Scognet */ 1955129198Scognet pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1956129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1957129198Scognet /* 1958129198Scognet * Now it is safe to enable pv_table recording. 1959129198Scognet */ 1960129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1961147114Scognet 1962152128Scognet TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1963152128Scognet 1964152128Scognet pv_entry_max = shpgperproc * maxproc + vm_page_array_size; 1965152128Scognet pv_entry_high_water = 9 * (pv_entry_max / 10); 1966152128Scognet l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1967152128Scognet NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1968152128Scognet l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 1969152128Scognet NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1970152128Scognet UMA_ZONE_VM | UMA_ZONE_NOFREE); 1971152128Scognet 1972152128Scognet uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1973152128Scognet 1974129198Scognet} 1975129198Scognet 1976129198Scognetint 1977129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1978129198Scognet{ 1979129198Scognet struct l2_dtable *l2; 1980129198Scognet struct l2_bucket *l2b; 1981129198Scognet pd_entry_t *pl1pd, l1pd; 1982129198Scognet pt_entry_t *ptep, pte; 1983129198Scognet vm_paddr_t pa; 1984129198Scognet u_int l1idx; 1985129198Scognet int rv = 0; 1986129198Scognet 1987129198Scognet l1idx = L1_IDX(va); 1988159384Salc vm_page_lock_queues(); 1989159384Salc PMAP_LOCK(pm); 1990129198Scognet 1991129198Scognet /* 1992129198Scognet * If there is no l2_dtable for this address, then the process 1993129198Scognet * has no business accessing it. 1994129198Scognet * 1995129198Scognet * Note: This will catch userland processes trying to access 1996129198Scognet * kernel addresses. 1997129198Scognet */ 1998129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1999129198Scognet if (l2 == NULL) 2000129198Scognet goto out; 2001129198Scognet 2002129198Scognet /* 2003129198Scognet * Likewise if there is no L2 descriptor table 2004129198Scognet */ 2005129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2006129198Scognet if (l2b->l2b_kva == NULL) 2007129198Scognet goto out; 2008129198Scognet 2009129198Scognet /* 2010129198Scognet * Check the PTE itself. 2011129198Scognet */ 2012129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2013129198Scognet pte = *ptep; 2014129198Scognet if (pte == 0) 2015129198Scognet goto out; 2016129198Scognet 2017129198Scognet /* 2018129198Scognet * Catch a userland access to the vector page mapped at 0x0 2019129198Scognet */ 2020129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 2021129198Scognet goto out; 2022157027Scognet if (va == vector_page) 2023157027Scognet goto out; 2024129198Scognet 2025129198Scognet pa = l2pte_pa(pte); 2026129198Scognet 2027129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2028129198Scognet /* 2029129198Scognet * This looks like a good candidate for "page modified" 2030129198Scognet * emulation... 2031129198Scognet */ 2032129198Scognet struct pv_entry *pv; 2033129198Scognet struct vm_page *pg; 2034129198Scognet 2035129198Scognet /* Extract the physical address of the page */ 2036129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 2037129198Scognet goto out; 2038129198Scognet } 2039129198Scognet /* Get the current flags for this page. */ 2040129198Scognet 2041129198Scognet pv = pmap_find_pv(pg, pm, va); 2042129198Scognet if (pv == NULL) { 2043129198Scognet goto out; 2044129198Scognet } 2045129198Scognet 2046129198Scognet /* 2047129198Scognet * Do the flags say this page is writable? If not then it 2048129198Scognet * is a genuine write fault. If yes then the write fault is 2049129198Scognet * our fault as we did not reflect the write access in the 2050129198Scognet * PTE. Now we know a write has occurred we can correct this 2051129198Scognet * and also set the modified bit 2052129198Scognet */ 2053129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 2054129198Scognet goto out; 2055129198Scognet } 2056129198Scognet 2057157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 2058157970Scognet vm_page_dirty(pg); 2059129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 2060129198Scognet 2061129198Scognet /* 2062129198Scognet * Re-enable write permissions for the page. No need to call 2063129198Scognet * pmap_vac_me_harder(), since this is just a 2064129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 2065129198Scognet * changing. We've already set the cacheable bits based on 2066129198Scognet * the assumption that we can write to this page. 2067129198Scognet */ 2068147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2069129198Scognet PTE_SYNC(ptep); 2070129198Scognet rv = 1; 2071129198Scognet } else 2072129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2073129198Scognet /* 2074129198Scognet * This looks like a good candidate for "page referenced" 2075129198Scognet * emulation. 2076129198Scognet */ 2077129198Scognet struct pv_entry *pv; 2078129198Scognet struct vm_page *pg; 2079129198Scognet 2080129198Scognet /* Extract the physical address of the page */ 2081159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2082129198Scognet goto out; 2083129198Scognet /* Get the current flags for this page. */ 2084129198Scognet 2085129198Scognet pv = pmap_find_pv(pg, pm, va); 2086159384Salc if (pv == NULL) 2087129198Scognet goto out; 2088129198Scognet 2089129198Scognet pg->md.pvh_attrs |= PVF_REF; 2090129198Scognet pv->pv_flags |= PVF_REF; 2091129198Scognet 2092129198Scognet 2093129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2094129198Scognet PTE_SYNC(ptep); 2095129198Scognet rv = 1; 2096129198Scognet } 2097129198Scognet 2098129198Scognet /* 2099129198Scognet * We know there is a valid mapping here, so simply 2100129198Scognet * fix up the L1 if necessary. 2101129198Scognet */ 2102129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2103129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2104129198Scognet if (*pl1pd != l1pd) { 2105129198Scognet *pl1pd = l1pd; 2106129198Scognet PTE_SYNC(pl1pd); 2107129198Scognet rv = 1; 2108129198Scognet } 2109129198Scognet 2110129198Scognet#ifdef CPU_SA110 2111129198Scognet /* 2112129198Scognet * There are bugs in the rev K SA110. This is a check for one 2113129198Scognet * of them. 2114129198Scognet */ 2115129198Scognet if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2116129198Scognet curcpu()->ci_arm_cpurev < 3) { 2117129198Scognet /* Always current pmap */ 2118129198Scognet if (l2pte_valid(pte)) { 2119129198Scognet extern int kernel_debug; 2120129198Scognet if (kernel_debug & 1) { 2121129198Scognet struct proc *p = curlwp->l_proc; 2122129198Scognet printf("prefetch_abort: page is already " 2123129198Scognet "mapped - pte=%p *pte=%08x\n", ptep, pte); 2124129198Scognet printf("prefetch_abort: pc=%08lx proc=%p " 2125129198Scognet "process=%s\n", va, p, p->p_comm); 2126129198Scognet printf("prefetch_abort: far=%08x fs=%x\n", 2127129198Scognet cpu_faultaddress(), cpu_faultstatus()); 2128129198Scognet } 2129129198Scognet#ifdef DDB 2130129198Scognet if (kernel_debug & 2) 2131129198Scognet Debugger(); 2132129198Scognet#endif 2133129198Scognet rv = 1; 2134129198Scognet } 2135129198Scognet } 2136129198Scognet#endif /* CPU_SA110 */ 2137129198Scognet 2138129198Scognet#ifdef DEBUG 2139129198Scognet /* 2140129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 2141129198Scognet * stale TLB entry for the faulting address. This happens when two or 2142129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 2143129198Scognet * a context switch between such processes, we can take domain faults 2144129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 2145129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2146129198Scognet * example. 2147129198Scognet * 2148129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 2149129198Scognet * entry for a recently entered mapping. In this case, the TLB is 2150129198Scognet * flushed for the new mapping, but there may still be TLB entries for 2151129198Scognet * other mappings belonging to other processes in the 1MB range 2152129198Scognet * covered by the L1 entry. 2153129198Scognet * 2154129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 2155129198Scognet * value, so the fault must be due to a stale TLB entry. 2156129198Scognet * 2157129198Scognet * Since we always need to flush the TLB anyway in the case where we 2158129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2159129198Scognet * stale TLB entries dynamically. 2160129198Scognet * 2161129198Scognet * However, the above condition can ONLY happen if the current L1 is 2162129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 2163129198Scognet * that other parts of the pmap are not doing their job WRT managing 2164129198Scognet * the TLB. 2165129198Scognet */ 2166129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2167129198Scognet extern int last_fault_code; 2168129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2169129198Scognet pm, va, ftype); 2170129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2171129198Scognet l2, l2b, ptep, pl1pd); 2172129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2173129198Scognet pte, l1pd, last_fault_code); 2174129198Scognet#ifdef DDB 2175129198Scognet Debugger(); 2176129198Scognet#endif 2177129198Scognet } 2178129198Scognet#endif 2179129198Scognet 2180129198Scognet cpu_tlb_flushID_SE(va); 2181129198Scognet cpu_cpwait(); 2182129198Scognet 2183129198Scognet rv = 1; 2184129198Scognet 2185129198Scognetout: 2186159384Salc vm_page_unlock_queues(); 2187159384Salc PMAP_UNLOCK(pm); 2188129198Scognet return (rv); 2189129198Scognet} 2190129198Scognet 2191129198Scognetvoid 2192152128Scognetpmap_postinit(void) 2193152128Scognet{ 2194129198Scognet struct l2_bucket *l2b; 2195129198Scognet struct l1_ttable *l1; 2196129198Scognet pd_entry_t *pl1pt; 2197129198Scognet pt_entry_t *ptep, pte; 2198129198Scognet vm_offset_t va, eva; 2199129198Scognet u_int loop, needed; 2200129198Scognet 2201129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2202129198Scognet needed -= 1; 2203129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2204129198Scognet 2205129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 2206129198Scognet /* Allocate a L1 page table */ 2207132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2208132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 2209129198Scognet 2210129198Scognet if (va == 0) 2211129198Scognet panic("Cannot allocate L1 KVM"); 2212129198Scognet 2213129198Scognet eva = va + L1_TABLE_SIZE; 2214129198Scognet pl1pt = (pd_entry_t *)va; 2215129198Scognet 2216135641Scognet while (va < eva) { 2217129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2218129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2219129198Scognet pte = *ptep; 2220129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2221129198Scognet *ptep = pte; 2222129198Scognet PTE_SYNC(ptep); 2223129198Scognet cpu_tlb_flushD_SE(va); 2224129198Scognet 2225129198Scognet va += PAGE_SIZE; 2226129198Scognet } 2227129198Scognet pmap_init_l1(l1, pl1pt); 2228129198Scognet } 2229129198Scognet 2230129198Scognet 2231129198Scognet#ifdef DEBUG 2232129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2233129198Scognet needed); 2234129198Scognet#endif 2235129198Scognet} 2236129198Scognet 2237129198Scognet/* 2238129198Scognet * This is used to stuff certain critical values into the PCB where they 2239129198Scognet * can be accessed quickly from cpu_switch() et al. 2240129198Scognet */ 2241129198Scognetvoid 2242129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2243129198Scognet{ 2244129198Scognet struct l2_bucket *l2b; 2245129198Scognet 2246129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2247129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2248129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2249129198Scognet 2250129198Scognet if (vector_page < KERNBASE) { 2251129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2252129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2253129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2254145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2255129198Scognet } else 2256129198Scognet pcb->pcb_pl1vec = NULL; 2257129198Scognet} 2258129198Scognet 2259129198Scognetvoid 2260129198Scognetpmap_activate(struct thread *td) 2261129198Scognet{ 2262129198Scognet pmap_t pm; 2263129198Scognet struct pcb *pcb; 2264129198Scognet 2265135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2266129198Scognet pcb = td->td_pcb; 2267129198Scognet 2268129198Scognet critical_enter(); 2269129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2270129198Scognet 2271129198Scognet if (td == curthread) { 2272129198Scognet u_int cur_dacr, cur_ttb; 2273129198Scognet 2274129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2275129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2276129198Scognet 2277129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2278129198Scognet 2279129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2280129198Scognet cur_dacr == pcb->pcb_dacr) { 2281129198Scognet /* 2282129198Scognet * No need to switch address spaces. 2283129198Scognet */ 2284129198Scognet critical_exit(); 2285129198Scognet return; 2286129198Scognet } 2287129198Scognet 2288129198Scognet 2289129198Scognet /* 2290129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2291129198Scognet * to 'vector_page' in the incoming L1 table before switching 2292129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2293129198Scognet * domain faults!) will jump into hyperspace. 2294129198Scognet */ 2295129198Scognet if (pcb->pcb_pl1vec) { 2296129198Scognet 2297129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2298129198Scognet /* 2299129198Scognet * Don't need to PTE_SYNC() at this point since 2300129198Scognet * cpu_setttb() is about to flush both the cache 2301129198Scognet * and the TLB. 2302129198Scognet */ 2303129198Scognet } 2304129198Scognet 2305129198Scognet cpu_domains(pcb->pcb_dacr); 2306129198Scognet cpu_setttb(pcb->pcb_pagedir); 2307129198Scognet } 2308129198Scognet critical_exit(); 2309129198Scognet} 2310129198Scognet 2311129198Scognetstatic int 2312129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2313129198Scognet{ 2314129198Scognet pd_entry_t *pdep, pde; 2315129198Scognet pt_entry_t *ptep, pte; 2316129198Scognet vm_offset_t pa; 2317129198Scognet int rv = 0; 2318129198Scognet 2319129198Scognet /* 2320129198Scognet * Make sure the descriptor itself has the correct cache mode 2321129198Scognet */ 2322129198Scognet pdep = &kl1[L1_IDX(va)]; 2323129198Scognet pde = *pdep; 2324129198Scognet 2325129198Scognet if (l1pte_section_p(pde)) { 2326129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2327129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2328129198Scognet pte_l1_s_cache_mode_pt; 2329129198Scognet PTE_SYNC(pdep); 2330129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2331129198Scognet sizeof(*pdep)); 2332129198Scognet rv = 1; 2333129198Scognet } 2334129198Scognet } else { 2335129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2336129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2337129198Scognet if (ptep == NULL) 2338129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2339129198Scognet 2340129198Scognet ptep = &ptep[l2pte_index(va)]; 2341129198Scognet pte = *ptep; 2342129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2343129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2344129198Scognet pte_l2_s_cache_mode_pt; 2345129198Scognet PTE_SYNC(ptep); 2346129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2347129198Scognet sizeof(*ptep)); 2348129198Scognet rv = 1; 2349129198Scognet } 2350129198Scognet } 2351129198Scognet 2352129198Scognet return (rv); 2353129198Scognet} 2354129198Scognet 2355129198Scognetstatic void 2356129198Scognetpmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2357129198Scognet pt_entry_t **ptep) 2358129198Scognet{ 2359129198Scognet vm_offset_t va = *availp; 2360129198Scognet struct l2_bucket *l2b; 2361129198Scognet 2362129198Scognet if (ptep) { 2363129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2364129198Scognet if (l2b == NULL) 2365129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2366129198Scognet 2367129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2368129198Scognet } 2369129198Scognet 2370129198Scognet *vap = va; 2371129198Scognet *availp = va + (PAGE_SIZE * pages); 2372129198Scognet} 2373129198Scognet 2374129198Scognet/* 2375129198Scognet * Bootstrap the system enough to run with virtual memory. 2376129198Scognet * 2377129198Scognet * On the arm this is called after mapping has already been enabled 2378129198Scognet * and just syncs the pmap module with what has already been done. 2379129198Scognet * [We can't call it easily with mapping off since the kernel is not 2380129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2381129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2382129198Scognet * (physical) address starting relative to 0] 2383129198Scognet */ 2384129198Scognet#define PMAP_STATIC_L2_SIZE 16 2385147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2386147114Scognetextern struct mtx smallalloc_mtx; 2387147114Scognetextern vm_offset_t alloc_curaddr; 2388147542Scognetextern vm_offset_t alloc_firstaddr; 2389147114Scognet#endif 2390147114Scognet 2391129198Scognetvoid 2392129198Scognetpmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2393129198Scognet{ 2394129198Scognet static struct l1_ttable static_l1; 2395129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2396129198Scognet struct l1_ttable *l1 = &static_l1; 2397129198Scognet struct l2_dtable *l2; 2398129198Scognet struct l2_bucket *l2b; 2399129198Scognet pd_entry_t pde; 2400129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2401129198Scognet pt_entry_t *ptep; 2402129198Scognet vm_paddr_t pa; 2403129198Scognet vm_offset_t va; 2404135641Scognet vm_size_t size; 2405129198Scognet int l1idx, l2idx, l2next = 0; 2406129198Scognet 2407129198Scognet PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n", 2408129198Scognet firstaddr, loadaddr)); 2409129198Scognet 2410129198Scognet virtual_avail = firstaddr; 2411129198Scognet kernel_pmap = &kernel_pmap_store; 2412129198Scognet kernel_pmap->pm_l1 = l1; 2413150865Scognet kernel_l1pa = l1pt->pv_pa; 2414143192Scognet 2415143192Scognet /* 2416129198Scognet * Scan the L1 translation table created by initarm() and create 2417129198Scognet * the required metadata for all valid mappings found in it. 2418129198Scognet */ 2419129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2420129198Scognet pde = kernel_l1pt[l1idx]; 2421129198Scognet 2422129198Scognet /* 2423129198Scognet * We're only interested in Coarse mappings. 2424129198Scognet * pmap_extract() can deal with section mappings without 2425129198Scognet * recourse to checking L2 metadata. 2426129198Scognet */ 2427129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2428129198Scognet continue; 2429129198Scognet 2430129198Scognet /* 2431129198Scognet * Lookup the KVA of this L2 descriptor table 2432129198Scognet */ 2433129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2434129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2435129198Scognet 2436129198Scognet if (ptep == NULL) { 2437129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2438129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2439129198Scognet } 2440129198Scognet 2441129198Scognet /* 2442129198Scognet * Fetch the associated L2 metadata structure. 2443129198Scognet * Allocate a new one if necessary. 2444129198Scognet */ 2445129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2446129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2447129198Scognet panic("pmap_bootstrap: out of static L2s"); 2448129198Scognet kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2449129198Scognet &static_l2[l2next++]; 2450129198Scognet } 2451129198Scognet 2452129198Scognet /* 2453129198Scognet * One more L1 slot tracked... 2454129198Scognet */ 2455129198Scognet l2->l2_occupancy++; 2456129198Scognet 2457129198Scognet /* 2458129198Scognet * Fill in the details of the L2 descriptor in the 2459129198Scognet * appropriate bucket. 2460129198Scognet */ 2461129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2462129198Scognet l2b->l2b_kva = ptep; 2463129198Scognet l2b->l2b_phys = pa; 2464129198Scognet l2b->l2b_l1idx = l1idx; 2465129198Scognet 2466129198Scognet /* 2467129198Scognet * Establish an initial occupancy count for this descriptor 2468129198Scognet */ 2469129198Scognet for (l2idx = 0; 2470129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2471129198Scognet l2idx++) { 2472129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2473129198Scognet l2b->l2b_occupancy++; 2474129198Scognet } 2475129198Scognet } 2476129198Scognet 2477129198Scognet /* 2478129198Scognet * Make sure the descriptor itself has the correct cache mode. 2479129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2480129198Scognet * should consider this a clue to fix up their initarm() 2481129198Scognet * function. :) 2482129198Scognet */ 2483129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2484129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2485129198Scognet "L2 pte @ %p\n", ptep); 2486129198Scognet } 2487129198Scognet } 2488129198Scognet 2489129198Scognet 2490129198Scognet /* 2491129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2492129198Scognet * a page table. Bitch if it is not correctly set. 2493129198Scognet */ 2494129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2495129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2496129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2497129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2498129198Scognet "primary L1 @ 0x%x\n", va); 2499129198Scognet } 2500129198Scognet 2501129198Scognet cpu_dcache_wbinv_all(); 2502129198Scognet cpu_tlb_flushID(); 2503129198Scognet cpu_cpwait(); 2504129198Scognet 2505159325Salc PMAP_LOCK_INIT(kernel_pmap); 2506129198Scognet kernel_pmap->pm_active = -1; 2507129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2508144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2509129198Scognet 2510129198Scognet /* 2511129198Scognet * Reserve some special page table entries/VA space for temporary 2512129198Scognet * mapping of pages. 2513129198Scognet */ 2514129198Scognet#define SYSMAP(c, p, v, n) \ 2515129198Scognet v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2516129198Scognet 2517129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2518129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2519129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2520129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2521135641Scognet size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2522135641Scognet pmap_alloc_specials(&virtual_avail, 2523135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2524135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2525135641Scognet 2526135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2527135641Scognet pmap_alloc_specials(&virtual_avail, 2528135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2529135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2530135641Scognet 2531137362Scognet pmap_alloc_specials(&virtual_avail, 2532137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2533135641Scognet SLIST_INIT(&l1_list); 2534129198Scognet TAILQ_INIT(&l1_lru_list); 2535129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2536129198Scognet pmap_init_l1(l1, kernel_l1pt); 2537129198Scognet cpu_dcache_wbinv_all(); 2538129198Scognet 2539129198Scognet virtual_avail = round_page(virtual_avail); 2540129198Scognet virtual_end = lastaddr; 2541135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2542156191Scognet arm_nocache_startaddr = lastaddr; 2543159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2544156191Scognet 2545147114Scognet#ifdef ARM_USE_SMALL_ALLOC 2546147114Scognet mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF); 2547156191Scognet alloc_firstaddr = alloc_curaddr = arm_nocache_startaddr + 2548156191Scognet ARM_NOCACHE_KVA_SIZE; 2549147114Scognet#endif 2550129198Scognet} 2551129198Scognet 2552129198Scognet/*************************************************** 2553129198Scognet * Pmap allocation/deallocation routines. 2554129198Scognet ***************************************************/ 2555129198Scognet 2556129198Scognet/* 2557129198Scognet * Release any resources held by the given physical map. 2558129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2559129198Scognet * Should only be called if the map contains no valid mappings. 2560129198Scognet */ 2561129198Scognetvoid 2562129198Scognetpmap_release(pmap_t pmap) 2563129198Scognet{ 2564135641Scognet struct pcb *pcb; 2565135641Scognet 2566135641Scognet pmap_idcache_wbinv_all(pmap); 2567135641Scognet pmap_tlb_flushID(pmap); 2568135641Scognet cpu_cpwait(); 2569135641Scognet if (vector_page < KERNBASE) { 2570135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2571135641Scognet pcb = thread0.td_pcb; 2572135641Scognet if (pmap_is_current(pmap)) { 2573135641Scognet /* 2574135641Scognet * Frob the L1 entry corresponding to the vector 2575135641Scognet * page so that it contains the kernel pmap's domain 2576135641Scognet * number. This will ensure pmap_remove() does not 2577135641Scognet * pull the current vector page out from under us. 2578135641Scognet */ 2579135641Scognet critical_enter(); 2580135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2581135641Scognet cpu_domains(pcb->pcb_dacr); 2582135641Scognet cpu_setttb(pcb->pcb_pagedir); 2583135641Scognet critical_exit(); 2584135641Scognet } 2585135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2586135641Scognet /* 2587135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2588135641Scognet * since this process has no remaining mappings of its own. 2589135641Scognet */ 2590135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2591135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2592135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2593135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2594135641Scognet 2595135641Scognet } 2596129198Scognet pmap_free_l1(pmap); 2597159325Salc PMAP_LOCK_DESTROY(pmap); 2598135641Scognet 2599129198Scognet dprintf("pmap_release()\n"); 2600129198Scognet} 2601129198Scognet 2602129198Scognet 2603135641Scognet 2604129198Scognet/* 2605135641Scognet * Helper function for pmap_grow_l2_bucket() 2606135641Scognet */ 2607135641Scognetstatic __inline int 2608135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2609135641Scognet{ 2610135641Scognet struct l2_bucket *l2b; 2611135641Scognet pt_entry_t *ptep; 2612135641Scognet vm_paddr_t pa; 2613135641Scognet struct vm_page *pg; 2614135641Scognet 2615150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2616135641Scognet if (pg == NULL) 2617135641Scognet return (1); 2618135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2619135641Scognet 2620135641Scognet if (pap) 2621135641Scognet *pap = pa; 2622135641Scognet 2623135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2624135641Scognet 2625135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2626135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2627135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2628135641Scognet PTE_SYNC(ptep); 2629135641Scognet return (0); 2630135641Scognet} 2631135641Scognet 2632135641Scognet/* 2633135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2634135641Scognet * used by pmap_growkernel(). 2635135641Scognet */ 2636135641Scognetstatic __inline struct l2_bucket * 2637135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2638135641Scognet{ 2639135641Scognet struct l2_dtable *l2; 2640135641Scognet struct l2_bucket *l2b; 2641135641Scognet struct l1_ttable *l1; 2642135641Scognet pd_entry_t *pl1pd; 2643135641Scognet u_short l1idx; 2644135641Scognet vm_offset_t nva; 2645135641Scognet 2646135641Scognet l1idx = L1_IDX(va); 2647135641Scognet 2648135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2649135641Scognet /* 2650135641Scognet * No mapping at this address, as there is 2651135641Scognet * no entry in the L1 table. 2652135641Scognet * Need to allocate a new l2_dtable. 2653135641Scognet */ 2654135641Scognet nva = pmap_kernel_l2dtable_kva; 2655135641Scognet if ((nva & PAGE_MASK) == 0) { 2656135641Scognet /* 2657135641Scognet * Need to allocate a backing page 2658135641Scognet */ 2659135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2660135641Scognet return (NULL); 2661135641Scognet } 2662135641Scognet 2663135641Scognet l2 = (struct l2_dtable *)nva; 2664135641Scognet nva += sizeof(struct l2_dtable); 2665135641Scognet 2666135641Scognet if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2667135641Scognet PAGE_MASK)) { 2668135641Scognet /* 2669135641Scognet * The new l2_dtable straddles a page boundary. 2670135641Scognet * Map in another page to cover it. 2671135641Scognet */ 2672135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2673135641Scognet return (NULL); 2674135641Scognet } 2675135641Scognet 2676135641Scognet pmap_kernel_l2dtable_kva = nva; 2677135641Scognet 2678135641Scognet /* 2679135641Scognet * Link it into the parent pmap 2680135641Scognet */ 2681135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2682150865Scognet memset(l2, 0, sizeof(*l2)); 2683135641Scognet } 2684135641Scognet 2685135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2686135641Scognet 2687135641Scognet /* 2688135641Scognet * Fetch pointer to the L2 page table associated with the address. 2689135641Scognet */ 2690135641Scognet if (l2b->l2b_kva == NULL) { 2691135641Scognet pt_entry_t *ptep; 2692135641Scognet 2693135641Scognet /* 2694135641Scognet * No L2 page table has been allocated. Chances are, this 2695135641Scognet * is because we just allocated the l2_dtable, above. 2696135641Scognet */ 2697135641Scognet nva = pmap_kernel_l2ptp_kva; 2698135641Scognet ptep = (pt_entry_t *)nva; 2699135641Scognet if ((nva & PAGE_MASK) == 0) { 2700135641Scognet /* 2701135641Scognet * Need to allocate a backing page 2702135641Scognet */ 2703135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2704135641Scognet &pmap_kernel_l2ptp_phys)) 2705135641Scognet return (NULL); 2706135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2707135641Scognet } 2708150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2709135641Scognet l2->l2_occupancy++; 2710135641Scognet l2b->l2b_kva = ptep; 2711135641Scognet l2b->l2b_l1idx = l1idx; 2712135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2713135641Scognet 2714135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2715135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2716135641Scognet } 2717135641Scognet 2718135641Scognet /* Distribute new L1 entry to all other L1s */ 2719135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2720145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2721135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2722135641Scognet L1_C_PROTO; 2723135641Scognet PTE_SYNC(pl1pd); 2724135641Scognet } 2725135641Scognet 2726135641Scognet return (l2b); 2727135641Scognet} 2728135641Scognet 2729135641Scognet 2730135641Scognet/* 2731129198Scognet * grow the number of kernel page table entries, if needed 2732129198Scognet */ 2733129198Scognetvoid 2734129198Scognetpmap_growkernel(vm_offset_t addr) 2735129198Scognet{ 2736135641Scognet pmap_t kpm = pmap_kernel(); 2737129198Scognet 2738135641Scognet if (addr <= pmap_curmaxkvaddr) 2739135641Scognet return; /* we are OK */ 2740135641Scognet 2741135641Scognet /* 2742135641Scognet * whoops! we need to add kernel PTPs 2743135641Scognet */ 2744135641Scognet 2745135641Scognet /* Map 1MB at a time */ 2746135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2747135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2748135641Scognet 2749135641Scognet /* 2750135641Scognet * flush out the cache, expensive but growkernel will happen so 2751135641Scognet * rarely 2752135641Scognet */ 2753135641Scognet cpu_dcache_wbinv_all(); 2754135641Scognet cpu_tlb_flushD(); 2755135641Scognet cpu_cpwait(); 2756135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2757135641Scognet 2758129198Scognet} 2759129198Scognet 2760129198Scognet 2761129198Scognet/* 2762129198Scognet * pmap_page_protect: 2763129198Scognet * 2764129198Scognet * Lower the permission for all mappings to a given page. 2765129198Scognet */ 2766129198Scognetvoid 2767129198Scognetpmap_page_protect(vm_page_t m, vm_prot_t prot) 2768129198Scognet{ 2769135641Scognet switch(prot) { 2770135641Scognet case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2771135641Scognet case VM_PROT_READ|VM_PROT_WRITE: 2772135641Scognet return; 2773135641Scognet 2774135641Scognet case VM_PROT_READ: 2775135641Scognet case VM_PROT_READ|VM_PROT_EXECUTE: 2776135641Scognet pmap_clearbit(m, PVF_WRITE); 2777135641Scognet break; 2778135641Scognet 2779135641Scognet default: 2780135641Scognet pmap_remove_all(m); 2781135641Scognet break; 2782129198Scognet } 2783135641Scognet 2784129198Scognet} 2785129198Scognet 2786129198Scognet 2787129198Scognet/* 2788129198Scognet * Remove all pages from specified address space 2789129198Scognet * this aids process exit speeds. Also, this code 2790129198Scognet * is special cased for current process only, but 2791129198Scognet * can have the more generic (and slightly slower) 2792129198Scognet * mode enabled. This is much faster than pmap_remove 2793129198Scognet * in the case of running down an entire address space. 2794129198Scognet */ 2795129198Scognetvoid 2796157443Speterpmap_remove_pages(pmap_t pmap) 2797129198Scognet{ 2798144760Scognet struct pv_entry *pv, *npv; 2799144760Scognet struct l2_bucket *l2b = NULL; 2800144760Scognet vm_page_t m; 2801144760Scognet pt_entry_t *pt; 2802144760Scognet 2803144760Scognet vm_page_lock_queues(); 2804159352Salc PMAP_LOCK(pmap); 2805144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2806144760Scognet if (pv->pv_flags & PVF_WIRED) { 2807144760Scognet /* The page is wired, cannot remove it now. */ 2808144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2809144760Scognet continue; 2810144760Scognet } 2811144760Scognet pmap->pm_stats.resident_count--; 2812144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2813144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2814144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2815144760Scognet m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2816144760Scognet *pt = 0; 2817144760Scognet PTE_SYNC(pt); 2818144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2819144760Scognet pmap_nuke_pv(m, pmap, pv); 2820150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2821150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 2822144760Scognet pmap_free_pv_entry(pv); 2823144760Scognet } 2824144760Scognet vm_page_unlock_queues(); 2825135641Scognet cpu_idcache_wbinv_all(); 2826135641Scognet cpu_tlb_flushID(); 2827135641Scognet cpu_cpwait(); 2828159352Salc PMAP_UNLOCK(pmap); 2829129198Scognet} 2830129198Scognet 2831129198Scognet 2832129198Scognet/*************************************************** 2833129198Scognet * Low level mapping routines..... 2834129198Scognet ***************************************************/ 2835129198Scognet 2836147114Scognet/* Map a section into the KVA. */ 2837147114Scognet 2838147114Scognetvoid 2839147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2840147114Scognet{ 2841147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2842147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2843147114Scognet struct l1_ttable *l1; 2844147114Scognet 2845147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2846147114Scognet ("Not a valid section mapping")); 2847147114Scognet if (flags & SECTION_CACHE) 2848147114Scognet pd |= pte_l1_s_cache_mode; 2849147114Scognet else if (flags & SECTION_PT) 2850147114Scognet pd |= pte_l1_s_cache_mode_pt; 2851147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2852147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2853147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2854147114Scognet } 2855147114Scognet} 2856147114Scognet 2857129198Scognet/* 2858129198Scognet * add a wired page to the kva 2859129198Scognet * note that in order for the mapping to take effect -- you 2860129198Scognet * should do a invltlb after doing the pmap_kenter... 2861129198Scognet */ 2862135641Scognetstatic PMAP_INLINE void 2863135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2864129198Scognet{ 2865129198Scognet struct l2_bucket *l2b; 2866129198Scognet pt_entry_t *pte; 2867129198Scognet pt_entry_t opte; 2868129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2869129198Scognet (uint32_t) va, (uint32_t) pa)); 2870129198Scognet 2871129198Scognet 2872129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2873135641Scognet if (l2b == NULL) 2874135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2875129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2876129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2877129198Scognet opte = *pte; 2878129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2879129198Scognet (uint32_t) pte, opte, *pte)); 2880129198Scognet if (l2pte_valid(opte)) { 2881129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2882129198Scognet cpu_tlb_flushD_SE(va); 2883129198Scognet cpu_cpwait(); 2884135641Scognet } else { 2885129198Scognet if (opte == 0) 2886129198Scognet l2b->l2b_occupancy++; 2887135641Scognet } 2888129198Scognet *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2889135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2890135641Scognet if (flags & KENTER_CACHE) 2891135641Scognet *pte |= pte_l2_s_cache_mode; 2892142570Scognet if (flags & KENTER_USER) 2893142570Scognet *pte |= L2_S_PROT_U; 2894129198Scognet PTE_SYNC(pte); 2895135641Scognet} 2896129198Scognet 2897135641Scognetvoid 2898135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2899135641Scognet{ 2900135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2901129198Scognet} 2902129198Scognet 2903142570Scognetvoid 2904156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2905156191Scognet{ 2906156191Scognet 2907156191Scognet pmap_kenter_internal(va, pa, 0); 2908156191Scognet} 2909156191Scognet 2910156191Scognetvoid 2911142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2912142570Scognet{ 2913143192Scognet 2914142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2915143192Scognet /* 2916143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2917143192Scognet * at the first use of the new address, or bad things will happen, 2918143192Scognet * as we use one of these addresses in the exception handlers. 2919143192Scognet */ 2920143192Scognet pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2921142570Scognet} 2922129198Scognet 2923129198Scognet/* 2924135641Scognet * remove a page rom the kernel pagetables 2925129198Scognet */ 2926129198ScognetPMAP_INLINE void 2927129198Scognetpmap_kremove(vm_offset_t va) 2928129198Scognet{ 2929135641Scognet struct l2_bucket *l2b; 2930135641Scognet pt_entry_t *pte, opte; 2931135641Scognet 2932135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2933145071Scognet if (!l2b) 2934145071Scognet return; 2935135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2936135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2937135641Scognet opte = *pte; 2938135641Scognet if (l2pte_valid(opte)) { 2939135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2940135641Scognet cpu_tlb_flushD_SE(va); 2941135641Scognet cpu_cpwait(); 2942144760Scognet *pte = 0; 2943135641Scognet } 2944129198Scognet} 2945129198Scognet 2946129198Scognet 2947129198Scognet/* 2948129198Scognet * Used to map a range of physical addresses into kernel 2949129198Scognet * virtual address space. 2950129198Scognet * 2951129198Scognet * The value passed in '*virt' is a suggested virtual address for 2952129198Scognet * the mapping. Architectures which can support a direct-mapped 2953129198Scognet * physical to virtual region can return the appropriate address 2954129198Scognet * within that region, leaving '*virt' unchanged. Other 2955129198Scognet * architectures should map the pages starting at '*virt' and 2956129198Scognet * update '*virt' with the first usable address after the mapped 2957129198Scognet * region. 2958129198Scognet */ 2959129198Scognetvm_offset_t 2960129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2961129198Scognet{ 2962129198Scognet vm_offset_t sva = *virt; 2963129198Scognet vm_offset_t va = sva; 2964129198Scognet 2965129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2966129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2967129198Scognet prot)); 2968129198Scognet 2969129198Scognet while (start < end) { 2970129198Scognet pmap_kenter(va, start); 2971129198Scognet va += PAGE_SIZE; 2972129198Scognet start += PAGE_SIZE; 2973129198Scognet } 2974129198Scognet *virt = va; 2975129198Scognet return (sva); 2976129198Scognet} 2977129198Scognet 2978143724Scognetstatic void 2979150865Scognetpmap_wb_page(vm_page_t m) 2980143724Scognet{ 2981143724Scognet struct pv_entry *pv; 2982129198Scognet 2983143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2984150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2985144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2986143724Scognet} 2987143724Scognet 2988150865Scognetstatic void 2989150865Scognetpmap_inv_page(vm_page_t m) 2990150865Scognet{ 2991150865Scognet struct pv_entry *pv; 2992150865Scognet 2993150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2994150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2995150865Scognet} 2996129198Scognet/* 2997129198Scognet * Add a list of wired pages to the kva 2998129198Scognet * this routine is only used for temporary 2999129198Scognet * kernel mappings that do not need to have 3000129198Scognet * page modification or references recorded. 3001129198Scognet * Note that old mappings are simply written 3002129198Scognet * over. The page *must* be wired. 3003129198Scognet */ 3004129198Scognetvoid 3005129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 3006129198Scognet{ 3007129198Scognet int i; 3008129198Scognet 3009129198Scognet for (i = 0; i < count; i++) { 3010150865Scognet pmap_wb_page(m[i]); 3011135641Scognet pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 3012135641Scognet KENTER_CACHE); 3013129198Scognet va += PAGE_SIZE; 3014129198Scognet } 3015129198Scognet} 3016129198Scognet 3017129198Scognet 3018129198Scognet/* 3019129198Scognet * this routine jerks page mappings from the 3020129198Scognet * kernel -- it is meant only for temporary mappings. 3021129198Scognet */ 3022129198Scognetvoid 3023129198Scognetpmap_qremove(vm_offset_t va, int count) 3024129198Scognet{ 3025146596Scognet vm_paddr_t pa; 3026129198Scognet int i; 3027129198Scognet 3028129198Scognet for (i = 0; i < count; i++) { 3029146596Scognet pa = vtophys(va); 3030146596Scognet if (pa) { 3031150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 3032146596Scognet pmap_kremove(va); 3033146596Scognet } 3034129198Scognet va += PAGE_SIZE; 3035129198Scognet } 3036129198Scognet} 3037129198Scognet 3038129198Scognet 3039129198Scognet/* 3040129198Scognet * pmap_object_init_pt preloads the ptes for a given object 3041129198Scognet * into the specified pmap. This eliminates the blast of soft 3042129198Scognet * faults on process startup and immediately after an mmap. 3043129198Scognet */ 3044129198Scognetvoid 3045129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3046129198Scognet vm_pindex_t pindex, vm_size_t size) 3047129198Scognet{ 3048157156Scognet 3049157156Scognet VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3050157156Scognet KASSERT(object->type == OBJT_DEVICE, 3051157156Scognet ("pmap_object_init_pt: non-device object")); 3052129198Scognet} 3053129198Scognet 3054129198Scognet 3055129198Scognet/* 3056129198Scognet * pmap_is_prefaultable: 3057129198Scognet * 3058129198Scognet * Return whether or not the specified virtual address is elgible 3059129198Scognet * for prefault. 3060129198Scognet */ 3061129198Scognetboolean_t 3062129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3063129198Scognet{ 3064135641Scognet pd_entry_t *pde; 3065129198Scognet pt_entry_t *pte; 3066129198Scognet 3067135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3068135641Scognet return (FALSE); 3069159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 3070135641Scognet if (*pte == 0) 3071135641Scognet return (TRUE); 3072135641Scognet return (FALSE); 3073129198Scognet} 3074129198Scognet 3075129198Scognet/* 3076129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3077129198Scognet * Returns TRUE if the mapping exists, else FALSE. 3078129198Scognet * 3079129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 3080129198Scognet * It is not safe to take any pmap locks here, since we could be right 3081129198Scognet * in the middle of debugging the pmap anyway... 3082129198Scognet * 3083129198Scognet * It is possible for this routine to return FALSE even though a valid 3084129198Scognet * mapping does exist. This is because we don't lock, so the metadata 3085129198Scognet * state may be inconsistent. 3086129198Scognet * 3087129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3088129198Scognet * a "section" mapping. 3089129198Scognet */ 3090129198Scognetboolean_t 3091129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3092129198Scognet{ 3093129198Scognet struct l2_dtable *l2; 3094129198Scognet pd_entry_t *pl1pd, l1pd; 3095129198Scognet pt_entry_t *ptep; 3096129198Scognet u_short l1idx; 3097129198Scognet 3098129198Scognet if (pm->pm_l1 == NULL) 3099129198Scognet return (FALSE); 3100129198Scognet 3101129198Scognet l1idx = L1_IDX(va); 3102129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3103129198Scognet l1pd = *pl1pd; 3104129198Scognet 3105129198Scognet if (l1pte_section_p(l1pd)) { 3106129198Scognet *ptp = NULL; 3107129198Scognet return (TRUE); 3108129198Scognet } 3109129198Scognet 3110129198Scognet if (pm->pm_l2 == NULL) 3111129198Scognet return (FALSE); 3112129198Scognet 3113129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3114129198Scognet 3115129198Scognet if (l2 == NULL || 3116129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3117129198Scognet return (FALSE); 3118129198Scognet } 3119129198Scognet 3120129198Scognet *ptp = &ptep[l2pte_index(va)]; 3121129198Scognet return (TRUE); 3122129198Scognet} 3123129198Scognet 3124129198Scognet/* 3125129198Scognet * Routine: pmap_remove_all 3126129198Scognet * Function: 3127129198Scognet * Removes this physical page from 3128129198Scognet * all physical maps in which it resides. 3129129198Scognet * Reflects back modify bits to the pager. 3130129198Scognet * 3131129198Scognet * Notes: 3132129198Scognet * Original versions of this routine were very 3133129198Scognet * inefficient because they iteratively called 3134129198Scognet * pmap_remove (slow...) 3135129198Scognet */ 3136129198Scognetvoid 3137129198Scognetpmap_remove_all(vm_page_t m) 3138129198Scognet{ 3139129198Scognet pv_entry_t pv; 3140135641Scognet pt_entry_t *ptep, pte; 3141135641Scognet struct l2_bucket *l2b; 3142135641Scognet boolean_t flush = FALSE; 3143135641Scognet pmap_t curpm; 3144135641Scognet int flags = 0; 3145129198Scognet 3146129198Scognet#if defined(PMAP_DEBUG) 3147129198Scognet /* 3148129198Scognet * XXX this makes pmap_page_protect(NONE) illegal for non-managed 3149129198Scognet * pages! 3150129198Scognet */ 3151147217Salc if (m->flags & PG_FICTITIOUS) { 3152129198Scognet panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m)); 3153129198Scognet } 3154129198Scognet#endif 3155129198Scognet 3156135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3157135641Scognet return; 3158135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3159129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3160135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3161135641Scognet pv->pv_pmap == pmap_kernel())) 3162135641Scognet flush = TRUE; 3163159352Salc PMAP_LOCK(pv->pv_pmap); 3164135641Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3165135641Scognet KASSERT(l2b != NULL, ("No l2 bucket")); 3166135641Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3167135641Scognet pte = *ptep; 3168135641Scognet *ptep = 0; 3169135641Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3170135641Scognet pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3171135641Scognet if (pv->pv_flags & PVF_WIRED) 3172135641Scognet pv->pv_pmap->pm_stats.wired_count--; 3173129198Scognet pv->pv_pmap->pm_stats.resident_count--; 3174135641Scognet flags |= pv->pv_flags; 3175135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3176159352Salc PMAP_UNLOCK(pv->pv_pmap); 3177129198Scognet pmap_free_pv_entry(pv); 3178129198Scognet } 3179129198Scognet 3180135641Scognet if (flush) { 3181135641Scognet if (PV_BEEN_EXECD(flags)) 3182135641Scognet pmap_tlb_flushID(curpm); 3183135641Scognet else 3184135641Scognet pmap_tlb_flushD(curpm); 3185135641Scognet } 3186150865Scognet vm_page_flag_clear(m, PG_WRITEABLE); 3187129198Scognet} 3188129198Scognet 3189129198Scognet 3190129198Scognet/* 3191129198Scognet * Set the physical protection on the 3192129198Scognet * specified range of this map as requested. 3193129198Scognet */ 3194129198Scognetvoid 3195129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3196129198Scognet{ 3197129198Scognet struct l2_bucket *l2b; 3198129198Scognet pt_entry_t *ptep, pte; 3199129198Scognet vm_offset_t next_bucket; 3200129198Scognet u_int flags; 3201129198Scognet int flush; 3202129198Scognet 3203129198Scognet if ((prot & VM_PROT_READ) == 0) { 3204129198Scognet pmap_remove(pm, sva, eva); 3205129198Scognet return; 3206129198Scognet } 3207129198Scognet 3208129198Scognet if (prot & VM_PROT_WRITE) { 3209129198Scognet /* 3210129198Scognet * If this is a read->write transition, just ignore it and let 3211135641Scognet * vm_fault() take care of it later. 3212129198Scognet */ 3213129198Scognet return; 3214129198Scognet } 3215129198Scognet 3216159352Salc vm_page_lock_queues(); 3217159352Salc PMAP_LOCK(pm); 3218129198Scognet 3219129198Scognet /* 3220129198Scognet * OK, at this point, we know we're doing write-protect operation. 3221129198Scognet * If the pmap is active, write-back the range. 3222129198Scognet */ 3223129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3224129198Scognet 3225129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3226129198Scognet flags = 0; 3227129198Scognet 3228129198Scognet while (sva < eva) { 3229129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3230129198Scognet if (next_bucket > eva) 3231129198Scognet next_bucket = eva; 3232129198Scognet 3233129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3234129198Scognet if (l2b == NULL) { 3235129198Scognet sva = next_bucket; 3236129198Scognet continue; 3237129198Scognet } 3238129198Scognet 3239129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3240129198Scognet 3241129198Scognet while (sva < next_bucket) { 3242129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3243129198Scognet struct vm_page *pg; 3244129198Scognet u_int f; 3245129198Scognet 3246129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3247129198Scognet pte &= ~L2_S_PROT_W; 3248129198Scognet *ptep = pte; 3249129198Scognet PTE_SYNC(ptep); 3250129198Scognet 3251129198Scognet if (pg != NULL) { 3252129198Scognet f = pmap_modify_pv(pg, pm, sva, 3253129198Scognet PVF_WRITE, 0); 3254129198Scognet pmap_vac_me_harder(pg, pm, sva); 3255157970Scognet vm_page_dirty(pg); 3256129198Scognet } else 3257129198Scognet f = PVF_REF | PVF_EXEC; 3258129198Scognet 3259129198Scognet if (flush >= 0) { 3260129198Scognet flush++; 3261129198Scognet flags |= f; 3262129198Scognet } else 3263129198Scognet if (PV_BEEN_EXECD(f)) 3264129198Scognet pmap_tlb_flushID_SE(pm, sva); 3265129198Scognet else 3266129198Scognet if (PV_BEEN_REFD(f)) 3267129198Scognet pmap_tlb_flushD_SE(pm, sva); 3268129198Scognet } 3269129198Scognet 3270129198Scognet sva += PAGE_SIZE; 3271129198Scognet ptep++; 3272129198Scognet } 3273129198Scognet } 3274129198Scognet 3275129198Scognet 3276129198Scognet if (flush) { 3277129198Scognet if (PV_BEEN_EXECD(flags)) 3278129198Scognet pmap_tlb_flushID(pm); 3279129198Scognet else 3280129198Scognet if (PV_BEEN_REFD(flags)) 3281129198Scognet pmap_tlb_flushD(pm); 3282129198Scognet } 3283144760Scognet vm_page_unlock_queues(); 3284129198Scognet 3285159352Salc PMAP_UNLOCK(pm); 3286129198Scognet} 3287129198Scognet 3288129198Scognet 3289129198Scognet/* 3290129198Scognet * Insert the given physical page (p) at 3291129198Scognet * the specified virtual address (v) in the 3292129198Scognet * target physical map with the protection requested. 3293129198Scognet * 3294129198Scognet * If specified, the page will be wired down, meaning 3295129198Scognet * that the related pte can not be reclaimed. 3296129198Scognet * 3297129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3298129198Scognet * or lose information. That is, this routine must actually 3299129198Scognet * insert this page into the given map NOW. 3300129198Scognet */ 3301135641Scognet 3302129198Scognetvoid 3303129198Scognetpmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3304129198Scognet boolean_t wired) 3305129198Scognet{ 3306159127Salc 3307159127Salc vm_page_lock_queues(); 3308159352Salc PMAP_LOCK(pmap); 3309160260Scognet pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK); 3310159127Salc vm_page_unlock_queues(); 3311159352Salc PMAP_UNLOCK(pmap); 3312159127Salc} 3313159127Salc 3314159127Salc/* 3315159127Salc * The page queues and pmap must be locked. 3316159127Salc */ 3317159127Salcstatic void 3318159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3319160260Scognet boolean_t wired, int flags) 3320159127Salc{ 3321135641Scognet struct l2_bucket *l2b = NULL; 3322129198Scognet struct vm_page *opg; 3323144760Scognet struct pv_entry *pve = NULL; 3324129198Scognet pt_entry_t *ptep, npte, opte; 3325129198Scognet u_int nflags; 3326129198Scognet u_int oflags; 3327129198Scognet vm_paddr_t pa; 3328129198Scognet 3329159325Salc PMAP_ASSERT_LOCKED(pmap); 3330159127Salc mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3331129198Scognet if (va == vector_page) { 3332129198Scognet pa = systempage.pv_pa; 3333129198Scognet m = NULL; 3334129198Scognet } else 3335129198Scognet pa = VM_PAGE_TO_PHYS(m); 3336129198Scognet nflags = 0; 3337129198Scognet if (prot & VM_PROT_WRITE) 3338129198Scognet nflags |= PVF_WRITE; 3339129198Scognet if (prot & VM_PROT_EXECUTE) 3340129198Scognet nflags |= PVF_EXEC; 3341129198Scognet if (wired) 3342129198Scognet nflags |= PVF_WIRED; 3343129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3344129198Scognet "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3345129198Scognet 3346135641Scognet if (pmap == pmap_kernel()) { 3347129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3348135641Scognet if (l2b == NULL) 3349135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3350160260Scognet } else { 3351160260Scognetdo_l2b_alloc: 3352129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3353160260Scognet if (l2b == NULL) { 3354160260Scognet if (flags & M_WAITOK) { 3355160260Scognet PMAP_UNLOCK(pmap); 3356160260Scognet vm_page_unlock_queues(); 3357160260Scognet VM_WAIT; 3358160260Scognet vm_page_lock_queues(); 3359160260Scognet PMAP_LOCK(pmap); 3360160260Scognet goto do_l2b_alloc; 3361160260Scognet } 3362160260Scognet return; 3363160260Scognet } 3364160260Scognet } 3365160260Scognet 3366129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3367129198Scognet 3368135641Scognet opte = *ptep; 3369129198Scognet npte = pa; 3370129198Scognet oflags = 0; 3371129198Scognet if (opte) { 3372129198Scognet /* 3373129198Scognet * There is already a mapping at this address. 3374129198Scognet * If the physical address is different, lookup the 3375129198Scognet * vm_page. 3376129198Scognet */ 3377129198Scognet if (l2pte_pa(opte) != pa) 3378129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3379129198Scognet else 3380129198Scognet opg = m; 3381129198Scognet } else 3382129198Scognet opg = NULL; 3383129198Scognet 3384135641Scognet if ((prot & (VM_PROT_ALL)) || 3385135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3386129198Scognet /* 3387135641Scognet * - The access type indicates that we don't need 3388135641Scognet * to do referenced emulation. 3389135641Scognet * OR 3390135641Scognet * - The physical page has already been referenced 3391135641Scognet * so no need to re-do referenced emulation here. 3392129198Scognet */ 3393135641Scognet npte |= L2_S_PROTO; 3394135641Scognet 3395135641Scognet nflags |= PVF_REF; 3396135641Scognet 3397144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3398144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3399129198Scognet /* 3400135641Scognet * This is a writable mapping, and the 3401135641Scognet * page's mod state indicates it has 3402135641Scognet * already been modified. Make it 3403135641Scognet * writable from the outset. 3404129198Scognet */ 3405135641Scognet nflags |= PVF_MOD; 3406157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3407144760Scognet vm_page_dirty(m); 3408129198Scognet } 3409144760Scognet if (m && opte) 3410144760Scognet vm_page_flag_set(m, PG_REFERENCED); 3411135641Scognet } else { 3412135641Scognet /* 3413135641Scognet * Need to do page referenced emulation. 3414135641Scognet */ 3415135641Scognet npte |= L2_TYPE_INV; 3416135641Scognet } 3417135641Scognet 3418135641Scognet if (prot & VM_PROT_WRITE) 3419135641Scognet npte |= L2_S_PROT_W; 3420135641Scognet npte |= pte_l2_s_cache_mode; 3421135641Scognet if (m && m == opg) { 3422135641Scognet /* 3423135641Scognet * We're changing the attrs of an existing mapping. 3424135641Scognet */ 3425135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3426135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3427135641Scognet PVF_MOD | PVF_REF, nflags); 3428135641Scognet 3429135641Scognet /* 3430135641Scognet * We may need to flush the cache if we're 3431135641Scognet * doing rw-ro... 3432135641Scognet */ 3433135641Scognet if (pmap_is_current(pmap) && 3434135641Scognet (oflags & PVF_NC) == 0 && 3435129198Scognet (opte & L2_S_PROT_W) != 0 && 3436129198Scognet (prot & VM_PROT_WRITE) == 0) 3437135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3438129198Scognet } else { 3439129198Scognet /* 3440135641Scognet * New mapping, or changing the backing page 3441135641Scognet * of an existing mapping. 3442129198Scognet */ 3443129198Scognet if (opg) { 3444129198Scognet /* 3445135641Scognet * Replacing an existing mapping with a new one. 3446135641Scognet * It is part of our managed memory so we 3447135641Scognet * must remove it from the PV list 3448129198Scognet */ 3449129198Scognet pve = pmap_remove_pv(opg, pmap, va); 3450159088Scognet if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) && 3451159088Scognet pve) 3452135641Scognet pmap_free_pv_entry(pve); 3453159088Scognet else if (!pve && 3454159088Scognet !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3455144760Scognet pve = pmap_get_pv_entry(); 3456135641Scognet KASSERT(pve != NULL, ("No pv")); 3457129198Scognet oflags = pve->pv_flags; 3458135641Scognet 3459135641Scognet /* 3460135641Scognet * If the old mapping was valid (ref/mod 3461135641Scognet * emulation creates 'invalid' mappings 3462135641Scognet * initially) then make sure to frob 3463135641Scognet * the cache. 3464135641Scognet */ 3465135641Scognet if ((oflags & PVF_NC) == 0 && 3466135641Scognet l2pte_valid(opte)) { 3467135641Scognet if (PV_BEEN_EXECD(oflags)) { 3468129198Scognet pmap_idcache_wbinv_range(pmap, va, 3469129198Scognet PAGE_SIZE); 3470135641Scognet } else 3471135641Scognet if (PV_BEEN_REFD(oflags)) { 3472135641Scognet pmap_dcache_wb_range(pmap, va, 3473135641Scognet PAGE_SIZE, TRUE, 3474135641Scognet (oflags & PVF_WRITE) == 0); 3475135641Scognet } 3476129198Scognet } 3477150865Scognet } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3478135641Scognet if ((pve = pmap_get_pv_entry()) == NULL) { 3479135641Scognet panic("pmap_enter: no pv entries"); 3480135641Scognet } 3481157970Scognet if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) { 3482157970Scognet KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3483157970Scognet ("pmap_enter: managed mapping within the clean submap")); 3484135641Scognet pmap_enter_pv(m, pve, pmap, va, nflags); 3485157970Scognet } 3486129198Scognet } 3487129198Scognet /* 3488129198Scognet * Make sure userland mappings get the right permissions 3489129198Scognet */ 3490129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3491129198Scognet npte |= L2_S_PROT_U; 3492129198Scognet } 3493129198Scognet 3494129198Scognet /* 3495129198Scognet * Keep the stats up to date 3496129198Scognet */ 3497129198Scognet if (opte == 0) { 3498129198Scognet l2b->l2b_occupancy++; 3499129198Scognet pmap->pm_stats.resident_count++; 3500129198Scognet } 3501129198Scognet 3502129198Scognet 3503129198Scognet /* 3504129198Scognet * If this is just a wiring change, the two PTEs will be 3505129198Scognet * identical, so there's no need to update the page table. 3506129198Scognet */ 3507129198Scognet if (npte != opte) { 3508135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3509129198Scognet 3510129198Scognet *ptep = npte; 3511129198Scognet if (is_cached) { 3512129198Scognet /* 3513129198Scognet * We only need to frob the cache/tlb if this pmap 3514129198Scognet * is current 3515129198Scognet */ 3516129198Scognet PTE_SYNC(ptep); 3517129198Scognet if (L1_IDX(va) != L1_IDX(vector_page) && 3518129198Scognet l2pte_valid(npte)) { 3519129198Scognet /* 3520129198Scognet * This mapping is likely to be accessed as 3521129198Scognet * soon as we return to userland. Fix up the 3522129198Scognet * L1 entry to avoid taking another 3523129198Scognet * page/domain fault. 3524129198Scognet */ 3525129198Scognet pd_entry_t *pl1pd, l1pd; 3526129198Scognet 3527129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3528129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3529144760Scognet L1_C_PROTO; 3530129198Scognet if (*pl1pd != l1pd) { 3531129198Scognet *pl1pd = l1pd; 3532129198Scognet PTE_SYNC(pl1pd); 3533129198Scognet } 3534129198Scognet } 3535129198Scognet } 3536129198Scognet 3537129198Scognet if (PV_BEEN_EXECD(oflags)) 3538129198Scognet pmap_tlb_flushID_SE(pmap, va); 3539135641Scognet else if (PV_BEEN_REFD(oflags)) 3540129198Scognet pmap_tlb_flushD_SE(pmap, va); 3541129198Scognet 3542129198Scognet 3543157025Scognet if (m) 3544157025Scognet pmap_vac_me_harder(m, pmap, va); 3545129198Scognet } 3546129198Scognet} 3547129198Scognet 3548129198Scognet/* 3549159303Salc * Maps a sequence of resident pages belonging to the same object. 3550159303Salc * The sequence begins with the given page m_start. This page is 3551159303Salc * mapped at the given virtual address start. Each subsequent page is 3552159303Salc * mapped at a virtual address that is offset from start by the same 3553159303Salc * amount as the page is offset from m_start within the object. The 3554159303Salc * last page in the sequence is the page with the largest offset from 3555159303Salc * m_start that can be mapped at a virtual address less than the given 3556159303Salc * virtual address end. Not every virtual page between start and end 3557159303Salc * is mapped; only those for which a resident page exists with the 3558159303Salc * corresponding offset from m_start are mapped. 3559159303Salc */ 3560159303Salcvoid 3561159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3562159303Salc vm_page_t m_start, vm_prot_t prot) 3563159303Salc{ 3564159303Salc vm_page_t m; 3565159303Salc vm_pindex_t diff, psize; 3566159303Salc 3567159303Salc psize = atop(end - start); 3568159303Salc m = m_start; 3569159325Salc PMAP_LOCK(pmap); 3570159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3571159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3572160260Scognet (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT); 3573159303Salc m = TAILQ_NEXT(m, listq); 3574159303Salc } 3575159325Salc PMAP_UNLOCK(pmap); 3576159303Salc} 3577159303Salc 3578159303Salc/* 3579129198Scognet * this code makes some *MAJOR* assumptions: 3580129198Scognet * 1. Current pmap & pmap exists. 3581129198Scognet * 2. Not wired. 3582129198Scognet * 3. Read access. 3583129198Scognet * 4. No page table pages. 3584129198Scognet * but is *MUCH* faster than pmap_enter... 3585129198Scognet */ 3586129198Scognet 3587159627Supsvoid 3588159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3589129198Scognet{ 3590138897Salc 3591159325Salc PMAP_LOCK(pmap); 3592159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3593160260Scognet FALSE, M_NOWAIT); 3594159325Salc PMAP_UNLOCK(pmap); 3595129198Scognet} 3596129198Scognet 3597129198Scognet/* 3598129198Scognet * Routine: pmap_change_wiring 3599129198Scognet * Function: Change the wiring attribute for a map/virtual-address 3600129198Scognet * pair. 3601129198Scognet * In/out conditions: 3602129198Scognet * The mapping must already exist in the pmap. 3603129198Scognet */ 3604129198Scognetvoid 3605129198Scognetpmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3606129198Scognet{ 3607129198Scognet struct l2_bucket *l2b; 3608129198Scognet pt_entry_t *ptep, pte; 3609129198Scognet vm_page_t pg; 3610129198Scognet 3611159352Salc vm_page_lock_queues(); 3612159325Salc PMAP_LOCK(pmap); 3613129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3614129198Scognet KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3615129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3616129198Scognet pte = *ptep; 3617129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3618129198Scognet if (pg) 3619129198Scognet pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired); 3620159352Salc vm_page_unlock_queues(); 3621159325Salc PMAP_UNLOCK(pmap); 3622129198Scognet} 3623129198Scognet 3624129198Scognet 3625129198Scognet/* 3626129198Scognet * Copy the range specified by src_addr/len 3627129198Scognet * from the source map to the range dst_addr/len 3628129198Scognet * in the destination map. 3629129198Scognet * 3630129198Scognet * This routine is only advisory and need not do anything. 3631129198Scognet */ 3632129198Scognetvoid 3633129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3634129198Scognet vm_size_t len, vm_offset_t src_addr) 3635129198Scognet{ 3636129198Scognet} 3637129198Scognet 3638129198Scognet 3639129198Scognet/* 3640129198Scognet * Routine: pmap_extract 3641129198Scognet * Function: 3642129198Scognet * Extract the physical page address associated 3643129198Scognet * with the given map/virtual_address pair. 3644129198Scognet */ 3645131658Salcvm_paddr_t 3646129198Scognetpmap_extract(pmap_t pm, vm_offset_t va) 3647129198Scognet{ 3648129198Scognet struct l2_dtable *l2; 3649159450Salc pd_entry_t l1pd; 3650129198Scognet pt_entry_t *ptep, pte; 3651129198Scognet vm_paddr_t pa; 3652129198Scognet u_int l1idx; 3653129198Scognet l1idx = L1_IDX(va); 3654129198Scognet 3655159450Salc PMAP_LOCK(pm); 3656159450Salc l1pd = pm->pm_l1->l1_kva[l1idx]; 3657129198Scognet if (l1pte_section_p(l1pd)) { 3658129198Scognet /* 3659129198Scognet * These should only happen for pmap_kernel() 3660129198Scognet */ 3661129198Scognet KASSERT(pm == pmap_kernel(), ("huh")); 3662129198Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3663129198Scognet } else { 3664129198Scognet /* 3665129198Scognet * Note that we can't rely on the validity of the L1 3666129198Scognet * descriptor as an indication that a mapping exists. 3667129198Scognet * We have to look it up in the L2 dtable. 3668129198Scognet */ 3669129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3670129198Scognet 3671129198Scognet if (l2 == NULL || 3672129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3673159450Salc PMAP_UNLOCK(pm); 3674129198Scognet return (0); 3675129198Scognet } 3676129198Scognet 3677129198Scognet ptep = &ptep[l2pte_index(va)]; 3678129198Scognet pte = *ptep; 3679129198Scognet 3680159450Salc if (pte == 0) { 3681159450Salc PMAP_UNLOCK(pm); 3682129198Scognet return (0); 3683159450Salc } 3684129198Scognet 3685129198Scognet switch (pte & L2_TYPE_MASK) { 3686129198Scognet case L2_TYPE_L: 3687129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3688129198Scognet break; 3689129198Scognet 3690129198Scognet default: 3691129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3692129198Scognet break; 3693129198Scognet } 3694129198Scognet } 3695129198Scognet 3696159450Salc PMAP_UNLOCK(pm); 3697129198Scognet return (pa); 3698129198Scognet} 3699129198Scognet 3700133453Salc/* 3701133453Salc * Atomically extract and hold the physical page with the given 3702133453Salc * pmap and virtual address pair if that mapping permits the given 3703133453Salc * protection. 3704133453Salc * 3705133453Salc */ 3706129198Scognetvm_page_t 3707129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3708129198Scognet{ 3709135641Scognet struct l2_dtable *l2; 3710159378Salc pd_entry_t l1pd; 3711135641Scognet pt_entry_t *ptep, pte; 3712129198Scognet vm_paddr_t pa; 3713135641Scognet vm_page_t m = NULL; 3714135641Scognet u_int l1idx; 3715135641Scognet l1idx = L1_IDX(va); 3716129198Scognet 3717135641Scognet vm_page_lock_queues(); 3718159325Salc PMAP_LOCK(pmap); 3719159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3720135641Scognet if (l1pte_section_p(l1pd)) { 3721135641Scognet /* 3722135641Scognet * These should only happen for pmap_kernel() 3723135641Scognet */ 3724135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3725135641Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3726135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3727135641Scognet m = PHYS_TO_VM_PAGE(pa); 3728135641Scognet vm_page_hold(m); 3729135641Scognet } 3730135641Scognet 3731135641Scognet } else { 3732135641Scognet /* 3733135641Scognet * Note that we can't rely on the validity of the L1 3734135641Scognet * descriptor as an indication that a mapping exists. 3735135641Scognet * We have to look it up in the L2 dtable. 3736135641Scognet */ 3737135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3738135641Scognet 3739135641Scognet if (l2 == NULL || 3740135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3741159325Salc PMAP_UNLOCK(pmap); 3742150865Scognet vm_page_unlock_queues(); 3743135641Scognet return (NULL); 3744135641Scognet } 3745135641Scognet 3746135641Scognet ptep = &ptep[l2pte_index(va)]; 3747135641Scognet pte = *ptep; 3748135641Scognet 3749150865Scognet if (pte == 0) { 3750159325Salc PMAP_UNLOCK(pmap); 3751150865Scognet vm_page_unlock_queues(); 3752135641Scognet return (NULL); 3753150865Scognet } 3754135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3755135641Scognet switch (pte & L2_TYPE_MASK) { 3756135641Scognet case L2_TYPE_L: 3757135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3758135641Scognet break; 3759135641Scognet 3760135641Scognet default: 3761135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3762135641Scognet break; 3763135641Scognet } 3764135641Scognet m = PHYS_TO_VM_PAGE(pa); 3765135641Scognet vm_page_hold(m); 3766135641Scognet } 3767129198Scognet } 3768135641Scognet 3769159325Salc PMAP_UNLOCK(pmap); 3770135641Scognet vm_page_unlock_queues(); 3771129198Scognet return (m); 3772129198Scognet} 3773129198Scognet 3774129198Scognet/* 3775129198Scognet * Initialize a preallocated and zeroed pmap structure, 3776129198Scognet * such as one in a vmspace structure. 3777129198Scognet */ 3778129198Scognet 3779129198Scognetvoid 3780129198Scognetpmap_pinit(pmap_t pmap) 3781129198Scognet{ 3782129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3783129198Scognet 3784159325Salc PMAP_LOCK_INIT(pmap); 3785129198Scognet pmap_alloc_l1(pmap); 3786129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3787129198Scognet 3788129198Scognet pmap->pm_count = 1; 3789129198Scognet pmap->pm_active = 0; 3790129198Scognet 3791144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3792129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3793129198Scognet pmap->pm_stats.resident_count = 1; 3794129198Scognet if (vector_page < KERNBASE) { 3795129198Scognet pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3796129198Scognet VM_PROT_READ, 1); 3797129198Scognet } 3798129198Scognet} 3799129198Scognet 3800129198Scognet 3801129198Scognet/*************************************************** 3802129198Scognet * page management routines. 3803129198Scognet ***************************************************/ 3804129198Scognet 3805129198Scognet 3806135641Scognetstatic void 3807129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3808129198Scognet{ 3809129198Scognet pv_entry_count--; 3810129198Scognet uma_zfree(pvzone, pv); 3811129198Scognet} 3812129198Scognet 3813129198Scognet 3814129198Scognet/* 3815129198Scognet * get a new pv_entry, allocating a block from the system 3816129198Scognet * when needed. 3817129198Scognet * the memory allocation is performed bypassing the malloc code 3818129198Scognet * because of the possibility of allocations at interrupt time. 3819129198Scognet */ 3820129198Scognetstatic pv_entry_t 3821129198Scognetpmap_get_pv_entry(void) 3822129198Scognet{ 3823129198Scognet pv_entry_t ret_value; 3824129198Scognet 3825129198Scognet pv_entry_count++; 3826159500Salc if (pv_entry_count > pv_entry_high_water) 3827159500Salc pagedaemon_wakeup(); 3828129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3829129198Scognet return ret_value; 3830129198Scognet} 3831129198Scognet 3832129198Scognet 3833129198Scognet/* 3834129198Scognet * Remove the given range of addresses from the specified map. 3835129198Scognet * 3836129198Scognet * It is assumed that the start and end are properly 3837129198Scognet * rounded to the page size. 3838129198Scognet */ 3839129198Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3840129198Scognetvoid 3841129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3842129198Scognet{ 3843129198Scognet struct l2_bucket *l2b; 3844129198Scognet vm_offset_t next_bucket; 3845129198Scognet pt_entry_t *ptep; 3846129198Scognet u_int cleanlist_idx, total, cnt; 3847129198Scognet struct { 3848129198Scognet vm_offset_t va; 3849129198Scognet pt_entry_t *pte; 3850129198Scognet } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3851129198Scognet u_int mappings, is_exec, is_refd; 3852135641Scognet int flushall = 0; 3853129198Scognet 3854129198Scognet 3855129198Scognet /* 3856129198Scognet * we lock in the pmap => pv_head direction 3857129198Scognet */ 3858129198Scognet 3859137664Scognet vm_page_lock_queues(); 3860159352Salc PMAP_LOCK(pm); 3861135641Scognet if (!pmap_is_current(pm)) { 3862129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3863129198Scognet } else 3864129198Scognet cleanlist_idx = 0; 3865129198Scognet 3866129198Scognet total = 0; 3867129198Scognet while (sva < eva) { 3868129198Scognet /* 3869129198Scognet * Do one L2 bucket's worth at a time. 3870129198Scognet */ 3871129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3872129198Scognet if (next_bucket > eva) 3873129198Scognet next_bucket = eva; 3874129198Scognet 3875129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3876129198Scognet if (l2b == NULL) { 3877129198Scognet sva = next_bucket; 3878129198Scognet continue; 3879129198Scognet } 3880129198Scognet 3881129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3882129198Scognet mappings = 0; 3883129198Scognet 3884129198Scognet while (sva < next_bucket) { 3885129198Scognet struct vm_page *pg; 3886129198Scognet pt_entry_t pte; 3887129198Scognet vm_paddr_t pa; 3888129198Scognet 3889129198Scognet pte = *ptep; 3890129198Scognet 3891129198Scognet if (pte == 0) { 3892129198Scognet /* 3893129198Scognet * Nothing here, move along 3894129198Scognet */ 3895129198Scognet sva += PAGE_SIZE; 3896129198Scognet ptep++; 3897129198Scognet continue; 3898129198Scognet } 3899129198Scognet 3900129198Scognet pm->pm_stats.resident_count--; 3901129198Scognet pa = l2pte_pa(pte); 3902129198Scognet is_exec = 0; 3903129198Scognet is_refd = 1; 3904129198Scognet 3905129198Scognet /* 3906129198Scognet * Update flags. In a number of circumstances, 3907129198Scognet * we could cluster a lot of these and do a 3908129198Scognet * number of sequential pages in one go. 3909129198Scognet */ 3910129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3911129198Scognet struct pv_entry *pve; 3912159474Salc 3913129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3914135641Scognet if (pve) { 3915159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3916159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3917129198Scognet pmap_free_pv_entry(pve); 3918129198Scognet } 3919129198Scognet } 3920129198Scognet 3921129198Scognet if (!l2pte_valid(pte)) { 3922129198Scognet *ptep = 0; 3923129198Scognet PTE_SYNC_CURRENT(pm, ptep); 3924129198Scognet sva += PAGE_SIZE; 3925129198Scognet ptep++; 3926129198Scognet mappings++; 3927129198Scognet continue; 3928129198Scognet } 3929129198Scognet 3930129198Scognet if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3931129198Scognet /* Add to the clean list. */ 3932129198Scognet cleanlist[cleanlist_idx].pte = ptep; 3933129198Scognet cleanlist[cleanlist_idx].va = 3934129198Scognet sva | (is_exec & 1); 3935129198Scognet cleanlist_idx++; 3936129198Scognet } else 3937129198Scognet if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3938129198Scognet /* Nuke everything if needed. */ 3939129198Scognet pmap_idcache_wbinv_all(pm); 3940129198Scognet pmap_tlb_flushID(pm); 3941129198Scognet 3942129198Scognet /* 3943129198Scognet * Roll back the previous PTE list, 3944129198Scognet * and zero out the current PTE. 3945129198Scognet */ 3946129198Scognet for (cnt = 0; 3947129198Scognet cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3948129198Scognet *cleanlist[cnt].pte = 0; 3949129198Scognet } 3950129198Scognet *ptep = 0; 3951129198Scognet PTE_SYNC(ptep); 3952129198Scognet cleanlist_idx++; 3953135641Scognet flushall = 1; 3954129198Scognet } else { 3955129198Scognet *ptep = 0; 3956129198Scognet PTE_SYNC(ptep); 3957129198Scognet if (is_exec) 3958129198Scognet pmap_tlb_flushID_SE(pm, sva); 3959129198Scognet else 3960129198Scognet if (is_refd) 3961129198Scognet pmap_tlb_flushD_SE(pm, sva); 3962129198Scognet } 3963129198Scognet 3964129198Scognet sva += PAGE_SIZE; 3965129198Scognet ptep++; 3966129198Scognet mappings++; 3967129198Scognet } 3968129198Scognet 3969129198Scognet /* 3970129198Scognet * Deal with any left overs 3971129198Scognet */ 3972129198Scognet if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3973129198Scognet total += cleanlist_idx; 3974129198Scognet for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3975135641Scognet vm_offset_t clva = 3976135641Scognet cleanlist[cnt].va & ~1; 3977135641Scognet if (cleanlist[cnt].va & 1) { 3978135641Scognet pmap_idcache_wbinv_range(pm, 3979135641Scognet clva, PAGE_SIZE); 3980135641Scognet pmap_tlb_flushID_SE(pm, clva); 3981135641Scognet } else { 3982135641Scognet pmap_dcache_wb_range(pm, 3983135641Scognet clva, PAGE_SIZE, TRUE, 3984135641Scognet FALSE); 3985135641Scognet pmap_tlb_flushD_SE(pm, clva); 3986129198Scognet } 3987129198Scognet *cleanlist[cnt].pte = 0; 3988129198Scognet PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 3989129198Scognet } 3990129198Scognet 3991129198Scognet if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3992129198Scognet cleanlist_idx = 0; 3993129198Scognet else { 3994144760Scognet /* 3995144760Scognet * We are removing so much entries it's just 3996144760Scognet * easier to flush the whole cache. 3997144760Scognet */ 3998129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3999129198Scognet pmap_idcache_wbinv_all(pm); 4000135641Scognet flushall = 1; 4001129198Scognet } 4002129198Scognet } 4003129198Scognet 4004129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 4005129198Scognet } 4006129198Scognet 4007137664Scognet vm_page_unlock_queues(); 4008135641Scognet if (flushall) 4009135641Scognet cpu_tlb_flushID(); 4010159352Salc PMAP_UNLOCK(pm); 4011129198Scognet} 4012129198Scognet 4013129198Scognet 4014129198Scognet 4015129198Scognet 4016129198Scognet/* 4017129198Scognet * pmap_zero_page() 4018129198Scognet * 4019129198Scognet * Zero a given physical page by mapping it at a page hook point. 4020129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 4021129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 4022129198Scognet * _any_ bulk data very slow. 4023129198Scognet */ 4024129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4025129198Scognetvoid 4026129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 4027129198Scognet{ 4028129198Scognet#ifdef DEBUG 4029129198Scognet struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 4030129198Scognet 4031129198Scognet if (pg->md.pvh_list != NULL) 4032129198Scognet panic("pmap_zero_page: page has mappings"); 4033129198Scognet#endif 4034129198Scognet 4035150865Scognet if (_arm_bzero && 4036150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4037150865Scognet return; 4038129198Scognet 4039150865Scognet 4040159088Scognet mtx_lock(&cmtx); 4041129198Scognet /* 4042129198Scognet * Hook in the page, zero it, and purge the cache for that 4043129198Scognet * zeroed page. Invalidate the TLB as needed. 4044129198Scognet */ 4045129198Scognet *cdst_pte = L2_S_PROTO | phys | 4046129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4047129198Scognet PTE_SYNC(cdst_pte); 4048129198Scognet cpu_tlb_flushD_SE(cdstp); 4049129198Scognet cpu_cpwait(); 4050135641Scognet if (off || size != PAGE_SIZE) 4051129198Scognet bzero((void *)(cdstp + off), size); 4052129198Scognet else 4053129198Scognet bzero_page(cdstp); 4054159088Scognet mtx_unlock(&cmtx); 4055129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4056129198Scognet} 4057129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4058129198Scognet 4059129198Scognet#if ARM_MMU_XSCALE == 1 4060129198Scognetvoid 4061129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 4062129198Scognet{ 4063150865Scognet 4064150865Scognet if (_arm_bzero && 4065150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4066150865Scognet return; 4067159088Scognet mtx_lock(&cmtx); 4068129198Scognet /* 4069129198Scognet * Hook in the page, zero it, and purge the cache for that 4070129198Scognet * zeroed page. Invalidate the TLB as needed. 4071129198Scognet */ 4072129198Scognet *cdst_pte = L2_S_PROTO | phys | 4073129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4074129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4075129198Scognet PTE_SYNC(cdst_pte); 4076129198Scognet cpu_tlb_flushD_SE(cdstp); 4077129198Scognet cpu_cpwait(); 4078135641Scognet if (off || size != PAGE_SIZE) 4079129198Scognet bzero((void *)(cdstp + off), size); 4080129198Scognet else 4081129198Scognet bzero_page(cdstp); 4082159088Scognet mtx_unlock(&cmtx); 4083129198Scognet xscale_cache_clean_minidata(); 4084129198Scognet} 4085129198Scognet 4086129198Scognet/* 4087129198Scognet * Change the PTEs for the specified kernel mappings such that they 4088129198Scognet * will use the mini data cache instead of the main data cache. 4089129198Scognet */ 4090129198Scognetvoid 4091135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 4092129198Scognet{ 4093129198Scognet struct l2_bucket *l2b; 4094129198Scognet pt_entry_t *ptep, *sptep, pte; 4095129198Scognet vm_offset_t next_bucket, eva; 4096129198Scognet 4097129198Scognet#if (ARM_NMMUS > 1) 4098129198Scognet if (xscale_use_minidata == 0) 4099129198Scognet return; 4100129198Scognet#endif 4101129198Scognet 4102135641Scognet eva = va + size; 4103129198Scognet 4104129198Scognet while (va < eva) { 4105129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4106129198Scognet if (next_bucket > eva) 4107129198Scognet next_bucket = eva; 4108129198Scognet 4109129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4110129198Scognet 4111129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4112129198Scognet 4113129198Scognet while (va < next_bucket) { 4114129198Scognet pte = *ptep; 4115129198Scognet if (!l2pte_minidata(pte)) { 4116129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4117129198Scognet cpu_tlb_flushD_SE(va); 4118129198Scognet *ptep = pte & ~L2_B; 4119129198Scognet } 4120129198Scognet ptep++; 4121129198Scognet va += PAGE_SIZE; 4122129198Scognet } 4123129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4124129198Scognet } 4125129198Scognet cpu_cpwait(); 4126129198Scognet} 4127129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4128129198Scognet 4129129198Scognet/* 4130129198Scognet * pmap_zero_page zeros the specified hardware page by mapping 4131129198Scognet * the page into KVM and using bzero to clear its contents. 4132129198Scognet */ 4133129198Scognetvoid 4134129198Scognetpmap_zero_page(vm_page_t m) 4135129198Scognet{ 4136135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4137129198Scognet} 4138129198Scognet 4139129198Scognet 4140129198Scognet/* 4141129198Scognet * pmap_zero_page_area zeros the specified hardware page by mapping 4142129198Scognet * the page into KVM and using bzero to clear its contents. 4143129198Scognet * 4144129198Scognet * off and size may not cover an area beyond a single hardware page. 4145129198Scognet */ 4146129198Scognetvoid 4147129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4148129198Scognet{ 4149129198Scognet 4150129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4151129198Scognet} 4152129198Scognet 4153129198Scognet 4154129198Scognet/* 4155129198Scognet * pmap_zero_page_idle zeros the specified hardware page by mapping 4156129198Scognet * the page into KVM and using bzero to clear its contents. This 4157129198Scognet * is intended to be called from the vm_pagezero process only and 4158129198Scognet * outside of Giant. 4159129198Scognet */ 4160129198Scognetvoid 4161129198Scognetpmap_zero_page_idle(vm_page_t m) 4162129198Scognet{ 4163129198Scognet 4164129198Scognet pmap_zero_page(m); 4165129198Scognet} 4166129198Scognet 4167150865Scognet#if 0 4168129198Scognet/* 4169129198Scognet * pmap_clean_page() 4170129198Scognet * 4171129198Scognet * This is a local function used to work out the best strategy to clean 4172129198Scognet * a single page referenced by its entry in the PV table. It's used by 4173129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4174129198Scognet * 4175129198Scognet * Its policy is effectively: 4176129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4177129198Scognet * o If there is one mapping, we clean just that page. 4178129198Scognet * o If there are multiple mappings, we clean the entire cache. 4179129198Scognet * 4180129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4181129198Scognet * clean the entire cache, or 1 if it did. 4182129198Scognet * 4183129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4184129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4185129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4186129198Scognet * it will just result in not the most efficient clean for the page. 4187129198Scognet */ 4188129198Scognetstatic int 4189129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4190129198Scognet{ 4191129198Scognet pmap_t pm, pm_to_clean = NULL; 4192129198Scognet struct pv_entry *npv; 4193129198Scognet u_int cache_needs_cleaning = 0; 4194129198Scognet u_int flags = 0; 4195129198Scognet vm_offset_t page_to_clean = 0; 4196129198Scognet 4197129198Scognet if (pv == NULL) { 4198129198Scognet /* nothing mapped in so nothing to flush */ 4199129198Scognet return (0); 4200129198Scognet } 4201129198Scognet 4202129198Scognet /* 4203129198Scognet * Since we flush the cache each time we change to a different 4204129198Scognet * user vmspace, we only need to flush the page if it is in the 4205129198Scognet * current pmap. 4206129198Scognet */ 4207135641Scognet if (curthread) 4208135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4209129198Scognet else 4210129198Scognet pm = pmap_kernel(); 4211129198Scognet 4212129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4213129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4214129198Scognet flags |= npv->pv_flags; 4215129198Scognet /* 4216129198Scognet * The page is mapped non-cacheable in 4217129198Scognet * this map. No need to flush the cache. 4218129198Scognet */ 4219129198Scognet if (npv->pv_flags & PVF_NC) { 4220129198Scognet#ifdef DIAGNOSTIC 4221129198Scognet if (cache_needs_cleaning) 4222129198Scognet panic("pmap_clean_page: " 4223129198Scognet "cache inconsistency"); 4224129198Scognet#endif 4225129198Scognet break; 4226129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4227129198Scognet continue; 4228129198Scognet if (cache_needs_cleaning) { 4229129198Scognet page_to_clean = 0; 4230129198Scognet break; 4231129198Scognet } else { 4232129198Scognet page_to_clean = npv->pv_va; 4233129198Scognet pm_to_clean = npv->pv_pmap; 4234129198Scognet } 4235129198Scognet cache_needs_cleaning = 1; 4236129198Scognet } 4237129198Scognet } 4238129198Scognet if (page_to_clean) { 4239129198Scognet if (PV_BEEN_EXECD(flags)) 4240129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4241129198Scognet PAGE_SIZE); 4242129198Scognet else 4243129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4244129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4245129198Scognet } else if (cache_needs_cleaning) { 4246129198Scognet if (PV_BEEN_EXECD(flags)) 4247129198Scognet pmap_idcache_wbinv_all(pm); 4248129198Scognet else 4249129198Scognet pmap_dcache_wbinv_all(pm); 4250129198Scognet return (1); 4251129198Scognet } 4252129198Scognet return (0); 4253129198Scognet} 4254150865Scognet#endif 4255129198Scognet 4256129198Scognet/* 4257129198Scognet * pmap_copy_page copies the specified (machine independent) 4258129198Scognet * page by mapping the page into virtual memory and using 4259129198Scognet * bcopy to copy the page, one machine dependent page at a 4260129198Scognet * time. 4261129198Scognet */ 4262129198Scognet 4263129198Scognet/* 4264129198Scognet * pmap_copy_page() 4265129198Scognet * 4266129198Scognet * Copy one physical page into another, by mapping the pages into 4267129198Scognet * hook points. The same comment regarding cachability as in 4268129198Scognet * pmap_zero_page also applies here. 4269129198Scognet */ 4270129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4271129198Scognetvoid 4272129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4273129198Scognet{ 4274151596Scognet#if 0 4275129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4276151596Scognet#endif 4277129198Scognet#ifdef DEBUG 4278129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4279129198Scognet 4280129198Scognet if (dst_pg->md.pvh_list != NULL) 4281129198Scognet panic("pmap_copy_page: dst page has mappings"); 4282129198Scognet#endif 4283129198Scognet 4284129198Scognet 4285129198Scognet /* 4286129198Scognet * Clean the source page. Hold the source page's lock for 4287129198Scognet * the duration of the copy so that no other mappings can 4288129198Scognet * be created while we have a potentially aliased mapping. 4289129198Scognet */ 4290129198Scognet#if 0 4291150865Scognet /* 4292150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4293150865Scognet * pmap_copy_page(). 4294150865Scognet */ 4295129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4296150865Scognet#endif 4297129198Scognet /* 4298129198Scognet * Map the pages into the page hook points, copy them, and purge 4299129198Scognet * the cache for the appropriate page. Invalidate the TLB 4300129198Scognet * as required. 4301129198Scognet */ 4302159088Scognet mtx_lock(&cmtx); 4303129198Scognet *csrc_pte = L2_S_PROTO | src | 4304129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4305129198Scognet PTE_SYNC(csrc_pte); 4306129198Scognet *cdst_pte = L2_S_PROTO | dst | 4307129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4308129198Scognet PTE_SYNC(cdst_pte); 4309129198Scognet cpu_tlb_flushD_SE(csrcp); 4310129198Scognet cpu_tlb_flushD_SE(cdstp); 4311129198Scognet cpu_cpwait(); 4312129198Scognet bcopy_page(csrcp, cdstp); 4313159088Scognet mtx_unlock(&cmtx); 4314129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4315129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4316129198Scognet} 4317129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4318129198Scognet 4319129198Scognet#if ARM_MMU_XSCALE == 1 4320129198Scognetvoid 4321129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4322129198Scognet{ 4323150865Scognet#if 0 4324150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4325129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4326150865Scognet#endif 4327129198Scognet#ifdef DEBUG 4328129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4329129198Scognet 4330129198Scognet if (dst_pg->md.pvh_list != NULL) 4331129198Scognet panic("pmap_copy_page: dst page has mappings"); 4332129198Scognet#endif 4333129198Scognet 4334129198Scognet 4335129198Scognet /* 4336129198Scognet * Clean the source page. Hold the source page's lock for 4337129198Scognet * the duration of the copy so that no other mappings can 4338129198Scognet * be created while we have a potentially aliased mapping. 4339129198Scognet */ 4340150865Scognet#if 0 4341150865Scognet /* 4342150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4343150865Scognet * pmap_copy_page(). 4344150865Scognet */ 4345130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4346150865Scognet#endif 4347129198Scognet /* 4348129198Scognet * Map the pages into the page hook points, copy them, and purge 4349129198Scognet * the cache for the appropriate page. Invalidate the TLB 4350129198Scognet * as required. 4351129198Scognet */ 4352159088Scognet mtx_lock(&cmtx); 4353129198Scognet *csrc_pte = L2_S_PROTO | src | 4354129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4355129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4356129198Scognet PTE_SYNC(csrc_pte); 4357129198Scognet *cdst_pte = L2_S_PROTO | dst | 4358129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4359129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4360129198Scognet PTE_SYNC(cdst_pte); 4361129198Scognet cpu_tlb_flushD_SE(csrcp); 4362129198Scognet cpu_tlb_flushD_SE(cdstp); 4363129198Scognet cpu_cpwait(); 4364129198Scognet bcopy_page(csrcp, cdstp); 4365159088Scognet mtx_unlock(&cmtx); 4366129198Scognet xscale_cache_clean_minidata(); 4367129198Scognet} 4368129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4369129198Scognet 4370129198Scognetvoid 4371129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4372129198Scognet{ 4373146596Scognet cpu_dcache_wbinv_all(); 4374150865Scognet if (_arm_memcpy && 4375150865Scognet _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4376150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4377150865Scognet return; 4378129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4379129198Scognet} 4380129198Scognet 4381129198Scognet 4382129198Scognet 4383129198Scognet 4384129198Scognet/* 4385129198Scognet * this routine returns true if a physical page resides 4386129198Scognet * in the given pmap. 4387129198Scognet */ 4388129198Scognetboolean_t 4389129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4390129198Scognet{ 4391129198Scognet pv_entry_t pv; 4392129198Scognet int loops = 0; 4393129198Scognet 4394147217Salc if (m->flags & PG_FICTITIOUS) 4395129198Scognet return (FALSE); 4396129198Scognet 4397129198Scognet /* 4398129198Scognet * Not found, check current mappings returning immediately 4399129198Scognet */ 4400129198Scognet for (pv = TAILQ_FIRST(&m->md.pv_list); 4401129198Scognet pv; 4402129198Scognet pv = TAILQ_NEXT(pv, pv_list)) { 4403129198Scognet if (pv->pv_pmap == pmap) { 4404129198Scognet return (TRUE); 4405129198Scognet } 4406129198Scognet loops++; 4407129198Scognet if (loops >= 16) 4408129198Scognet break; 4409129198Scognet } 4410129198Scognet return (FALSE); 4411129198Scognet} 4412129198Scognet 4413129198Scognet 4414129198Scognet/* 4415129198Scognet * pmap_ts_referenced: 4416129198Scognet * 4417129198Scognet * Return the count of reference bits for a page, clearing all of them. 4418129198Scognet */ 4419129198Scognetint 4420129198Scognetpmap_ts_referenced(vm_page_t m) 4421129198Scognet{ 4422135641Scognet return (pmap_clearbit(m, PVF_REF)); 4423129198Scognet} 4424129198Scognet 4425129198Scognet 4426129198Scognetboolean_t 4427129198Scognetpmap_is_modified(vm_page_t m) 4428129198Scognet{ 4429135641Scognet 4430135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4431135641Scognet return (TRUE); 4432129198Scognet 4433129198Scognet return(FALSE); 4434129198Scognet} 4435129198Scognet 4436129198Scognet 4437129198Scognet/* 4438129198Scognet * Clear the modify bits on the specified physical page. 4439129198Scognet */ 4440129198Scognetvoid 4441129198Scognetpmap_clear_modify(vm_page_t m) 4442129198Scognet{ 4443129198Scognet 4444129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4445129198Scognet pmap_clearbit(m, PVF_MOD); 4446129198Scognet} 4447129198Scognet 4448129198Scognet 4449129198Scognet/* 4450129198Scognet * pmap_clear_reference: 4451129198Scognet * 4452129198Scognet * Clear the reference bit on the specified physical page. 4453129198Scognet */ 4454129198Scognetvoid 4455129198Scognetpmap_clear_reference(vm_page_t m) 4456129198Scognet{ 4457129198Scognet 4458129198Scognet if (m->md.pvh_attrs & PVF_REF) 4459129198Scognet pmap_clearbit(m, PVF_REF); 4460129198Scognet} 4461129198Scognet 4462129198Scognet 4463129198Scognet/* 4464160537Salc * Clear the write and modified bits in each of the given page's mappings. 4465160537Salc */ 4466160537Salcvoid 4467160537Salcpmap_clear_write(vm_page_t m) 4468160537Salc{ 4469160537Salc 4470160537Salc if (m->md.pvh_attrs & PVF_WRITE) 4471160537Salc pmap_clearbit(m, PVF_WRITE); 4472160537Salc else 4473160537Salc KASSERT((m->flags & PG_WRITEABLE) == 0, 4474160537Salc ("pmap_clear_write: page %p has PG_WRITEABLE set", m)); 4475160537Salc} 4476160537Salc 4477160537Salc 4478160537Salc/* 4479129198Scognet * perform the pmap work for mincore 4480129198Scognet */ 4481129198Scognetint 4482129198Scognetpmap_mincore(pmap_t pmap, vm_offset_t addr) 4483129198Scognet{ 4484129198Scognet printf("pmap_mincore()\n"); 4485129198Scognet 4486129198Scognet return (0); 4487129198Scognet} 4488129198Scognet 4489129198Scognet 4490129198Scognetvm_offset_t 4491129198Scognetpmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 4492129198Scognet{ 4493129198Scognet 4494129198Scognet return(addr); 4495129198Scognet} 4496129198Scognet 4497129198Scognet 4498129198Scognet/* 4499129198Scognet * Map a set of physical memory pages into the kernel virtual 4500129198Scognet * address space. Return a pointer to where it is mapped. This 4501129198Scognet * routine is intended to be used for mapping device memory, 4502129198Scognet * NOT real memory. 4503129198Scognet */ 4504129198Scognetvoid * 4505129198Scognetpmap_mapdev(vm_offset_t pa, vm_size_t size) 4506129198Scognet{ 4507129198Scognet vm_offset_t va, tmpva, offset; 4508129198Scognet 4509129198Scognet offset = pa & PAGE_MASK; 4510135641Scognet size = roundup(size, PAGE_SIZE); 4511129198Scognet 4512129198Scognet GIANT_REQUIRED; 4513129198Scognet 4514132560Salc va = kmem_alloc_nofault(kernel_map, size); 4515129198Scognet if (!va) 4516129198Scognet panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4517129198Scognet for (tmpva = va; size > 0;) { 4518135641Scognet pmap_kenter_internal(tmpva, pa, 0); 4519129198Scognet size -= PAGE_SIZE; 4520129198Scognet tmpva += PAGE_SIZE; 4521129198Scognet pa += PAGE_SIZE; 4522129198Scognet } 4523129198Scognet 4524159068Sbenno return ((void *)(va + offset)); 4525129198Scognet} 4526129198Scognet 4527129198Scognet#define BOOTSTRAP_DEBUG 4528129198Scognet 4529129198Scognet/* 4530129198Scognet * pmap_map_section: 4531129198Scognet * 4532129198Scognet * Create a single section mapping. 4533129198Scognet */ 4534129198Scognetvoid 4535129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4536129198Scognet int prot, int cache) 4537129198Scognet{ 4538129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4539129198Scognet pd_entry_t fl; 4540129198Scognet 4541129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4542129198Scognet 4543129198Scognet switch (cache) { 4544129198Scognet case PTE_NOCACHE: 4545129198Scognet default: 4546129198Scognet fl = 0; 4547129198Scognet break; 4548129198Scognet 4549129198Scognet case PTE_CACHE: 4550129198Scognet fl = pte_l1_s_cache_mode; 4551129198Scognet break; 4552129198Scognet 4553129198Scognet case PTE_PAGETABLE: 4554129198Scognet fl = pte_l1_s_cache_mode_pt; 4555129198Scognet break; 4556129198Scognet } 4557129198Scognet 4558129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4559129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4560129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4561129198Scognet 4562129198Scognet} 4563129198Scognet 4564129198Scognet/* 4565129198Scognet * pmap_link_l2pt: 4566129198Scognet * 4567129198Scognet * Link the L2 page table specified by "pa" into the L1 4568129198Scognet * page table at the slot for "va". 4569129198Scognet */ 4570129198Scognetvoid 4571129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4572129198Scognet{ 4573129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4574129198Scognet u_int slot = va >> L1_S_SHIFT; 4575129198Scognet 4576129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4577129198Scognet 4578129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4579129198Scognet PTE_SYNC(&pde[slot]); 4580129198Scognet 4581129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4582129198Scognet 4583129198Scognet 4584129198Scognet} 4585129198Scognet 4586129198Scognet/* 4587129198Scognet * pmap_map_entry 4588129198Scognet * 4589129198Scognet * Create a single page mapping. 4590129198Scognet */ 4591129198Scognetvoid 4592129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4593129198Scognet int cache) 4594129198Scognet{ 4595129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4596129198Scognet pt_entry_t fl; 4597129198Scognet pt_entry_t *pte; 4598129198Scognet 4599129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4600129198Scognet 4601129198Scognet switch (cache) { 4602129198Scognet case PTE_NOCACHE: 4603129198Scognet default: 4604129198Scognet fl = 0; 4605129198Scognet break; 4606129198Scognet 4607129198Scognet case PTE_CACHE: 4608129198Scognet fl = pte_l2_s_cache_mode; 4609129198Scognet break; 4610129198Scognet 4611129198Scognet case PTE_PAGETABLE: 4612129198Scognet fl = pte_l2_s_cache_mode_pt; 4613129198Scognet break; 4614129198Scognet } 4615129198Scognet 4616129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4617129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4618129198Scognet 4619129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4620129198Scognet 4621129198Scognet if (pte == NULL) 4622129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4623129198Scognet 4624129198Scognet pte[l2pte_index(va)] = 4625129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4626129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4627129198Scognet} 4628129198Scognet 4629129198Scognet/* 4630129198Scognet * pmap_map_chunk: 4631129198Scognet * 4632129198Scognet * Map a chunk of memory using the most efficient mappings 4633129198Scognet * possible (section. large page, small page) into the 4634129198Scognet * provided L1 and L2 tables at the specified virtual address. 4635129198Scognet */ 4636129198Scognetvm_size_t 4637129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4638129198Scognet vm_size_t size, int prot, int cache) 4639129198Scognet{ 4640129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4641129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4642129198Scognet vm_size_t resid; 4643129198Scognet int i; 4644129198Scognet 4645129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4646129198Scognet 4647129198Scognet if (l1pt == 0) 4648129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4649129198Scognet 4650129198Scognet#ifdef VERBOSE_INIT_ARM 4651159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4652129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4653129198Scognet#endif 4654129198Scognet 4655129198Scognet switch (cache) { 4656129198Scognet case PTE_NOCACHE: 4657129198Scognet default: 4658129198Scognet f1 = 0; 4659129198Scognet f2l = 0; 4660129198Scognet f2s = 0; 4661129198Scognet break; 4662129198Scognet 4663129198Scognet case PTE_CACHE: 4664129198Scognet f1 = pte_l1_s_cache_mode; 4665129198Scognet f2l = pte_l2_l_cache_mode; 4666129198Scognet f2s = pte_l2_s_cache_mode; 4667129198Scognet break; 4668129198Scognet 4669129198Scognet case PTE_PAGETABLE: 4670129198Scognet f1 = pte_l1_s_cache_mode_pt; 4671129198Scognet f2l = pte_l2_l_cache_mode_pt; 4672129198Scognet f2s = pte_l2_s_cache_mode_pt; 4673129198Scognet break; 4674129198Scognet } 4675129198Scognet 4676129198Scognet size = resid; 4677129198Scognet 4678129198Scognet while (resid > 0) { 4679129198Scognet /* See if we can use a section mapping. */ 4680129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4681129198Scognet#ifdef VERBOSE_INIT_ARM 4682129198Scognet printf("S"); 4683129198Scognet#endif 4684129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4685129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4686129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4687129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4688129198Scognet va += L1_S_SIZE; 4689129198Scognet pa += L1_S_SIZE; 4690129198Scognet resid -= L1_S_SIZE; 4691129198Scognet continue; 4692129198Scognet } 4693129198Scognet 4694129198Scognet /* 4695129198Scognet * Ok, we're going to use an L2 table. Make sure 4696129198Scognet * one is actually in the corresponding L1 slot 4697129198Scognet * for the current VA. 4698129198Scognet */ 4699129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4700129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4701129198Scognet 4702129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4703129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4704129198Scognet if (pte == NULL) 4705129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4706129198Scognet "0x%08x", va); 4707129198Scognet /* See if we can use a L2 large page mapping. */ 4708129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4709129198Scognet#ifdef VERBOSE_INIT_ARM 4710129198Scognet printf("L"); 4711129198Scognet#endif 4712129198Scognet for (i = 0; i < 16; i++) { 4713129198Scognet pte[l2pte_index(va) + i] = 4714129198Scognet L2_L_PROTO | pa | 4715129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4716129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4717129198Scognet } 4718129198Scognet va += L2_L_SIZE; 4719129198Scognet pa += L2_L_SIZE; 4720129198Scognet resid -= L2_L_SIZE; 4721129198Scognet continue; 4722129198Scognet } 4723129198Scognet 4724129198Scognet /* Use a small page mapping. */ 4725129198Scognet#ifdef VERBOSE_INIT_ARM 4726129198Scognet printf("P"); 4727129198Scognet#endif 4728129198Scognet pte[l2pte_index(va)] = 4729129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4730129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4731129198Scognet va += PAGE_SIZE; 4732129198Scognet pa += PAGE_SIZE; 4733129198Scognet resid -= PAGE_SIZE; 4734129198Scognet } 4735129198Scognet#ifdef VERBOSE_INIT_ARM 4736129198Scognet printf("\n"); 4737129198Scognet#endif 4738129198Scognet return (size); 4739129198Scognet 4740129198Scognet} 4741129198Scognet 4742135641Scognet/********************** Static device map routines ***************************/ 4743135641Scognet 4744135641Scognetstatic const struct pmap_devmap *pmap_devmap_table; 4745135641Scognet 4746135641Scognet/* 4747135641Scognet * Register the devmap table. This is provided in case early console 4748135641Scognet * initialization needs to register mappings created by bootstrap code 4749135641Scognet * before pmap_devmap_bootstrap() is called. 4750135641Scognet */ 4751135641Scognetvoid 4752135641Scognetpmap_devmap_register(const struct pmap_devmap *table) 4753135641Scognet{ 4754135641Scognet 4755135641Scognet pmap_devmap_table = table; 4756135641Scognet} 4757135641Scognet 4758135641Scognet/* 4759135641Scognet * Map all of the static regions in the devmap table, and remember 4760135641Scognet * the devmap table so other parts of the kernel can look up entries 4761135641Scognet * later. 4762135641Scognet */ 4763135641Scognetvoid 4764135641Scognetpmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4765135641Scognet{ 4766135641Scognet int i; 4767135641Scognet 4768135641Scognet pmap_devmap_table = table; 4769135641Scognet 4770135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4771135641Scognet#ifdef VERBOSE_INIT_ARM 4772159322Scognet printf("devmap: %08x -> %08x @ %08x\n", 4773135641Scognet pmap_devmap_table[i].pd_pa, 4774135641Scognet pmap_devmap_table[i].pd_pa + 4775135641Scognet pmap_devmap_table[i].pd_size - 1, 4776135641Scognet pmap_devmap_table[i].pd_va); 4777135641Scognet#endif 4778135641Scognet pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4779135641Scognet pmap_devmap_table[i].pd_pa, 4780135641Scognet pmap_devmap_table[i].pd_size, 4781135641Scognet pmap_devmap_table[i].pd_prot, 4782135641Scognet pmap_devmap_table[i].pd_cache); 4783135641Scognet } 4784135641Scognet} 4785135641Scognet 4786135641Scognetconst struct pmap_devmap * 4787135641Scognetpmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4788135641Scognet{ 4789135641Scognet int i; 4790135641Scognet 4791135641Scognet if (pmap_devmap_table == NULL) 4792135641Scognet return (NULL); 4793135641Scognet 4794135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4795135641Scognet if (pa >= pmap_devmap_table[i].pd_pa && 4796135641Scognet pa + size <= pmap_devmap_table[i].pd_pa + 4797135641Scognet pmap_devmap_table[i].pd_size) 4798135641Scognet return (&pmap_devmap_table[i]); 4799135641Scognet } 4800135641Scognet 4801135641Scognet return (NULL); 4802135641Scognet} 4803135641Scognet 4804135641Scognetconst struct pmap_devmap * 4805135641Scognetpmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4806135641Scognet{ 4807135641Scognet int i; 4808135641Scognet 4809135641Scognet if (pmap_devmap_table == NULL) 4810135641Scognet return (NULL); 4811135641Scognet 4812135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4813135641Scognet if (va >= pmap_devmap_table[i].pd_va && 4814135641Scognet va + size <= pmap_devmap_table[i].pd_va + 4815135641Scognet pmap_devmap_table[i].pd_size) 4816135641Scognet return (&pmap_devmap_table[i]); 4817135641Scognet } 4818135641Scognet 4819135641Scognet return (NULL); 4820135641Scognet} 4821135641Scognet 4822