pmap-v4.c revision 159068
1/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2/*- 3 * Copyright 2004 Olivier Houchard. 4 * Copyright 2003 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Steve C. Woodford for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/*- 39 * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40 * Copyright (c) 2001 Richard Earnshaw 41 * Copyright (c) 2001-2002 Christopher Gilbert 42 * All rights reserved. 43 * 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company nor the name of the author may be used to 50 * endorse or promote products derived from this software without specific 51 * prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 */ 65/*- 66 * Copyright (c) 1999 The NetBSD Foundation, Inc. 67 * All rights reserved. 68 * 69 * This code is derived from software contributed to The NetBSD Foundation 70 * by Charles M. Hannum. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 3. All advertising materials mentioning features or use of this software 81 * must display the following acknowledgement: 82 * This product includes software developed by the NetBSD 83 * Foundation, Inc. and its contributors. 84 * 4. Neither the name of The NetBSD Foundation nor the names of its 85 * contributors may be used to endorse or promote products derived 86 * from this software without specific prior written permission. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98 * POSSIBILITY OF SUCH DAMAGE. 99 */ 100 101/*- 102 * Copyright (c) 1994-1998 Mark Brinicombe. 103 * Copyright (c) 1994 Brini. 104 * All rights reserved. 105 * 106 * This code is derived from software written for Brini by Mark Brinicombe 107 * 108 * Redistribution and use in source and binary forms, with or without 109 * modification, are permitted provided that the following conditions 110 * are met: 111 * 1. Redistributions of source code must retain the above copyright 112 * notice, this list of conditions and the following disclaimer. 113 * 2. Redistributions in binary form must reproduce the above copyright 114 * notice, this list of conditions and the following disclaimer in the 115 * documentation and/or other materials provided with the distribution. 116 * 3. All advertising materials mentioning features or use of this software 117 * must display the following acknowledgement: 118 * This product includes software developed by Mark Brinicombe. 119 * 4. The name of the author may not be used to endorse or promote products 120 * derived from this software without specific prior written permission. 121 * 122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 131 * 132 * RiscBSD kernel project 133 * 134 * pmap.c 135 * 136 * Machine dependant vm stuff 137 * 138 * Created : 20/09/94 139 */ 140 141/* 142 * Special compilation symbols 143 * PMAP_DEBUG - Build in pmap_debug_level code 144 */ 145/* Include header files */ 146 147#include "opt_vm.h" 148 149#include <sys/cdefs.h> 150__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 159068 2006-05-30 14:21:09Z benno $"); 151#include <sys/param.h> 152#include <sys/systm.h> 153#include <sys/kernel.h> 154#include <sys/proc.h> 155#include <sys/malloc.h> 156#include <sys/msgbuf.h> 157#include <sys/vmmeter.h> 158#include <sys/mman.h> 159#include <sys/smp.h> 160#include <sys/sx.h> 161#include <sys/sched.h> 162 163#include <vm/vm.h> 164#include <vm/uma.h> 165#include <vm/pmap.h> 166#include <vm/vm_kern.h> 167#include <vm/vm_object.h> 168#include <vm/vm_map.h> 169#include <vm/vm_page.h> 170#include <vm/vm_pageout.h> 171#include <vm/vm_extern.h> 172#include <sys/lock.h> 173#include <sys/mutex.h> 174#include <machine/md_var.h> 175#include <machine/vmparam.h> 176#include <machine/cpu.h> 177#include <machine/cpufunc.h> 178#include <machine/pcb.h> 179 180#ifdef PMAP_DEBUG 181#define PDEBUG(_lev_,_stat_) \ 182 if (pmap_debug_level >= (_lev_)) \ 183 ((_stat_)) 184#define dprintf printf 185 186int pmap_debug_level = 0; 187#define PMAP_INLINE 188#else /* PMAP_DEBUG */ 189#define PDEBUG(_lev_,_stat_) /* Nothing */ 190#define dprintf(x, arg...) 191#define PMAP_INLINE __inline 192#endif /* PMAP_DEBUG */ 193 194extern struct pv_addr systempage; 195/* 196 * Internal function prototypes 197 */ 198static void pmap_free_pv_entry (pv_entry_t); 199static pv_entry_t pmap_get_pv_entry(void); 200 201static void pmap_vac_me_harder(struct vm_page *, pmap_t, 202 vm_offset_t); 203static void pmap_vac_me_kpmap(struct vm_page *, pmap_t, 204 vm_offset_t); 205static void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t); 206static void pmap_alloc_l1(pmap_t); 207static void pmap_free_l1(pmap_t); 208static void pmap_use_l1(pmap_t); 209 210static int pmap_clearbit(struct vm_page *, u_int); 211 212static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 213static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 214static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 215static vm_offset_t kernel_pt_lookup(vm_paddr_t); 216 217static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 218 219vm_offset_t avail_end; /* PA of last available physical page */ 220vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 221vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 222vm_offset_t pmap_curmaxkvaddr; 223vm_paddr_t kernel_l1pa; 224 225extern void *end; 226vm_offset_t kernel_vm_end = 0; 227 228struct pmap kernel_pmap_store; 229pmap_t kernel_pmap; 230 231static pt_entry_t *csrc_pte, *cdst_pte; 232static vm_offset_t csrcp, cdstp; 233static void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 234/* 235 * These routines are called when the CPU type is identified to set up 236 * the PTE prototypes, cache modes, etc. 237 * 238 * The variables are always here, just in case LKMs need to reference 239 * them (though, they shouldn't). 240 */ 241 242pt_entry_t pte_l1_s_cache_mode; 243pt_entry_t pte_l1_s_cache_mode_pt; 244pt_entry_t pte_l1_s_cache_mask; 245 246pt_entry_t pte_l2_l_cache_mode; 247pt_entry_t pte_l2_l_cache_mode_pt; 248pt_entry_t pte_l2_l_cache_mask; 249 250pt_entry_t pte_l2_s_cache_mode; 251pt_entry_t pte_l2_s_cache_mode_pt; 252pt_entry_t pte_l2_s_cache_mask; 253 254pt_entry_t pte_l2_s_prot_u; 255pt_entry_t pte_l2_s_prot_w; 256pt_entry_t pte_l2_s_prot_mask; 257 258pt_entry_t pte_l1_s_proto; 259pt_entry_t pte_l1_c_proto; 260pt_entry_t pte_l2_s_proto; 261 262void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 263void (*pmap_zero_page_func)(vm_paddr_t, int, int); 264/* 265 * Which pmap is currently 'live' in the cache 266 * 267 * XXXSCW: Fix for SMP ... 268 */ 269union pmap_cache_state *pmap_cache_state; 270 271LIST_HEAD(pmaplist, pmap); 272struct pmaplist allpmaps; 273 274/* static pt_entry_t *msgbufmap;*/ 275struct msgbuf *msgbufp = 0; 276 277extern void bcopy_page(vm_offset_t, vm_offset_t); 278extern void bzero_page(vm_offset_t); 279 280char *_tmppt; 281 282/* 283 * Metadata for L1 translation tables. 284 */ 285struct l1_ttable { 286 /* Entry on the L1 Table list */ 287 SLIST_ENTRY(l1_ttable) l1_link; 288 289 /* Entry on the L1 Least Recently Used list */ 290 TAILQ_ENTRY(l1_ttable) l1_lru; 291 292 /* Track how many domains are allocated from this L1 */ 293 volatile u_int l1_domain_use_count; 294 295 /* 296 * A free-list of domain numbers for this L1. 297 * We avoid using ffs() and a bitmap to track domains since ffs() 298 * is slow on ARM. 299 */ 300 u_int8_t l1_domain_first; 301 u_int8_t l1_domain_free[PMAP_DOMAINS]; 302 303 /* Physical address of this L1 page table */ 304 vm_paddr_t l1_physaddr; 305 306 /* KVA of this L1 page table */ 307 pd_entry_t *l1_kva; 308}; 309 310/* 311 * Convert a virtual address into its L1 table index. That is, the 312 * index used to locate the L2 descriptor table pointer in an L1 table. 313 * This is basically used to index l1->l1_kva[]. 314 * 315 * Each L2 descriptor table represents 1MB of VA space. 316 */ 317#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 318 319/* 320 * L1 Page Tables are tracked using a Least Recently Used list. 321 * - New L1s are allocated from the HEAD. 322 * - Freed L1s are added to the TAIl. 323 * - Recently accessed L1s (where an 'access' is some change to one of 324 * the userland pmaps which owns this L1) are moved to the TAIL. 325 */ 326static TAILQ_HEAD(, l1_ttable) l1_lru_list; 327/* 328 * A list of all L1 tables 329 */ 330static SLIST_HEAD(, l1_ttable) l1_list; 331static struct mtx l1_lru_lock; 332 333/* 334 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 335 * 336 * This is normally 16MB worth L2 page descriptors for any given pmap. 337 * Reference counts are maintained for L2 descriptors so they can be 338 * freed when empty. 339 */ 340struct l2_dtable { 341 /* The number of L2 page descriptors allocated to this l2_dtable */ 342 u_int l2_occupancy; 343 344 /* List of L2 page descriptors */ 345 struct l2_bucket { 346 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 347 vm_paddr_t l2b_phys; /* Physical address of same */ 348 u_short l2b_l1idx; /* This L2 table's L1 index */ 349 u_short l2b_occupancy; /* How many active descriptors */ 350 } l2_bucket[L2_BUCKET_SIZE]; 351}; 352 353/* pmap_kenter_internal flags */ 354#define KENTER_CACHE 0x1 355#define KENTER_USER 0x2 356 357/* 358 * Given an L1 table index, calculate the corresponding l2_dtable index 359 * and bucket index within the l2_dtable. 360 */ 361#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 362 (L2_SIZE - 1)) 363#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 364 365/* 366 * Given a virtual address, this macro returns the 367 * virtual address required to drop into the next L2 bucket. 368 */ 369#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 370 371/* 372 * L2 allocation. 373 */ 374#define pmap_alloc_l2_dtable() \ 375 (void*)uma_zalloc(l2table_zone, M_NOWAIT) 376#define pmap_free_l2_dtable(l2) \ 377 uma_zfree(l2table_zone, l2) 378 379/* 380 * We try to map the page tables write-through, if possible. However, not 381 * all CPUs have a write-through cache mode, so on those we have to sync 382 * the cache when we frob page tables. 383 * 384 * We try to evaluate this at compile time, if possible. However, it's 385 * not always possible to do that, hence this run-time var. 386 */ 387int pmap_needs_pte_sync; 388 389/* 390 * Macro to determine if a mapping might be resident in the 391 * instruction cache and/or TLB 392 */ 393#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 394 395/* 396 * Macro to determine if a mapping might be resident in the 397 * data cache and/or TLB 398 */ 399#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 400 401#ifndef PMAP_SHPGPERPROC 402#define PMAP_SHPGPERPROC 200 403#endif 404 405#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 406 curproc->p_vmspace->vm_map.pmap == (pm)) 407static uma_zone_t pvzone; 408uma_zone_t l2zone; 409static uma_zone_t l2table_zone; 410static vm_offset_t pmap_kernel_l2dtable_kva; 411static vm_offset_t pmap_kernel_l2ptp_kva; 412static vm_paddr_t pmap_kernel_l2ptp_phys; 413static struct vm_object pvzone_obj; 414static struct vm_object l2zone_obj; 415static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 416int pmap_pagedaemon_waken = 0; 417 418/* 419 * This list exists for the benefit of pmap_map_chunk(). It keeps track 420 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 421 * find them as necessary. 422 * 423 * Note that the data on this list MUST remain valid after initarm() returns, 424 * as pmap_bootstrap() uses it to contruct L2 table metadata. 425 */ 426SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 427 428static void 429pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 430{ 431 int i; 432 433 l1->l1_kva = l1pt; 434 l1->l1_domain_use_count = 0; 435 l1->l1_domain_first = 0; 436 437 for (i = 0; i < PMAP_DOMAINS; i++) 438 l1->l1_domain_free[i] = i + 1; 439 440 /* 441 * Copy the kernel's L1 entries to each new L1. 442 */ 443 if (l1pt != pmap_kernel()->pm_l1->l1_kva) 444 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 445 446 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 447 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 448 SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 449 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 450} 451 452static vm_offset_t 453kernel_pt_lookup(vm_paddr_t pa) 454{ 455 struct pv_addr *pv; 456 457 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 458#ifndef ARM32_NEW_VM_LAYOUT 459 if (pv->pv_pa == (pa & ~PAGE_MASK)) { 460 return (pv->pv_va | (pa & PAGE_MASK)); 461 } 462#else 463 if (pv->pv_pa == pa) 464 return (pv->pv_va); 465#endif 466 } 467 return (0); 468} 469 470#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 471void 472pmap_pte_init_generic(void) 473{ 474 475 pte_l1_s_cache_mode = L1_S_B|L1_S_C; 476 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 477 478 pte_l2_l_cache_mode = L2_B|L2_C; 479 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 480 481 pte_l2_s_cache_mode = L2_B|L2_C; 482 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 483 484 /* 485 * If we have a write-through cache, set B and C. If 486 * we have a write-back cache, then we assume setting 487 * only C will make those pages write-through. 488 */ 489 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 490 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 491 pte_l2_l_cache_mode_pt = L2_B|L2_C; 492 pte_l2_s_cache_mode_pt = L2_B|L2_C; 493 } else { 494 pte_l1_s_cache_mode_pt = L1_S_C; 495 pte_l2_l_cache_mode_pt = L2_C; 496 pte_l2_s_cache_mode_pt = L2_C; 497 } 498 499 pte_l2_s_prot_u = L2_S_PROT_U_generic; 500 pte_l2_s_prot_w = L2_S_PROT_W_generic; 501 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 502 503 pte_l1_s_proto = L1_S_PROTO_generic; 504 pte_l1_c_proto = L1_C_PROTO_generic; 505 pte_l2_s_proto = L2_S_PROTO_generic; 506 507 pmap_copy_page_func = pmap_copy_page_generic; 508 pmap_zero_page_func = pmap_zero_page_generic; 509} 510 511#if defined(CPU_ARM8) 512void 513pmap_pte_init_arm8(void) 514{ 515 516 /* 517 * ARM8 is compatible with generic, but we need to use 518 * the page tables uncached. 519 */ 520 pmap_pte_init_generic(); 521 522 pte_l1_s_cache_mode_pt = 0; 523 pte_l2_l_cache_mode_pt = 0; 524 pte_l2_s_cache_mode_pt = 0; 525} 526#endif /* CPU_ARM8 */ 527 528#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 529void 530pmap_pte_init_arm9(void) 531{ 532 533 /* 534 * ARM9 is compatible with generic, but we want to use 535 * write-through caching for now. 536 */ 537 pmap_pte_init_generic(); 538 539 pte_l1_s_cache_mode = L1_S_C; 540 pte_l2_l_cache_mode = L2_C; 541 pte_l2_s_cache_mode = L2_C; 542 543 pte_l1_s_cache_mode_pt = L1_S_C; 544 pte_l2_l_cache_mode_pt = L2_C; 545 pte_l2_s_cache_mode_pt = L2_C; 546} 547#endif /* CPU_ARM9 */ 548#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 549 550#if defined(CPU_ARM10) 551void 552pmap_pte_init_arm10(void) 553{ 554 555 /* 556 * ARM10 is compatible with generic, but we want to use 557 * write-through caching for now. 558 */ 559 pmap_pte_init_generic(); 560 561 pte_l1_s_cache_mode = L1_S_B | L1_S_C; 562 pte_l2_l_cache_mode = L2_B | L2_C; 563 pte_l2_s_cache_mode = L2_B | L2_C; 564 565 pte_l1_s_cache_mode_pt = L1_S_C; 566 pte_l2_l_cache_mode_pt = L2_C; 567 pte_l2_s_cache_mode_pt = L2_C; 568 569} 570#endif /* CPU_ARM10 */ 571 572#if ARM_MMU_SA1 == 1 573void 574pmap_pte_init_sa1(void) 575{ 576 577 /* 578 * The StrongARM SA-1 cache does not have a write-through 579 * mode. So, do the generic initialization, then reset 580 * the page table cache mode to B=1,C=1, and note that 581 * the PTEs need to be sync'd. 582 */ 583 pmap_pte_init_generic(); 584 585 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 586 pte_l2_l_cache_mode_pt = L2_B|L2_C; 587 pte_l2_s_cache_mode_pt = L2_B|L2_C; 588 589 pmap_needs_pte_sync = 1; 590} 591#endif /* ARM_MMU_SA1 == 1*/ 592 593#if ARM_MMU_XSCALE == 1 594#if (ARM_NMMUS > 1) 595static u_int xscale_use_minidata; 596#endif 597 598void 599pmap_pte_init_xscale(void) 600{ 601 uint32_t auxctl; 602 int write_through = 0; 603 604 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 605 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 606 607 pte_l2_l_cache_mode = L2_B|L2_C; 608 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 609 610 pte_l2_s_cache_mode = L2_B|L2_C; 611 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 612 613 pte_l1_s_cache_mode_pt = L1_S_C; 614 pte_l2_l_cache_mode_pt = L2_C; 615 pte_l2_s_cache_mode_pt = L2_C; 616#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 617 /* 618 * The XScale core has an enhanced mode where writes that 619 * miss the cache cause a cache line to be allocated. This 620 * is significantly faster than the traditional, write-through 621 * behavior of this case. 622 */ 623 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 624 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 625 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 626#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 627#ifdef XSCALE_CACHE_WRITE_THROUGH 628 /* 629 * Some versions of the XScale core have various bugs in 630 * their cache units, the work-around for which is to run 631 * the cache in write-through mode. Unfortunately, this 632 * has a major (negative) impact on performance. So, we 633 * go ahead and run fast-and-loose, in the hopes that we 634 * don't line up the planets in a way that will trip the 635 * bugs. 636 * 637 * However, we give you the option to be slow-but-correct. 638 */ 639 write_through = 1; 640#elif defined(XSCALE_CACHE_WRITE_BACK) 641 /* force write back cache mode */ 642 write_through = 0; 643#elif defined(CPU_XSCALE_PXA2X0) 644 /* 645 * Intel PXA2[15]0 processors are known to have a bug in 646 * write-back cache on revision 4 and earlier (stepping 647 * A[01] and B[012]). Fixed for C0 and later. 648 */ 649 { 650 uint32_t id, type; 651 652 id = cpufunc_id(); 653 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 654 655 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 656 if ((id & CPU_ID_REVISION_MASK) < 5) { 657 /* write through for stepping A0-1 and B0-2 */ 658 write_through = 1; 659 } 660 } 661 } 662#endif /* XSCALE_CACHE_WRITE_THROUGH */ 663 664 if (write_through) { 665 pte_l1_s_cache_mode = L1_S_C; 666 pte_l2_l_cache_mode = L2_C; 667 pte_l2_s_cache_mode = L2_C; 668 } 669 670#if (ARM_NMMUS > 1) 671 xscale_use_minidata = 1; 672#endif 673 674 pte_l2_s_prot_u = L2_S_PROT_U_xscale; 675 pte_l2_s_prot_w = L2_S_PROT_W_xscale; 676 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 677 678 pte_l1_s_proto = L1_S_PROTO_xscale; 679 pte_l1_c_proto = L1_C_PROTO_xscale; 680 pte_l2_s_proto = L2_S_PROTO_xscale; 681 682 pmap_copy_page_func = pmap_copy_page_xscale; 683 pmap_zero_page_func = pmap_zero_page_xscale; 684 685 /* 686 * Disable ECC protection of page table access, for now. 687 */ 688 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 689 auxctl &= ~XSCALE_AUXCTL_P; 690 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 691} 692 693/* 694 * xscale_setup_minidata: 695 * 696 * Set up the mini-data cache clean area. We require the 697 * caller to allocate the right amount of physically and 698 * virtually contiguous space. 699 */ 700extern vm_offset_t xscale_minidata_clean_addr; 701extern vm_size_t xscale_minidata_clean_size; /* already initialized */ 702void 703xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 704{ 705 pd_entry_t *pde = (pd_entry_t *) l1pt; 706 pt_entry_t *pte; 707 vm_size_t size; 708 uint32_t auxctl; 709 710 xscale_minidata_clean_addr = va; 711 712 /* Round it to page size. */ 713 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 714 715 for (; size != 0; 716 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 717#ifndef ARM32_NEW_VM_LAYOUT 718 pte = (pt_entry_t *) 719 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 720#else 721 pte = (pt_entry_t *) kernel_pt_lookup( 722 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 723#endif 724 if (pte == NULL) 725 panic("xscale_setup_minidata: can't find L2 table for " 726 "VA 0x%08x", (u_int32_t) va); 727#ifndef ARM32_NEW_VM_LAYOUT 728 pte[(va >> PAGE_SHIFT) & 0x3ff] = 729#else 730 pte[l2pte_index(va)] = 731#endif 732 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 733 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 734 } 735 736 /* 737 * Configure the mini-data cache for write-back with 738 * read/write-allocate. 739 * 740 * NOTE: In order to reconfigure the mini-data cache, we must 741 * make sure it contains no valid data! In order to do that, 742 * we must issue a global data cache invalidate command! 743 * 744 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 745 * THIS IS VERY IMPORTANT! 746 */ 747 748 /* Invalidate data and mini-data. */ 749 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 750 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 751 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 752 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 753} 754#endif 755 756/* 757 * Allocate an L1 translation table for the specified pmap. 758 * This is called at pmap creation time. 759 */ 760static void 761pmap_alloc_l1(pmap_t pm) 762{ 763 struct l1_ttable *l1; 764 u_int8_t domain; 765 766 /* 767 * Remove the L1 at the head of the LRU list 768 */ 769 mtx_lock(&l1_lru_lock); 770 l1 = TAILQ_FIRST(&l1_lru_list); 771 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 772 773 /* 774 * Pick the first available domain number, and update 775 * the link to the next number. 776 */ 777 domain = l1->l1_domain_first; 778 l1->l1_domain_first = l1->l1_domain_free[domain]; 779 780 /* 781 * If there are still free domain numbers in this L1, 782 * put it back on the TAIL of the LRU list. 783 */ 784 if (++l1->l1_domain_use_count < PMAP_DOMAINS) 785 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 786 787 mtx_unlock(&l1_lru_lock); 788 789 /* 790 * Fix up the relevant bits in the pmap structure 791 */ 792 pm->pm_l1 = l1; 793 pm->pm_domain = domain; 794} 795 796/* 797 * Free an L1 translation table. 798 * This is called at pmap destruction time. 799 */ 800static void 801pmap_free_l1(pmap_t pm) 802{ 803 struct l1_ttable *l1 = pm->pm_l1; 804 805 mtx_lock(&l1_lru_lock); 806 807 /* 808 * If this L1 is currently on the LRU list, remove it. 809 */ 810 if (l1->l1_domain_use_count < PMAP_DOMAINS) 811 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 812 813 /* 814 * Free up the domain number which was allocated to the pmap 815 */ 816 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 817 l1->l1_domain_first = pm->pm_domain; 818 l1->l1_domain_use_count--; 819 820 /* 821 * The L1 now must have at least 1 free domain, so add 822 * it back to the LRU list. If the use count is zero, 823 * put it at the head of the list, otherwise it goes 824 * to the tail. 825 */ 826 if (l1->l1_domain_use_count == 0) { 827 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 828 } else 829 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 830 831 mtx_unlock(&l1_lru_lock); 832} 833 834static PMAP_INLINE void 835pmap_use_l1(pmap_t pm) 836{ 837 struct l1_ttable *l1; 838 839 /* 840 * Do nothing if we're in interrupt context. 841 * Access to an L1 by the kernel pmap must not affect 842 * the LRU list. 843 */ 844 if (pm == pmap_kernel()) 845 return; 846 847 l1 = pm->pm_l1; 848 849 /* 850 * If the L1 is not currently on the LRU list, just return 851 */ 852 if (l1->l1_domain_use_count == PMAP_DOMAINS) 853 return; 854 855 mtx_lock(&l1_lru_lock); 856 857 /* 858 * Check the use count again, now that we've acquired the lock 859 */ 860 if (l1->l1_domain_use_count == PMAP_DOMAINS) { 861 mtx_unlock(&l1_lru_lock); 862 return; 863 } 864 865 /* 866 * Move the L1 to the back of the LRU list 867 */ 868 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 869 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 870 871 mtx_unlock(&l1_lru_lock); 872} 873 874 875/* 876 * Returns a pointer to the L2 bucket associated with the specified pmap 877 * and VA, or NULL if no L2 bucket exists for the address. 878 */ 879static PMAP_INLINE struct l2_bucket * 880pmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 881{ 882 struct l2_dtable *l2; 883 struct l2_bucket *l2b; 884 u_short l1idx; 885 886 l1idx = L1_IDX(va); 887 888 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 889 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 890 return (NULL); 891 892 return (l2b); 893} 894 895/* 896 * Returns a pointer to the L2 bucket associated with the specified pmap 897 * and VA. 898 * 899 * If no L2 bucket exists, perform the necessary allocations to put an L2 900 * bucket/page table in place. 901 * 902 * Note that if a new L2 bucket/page was allocated, the caller *must* 903 * increment the bucket occupancy counter appropriately *before* 904 * releasing the pmap's lock to ensure no other thread or cpu deallocates 905 * the bucket/page in the meantime. 906 */ 907static struct l2_bucket * 908pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 909{ 910 struct l2_dtable *l2; 911 struct l2_bucket *l2b; 912 u_short l1idx; 913 914 l1idx = L1_IDX(va); 915 916 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 917 /* 918 * No mapping at this address, as there is 919 * no entry in the L1 table. 920 * Need to allocate a new l2_dtable. 921 */ 922 if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 923 return (NULL); 924 } 925 bzero(l2, sizeof(*l2)); 926 /* 927 * Link it into the parent pmap 928 */ 929 pm->pm_l2[L2_IDX(l1idx)] = l2; 930 } 931 932 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 933 934 /* 935 * Fetch pointer to the L2 page table associated with the address. 936 */ 937 if (l2b->l2b_kva == NULL) { 938 pt_entry_t *ptep; 939 940 /* 941 * No L2 page table has been allocated. Chances are, this 942 * is because we just allocated the l2_dtable, above. 943 */ 944 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT); 945 l2b->l2b_phys = vtophys(ptep); 946 if (ptep == NULL) { 947 /* 948 * Oops, no more L2 page tables available at this 949 * time. We may need to deallocate the l2_dtable 950 * if we allocated a new one above. 951 */ 952 if (l2->l2_occupancy == 0) { 953 pm->pm_l2[L2_IDX(l1idx)] = NULL; 954 pmap_free_l2_dtable(l2); 955 } 956 return (NULL); 957 } 958 959 l2->l2_occupancy++; 960 l2b->l2b_kva = ptep; 961 l2b->l2b_l1idx = l1idx; 962 } 963 964 return (l2b); 965} 966 967static PMAP_INLINE void 968#ifndef PMAP_INCLUDE_PTE_SYNC 969pmap_free_l2_ptp(pt_entry_t *l2) 970#else 971pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 972#endif 973{ 974#ifdef PMAP_INCLUDE_PTE_SYNC 975 /* 976 * Note: With a write-back cache, we may need to sync this 977 * L2 table before re-using it. 978 * This is because it may have belonged to a non-current 979 * pmap, in which case the cache syncs would have been 980 * skipped when the pages were being unmapped. If the 981 * L2 table were then to be immediately re-allocated to 982 * the *current* pmap, it may well contain stale mappings 983 * which have not yet been cleared by a cache write-back 984 * and so would still be visible to the mmu. 985 */ 986 if (need_sync) 987 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 988#endif 989 uma_zfree(l2zone, l2); 990} 991/* 992 * One or more mappings in the specified L2 descriptor table have just been 993 * invalidated. 994 * 995 * Garbage collect the metadata and descriptor table itself if necessary. 996 * 997 * The pmap lock must be acquired when this is called (not necessary 998 * for the kernel pmap). 999 */ 1000static void 1001pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1002{ 1003 struct l2_dtable *l2; 1004 pd_entry_t *pl1pd, l1pd; 1005 pt_entry_t *ptep; 1006 u_short l1idx; 1007 1008 1009 /* 1010 * Update the bucket's reference count according to how many 1011 * PTEs the caller has just invalidated. 1012 */ 1013 l2b->l2b_occupancy -= count; 1014 1015 /* 1016 * Note: 1017 * 1018 * Level 2 page tables allocated to the kernel pmap are never freed 1019 * as that would require checking all Level 1 page tables and 1020 * removing any references to the Level 2 page table. See also the 1021 * comment elsewhere about never freeing bootstrap L2 descriptors. 1022 * 1023 * We make do with just invalidating the mapping in the L2 table. 1024 * 1025 * This isn't really a big deal in practice and, in fact, leads 1026 * to a performance win over time as we don't need to continually 1027 * alloc/free. 1028 */ 1029 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1030 return; 1031 1032 /* 1033 * There are no more valid mappings in this level 2 page table. 1034 * Go ahead and NULL-out the pointer in the bucket, then 1035 * free the page table. 1036 */ 1037 l1idx = l2b->l2b_l1idx; 1038 ptep = l2b->l2b_kva; 1039 l2b->l2b_kva = NULL; 1040 1041 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1042 1043 /* 1044 * If the L1 slot matches the pmap's domain 1045 * number, then invalidate it. 1046 */ 1047 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1048 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1049 *pl1pd = 0; 1050 PTE_SYNC(pl1pd); 1051 } 1052 1053 /* 1054 * Release the L2 descriptor table back to the pool cache. 1055 */ 1056#ifndef PMAP_INCLUDE_PTE_SYNC 1057 pmap_free_l2_ptp(ptep); 1058#else 1059 pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1060#endif 1061 1062 /* 1063 * Update the reference count in the associated l2_dtable 1064 */ 1065 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1066 if (--l2->l2_occupancy > 0) 1067 return; 1068 1069 /* 1070 * There are no more valid mappings in any of the Level 1 1071 * slots managed by this l2_dtable. Go ahead and NULL-out 1072 * the pointer in the parent pmap and free the l2_dtable. 1073 */ 1074 pm->pm_l2[L2_IDX(l1idx)] = NULL; 1075 pmap_free_l2_dtable(l2); 1076} 1077 1078/* 1079 * Pool cache constructors for L2 descriptor tables, metadata and pmap 1080 * structures. 1081 */ 1082static int 1083pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1084{ 1085#ifndef PMAP_INCLUDE_PTE_SYNC 1086 struct l2_bucket *l2b; 1087 pt_entry_t *ptep, pte; 1088#ifdef ARM_USE_SMALL_ALLOC 1089 pd_entry_t *pde; 1090#endif 1091 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1092 1093 /* 1094 * The mappings for these page tables were initially made using 1095 * pmap_kenter() by the pool subsystem. Therefore, the cache- 1096 * mode will not be right for page table mappings. To avoid 1097 * polluting the pmap_kenter() code with a special case for 1098 * page tables, we simply fix up the cache-mode here if it's not 1099 * correct. 1100 */ 1101#ifdef ARM_USE_SMALL_ALLOC 1102 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)]; 1103 if (!l1pte_section_p(*pde)) { 1104#endif 1105 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1106 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1107 pte = *ptep; 1108 1109 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1110 /* 1111 * Page tables must have the cache-mode set to 1112 * Write-Thru. 1113 */ 1114 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1115 PTE_SYNC(ptep); 1116 cpu_tlb_flushD_SE(va); 1117 cpu_cpwait(); 1118 } 1119 1120#ifdef ARM_USE_SMALL_ALLOC 1121 } 1122#endif 1123#endif 1124 memset(mem, 0, L2_TABLE_SIZE_REAL); 1125 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1126 return (0); 1127} 1128 1129/* 1130 * A bunch of routines to conditionally flush the caches/TLB depending 1131 * on whether the specified pmap actually needs to be flushed at any 1132 * given time. 1133 */ 1134static PMAP_INLINE void 1135pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1136{ 1137 1138 if (pmap_is_current(pm)) 1139 cpu_tlb_flushID_SE(va); 1140} 1141 1142static PMAP_INLINE void 1143pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1144{ 1145 1146 if (pmap_is_current(pm)) 1147 cpu_tlb_flushD_SE(va); 1148} 1149 1150static PMAP_INLINE void 1151pmap_tlb_flushID(pmap_t pm) 1152{ 1153 1154 if (pmap_is_current(pm)) 1155 cpu_tlb_flushID(); 1156} 1157static PMAP_INLINE void 1158pmap_tlb_flushD(pmap_t pm) 1159{ 1160 1161 if (pmap_is_current(pm)) 1162 cpu_tlb_flushD(); 1163} 1164 1165static PMAP_INLINE void 1166pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1167{ 1168 1169 if (pmap_is_current(pm)) 1170 cpu_idcache_wbinv_range(va, len); 1171} 1172 1173static PMAP_INLINE void 1174pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, 1175 boolean_t do_inv, boolean_t rd_only) 1176{ 1177 1178 if (pmap_is_current(pm)) { 1179 if (do_inv) { 1180 if (rd_only) 1181 cpu_dcache_inv_range(va, len); 1182 else 1183 cpu_dcache_wbinv_range(va, len); 1184 } else 1185 if (!rd_only) 1186 cpu_dcache_wb_range(va, len); 1187 } 1188} 1189 1190static PMAP_INLINE void 1191pmap_idcache_wbinv_all(pmap_t pm) 1192{ 1193 1194 if (pmap_is_current(pm)) 1195 cpu_idcache_wbinv_all(); 1196} 1197 1198static PMAP_INLINE void 1199pmap_dcache_wbinv_all(pmap_t pm) 1200{ 1201 1202 if (pmap_is_current(pm)) 1203 cpu_dcache_wbinv_all(); 1204} 1205 1206/* 1207 * PTE_SYNC_CURRENT: 1208 * 1209 * Make sure the pte is written out to RAM. 1210 * We need to do this for one of two cases: 1211 * - We're dealing with the kernel pmap 1212 * - There is no pmap active in the cache/tlb. 1213 * - The specified pmap is 'active' in the cache/tlb. 1214 */ 1215#ifdef PMAP_INCLUDE_PTE_SYNC 1216#define PTE_SYNC_CURRENT(pm, ptep) \ 1217do { \ 1218 if (PMAP_NEEDS_PTE_SYNC && \ 1219 pmap_is_current(pm)) \ 1220 PTE_SYNC(ptep); \ 1221} while (/*CONSTCOND*/0) 1222#else 1223#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1224#endif 1225 1226/* 1227 * Since we have a virtually indexed cache, we may need to inhibit caching if 1228 * there is more than one mapping and at least one of them is writable. 1229 * Since we purge the cache on every context switch, we only need to check for 1230 * other mappings within the same pmap, or kernel_pmap. 1231 * This function is also called when a page is unmapped, to possibly reenable 1232 * caching on any remaining mappings. 1233 * 1234 * The code implements the following logic, where: 1235 * 1236 * KW = # of kernel read/write pages 1237 * KR = # of kernel read only pages 1238 * UW = # of user read/write pages 1239 * UR = # of user read only pages 1240 * 1241 * KC = kernel mapping is cacheable 1242 * UC = user mapping is cacheable 1243 * 1244 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1245 * +--------------------------------------------- 1246 * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1247 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1248 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1249 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1250 */ 1251 1252static const int pmap_vac_flags[4][4] = { 1253 {-1, 0, 0, PVF_KNC}, 1254 {0, 0, PVF_NC, PVF_NC}, 1255 {0, PVF_NC, PVF_NC, PVF_NC}, 1256 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1257}; 1258 1259static PMAP_INLINE int 1260pmap_get_vac_flags(const struct vm_page *pg) 1261{ 1262 int kidx, uidx; 1263 1264 kidx = 0; 1265 if (pg->md.kro_mappings || pg->md.krw_mappings > 1) 1266 kidx |= 1; 1267 if (pg->md.krw_mappings) 1268 kidx |= 2; 1269 1270 uidx = 0; 1271 if (pg->md.uro_mappings || pg->md.urw_mappings > 1) 1272 uidx |= 1; 1273 if (pg->md.urw_mappings) 1274 uidx |= 2; 1275 1276 return (pmap_vac_flags[uidx][kidx]); 1277} 1278 1279static __inline void 1280pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1281{ 1282 int nattr; 1283 1284 nattr = pmap_get_vac_flags(pg); 1285 1286 if (nattr < 0) { 1287 pg->md.pvh_attrs &= ~PVF_NC; 1288 return; 1289 } 1290 1291 if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) { 1292 return; 1293 } 1294 1295 if (pm == pmap_kernel()) 1296 pmap_vac_me_kpmap(pg, pm, va); 1297 else 1298 pmap_vac_me_user(pg, pm, va); 1299 1300 pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr; 1301} 1302 1303static void 1304pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1305{ 1306 u_int u_cacheable, u_entries; 1307 struct pv_entry *pv; 1308 pmap_t last_pmap = pm; 1309 1310 /* 1311 * Pass one, see if there are both kernel and user pmaps for 1312 * this page. Calculate whether there are user-writable or 1313 * kernel-writable pages. 1314 */ 1315 u_cacheable = 0; 1316 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1317 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1318 u_cacheable++; 1319 } 1320 1321 u_entries = pg->md.urw_mappings + pg->md.uro_mappings; 1322 1323 /* 1324 * We know we have just been updating a kernel entry, so if 1325 * all user pages are already cacheable, then there is nothing 1326 * further to do. 1327 */ 1328 if (pg->md.k_mappings == 0 && u_cacheable == u_entries) 1329 return; 1330 1331 if (u_entries) { 1332 /* 1333 * Scan over the list again, for each entry, if it 1334 * might not be set correctly, call pmap_vac_me_user 1335 * to recalculate the settings. 1336 */ 1337 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1338 /* 1339 * We know kernel mappings will get set 1340 * correctly in other calls. We also know 1341 * that if the pmap is the same as last_pmap 1342 * then we've just handled this entry. 1343 */ 1344 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1345 continue; 1346 1347 /* 1348 * If there are kernel entries and this page 1349 * is writable but non-cacheable, then we can 1350 * skip this entry also. 1351 */ 1352 if (pg->md.k_mappings && 1353 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1354 (PVF_NC | PVF_WRITE)) 1355 continue; 1356 1357 /* 1358 * Similarly if there are no kernel-writable 1359 * entries and the page is already 1360 * read-only/cacheable. 1361 */ 1362 if (pg->md.krw_mappings == 0 && 1363 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1364 continue; 1365 1366 /* 1367 * For some of the remaining cases, we know 1368 * that we must recalculate, but for others we 1369 * can't tell if they are correct or not, so 1370 * we recalculate anyway. 1371 */ 1372 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1373 } 1374 1375 if (pg->md.k_mappings == 0) 1376 return; 1377 } 1378 1379 pmap_vac_me_user(pg, pm, va); 1380} 1381 1382static void 1383pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1384{ 1385 pmap_t kpmap = pmap_kernel(); 1386 struct pv_entry *pv, *npv; 1387 struct l2_bucket *l2b; 1388 pt_entry_t *ptep, pte; 1389 u_int entries = 0; 1390 u_int writable = 0; 1391 u_int cacheable_entries = 0; 1392 u_int kern_cacheable = 0; 1393 u_int other_writable = 0; 1394 1395 /* 1396 * Count mappings and writable mappings in this pmap. 1397 * Include kernel mappings as part of our own. 1398 * Keep a pointer to the first one. 1399 */ 1400 npv = TAILQ_FIRST(&pg->md.pv_list); 1401 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1402 /* Count mappings in the same pmap */ 1403 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1404 if (entries++ == 0) 1405 npv = pv; 1406 1407 /* Cacheable mappings */ 1408 if ((pv->pv_flags & PVF_NC) == 0) { 1409 cacheable_entries++; 1410 if (kpmap == pv->pv_pmap) 1411 kern_cacheable++; 1412 } 1413 1414 /* Writable mappings */ 1415 if (pv->pv_flags & PVF_WRITE) 1416 ++writable; 1417 } else 1418 if (pv->pv_flags & PVF_WRITE) 1419 other_writable = 1; 1420 } 1421 1422 /* 1423 * Enable or disable caching as necessary. 1424 * Note: the first entry might be part of the kernel pmap, 1425 * so we can't assume this is indicative of the state of the 1426 * other (maybe non-kpmap) entries. 1427 */ 1428 if ((entries > 1 && writable) || 1429 (entries > 0 && pm == kpmap && other_writable)) { 1430 if (cacheable_entries == 0) 1431 return; 1432 1433 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1434 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1435 (pv->pv_flags & PVF_NC)) 1436 continue; 1437 1438 pv->pv_flags |= PVF_NC; 1439 1440 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1441 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1442 pte = *ptep & ~L2_S_CACHE_MASK; 1443 1444 if ((va != pv->pv_va || pm != pv->pv_pmap) && 1445 l2pte_valid(pte)) { 1446 if (PV_BEEN_EXECD(pv->pv_flags)) { 1447 pmap_idcache_wbinv_range(pv->pv_pmap, 1448 pv->pv_va, PAGE_SIZE); 1449 pmap_tlb_flushID_SE(pv->pv_pmap, 1450 pv->pv_va); 1451 } else 1452 if (PV_BEEN_REFD(pv->pv_flags)) { 1453 pmap_dcache_wb_range(pv->pv_pmap, 1454 pv->pv_va, PAGE_SIZE, TRUE, 1455 (pv->pv_flags & PVF_WRITE) == 0); 1456 pmap_tlb_flushD_SE(pv->pv_pmap, 1457 pv->pv_va); 1458 } 1459 } 1460 1461 *ptep = pte; 1462 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1463 } 1464 cpu_cpwait(); 1465 } else 1466 if (entries > cacheable_entries) { 1467 /* 1468 * Turn cacheing back on for some pages. If it is a kernel 1469 * page, only do so if there are no other writable pages. 1470 */ 1471 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1472 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1473 (kpmap != pv->pv_pmap || other_writable))) 1474 continue; 1475 1476 pv->pv_flags &= ~PVF_NC; 1477 1478 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1479 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1480 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1481 1482 if (l2pte_valid(pte)) { 1483 if (PV_BEEN_EXECD(pv->pv_flags)) { 1484 pmap_tlb_flushID_SE(pv->pv_pmap, 1485 pv->pv_va); 1486 } else 1487 if (PV_BEEN_REFD(pv->pv_flags)) { 1488 pmap_tlb_flushD_SE(pv->pv_pmap, 1489 pv->pv_va); 1490 } 1491 } 1492 1493 *ptep = pte; 1494 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1495 } 1496 } 1497} 1498 1499/* 1500 * Modify pte bits for all ptes corresponding to the given physical address. 1501 * We use `maskbits' rather than `clearbits' because we're always passing 1502 * constants and the latter would require an extra inversion at run-time. 1503 */ 1504static int 1505pmap_clearbit(struct vm_page *pg, u_int maskbits) 1506{ 1507 struct l2_bucket *l2b; 1508 struct pv_entry *pv; 1509 pt_entry_t *ptep, npte, opte; 1510 pmap_t pm; 1511 vm_offset_t va; 1512 u_int oflags; 1513 int count = 0; 1514#if 0 1515 PMAP_HEAD_TO_MAP_LOCK(); 1516 simple_lock(&pg->mdpage.pvh_slock); 1517#endif 1518 1519 /* 1520 * Clear saved attributes (modify, reference) 1521 */ 1522 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1523 1524 if (TAILQ_EMPTY(&pg->md.pv_list)) { 1525#if 0 1526 simple_unlock(&pg->mdpage.pvh_slock); 1527 PMAP_HEAD_TO_MAP_UNLOCK(); 1528#endif 1529 return (0); 1530 } 1531 1532 /* 1533 * Loop over all current mappings setting/clearing as appropos 1534 */ 1535 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1536 va = pv->pv_va; 1537 pm = pv->pv_pmap; 1538 oflags = pv->pv_flags; 1539 pv->pv_flags &= ~maskbits; 1540 1541#if 0 1542 pmap_acquire_pmap_lock(pm); 1543#endif 1544 1545 l2b = pmap_get_l2_bucket(pm, va); 1546 1547 ptep = &l2b->l2b_kva[l2pte_index(va)]; 1548 npte = opte = *ptep; 1549 1550 if (maskbits & (PVF_WRITE|PVF_MOD)) { 1551 if ((pv->pv_flags & PVF_NC)) { 1552 /* 1553 * Entry is not cacheable: 1554 * 1555 * Don't turn caching on again if this is a 1556 * modified emulation. This would be 1557 * inconsitent with the settings created by 1558 * pmap_vac_me_harder(). Otherwise, it's safe 1559 * to re-enable cacheing. 1560 * 1561 * There's no need to call pmap_vac_me_harder() 1562 * here: all pages are losing their write 1563 * permission. 1564 */ 1565 if (maskbits & PVF_WRITE) { 1566 npte |= pte_l2_s_cache_mode; 1567 pv->pv_flags &= ~PVF_NC; 1568 } 1569 } else 1570 if (opte & L2_S_PROT_W) { 1571 vm_page_dirty(pg); 1572 /* 1573 * Entry is writable/cacheable: check if pmap 1574 * is current if it is flush it, otherwise it 1575 * won't be in the cache 1576 */ 1577 if (PV_BEEN_EXECD(oflags)) 1578 pmap_idcache_wbinv_range(pm, pv->pv_va, 1579 PAGE_SIZE); 1580 else 1581 if (PV_BEEN_REFD(oflags)) 1582 pmap_dcache_wb_range(pm, pv->pv_va, 1583 PAGE_SIZE, 1584 (maskbits & PVF_REF) ? TRUE : FALSE, 1585 FALSE); 1586 } 1587 1588 /* make the pte read only */ 1589 npte &= ~L2_S_PROT_W; 1590 1591 if (maskbits & PVF_WRITE) { 1592 /* 1593 * Keep alias accounting up to date 1594 */ 1595 if (pv->pv_pmap == pmap_kernel()) { 1596 if (oflags & PVF_WRITE) { 1597 pg->md.krw_mappings--; 1598 pg->md.kro_mappings++; 1599 } 1600 } else 1601 if (oflags & PVF_WRITE) { 1602 pg->md.urw_mappings--; 1603 pg->md.uro_mappings++; 1604 } 1605 } 1606 } 1607 1608 if (maskbits & PVF_REF) { 1609 if ((pv->pv_flags & PVF_NC) == 0 && 1610 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1611 /* 1612 * Check npte here; we may have already 1613 * done the wbinv above, and the validity 1614 * of the PTE is the same for opte and 1615 * npte. 1616 */ 1617 if (npte & L2_S_PROT_W) { 1618 if (PV_BEEN_EXECD(oflags)) 1619 pmap_idcache_wbinv_range(pm, 1620 pv->pv_va, PAGE_SIZE); 1621 else 1622 if (PV_BEEN_REFD(oflags)) 1623 pmap_dcache_wb_range(pm, 1624 pv->pv_va, PAGE_SIZE, 1625 TRUE, FALSE); 1626 } else 1627 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1628 /* XXXJRT need idcache_inv_range */ 1629 if (PV_BEEN_EXECD(oflags)) 1630 pmap_idcache_wbinv_range(pm, 1631 pv->pv_va, PAGE_SIZE); 1632 else 1633 if (PV_BEEN_REFD(oflags)) 1634 pmap_dcache_wb_range(pm, 1635 pv->pv_va, PAGE_SIZE, 1636 TRUE, TRUE); 1637 } 1638 } 1639 1640 /* 1641 * Make the PTE invalid so that we will take a 1642 * page fault the next time the mapping is 1643 * referenced. 1644 */ 1645 npte &= ~L2_TYPE_MASK; 1646 npte |= L2_TYPE_INV; 1647 } 1648 1649 if (npte != opte) { 1650 count++; 1651 *ptep = npte; 1652 PTE_SYNC(ptep); 1653 /* Flush the TLB entry if a current pmap. */ 1654 if (PV_BEEN_EXECD(oflags)) 1655 pmap_tlb_flushID_SE(pm, pv->pv_va); 1656 else 1657 if (PV_BEEN_REFD(oflags)) 1658 pmap_tlb_flushD_SE(pm, pv->pv_va); 1659 } 1660 1661#if 0 1662 pmap_release_pmap_lock(pm); 1663#endif 1664 1665 } 1666 1667#if 0 1668 simple_unlock(&pg->mdpage.pvh_slock); 1669 PMAP_HEAD_TO_MAP_UNLOCK(); 1670#endif 1671 if (maskbits & PVF_WRITE) 1672 vm_page_flag_clear(pg, PG_WRITEABLE); 1673 return (count); 1674} 1675 1676/* 1677 * main pv_entry manipulation functions: 1678 * pmap_enter_pv: enter a mapping onto a vm_page list 1679 * pmap_remove_pv: remove a mappiing from a vm_page list 1680 * 1681 * NOTE: pmap_enter_pv expects to lock the pvh itself 1682 * pmap_remove_pv expects te caller to lock the pvh before calling 1683 */ 1684 1685/* 1686 * pmap_enter_pv: enter a mapping onto a vm_page lst 1687 * 1688 * => caller should hold the proper lock on pmap_main_lock 1689 * => caller should have pmap locked 1690 * => we will gain the lock on the vm_page and allocate the new pv_entry 1691 * => caller should adjust ptp's wire_count before calling 1692 * => caller should not adjust pmap's wire_count 1693 */ 1694static void 1695pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1696 vm_offset_t va, u_int flags) 1697{ 1698 1699 1700 pve->pv_pmap = pm; 1701 pve->pv_va = va; 1702 pve->pv_flags = flags; 1703 1704#if 0 1705 mtx_lock(&pg->md.pvh_mtx); 1706#endif 1707 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1708 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1709 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1710 if (pm == pmap_kernel()) { 1711 if (flags & PVF_WRITE) 1712 pg->md.krw_mappings++; 1713 else 1714 pg->md.kro_mappings++; 1715 } 1716 if (flags & PVF_WRITE) 1717 pg->md.urw_mappings++; 1718 else 1719 pg->md.uro_mappings++; 1720 pg->md.pv_list_count++; 1721#if 0 1722 mtx_unlock(&pg->md.pvh_mtx); 1723#endif 1724 if (pve->pv_flags & PVF_WIRED) 1725 ++pm->pm_stats.wired_count; 1726 vm_page_flag_set(pg, PG_REFERENCED); 1727} 1728 1729/* 1730 * 1731 * pmap_find_pv: Find a pv entry 1732 * 1733 * => caller should hold lock on vm_page 1734 */ 1735static PMAP_INLINE struct pv_entry * 1736pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1737{ 1738 struct pv_entry *pv; 1739 1740 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1741 if (pm == pv->pv_pmap && va == pv->pv_va) 1742 break; 1743 return (pv); 1744} 1745 1746/* 1747 * vector_page_setprot: 1748 * 1749 * Manipulate the protection of the vector page. 1750 */ 1751void 1752vector_page_setprot(int prot) 1753{ 1754 struct l2_bucket *l2b; 1755 pt_entry_t *ptep; 1756 1757 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1758 1759 ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1760 1761 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1762 PTE_SYNC(ptep); 1763 cpu_tlb_flushD_SE(vector_page); 1764 cpu_cpwait(); 1765} 1766 1767/* 1768 * pmap_remove_pv: try to remove a mapping from a pv_list 1769 * 1770 * => caller should hold proper lock on pmap_main_lock 1771 * => pmap should be locked 1772 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1773 * => caller should adjust ptp's wire_count and free PTP if needed 1774 * => caller should NOT adjust pmap's wire_count 1775 * => we return the removed pve 1776 */ 1777 1778static void 1779pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1780{ 1781 1782 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1783 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1784 if (pve->pv_flags & PVF_WIRED) 1785 --pm->pm_stats.wired_count; 1786 pg->md.pv_list_count--; 1787 if (pg->md.pvh_attrs & PVF_MOD) 1788 vm_page_dirty(pg); 1789 if (pm == pmap_kernel()) { 1790 if (pve->pv_flags & PVF_WRITE) 1791 pg->md.krw_mappings--; 1792 else 1793 pg->md.kro_mappings--; 1794 } else 1795 if (pve->pv_flags & PVF_WRITE) 1796 pg->md.urw_mappings--; 1797 else 1798 pg->md.uro_mappings--; 1799 if (TAILQ_FIRST(&pg->md.pv_list) == NULL || 1800 (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) { 1801 pg->md.pvh_attrs &= ~PVF_MOD; 1802 if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1803 pg->md.pvh_attrs &= ~PVF_REF; 1804 vm_page_flag_clear(pg, PG_WRITEABLE); 1805 } 1806 if (TAILQ_FIRST(&pg->md.pv_list)) 1807 vm_page_flag_set(pg, PG_REFERENCED); 1808 if (pve->pv_flags & PVF_WRITE) 1809 pmap_vac_me_harder(pg, pm, 0); 1810} 1811 1812static struct pv_entry * 1813pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1814{ 1815 struct pv_entry *pve; 1816 1817 pve = TAILQ_FIRST(&pg->md.pv_list); 1818 1819 while (pve) { 1820 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1821 pmap_nuke_pv(pg, pm, pve); 1822 break; 1823 } 1824 pve = TAILQ_NEXT(pve, pv_list); 1825 } 1826 1827 return(pve); /* return removed pve */ 1828} 1829/* 1830 * 1831 * pmap_modify_pv: Update pv flags 1832 * 1833 * => caller should hold lock on vm_page [so that attrs can be adjusted] 1834 * => caller should NOT adjust pmap's wire_count 1835 * => caller must call pmap_vac_me_harder() if writable status of a page 1836 * may have changed. 1837 * => we return the old flags 1838 * 1839 * Modify a physical-virtual mapping in the pv table 1840 */ 1841static u_int 1842pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1843 u_int clr_mask, u_int set_mask) 1844{ 1845 struct pv_entry *npv; 1846 u_int flags, oflags; 1847 1848 if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1849 return (0); 1850 1851 /* 1852 * There is at least one VA mapping this page. 1853 */ 1854 1855 if (clr_mask & (PVF_REF | PVF_MOD)) 1856 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1857 1858 oflags = npv->pv_flags; 1859 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1860 1861 if ((flags ^ oflags) & PVF_WIRED) { 1862 if (flags & PVF_WIRED) 1863 ++pm->pm_stats.wired_count; 1864 else 1865 --pm->pm_stats.wired_count; 1866 } 1867 1868 if ((flags ^ oflags) & PVF_WRITE) { 1869 if (pm == pmap_kernel()) { 1870 if (flags & PVF_WRITE) { 1871 pg->md.krw_mappings++; 1872 pg->md.kro_mappings--; 1873 } else { 1874 pg->md.kro_mappings++; 1875 pg->md.krw_mappings--; 1876 } 1877 } else 1878 if (flags & PVF_WRITE) { 1879 pg->md.urw_mappings++; 1880 pg->md.uro_mappings--; 1881 } else { 1882 pg->md.uro_mappings++; 1883 pg->md.urw_mappings--; 1884 } 1885 if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) { 1886 pg->md.pvh_attrs &= ~PVF_MOD; 1887 vm_page_flag_clear(pg, PG_WRITEABLE); 1888 } 1889 pmap_vac_me_harder(pg, pm, 0); 1890 } 1891 1892 return (oflags); 1893} 1894 1895/* Function to set the debug level of the pmap code */ 1896#ifdef PMAP_DEBUG 1897void 1898pmap_debug(int level) 1899{ 1900 pmap_debug_level = level; 1901 dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1902} 1903#endif /* PMAP_DEBUG */ 1904 1905void 1906pmap_pinit0(struct pmap *pmap) 1907{ 1908 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1909 1910 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1911 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1912 bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1913} 1914 1915/* 1916 * Initialize a vm_page's machine-dependent fields. 1917 */ 1918void 1919pmap_page_init(vm_page_t m) 1920{ 1921 1922 TAILQ_INIT(&m->md.pv_list); 1923 m->md.pv_list_count = 0; 1924} 1925 1926/* 1927 * Initialize the pmap module. 1928 * Called by vm_init, to initialize any structures that the pmap 1929 * system needs to map virtual memory. 1930 */ 1931void 1932pmap_init(void) 1933{ 1934 int shpgperproc = PMAP_SHPGPERPROC; 1935 1936 PDEBUG(1, printf("pmap_init: phys_start = %08x\n")); 1937 1938 /* 1939 * init the pv free list 1940 */ 1941 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1942 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1943 /* 1944 * Now it is safe to enable pv_table recording. 1945 */ 1946 PDEBUG(1, printf("pmap_init: done!\n")); 1947 1948 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1949 1950 pv_entry_max = shpgperproc * maxproc + vm_page_array_size; 1951 pv_entry_high_water = 9 * (pv_entry_max / 10); 1952 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1953 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1954 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 1955 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1956 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1957 1958 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1959 uma_zone_set_obj(l2zone, &l2zone_obj, pv_entry_max); 1960 1961} 1962 1963int 1964pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1965{ 1966 struct l2_dtable *l2; 1967 struct l2_bucket *l2b; 1968 pd_entry_t *pl1pd, l1pd; 1969 pt_entry_t *ptep, pte; 1970 vm_paddr_t pa; 1971 u_int l1idx; 1972 int rv = 0; 1973 1974#if 0 1975 PMAP_MAP_TO_HEAD_LOCK(); 1976 pmap_acquire_pmap_lock(pm); 1977#endif 1978 l1idx = L1_IDX(va); 1979 1980 /* 1981 * If there is no l2_dtable for this address, then the process 1982 * has no business accessing it. 1983 * 1984 * Note: This will catch userland processes trying to access 1985 * kernel addresses. 1986 */ 1987 l2 = pm->pm_l2[L2_IDX(l1idx)]; 1988 if (l2 == NULL) 1989 goto out; 1990 1991 /* 1992 * Likewise if there is no L2 descriptor table 1993 */ 1994 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1995 if (l2b->l2b_kva == NULL) 1996 goto out; 1997 1998 /* 1999 * Check the PTE itself. 2000 */ 2001 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2002 pte = *ptep; 2003 if (pte == 0) 2004 goto out; 2005 2006 /* 2007 * Catch a userland access to the vector page mapped at 0x0 2008 */ 2009 if (user && (pte & L2_S_PROT_U) == 0) 2010 goto out; 2011 if (va == vector_page) 2012 goto out; 2013 2014 pa = l2pte_pa(pte); 2015 2016 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 2017 /* 2018 * This looks like a good candidate for "page modified" 2019 * emulation... 2020 */ 2021 struct pv_entry *pv; 2022 struct vm_page *pg; 2023 2024 /* Extract the physical address of the page */ 2025 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 2026 goto out; 2027 } 2028 /* Get the current flags for this page. */ 2029 2030 pv = pmap_find_pv(pg, pm, va); 2031 if (pv == NULL) { 2032 goto out; 2033 } 2034 2035 /* 2036 * Do the flags say this page is writable? If not then it 2037 * is a genuine write fault. If yes then the write fault is 2038 * our fault as we did not reflect the write access in the 2039 * PTE. Now we know a write has occurred we can correct this 2040 * and also set the modified bit 2041 */ 2042 if ((pv->pv_flags & PVF_WRITE) == 0) { 2043 goto out; 2044 } 2045 2046 pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 2047 vm_page_dirty(pg); 2048 pv->pv_flags |= PVF_REF | PVF_MOD; 2049 2050 /* 2051 * Re-enable write permissions for the page. No need to call 2052 * pmap_vac_me_harder(), since this is just a 2053 * modified-emulation fault, and the PVF_WRITE bit isn't 2054 * changing. We've already set the cacheable bits based on 2055 * the assumption that we can write to this page. 2056 */ 2057 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 2058 PTE_SYNC(ptep); 2059 rv = 1; 2060 } else 2061 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2062 /* 2063 * This looks like a good candidate for "page referenced" 2064 * emulation. 2065 */ 2066 struct pv_entry *pv; 2067 struct vm_page *pg; 2068 2069 /* Extract the physical address of the page */ 2070 vm_page_lock_queues(); 2071 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 2072 vm_page_unlock_queues(); 2073 goto out; 2074 } 2075 /* Get the current flags for this page. */ 2076 2077 pv = pmap_find_pv(pg, pm, va); 2078 if (pv == NULL) { 2079 vm_page_unlock_queues(); 2080 goto out; 2081 } 2082 2083 pg->md.pvh_attrs |= PVF_REF; 2084 pv->pv_flags |= PVF_REF; 2085 2086 2087 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2088 PTE_SYNC(ptep); 2089 rv = 1; 2090 vm_page_unlock_queues(); 2091 } 2092 2093 /* 2094 * We know there is a valid mapping here, so simply 2095 * fix up the L1 if necessary. 2096 */ 2097 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2098 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2099 if (*pl1pd != l1pd) { 2100 *pl1pd = l1pd; 2101 PTE_SYNC(pl1pd); 2102 rv = 1; 2103 } 2104 2105#ifdef CPU_SA110 2106 /* 2107 * There are bugs in the rev K SA110. This is a check for one 2108 * of them. 2109 */ 2110 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2111 curcpu()->ci_arm_cpurev < 3) { 2112 /* Always current pmap */ 2113 if (l2pte_valid(pte)) { 2114 extern int kernel_debug; 2115 if (kernel_debug & 1) { 2116 struct proc *p = curlwp->l_proc; 2117 printf("prefetch_abort: page is already " 2118 "mapped - pte=%p *pte=%08x\n", ptep, pte); 2119 printf("prefetch_abort: pc=%08lx proc=%p " 2120 "process=%s\n", va, p, p->p_comm); 2121 printf("prefetch_abort: far=%08x fs=%x\n", 2122 cpu_faultaddress(), cpu_faultstatus()); 2123 } 2124#ifdef DDB 2125 if (kernel_debug & 2) 2126 Debugger(); 2127#endif 2128 rv = 1; 2129 } 2130 } 2131#endif /* CPU_SA110 */ 2132 2133#ifdef DEBUG 2134 /* 2135 * If 'rv == 0' at this point, it generally indicates that there is a 2136 * stale TLB entry for the faulting address. This happens when two or 2137 * more processes are sharing an L1. Since we don't flush the TLB on 2138 * a context switch between such processes, we can take domain faults 2139 * for mappings which exist at the same VA in both processes. EVEN IF 2140 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2141 * example. 2142 * 2143 * This is extremely likely to happen if pmap_enter() updated the L1 2144 * entry for a recently entered mapping. In this case, the TLB is 2145 * flushed for the new mapping, but there may still be TLB entries for 2146 * other mappings belonging to other processes in the 1MB range 2147 * covered by the L1 entry. 2148 * 2149 * Since 'rv == 0', we know that the L1 already contains the correct 2150 * value, so the fault must be due to a stale TLB entry. 2151 * 2152 * Since we always need to flush the TLB anyway in the case where we 2153 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2154 * stale TLB entries dynamically. 2155 * 2156 * However, the above condition can ONLY happen if the current L1 is 2157 * being shared. If it happens when the L1 is unshared, it indicates 2158 * that other parts of the pmap are not doing their job WRT managing 2159 * the TLB. 2160 */ 2161 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2162 extern int last_fault_code; 2163 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2164 pm, va, ftype); 2165 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2166 l2, l2b, ptep, pl1pd); 2167 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2168 pte, l1pd, last_fault_code); 2169#ifdef DDB 2170 Debugger(); 2171#endif 2172 } 2173#endif 2174 2175 cpu_tlb_flushID_SE(va); 2176 cpu_cpwait(); 2177 2178 rv = 1; 2179 2180out: 2181#if 0 2182 pmap_release_pmap_lock(pm); 2183 PMAP_MAP_TO_HEAD_UNLOCK(); 2184#endif 2185 return (rv); 2186} 2187 2188void 2189pmap_postinit(void) 2190{ 2191 struct l2_bucket *l2b; 2192 struct l1_ttable *l1; 2193 pd_entry_t *pl1pt; 2194 pt_entry_t *ptep, pte; 2195 vm_offset_t va, eva; 2196 u_int loop, needed; 2197 2198 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2199 needed -= 1; 2200 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2201 2202 for (loop = 0; loop < needed; loop++, l1++) { 2203 /* Allocate a L1 page table */ 2204 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2205 0xffffffff, L1_TABLE_SIZE, 0); 2206 2207 if (va == 0) 2208 panic("Cannot allocate L1 KVM"); 2209 2210 eva = va + L1_TABLE_SIZE; 2211 pl1pt = (pd_entry_t *)va; 2212 2213 while (va < eva) { 2214 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2215 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2216 pte = *ptep; 2217 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2218 *ptep = pte; 2219 PTE_SYNC(ptep); 2220 cpu_tlb_flushD_SE(va); 2221 2222 va += PAGE_SIZE; 2223 } 2224 pmap_init_l1(l1, pl1pt); 2225 } 2226 2227 2228#ifdef DEBUG 2229 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2230 needed); 2231#endif 2232} 2233 2234/* 2235 * This is used to stuff certain critical values into the PCB where they 2236 * can be accessed quickly from cpu_switch() et al. 2237 */ 2238void 2239pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2240{ 2241 struct l2_bucket *l2b; 2242 2243 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2244 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2245 (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2246 2247 if (vector_page < KERNBASE) { 2248 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2249 l2b = pmap_get_l2_bucket(pm, vector_page); 2250 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2251 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2252 } else 2253 pcb->pcb_pl1vec = NULL; 2254} 2255 2256void 2257pmap_activate(struct thread *td) 2258{ 2259 pmap_t pm; 2260 struct pcb *pcb; 2261 int s; 2262 2263 pm = vmspace_pmap(td->td_proc->p_vmspace); 2264 pcb = td->td_pcb; 2265 2266 critical_enter(); 2267 pmap_set_pcb_pagedir(pm, pcb); 2268 2269 if (td == curthread) { 2270 u_int cur_dacr, cur_ttb; 2271 2272 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2273 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2274 2275 cur_ttb &= ~(L1_TABLE_SIZE - 1); 2276 2277 if (cur_ttb == (u_int)pcb->pcb_pagedir && 2278 cur_dacr == pcb->pcb_dacr) { 2279 /* 2280 * No need to switch address spaces. 2281 */ 2282 critical_exit(); 2283 return; 2284 } 2285 2286 2287 /* 2288 * We MUST, I repeat, MUST fix up the L1 entry corresponding 2289 * to 'vector_page' in the incoming L1 table before switching 2290 * to it otherwise subsequent interrupts/exceptions (including 2291 * domain faults!) will jump into hyperspace. 2292 */ 2293 if (pcb->pcb_pl1vec) { 2294 2295 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2296 /* 2297 * Don't need to PTE_SYNC() at this point since 2298 * cpu_setttb() is about to flush both the cache 2299 * and the TLB. 2300 */ 2301 } 2302 2303 cpu_domains(pcb->pcb_dacr); 2304 cpu_setttb(pcb->pcb_pagedir); 2305 2306 splx(s); 2307 } 2308 critical_exit(); 2309} 2310 2311static int 2312pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2313{ 2314 pd_entry_t *pdep, pde; 2315 pt_entry_t *ptep, pte; 2316 vm_offset_t pa; 2317 int rv = 0; 2318 2319 /* 2320 * Make sure the descriptor itself has the correct cache mode 2321 */ 2322 pdep = &kl1[L1_IDX(va)]; 2323 pde = *pdep; 2324 2325 if (l1pte_section_p(pde)) { 2326 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2327 *pdep = (pde & ~L1_S_CACHE_MASK) | 2328 pte_l1_s_cache_mode_pt; 2329 PTE_SYNC(pdep); 2330 cpu_dcache_wbinv_range((vm_offset_t)pdep, 2331 sizeof(*pdep)); 2332 rv = 1; 2333 } 2334 } else { 2335 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2336 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2337 if (ptep == NULL) 2338 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2339 2340 ptep = &ptep[l2pte_index(va)]; 2341 pte = *ptep; 2342 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2343 *ptep = (pte & ~L2_S_CACHE_MASK) | 2344 pte_l2_s_cache_mode_pt; 2345 PTE_SYNC(ptep); 2346 cpu_dcache_wbinv_range((vm_offset_t)ptep, 2347 sizeof(*ptep)); 2348 rv = 1; 2349 } 2350 } 2351 2352 return (rv); 2353} 2354 2355static void 2356pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2357 pt_entry_t **ptep) 2358{ 2359 vm_offset_t va = *availp; 2360 struct l2_bucket *l2b; 2361 2362 if (ptep) { 2363 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2364 if (l2b == NULL) 2365 panic("pmap_alloc_specials: no l2b for 0x%x", va); 2366 2367 *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2368 } 2369 2370 *vap = va; 2371 *availp = va + (PAGE_SIZE * pages); 2372} 2373 2374/* 2375 * Bootstrap the system enough to run with virtual memory. 2376 * 2377 * On the arm this is called after mapping has already been enabled 2378 * and just syncs the pmap module with what has already been done. 2379 * [We can't call it easily with mapping off since the kernel is not 2380 * mapped with PA == VA, hence we would have to relocate every address 2381 * from the linked base (virtual) address "KERNBASE" to the actual 2382 * (physical) address starting relative to 0] 2383 */ 2384#define PMAP_STATIC_L2_SIZE 16 2385#ifdef ARM_USE_SMALL_ALLOC 2386extern struct mtx smallalloc_mtx; 2387extern vm_offset_t alloc_curaddr; 2388extern vm_offset_t alloc_firstaddr; 2389#endif 2390 2391void 2392pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2393{ 2394 static struct l1_ttable static_l1; 2395 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2396 struct l1_ttable *l1 = &static_l1; 2397 struct l2_dtable *l2; 2398 struct l2_bucket *l2b; 2399 pd_entry_t pde; 2400 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2401 pt_entry_t *ptep; 2402 vm_paddr_t pa; 2403 vm_offset_t va; 2404 vm_size_t size; 2405 int l1idx, l2idx, l2next = 0; 2406 2407 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n", 2408 firstaddr, loadaddr)); 2409 2410 virtual_avail = firstaddr; 2411 kernel_pmap = &kernel_pmap_store; 2412 kernel_pmap->pm_l1 = l1; 2413 kernel_l1pa = l1pt->pv_pa; 2414 2415 /* 2416 * Scan the L1 translation table created by initarm() and create 2417 * the required metadata for all valid mappings found in it. 2418 */ 2419 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2420 pde = kernel_l1pt[l1idx]; 2421 2422 /* 2423 * We're only interested in Coarse mappings. 2424 * pmap_extract() can deal with section mappings without 2425 * recourse to checking L2 metadata. 2426 */ 2427 if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2428 continue; 2429 2430 /* 2431 * Lookup the KVA of this L2 descriptor table 2432 */ 2433 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2434 ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2435 2436 if (ptep == NULL) { 2437 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2438 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2439 } 2440 2441 /* 2442 * Fetch the associated L2 metadata structure. 2443 * Allocate a new one if necessary. 2444 */ 2445 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2446 if (l2next == PMAP_STATIC_L2_SIZE) 2447 panic("pmap_bootstrap: out of static L2s"); 2448 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2449 &static_l2[l2next++]; 2450 } 2451 2452 /* 2453 * One more L1 slot tracked... 2454 */ 2455 l2->l2_occupancy++; 2456 2457 /* 2458 * Fill in the details of the L2 descriptor in the 2459 * appropriate bucket. 2460 */ 2461 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2462 l2b->l2b_kva = ptep; 2463 l2b->l2b_phys = pa; 2464 l2b->l2b_l1idx = l1idx; 2465 2466 /* 2467 * Establish an initial occupancy count for this descriptor 2468 */ 2469 for (l2idx = 0; 2470 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2471 l2idx++) { 2472 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2473 l2b->l2b_occupancy++; 2474 } 2475 } 2476 2477 /* 2478 * Make sure the descriptor itself has the correct cache mode. 2479 * If not, fix it, but whine about the problem. Port-meisters 2480 * should consider this a clue to fix up their initarm() 2481 * function. :) 2482 */ 2483 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2484 printf("pmap_bootstrap: WARNING! wrong cache mode for " 2485 "L2 pte @ %p\n", ptep); 2486 } 2487 } 2488 2489 2490 /* 2491 * Ensure the primary (kernel) L1 has the correct cache mode for 2492 * a page table. Bitch if it is not correctly set. 2493 */ 2494 for (va = (vm_offset_t)kernel_l1pt; 2495 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2496 if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2497 printf("pmap_bootstrap: WARNING! wrong cache mode for " 2498 "primary L1 @ 0x%x\n", va); 2499 } 2500 2501 cpu_dcache_wbinv_all(); 2502 cpu_tlb_flushID(); 2503 cpu_cpwait(); 2504 2505 kernel_pmap->pm_active = -1; 2506 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2507 LIST_INIT(&allpmaps); 2508 TAILQ_INIT(&kernel_pmap->pm_pvlist); 2509 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 2510 2511 /* 2512 * Reserve some special page table entries/VA space for temporary 2513 * mapping of pages. 2514 */ 2515#define SYSMAP(c, p, v, n) \ 2516 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2517 2518 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2519 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2520 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2521 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2522 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2523 pmap_alloc_specials(&virtual_avail, 2524 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2525 &pmap_kernel_l2ptp_kva, NULL); 2526 2527 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2528 pmap_alloc_specials(&virtual_avail, 2529 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2530 &pmap_kernel_l2dtable_kva, NULL); 2531 2532 pmap_alloc_specials(&virtual_avail, 2533 1, (vm_offset_t*)&_tmppt, NULL); 2534 SLIST_INIT(&l1_list); 2535 TAILQ_INIT(&l1_lru_list); 2536 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2537 pmap_init_l1(l1, kernel_l1pt); 2538 cpu_dcache_wbinv_all(); 2539 2540 virtual_avail = round_page(virtual_avail); 2541 virtual_end = lastaddr; 2542 kernel_vm_end = pmap_curmaxkvaddr; 2543 arm_nocache_startaddr = lastaddr; 2544 2545#ifdef ARM_USE_SMALL_ALLOC 2546 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF); 2547 alloc_firstaddr = alloc_curaddr = arm_nocache_startaddr + 2548 ARM_NOCACHE_KVA_SIZE; 2549#endif 2550} 2551 2552/*************************************************** 2553 * Pmap allocation/deallocation routines. 2554 ***************************************************/ 2555 2556/* 2557 * Release any resources held by the given physical map. 2558 * Called when a pmap initialized by pmap_pinit is being released. 2559 * Should only be called if the map contains no valid mappings. 2560 */ 2561void 2562pmap_release(pmap_t pmap) 2563{ 2564 struct pcb *pcb; 2565 2566 pmap_idcache_wbinv_all(pmap); 2567 pmap_tlb_flushID(pmap); 2568 cpu_cpwait(); 2569 LIST_REMOVE(pmap, pm_list); 2570 if (vector_page < KERNBASE) { 2571 struct pcb *curpcb = PCPU_GET(curpcb); 2572 pcb = thread0.td_pcb; 2573 if (pmap_is_current(pmap)) { 2574 /* 2575 * Frob the L1 entry corresponding to the vector 2576 * page so that it contains the kernel pmap's domain 2577 * number. This will ensure pmap_remove() does not 2578 * pull the current vector page out from under us. 2579 */ 2580 critical_enter(); 2581 *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2582 cpu_domains(pcb->pcb_dacr); 2583 cpu_setttb(pcb->pcb_pagedir); 2584 critical_exit(); 2585 } 2586 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2587 /* 2588 * Make sure cpu_switch(), et al, DTRT. This is safe to do 2589 * since this process has no remaining mappings of its own. 2590 */ 2591 curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2592 curpcb->pcb_l1vec = pcb->pcb_l1vec; 2593 curpcb->pcb_dacr = pcb->pcb_dacr; 2594 curpcb->pcb_pagedir = pcb->pcb_pagedir; 2595 2596 } 2597 pmap_free_l1(pmap); 2598 2599 dprintf("pmap_release()\n"); 2600} 2601 2602 2603 2604/* 2605 * Helper function for pmap_grow_l2_bucket() 2606 */ 2607static __inline int 2608pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2609{ 2610 struct l2_bucket *l2b; 2611 pt_entry_t *ptep; 2612 vm_paddr_t pa; 2613 struct vm_page *pg; 2614 2615 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2616 if (pg == NULL) 2617 return (1); 2618 pa = VM_PAGE_TO_PHYS(pg); 2619 2620 if (pap) 2621 *pap = pa; 2622 2623 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2624 2625 ptep = &l2b->l2b_kva[l2pte_index(va)]; 2626 *ptep = L2_S_PROTO | pa | cache_mode | 2627 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2628 PTE_SYNC(ptep); 2629 return (0); 2630} 2631 2632/* 2633 * This is the same as pmap_alloc_l2_bucket(), except that it is only 2634 * used by pmap_growkernel(). 2635 */ 2636static __inline struct l2_bucket * 2637pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2638{ 2639 struct l2_dtable *l2; 2640 struct l2_bucket *l2b; 2641 struct l1_ttable *l1; 2642 pd_entry_t *pl1pd; 2643 u_short l1idx; 2644 vm_offset_t nva; 2645 2646 l1idx = L1_IDX(va); 2647 2648 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2649 /* 2650 * No mapping at this address, as there is 2651 * no entry in the L1 table. 2652 * Need to allocate a new l2_dtable. 2653 */ 2654 nva = pmap_kernel_l2dtable_kva; 2655 if ((nva & PAGE_MASK) == 0) { 2656 /* 2657 * Need to allocate a backing page 2658 */ 2659 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2660 return (NULL); 2661 } 2662 2663 l2 = (struct l2_dtable *)nva; 2664 nva += sizeof(struct l2_dtable); 2665 2666 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2667 PAGE_MASK)) { 2668 /* 2669 * The new l2_dtable straddles a page boundary. 2670 * Map in another page to cover it. 2671 */ 2672 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2673 return (NULL); 2674 } 2675 2676 pmap_kernel_l2dtable_kva = nva; 2677 2678 /* 2679 * Link it into the parent pmap 2680 */ 2681 pm->pm_l2[L2_IDX(l1idx)] = l2; 2682 memset(l2, 0, sizeof(*l2)); 2683 } 2684 2685 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2686 2687 /* 2688 * Fetch pointer to the L2 page table associated with the address. 2689 */ 2690 if (l2b->l2b_kva == NULL) { 2691 pt_entry_t *ptep; 2692 2693 /* 2694 * No L2 page table has been allocated. Chances are, this 2695 * is because we just allocated the l2_dtable, above. 2696 */ 2697 nva = pmap_kernel_l2ptp_kva; 2698 ptep = (pt_entry_t *)nva; 2699 if ((nva & PAGE_MASK) == 0) { 2700 /* 2701 * Need to allocate a backing page 2702 */ 2703 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2704 &pmap_kernel_l2ptp_phys)) 2705 return (NULL); 2706 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2707 } 2708 memset(ptep, 0, L2_TABLE_SIZE_REAL); 2709 l2->l2_occupancy++; 2710 l2b->l2b_kva = ptep; 2711 l2b->l2b_l1idx = l1idx; 2712 l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2713 2714 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2715 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2716 } 2717 2718 /* Distribute new L1 entry to all other L1s */ 2719 SLIST_FOREACH(l1, &l1_list, l1_link) { 2720 pl1pd = &l1->l1_kva[L1_IDX(va)]; 2721 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2722 L1_C_PROTO; 2723 PTE_SYNC(pl1pd); 2724 } 2725 2726 return (l2b); 2727} 2728 2729 2730/* 2731 * grow the number of kernel page table entries, if needed 2732 */ 2733void 2734pmap_growkernel(vm_offset_t addr) 2735{ 2736 pmap_t kpm = pmap_kernel(); 2737 int s; 2738 2739 if (addr <= pmap_curmaxkvaddr) 2740 return; /* we are OK */ 2741 2742 /* 2743 * whoops! we need to add kernel PTPs 2744 */ 2745 2746 s = splhigh(); /* to be safe */ 2747 2748 /* Map 1MB at a time */ 2749 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2750 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2751 2752 /* 2753 * flush out the cache, expensive but growkernel will happen so 2754 * rarely 2755 */ 2756 cpu_dcache_wbinv_all(); 2757 cpu_tlb_flushD(); 2758 cpu_cpwait(); 2759 kernel_vm_end = pmap_curmaxkvaddr; 2760 2761} 2762 2763 2764/* 2765 * pmap_page_protect: 2766 * 2767 * Lower the permission for all mappings to a given page. 2768 */ 2769void 2770pmap_page_protect(vm_page_t m, vm_prot_t prot) 2771{ 2772 switch(prot) { 2773 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2774 case VM_PROT_READ|VM_PROT_WRITE: 2775 return; 2776 2777 case VM_PROT_READ: 2778 case VM_PROT_READ|VM_PROT_EXECUTE: 2779 pmap_clearbit(m, PVF_WRITE); 2780 break; 2781 2782 default: 2783 pmap_remove_all(m); 2784 break; 2785 } 2786 2787} 2788 2789 2790/* 2791 * Remove all pages from specified address space 2792 * this aids process exit speeds. Also, this code 2793 * is special cased for current process only, but 2794 * can have the more generic (and slightly slower) 2795 * mode enabled. This is much faster than pmap_remove 2796 * in the case of running down an entire address space. 2797 */ 2798void 2799pmap_remove_pages(pmap_t pmap) 2800{ 2801 struct pv_entry *pv, *npv; 2802 struct l2_bucket *l2b = NULL; 2803 vm_page_t m; 2804 pt_entry_t *pt; 2805 2806 vm_page_lock_queues(); 2807 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2808 if (pv->pv_flags & PVF_WIRED) { 2809 /* The page is wired, cannot remove it now. */ 2810 npv = TAILQ_NEXT(pv, pv_plist); 2811 continue; 2812 } 2813 pmap->pm_stats.resident_count--; 2814 l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2815 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2816 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2817 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK); 2818 *pt = 0; 2819 PTE_SYNC(pt); 2820 npv = TAILQ_NEXT(pv, pv_plist); 2821 pmap_nuke_pv(m, pmap, pv); 2822 if (TAILQ_EMPTY(&m->md.pv_list)) 2823 vm_page_flag_clear(m, PG_WRITEABLE); 2824 pmap_free_pv_entry(pv); 2825 } 2826 vm_page_unlock_queues(); 2827 cpu_idcache_wbinv_all(); 2828 cpu_tlb_flushID(); 2829 cpu_cpwait(); 2830} 2831 2832 2833/*************************************************** 2834 * Low level mapping routines..... 2835 ***************************************************/ 2836 2837/* Map a section into the KVA. */ 2838 2839void 2840pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2841{ 2842 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2843 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2844 struct l1_ttable *l1; 2845 2846 KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2847 ("Not a valid section mapping")); 2848 if (flags & SECTION_CACHE) 2849 pd |= pte_l1_s_cache_mode; 2850 else if (flags & SECTION_PT) 2851 pd |= pte_l1_s_cache_mode_pt; 2852 SLIST_FOREACH(l1, &l1_list, l1_link) { 2853 l1->l1_kva[L1_IDX(va)] = pd; 2854 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2855 } 2856} 2857 2858/* 2859 * add a wired page to the kva 2860 * note that in order for the mapping to take effect -- you 2861 * should do a invltlb after doing the pmap_kenter... 2862 */ 2863static PMAP_INLINE void 2864pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2865{ 2866 struct l2_bucket *l2b; 2867 pt_entry_t *pte; 2868 pt_entry_t opte; 2869 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2870 (uint32_t) va, (uint32_t) pa)); 2871 2872 2873 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2874 if (l2b == NULL) 2875 l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2876 KASSERT(l2b != NULL, ("No L2 Bucket")); 2877 pte = &l2b->l2b_kva[l2pte_index(va)]; 2878 opte = *pte; 2879 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2880 (uint32_t) pte, opte, *pte)); 2881 if (l2pte_valid(opte)) { 2882 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2883 cpu_tlb_flushD_SE(va); 2884 cpu_cpwait(); 2885 } else { 2886 if (opte == 0) 2887 l2b->l2b_occupancy++; 2888 } 2889 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2890 VM_PROT_READ | VM_PROT_WRITE); 2891 if (flags & KENTER_CACHE) 2892 *pte |= pte_l2_s_cache_mode; 2893 if (flags & KENTER_USER) 2894 *pte |= L2_S_PROT_U; 2895 PTE_SYNC(pte); 2896} 2897 2898void 2899pmap_kenter(vm_offset_t va, vm_paddr_t pa) 2900{ 2901 pmap_kenter_internal(va, pa, KENTER_CACHE); 2902} 2903 2904void 2905pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2906{ 2907 2908 pmap_kenter_internal(va, pa, 0); 2909} 2910 2911void 2912pmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2913{ 2914 2915 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2916 /* 2917 * Call pmap_fault_fixup now, to make sure we'll have no exception 2918 * at the first use of the new address, or bad things will happen, 2919 * as we use one of these addresses in the exception handlers. 2920 */ 2921 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1); 2922} 2923 2924/* 2925 * remove a page rom the kernel pagetables 2926 */ 2927PMAP_INLINE void 2928pmap_kremove(vm_offset_t va) 2929{ 2930 struct l2_bucket *l2b; 2931 pt_entry_t *pte, opte; 2932 2933 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2934 if (!l2b) 2935 return; 2936 KASSERT(l2b != NULL, ("No L2 Bucket")); 2937 pte = &l2b->l2b_kva[l2pte_index(va)]; 2938 opte = *pte; 2939 if (l2pte_valid(opte)) { 2940 cpu_dcache_wbinv_range(va, PAGE_SIZE); 2941 cpu_tlb_flushD_SE(va); 2942 cpu_cpwait(); 2943 *pte = 0; 2944 } 2945} 2946 2947 2948/* 2949 * Used to map a range of physical addresses into kernel 2950 * virtual address space. 2951 * 2952 * The value passed in '*virt' is a suggested virtual address for 2953 * the mapping. Architectures which can support a direct-mapped 2954 * physical to virtual region can return the appropriate address 2955 * within that region, leaving '*virt' unchanged. Other 2956 * architectures should map the pages starting at '*virt' and 2957 * update '*virt' with the first usable address after the mapped 2958 * region. 2959 */ 2960vm_offset_t 2961pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2962{ 2963 vm_offset_t sva = *virt; 2964 vm_offset_t va = sva; 2965 2966 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2967 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2968 prot)); 2969 2970 while (start < end) { 2971 pmap_kenter(va, start); 2972 va += PAGE_SIZE; 2973 start += PAGE_SIZE; 2974 } 2975 *virt = va; 2976 return (sva); 2977} 2978 2979static void 2980pmap_wb_page(vm_page_t m) 2981{ 2982 struct pv_entry *pv; 2983 2984 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2985 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2986 (pv->pv_flags & PVF_WRITE) == 0); 2987} 2988 2989static void 2990pmap_inv_page(vm_page_t m) 2991{ 2992 struct pv_entry *pv; 2993 2994 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2995 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2996} 2997/* 2998 * Add a list of wired pages to the kva 2999 * this routine is only used for temporary 3000 * kernel mappings that do not need to have 3001 * page modification or references recorded. 3002 * Note that old mappings are simply written 3003 * over. The page *must* be wired. 3004 */ 3005void 3006pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 3007{ 3008 int i; 3009 3010 for (i = 0; i < count; i++) { 3011 pmap_wb_page(m[i]); 3012 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 3013 KENTER_CACHE); 3014 va += PAGE_SIZE; 3015 } 3016} 3017 3018 3019/* 3020 * this routine jerks page mappings from the 3021 * kernel -- it is meant only for temporary mappings. 3022 */ 3023void 3024pmap_qremove(vm_offset_t va, int count) 3025{ 3026 vm_paddr_t pa; 3027 int i; 3028 3029 for (i = 0; i < count; i++) { 3030 pa = vtophys(va); 3031 if (pa) { 3032 pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 3033 pmap_kremove(va); 3034 } 3035 va += PAGE_SIZE; 3036 } 3037} 3038 3039 3040/* 3041 * pmap_object_init_pt preloads the ptes for a given object 3042 * into the specified pmap. This eliminates the blast of soft 3043 * faults on process startup and immediately after an mmap. 3044 */ 3045void 3046pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3047 vm_pindex_t pindex, vm_size_t size) 3048{ 3049 3050 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3051 KASSERT(object->type == OBJT_DEVICE, 3052 ("pmap_object_init_pt: non-device object")); 3053} 3054 3055 3056/* 3057 * pmap_is_prefaultable: 3058 * 3059 * Return whether or not the specified virtual address is elgible 3060 * for prefault. 3061 */ 3062boolean_t 3063pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3064{ 3065 pd_entry_t *pde; 3066 pt_entry_t *pte; 3067 3068 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 3069 return (FALSE); 3070 if (*pte == 0) 3071 return (TRUE); 3072 return (FALSE); 3073} 3074 3075/* 3076 * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 3077 * Returns TRUE if the mapping exists, else FALSE. 3078 * 3079 * NOTE: This function is only used by a couple of arm-specific modules. 3080 * It is not safe to take any pmap locks here, since we could be right 3081 * in the middle of debugging the pmap anyway... 3082 * 3083 * It is possible for this routine to return FALSE even though a valid 3084 * mapping does exist. This is because we don't lock, so the metadata 3085 * state may be inconsistent. 3086 * 3087 * NOTE: We can return a NULL *ptp in the case where the L1 pde is 3088 * a "section" mapping. 3089 */ 3090boolean_t 3091pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 3092{ 3093 struct l2_dtable *l2; 3094 pd_entry_t *pl1pd, l1pd; 3095 pt_entry_t *ptep; 3096 u_short l1idx; 3097 3098 if (pm->pm_l1 == NULL) 3099 return (FALSE); 3100 3101 l1idx = L1_IDX(va); 3102 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3103 l1pd = *pl1pd; 3104 3105 if (l1pte_section_p(l1pd)) { 3106 *ptp = NULL; 3107 return (TRUE); 3108 } 3109 3110 if (pm->pm_l2 == NULL) 3111 return (FALSE); 3112 3113 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3114 3115 if (l2 == NULL || 3116 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3117 return (FALSE); 3118 } 3119 3120 *ptp = &ptep[l2pte_index(va)]; 3121 return (TRUE); 3122} 3123 3124/* 3125 * Routine: pmap_remove_all 3126 * Function: 3127 * Removes this physical page from 3128 * all physical maps in which it resides. 3129 * Reflects back modify bits to the pager. 3130 * 3131 * Notes: 3132 * Original versions of this routine were very 3133 * inefficient because they iteratively called 3134 * pmap_remove (slow...) 3135 */ 3136void 3137pmap_remove_all(vm_page_t m) 3138{ 3139 pv_entry_t pv; 3140 pt_entry_t *ptep, pte; 3141 struct l2_bucket *l2b; 3142 boolean_t flush = FALSE; 3143 pmap_t curpm; 3144 int flags = 0; 3145 3146#if defined(PMAP_DEBUG) 3147 /* 3148 * XXX this makes pmap_page_protect(NONE) illegal for non-managed 3149 * pages! 3150 */ 3151 if (m->flags & PG_FICTITIOUS) { 3152 panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m)); 3153 } 3154#endif 3155 3156 if (TAILQ_EMPTY(&m->md.pv_list)) 3157 return; 3158 curpm = vmspace_pmap(curproc->p_vmspace); 3159 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3160 if (flush == FALSE && (pv->pv_pmap == curpm || 3161 pv->pv_pmap == pmap_kernel())) 3162 flush = TRUE; 3163 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3164 KASSERT(l2b != NULL, ("No l2 bucket")); 3165 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3166 pte = *ptep; 3167 *ptep = 0; 3168 PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3169 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3170 if (pv->pv_flags & PVF_WIRED) 3171 pv->pv_pmap->pm_stats.wired_count--; 3172 pv->pv_pmap->pm_stats.resident_count--; 3173 flags |= pv->pv_flags; 3174 pmap_nuke_pv(m, pv->pv_pmap, pv); 3175 pmap_free_pv_entry(pv); 3176 } 3177 3178 if (flush) { 3179 if (PV_BEEN_EXECD(flags)) 3180 pmap_tlb_flushID(curpm); 3181 else 3182 pmap_tlb_flushD(curpm); 3183 } 3184 vm_page_flag_clear(m, PG_WRITEABLE); 3185} 3186 3187 3188/* 3189 * Set the physical protection on the 3190 * specified range of this map as requested. 3191 */ 3192void 3193pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3194{ 3195 struct l2_bucket *l2b; 3196 pt_entry_t *ptep, pte; 3197 vm_offset_t next_bucket; 3198 u_int flags; 3199 int flush; 3200 3201 if ((prot & VM_PROT_READ) == 0) { 3202 mtx_lock(&Giant); 3203 pmap_remove(pm, sva, eva); 3204 mtx_unlock(&Giant); 3205 return; 3206 } 3207 3208 if (prot & VM_PROT_WRITE) { 3209 /* 3210 * If this is a read->write transition, just ignore it and let 3211 * vm_fault() take care of it later. 3212 */ 3213 return; 3214 } 3215 3216 mtx_lock(&Giant); 3217 3218 /* 3219 * OK, at this point, we know we're doing write-protect operation. 3220 * If the pmap is active, write-back the range. 3221 */ 3222 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3223 3224 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3225 flags = 0; 3226 3227 vm_page_lock_queues(); 3228 while (sva < eva) { 3229 next_bucket = L2_NEXT_BUCKET(sva); 3230 if (next_bucket > eva) 3231 next_bucket = eva; 3232 3233 l2b = pmap_get_l2_bucket(pm, sva); 3234 if (l2b == NULL) { 3235 sva = next_bucket; 3236 continue; 3237 } 3238 3239 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3240 3241 while (sva < next_bucket) { 3242 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3243 struct vm_page *pg; 3244 u_int f; 3245 3246 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3247 pte &= ~L2_S_PROT_W; 3248 *ptep = pte; 3249 PTE_SYNC(ptep); 3250 3251 if (pg != NULL) { 3252 f = pmap_modify_pv(pg, pm, sva, 3253 PVF_WRITE, 0); 3254 pmap_vac_me_harder(pg, pm, sva); 3255 vm_page_dirty(pg); 3256 } else 3257 f = PVF_REF | PVF_EXEC; 3258 3259 if (flush >= 0) { 3260 flush++; 3261 flags |= f; 3262 } else 3263 if (PV_BEEN_EXECD(f)) 3264 pmap_tlb_flushID_SE(pm, sva); 3265 else 3266 if (PV_BEEN_REFD(f)) 3267 pmap_tlb_flushD_SE(pm, sva); 3268 } 3269 3270 sva += PAGE_SIZE; 3271 ptep++; 3272 } 3273 } 3274 3275 3276 if (flush) { 3277 if (PV_BEEN_EXECD(flags)) 3278 pmap_tlb_flushID(pm); 3279 else 3280 if (PV_BEEN_REFD(flags)) 3281 pmap_tlb_flushD(pm); 3282 } 3283 vm_page_unlock_queues(); 3284 3285 mtx_unlock(&Giant); 3286} 3287 3288 3289/* 3290 * Insert the given physical page (p) at 3291 * the specified virtual address (v) in the 3292 * target physical map with the protection requested. 3293 * 3294 * If specified, the page will be wired down, meaning 3295 * that the related pte can not be reclaimed. 3296 * 3297 * NB: This is the only routine which MAY NOT lazy-evaluate 3298 * or lose information. That is, this routine must actually 3299 * insert this page into the given map NOW. 3300 */ 3301 3302void 3303pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3304 boolean_t wired) 3305{ 3306 struct l2_bucket *l2b = NULL; 3307 struct vm_page *opg; 3308 struct pv_entry *pve = NULL; 3309 pt_entry_t *ptep, npte, opte; 3310 u_int nflags; 3311 u_int oflags; 3312 vm_paddr_t pa; 3313 3314 vm_page_lock_queues(); 3315 if (va == vector_page) { 3316 pa = systempage.pv_pa; 3317 m = NULL; 3318 } else 3319 pa = VM_PAGE_TO_PHYS(m); 3320 nflags = 0; 3321 if (prot & VM_PROT_WRITE) 3322 nflags |= PVF_WRITE; 3323 if (prot & VM_PROT_EXECUTE) 3324 nflags |= PVF_EXEC; 3325 if (wired) 3326 nflags |= PVF_WIRED; 3327 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3328 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3329 3330 if (pmap == pmap_kernel()) { 3331 l2b = pmap_get_l2_bucket(pmap, va); 3332 if (l2b == NULL) 3333 l2b = pmap_grow_l2_bucket(pmap, va); 3334 } else 3335 l2b = pmap_alloc_l2_bucket(pmap, va); 3336 KASSERT(l2b != NULL, 3337 ("pmap_enter: failed to allocate l2 bucket")); 3338 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3339 3340 opte = *ptep; 3341 npte = pa; 3342 oflags = 0; 3343 if (opte) { 3344 /* 3345 * There is already a mapping at this address. 3346 * If the physical address is different, lookup the 3347 * vm_page. 3348 */ 3349 if (l2pte_pa(opte) != pa) 3350 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3351 else 3352 opg = m; 3353 } else 3354 opg = NULL; 3355 3356 if ((prot & (VM_PROT_ALL)) || 3357 (!m || m->md.pvh_attrs & PVF_REF)) { 3358 /* 3359 * - The access type indicates that we don't need 3360 * to do referenced emulation. 3361 * OR 3362 * - The physical page has already been referenced 3363 * so no need to re-do referenced emulation here. 3364 */ 3365 npte |= L2_S_PROTO; 3366 3367 nflags |= PVF_REF; 3368 3369 if (m && ((prot & VM_PROT_WRITE) != 0 || 3370 (m->md.pvh_attrs & PVF_MOD))) { 3371 /* 3372 * This is a writable mapping, and the 3373 * page's mod state indicates it has 3374 * already been modified. Make it 3375 * writable from the outset. 3376 */ 3377 nflags |= PVF_MOD; 3378 if (!(m->md.pvh_attrs & PVF_MOD)) 3379 vm_page_dirty(m); 3380 } 3381 if (m && opte) 3382 vm_page_flag_set(m, PG_REFERENCED); 3383 } else { 3384 /* 3385 * Need to do page referenced emulation. 3386 */ 3387 npte |= L2_TYPE_INV; 3388 } 3389 3390 if (prot & VM_PROT_WRITE) 3391 npte |= L2_S_PROT_W; 3392 npte |= pte_l2_s_cache_mode; 3393 if (m && m == opg) { 3394 /* 3395 * We're changing the attrs of an existing mapping. 3396 */ 3397#if 0 3398 simple_lock(&pg->mdpage.pvh_slock); 3399#endif 3400 oflags = pmap_modify_pv(m, pmap, va, 3401 PVF_WRITE | PVF_EXEC | PVF_WIRED | 3402 PVF_MOD | PVF_REF, nflags); 3403#if 0 3404 simple_unlock(&pg->mdpage.pvh_slock); 3405#endif 3406 3407 /* 3408 * We may need to flush the cache if we're 3409 * doing rw-ro... 3410 */ 3411 if (pmap_is_current(pmap) && 3412 (oflags & PVF_NC) == 0 && 3413 (opte & L2_S_PROT_W) != 0 && 3414 (prot & VM_PROT_WRITE) == 0) 3415 cpu_dcache_wb_range(va, PAGE_SIZE); 3416 } else { 3417 /* 3418 * New mapping, or changing the backing page 3419 * of an existing mapping. 3420 */ 3421 if (opg) { 3422 /* 3423 * Replacing an existing mapping with a new one. 3424 * It is part of our managed memory so we 3425 * must remove it from the PV list 3426 */ 3427#if 0 3428 simple_lock(&opg->mdpage.pvh_slock); 3429#endif 3430 pve = pmap_remove_pv(opg, pmap, va); 3431 if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) && pve) 3432 pmap_free_pv_entry(pve); 3433 else if (!pve) 3434 pve = pmap_get_pv_entry(); 3435 KASSERT(pve != NULL, ("No pv")); 3436#if 0 3437 simple_unlock(&opg->mdpage.pvh_slock); 3438#endif 3439 oflags = pve->pv_flags; 3440 3441 /* 3442 * If the old mapping was valid (ref/mod 3443 * emulation creates 'invalid' mappings 3444 * initially) then make sure to frob 3445 * the cache. 3446 */ 3447 if ((oflags & PVF_NC) == 0 && 3448 l2pte_valid(opte)) { 3449 if (PV_BEEN_EXECD(oflags)) { 3450 pmap_idcache_wbinv_range(pmap, va, 3451 PAGE_SIZE); 3452 } else 3453 if (PV_BEEN_REFD(oflags)) { 3454 pmap_dcache_wb_range(pmap, va, 3455 PAGE_SIZE, TRUE, 3456 (oflags & PVF_WRITE) == 0); 3457 } 3458 } 3459 } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) 3460 if ((pve = pmap_get_pv_entry()) == NULL) { 3461 panic("pmap_enter: no pv entries"); 3462 } 3463 if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS))) { 3464 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3465 ("pmap_enter: managed mapping within the clean submap")); 3466 pmap_enter_pv(m, pve, pmap, va, nflags); 3467 } 3468 } 3469 /* 3470 * Make sure userland mappings get the right permissions 3471 */ 3472 if (pmap != pmap_kernel() && va != vector_page) { 3473 npte |= L2_S_PROT_U; 3474 } 3475 3476 /* 3477 * Keep the stats up to date 3478 */ 3479 if (opte == 0) { 3480 l2b->l2b_occupancy++; 3481 pmap->pm_stats.resident_count++; 3482 } 3483 3484 3485 /* 3486 * If this is just a wiring change, the two PTEs will be 3487 * identical, so there's no need to update the page table. 3488 */ 3489 if (npte != opte) { 3490 boolean_t is_cached = pmap_is_current(pmap); 3491 3492 *ptep = npte; 3493 if (is_cached) { 3494 /* 3495 * We only need to frob the cache/tlb if this pmap 3496 * is current 3497 */ 3498 PTE_SYNC(ptep); 3499 if (L1_IDX(va) != L1_IDX(vector_page) && 3500 l2pte_valid(npte)) { 3501 /* 3502 * This mapping is likely to be accessed as 3503 * soon as we return to userland. Fix up the 3504 * L1 entry to avoid taking another 3505 * page/domain fault. 3506 */ 3507 pd_entry_t *pl1pd, l1pd; 3508 3509 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3510 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3511 L1_C_PROTO; 3512 if (*pl1pd != l1pd) { 3513 *pl1pd = l1pd; 3514 PTE_SYNC(pl1pd); 3515 } 3516 } 3517 } 3518 3519 if (PV_BEEN_EXECD(oflags)) 3520 pmap_tlb_flushID_SE(pmap, va); 3521 else if (PV_BEEN_REFD(oflags)) 3522 pmap_tlb_flushD_SE(pmap, va); 3523 3524 3525 if (m) 3526 pmap_vac_me_harder(m, pmap, va); 3527 } 3528 vm_page_unlock_queues(); 3529} 3530 3531/* 3532 * this code makes some *MAJOR* assumptions: 3533 * 1. Current pmap & pmap exists. 3534 * 2. Not wired. 3535 * 3. Read access. 3536 * 4. No page table pages. 3537 * but is *MUCH* faster than pmap_enter... 3538 */ 3539 3540vm_page_t 3541pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3542 vm_page_t mpte) 3543{ 3544 3545 vm_page_busy(m); 3546 vm_page_unlock_queues(); 3547 VM_OBJECT_UNLOCK(m->object); 3548 mtx_lock(&Giant); 3549 pmap_enter(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 3550 mtx_unlock(&Giant); 3551 VM_OBJECT_LOCK(m->object); 3552 vm_page_lock_queues(); 3553 vm_page_wakeup(m); 3554 return (NULL); 3555} 3556 3557/* 3558 * Routine: pmap_change_wiring 3559 * Function: Change the wiring attribute for a map/virtual-address 3560 * pair. 3561 * In/out conditions: 3562 * The mapping must already exist in the pmap. 3563 */ 3564void 3565pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3566{ 3567 struct l2_bucket *l2b; 3568 pt_entry_t *ptep, pte; 3569 vm_page_t pg; 3570 3571 l2b = pmap_get_l2_bucket(pmap, va); 3572 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3573 ptep = &l2b->l2b_kva[l2pte_index(va)]; 3574 pte = *ptep; 3575 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3576 if (pg) 3577 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired); 3578} 3579 3580 3581/* 3582 * Copy the range specified by src_addr/len 3583 * from the source map to the range dst_addr/len 3584 * in the destination map. 3585 * 3586 * This routine is only advisory and need not do anything. 3587 */ 3588void 3589pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3590 vm_size_t len, vm_offset_t src_addr) 3591{ 3592} 3593 3594 3595/* 3596 * Routine: pmap_extract 3597 * Function: 3598 * Extract the physical page address associated 3599 * with the given map/virtual_address pair. 3600 */ 3601vm_paddr_t 3602pmap_extract(pmap_t pm, vm_offset_t va) 3603{ 3604 struct l2_dtable *l2; 3605 pd_entry_t *pl1pd, l1pd; 3606 pt_entry_t *ptep, pte; 3607 vm_paddr_t pa; 3608 u_int l1idx; 3609 l1idx = L1_IDX(va); 3610 pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3611 l1pd = *pl1pd; 3612 3613 if (l1pte_section_p(l1pd)) { 3614 /* 3615 * These should only happen for pmap_kernel() 3616 */ 3617 KASSERT(pm == pmap_kernel(), ("huh")); 3618 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3619 } else { 3620 /* 3621 * Note that we can't rely on the validity of the L1 3622 * descriptor as an indication that a mapping exists. 3623 * We have to look it up in the L2 dtable. 3624 */ 3625 l2 = pm->pm_l2[L2_IDX(l1idx)]; 3626 3627 if (l2 == NULL || 3628 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3629 return (0); 3630 } 3631 3632 ptep = &ptep[l2pte_index(va)]; 3633 pte = *ptep; 3634 3635 if (pte == 0) 3636 return (0); 3637 3638 switch (pte & L2_TYPE_MASK) { 3639 case L2_TYPE_L: 3640 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3641 break; 3642 3643 default: 3644 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3645 break; 3646 } 3647 } 3648 3649 return (pa); 3650} 3651 3652/* 3653 * Atomically extract and hold the physical page with the given 3654 * pmap and virtual address pair if that mapping permits the given 3655 * protection. 3656 * 3657 */ 3658vm_page_t 3659pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3660{ 3661 struct l2_dtable *l2; 3662 pd_entry_t *pl1pd, l1pd; 3663 pt_entry_t *ptep, pte; 3664 vm_paddr_t pa; 3665 vm_page_t m = NULL; 3666 u_int l1idx; 3667 l1idx = L1_IDX(va); 3668 pl1pd = &pmap->pm_l1->l1_kva[l1idx]; 3669 l1pd = *pl1pd; 3670 3671 vm_page_lock_queues(); 3672 if (l1pte_section_p(l1pd)) { 3673 /* 3674 * These should only happen for pmap_kernel() 3675 */ 3676 KASSERT(pmap == pmap_kernel(), ("huh")); 3677 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3678 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3679 m = PHYS_TO_VM_PAGE(pa); 3680 vm_page_hold(m); 3681 } 3682 3683 } else { 3684 /* 3685 * Note that we can't rely on the validity of the L1 3686 * descriptor as an indication that a mapping exists. 3687 * We have to look it up in the L2 dtable. 3688 */ 3689 l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3690 3691 if (l2 == NULL || 3692 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3693 vm_page_unlock_queues(); 3694 return (NULL); 3695 } 3696 3697 ptep = &ptep[l2pte_index(va)]; 3698 pte = *ptep; 3699 3700 if (pte == 0) { 3701 vm_page_unlock_queues(); 3702 return (NULL); 3703 } 3704 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3705 switch (pte & L2_TYPE_MASK) { 3706 case L2_TYPE_L: 3707 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3708 break; 3709 3710 default: 3711 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3712 break; 3713 } 3714 m = PHYS_TO_VM_PAGE(pa); 3715 vm_page_hold(m); 3716 } 3717 } 3718 3719 vm_page_unlock_queues(); 3720 return (m); 3721} 3722 3723/* 3724 * Initialize a preallocated and zeroed pmap structure, 3725 * such as one in a vmspace structure. 3726 */ 3727 3728void 3729pmap_pinit(pmap_t pmap) 3730{ 3731 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3732 3733 pmap_alloc_l1(pmap); 3734 bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3735 3736 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 3737 pmap->pm_count = 1; 3738 pmap->pm_active = 0; 3739 3740 TAILQ_INIT(&pmap->pm_pvlist); 3741 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3742 pmap->pm_stats.resident_count = 1; 3743 if (vector_page < KERNBASE) { 3744 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3745 VM_PROT_READ, 1); 3746 } 3747} 3748 3749 3750/*************************************************** 3751 * page management routines. 3752 ***************************************************/ 3753 3754 3755static void 3756pmap_free_pv_entry(pv_entry_t pv) 3757{ 3758 pv_entry_count--; 3759 uma_zfree(pvzone, pv); 3760} 3761 3762 3763/* 3764 * get a new pv_entry, allocating a block from the system 3765 * when needed. 3766 * the memory allocation is performed bypassing the malloc code 3767 * because of the possibility of allocations at interrupt time. 3768 */ 3769static pv_entry_t 3770pmap_get_pv_entry(void) 3771{ 3772 pv_entry_t ret_value; 3773 3774 pv_entry_count++; 3775 if ((pv_entry_count > pv_entry_high_water) && 3776 (pmap_pagedaemon_waken == 0)) { 3777 pmap_pagedaemon_waken = 1; 3778 wakeup (&vm_pages_needed); 3779 } 3780 ret_value = uma_zalloc(pvzone, M_NOWAIT); 3781 return ret_value; 3782} 3783 3784 3785/* 3786 * Remove the given range of addresses from the specified map. 3787 * 3788 * It is assumed that the start and end are properly 3789 * rounded to the page size. 3790 */ 3791#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3792void 3793pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3794{ 3795 struct l2_bucket *l2b; 3796 vm_offset_t next_bucket; 3797 pt_entry_t *ptep; 3798 u_int cleanlist_idx, total, cnt; 3799 struct { 3800 vm_offset_t va; 3801 pt_entry_t *pte; 3802 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3803 u_int mappings, is_exec, is_refd; 3804 int flushall = 0; 3805 3806 3807 /* 3808 * we lock in the pmap => pv_head direction 3809 */ 3810#if 0 3811 PMAP_MAP_TO_HEAD_LOCK(); 3812 pmap_acquire_pmap_lock(pm); 3813#endif 3814 3815 vm_page_lock_queues(); 3816 if (!pmap_is_current(pm)) { 3817 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3818 } else 3819 cleanlist_idx = 0; 3820 3821 total = 0; 3822 while (sva < eva) { 3823 /* 3824 * Do one L2 bucket's worth at a time. 3825 */ 3826 next_bucket = L2_NEXT_BUCKET(sva); 3827 if (next_bucket > eva) 3828 next_bucket = eva; 3829 3830 l2b = pmap_get_l2_bucket(pm, sva); 3831 if (l2b == NULL) { 3832 sva = next_bucket; 3833 continue; 3834 } 3835 3836 ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3837 mappings = 0; 3838 3839 while (sva < next_bucket) { 3840 struct vm_page *pg; 3841 pt_entry_t pte; 3842 vm_paddr_t pa; 3843 3844 pte = *ptep; 3845 3846 if (pte == 0) { 3847 /* 3848 * Nothing here, move along 3849 */ 3850 sva += PAGE_SIZE; 3851 ptep++; 3852 continue; 3853 } 3854 3855 pm->pm_stats.resident_count--; 3856 pa = l2pte_pa(pte); 3857 is_exec = 0; 3858 is_refd = 1; 3859 3860 /* 3861 * Update flags. In a number of circumstances, 3862 * we could cluster a lot of these and do a 3863 * number of sequential pages in one go. 3864 */ 3865 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3866 struct pv_entry *pve; 3867#if 0 3868 simple_lock(&pg->mdpage.pvh_slock); 3869#endif 3870 pve = pmap_remove_pv(pg, pm, sva); 3871 if (pve) { 3872#if 0 3873 simple_unlock(&pg->mdpage.pvh_slock); 3874#endif 3875 is_exec = 3876 PV_BEEN_EXECD(pve->pv_flags); 3877 is_refd = 3878 PV_BEEN_REFD(pve->pv_flags); 3879 pmap_free_pv_entry(pve); 3880 } 3881 } 3882 3883 if (!l2pte_valid(pte)) { 3884 *ptep = 0; 3885 PTE_SYNC_CURRENT(pm, ptep); 3886 sva += PAGE_SIZE; 3887 ptep++; 3888 mappings++; 3889 continue; 3890 } 3891 3892 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3893 /* Add to the clean list. */ 3894 cleanlist[cleanlist_idx].pte = ptep; 3895 cleanlist[cleanlist_idx].va = 3896 sva | (is_exec & 1); 3897 cleanlist_idx++; 3898 } else 3899 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3900 /* Nuke everything if needed. */ 3901 pmap_idcache_wbinv_all(pm); 3902 pmap_tlb_flushID(pm); 3903 3904 /* 3905 * Roll back the previous PTE list, 3906 * and zero out the current PTE. 3907 */ 3908 for (cnt = 0; 3909 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3910 *cleanlist[cnt].pte = 0; 3911 } 3912 *ptep = 0; 3913 PTE_SYNC(ptep); 3914 cleanlist_idx++; 3915 flushall = 1; 3916 } else { 3917 *ptep = 0; 3918 PTE_SYNC(ptep); 3919 if (is_exec) 3920 pmap_tlb_flushID_SE(pm, sva); 3921 else 3922 if (is_refd) 3923 pmap_tlb_flushD_SE(pm, sva); 3924 } 3925 3926 sva += PAGE_SIZE; 3927 ptep++; 3928 mappings++; 3929 } 3930 3931 /* 3932 * Deal with any left overs 3933 */ 3934 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3935 total += cleanlist_idx; 3936 for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3937 vm_offset_t clva = 3938 cleanlist[cnt].va & ~1; 3939 if (cleanlist[cnt].va & 1) { 3940 pmap_idcache_wbinv_range(pm, 3941 clva, PAGE_SIZE); 3942 pmap_tlb_flushID_SE(pm, clva); 3943 } else { 3944 pmap_dcache_wb_range(pm, 3945 clva, PAGE_SIZE, TRUE, 3946 FALSE); 3947 pmap_tlb_flushD_SE(pm, clva); 3948 } 3949 *cleanlist[cnt].pte = 0; 3950 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 3951 } 3952 3953 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3954 cleanlist_idx = 0; 3955 else { 3956 /* 3957 * We are removing so much entries it's just 3958 * easier to flush the whole cache. 3959 */ 3960 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3961 pmap_idcache_wbinv_all(pm); 3962 flushall = 1; 3963 } 3964 } 3965 3966 pmap_free_l2_bucket(pm, l2b, mappings); 3967 } 3968 3969 vm_page_unlock_queues(); 3970 if (flushall) 3971 cpu_tlb_flushID(); 3972#if 0 3973 pmap_release_pmap_lock(pm); 3974 PMAP_MAP_TO_HEAD_UNLOCK(); 3975#endif 3976} 3977 3978 3979 3980 3981/* 3982 * pmap_zero_page() 3983 * 3984 * Zero a given physical page by mapping it at a page hook point. 3985 * In doing the zero page op, the page we zero is mapped cachable, as with 3986 * StrongARM accesses to non-cached pages are non-burst making writing 3987 * _any_ bulk data very slow. 3988 */ 3989#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3990void 3991pmap_zero_page_generic(vm_paddr_t phys, int off, int size) 3992{ 3993#ifdef DEBUG 3994 struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3995 3996 if (pg->md.pvh_list != NULL) 3997 panic("pmap_zero_page: page has mappings"); 3998#endif 3999 4000 if (_arm_bzero && 4001 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4002 return; 4003 4004 4005 /* 4006 * Hook in the page, zero it, and purge the cache for that 4007 * zeroed page. Invalidate the TLB as needed. 4008 */ 4009 *cdst_pte = L2_S_PROTO | phys | 4010 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4011 PTE_SYNC(cdst_pte); 4012 cpu_tlb_flushD_SE(cdstp); 4013 cpu_cpwait(); 4014 if (off || size != PAGE_SIZE) 4015 bzero((void *)(cdstp + off), size); 4016 else 4017 bzero_page(cdstp); 4018 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4019} 4020#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4021 4022#if ARM_MMU_XSCALE == 1 4023void 4024pmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 4025{ 4026 4027 if (_arm_bzero && 4028 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 4029 return; 4030 /* 4031 * Hook in the page, zero it, and purge the cache for that 4032 * zeroed page. Invalidate the TLB as needed. 4033 */ 4034 *cdst_pte = L2_S_PROTO | phys | 4035 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4036 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4037 PTE_SYNC(cdst_pte); 4038 cpu_tlb_flushD_SE(cdstp); 4039 cpu_cpwait(); 4040 if (off || size != PAGE_SIZE) 4041 bzero((void *)(cdstp + off), size); 4042 else 4043 bzero_page(cdstp); 4044 xscale_cache_clean_minidata(); 4045} 4046 4047/* 4048 * Change the PTEs for the specified kernel mappings such that they 4049 * will use the mini data cache instead of the main data cache. 4050 */ 4051void 4052pmap_use_minicache(vm_offset_t va, vm_size_t size) 4053{ 4054 struct l2_bucket *l2b; 4055 pt_entry_t *ptep, *sptep, pte; 4056 vm_offset_t next_bucket, eva; 4057 4058#if (ARM_NMMUS > 1) 4059 if (xscale_use_minidata == 0) 4060 return; 4061#endif 4062 4063 eva = va + size; 4064 4065 while (va < eva) { 4066 next_bucket = L2_NEXT_BUCKET(va); 4067 if (next_bucket > eva) 4068 next_bucket = eva; 4069 4070 l2b = pmap_get_l2_bucket(pmap_kernel(), va); 4071 4072 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4073 4074 while (va < next_bucket) { 4075 pte = *ptep; 4076 if (!l2pte_minidata(pte)) { 4077 cpu_dcache_wbinv_range(va, PAGE_SIZE); 4078 cpu_tlb_flushD_SE(va); 4079 *ptep = pte & ~L2_B; 4080 } 4081 ptep++; 4082 va += PAGE_SIZE; 4083 } 4084 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4085 } 4086 cpu_cpwait(); 4087} 4088#endif /* ARM_MMU_XSCALE == 1 */ 4089 4090/* 4091 * pmap_zero_page zeros the specified hardware page by mapping 4092 * the page into KVM and using bzero to clear its contents. 4093 */ 4094void 4095pmap_zero_page(vm_page_t m) 4096{ 4097 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4098} 4099 4100 4101/* 4102 * pmap_zero_page_area zeros the specified hardware page by mapping 4103 * the page into KVM and using bzero to clear its contents. 4104 * 4105 * off and size may not cover an area beyond a single hardware page. 4106 */ 4107void 4108pmap_zero_page_area(vm_page_t m, int off, int size) 4109{ 4110 4111 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4112} 4113 4114 4115/* 4116 * pmap_zero_page_idle zeros the specified hardware page by mapping 4117 * the page into KVM and using bzero to clear its contents. This 4118 * is intended to be called from the vm_pagezero process only and 4119 * outside of Giant. 4120 */ 4121void 4122pmap_zero_page_idle(vm_page_t m) 4123{ 4124 4125 pmap_zero_page(m); 4126} 4127 4128#if 0 4129/* 4130 * pmap_clean_page() 4131 * 4132 * This is a local function used to work out the best strategy to clean 4133 * a single page referenced by its entry in the PV table. It's used by 4134 * pmap_copy_page, pmap_zero page and maybe some others later on. 4135 * 4136 * Its policy is effectively: 4137 * o If there are no mappings, we don't bother doing anything with the cache. 4138 * o If there is one mapping, we clean just that page. 4139 * o If there are multiple mappings, we clean the entire cache. 4140 * 4141 * So that some functions can be further optimised, it returns 0 if it didn't 4142 * clean the entire cache, or 1 if it did. 4143 * 4144 * XXX One bug in this routine is that if the pv_entry has a single page 4145 * mapped at 0x00000000 a whole cache clean will be performed rather than 4146 * just the 1 page. Since this should not occur in everyday use and if it does 4147 * it will just result in not the most efficient clean for the page. 4148 */ 4149static int 4150pmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4151{ 4152 pmap_t pm, pm_to_clean = NULL; 4153 struct pv_entry *npv; 4154 u_int cache_needs_cleaning = 0; 4155 u_int flags = 0; 4156 vm_offset_t page_to_clean = 0; 4157 4158 if (pv == NULL) { 4159 /* nothing mapped in so nothing to flush */ 4160 return (0); 4161 } 4162 4163 /* 4164 * Since we flush the cache each time we change to a different 4165 * user vmspace, we only need to flush the page if it is in the 4166 * current pmap. 4167 */ 4168 if (curthread) 4169 pm = vmspace_pmap(curproc->p_vmspace); 4170 else 4171 pm = pmap_kernel(); 4172 4173 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4174 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4175 flags |= npv->pv_flags; 4176 /* 4177 * The page is mapped non-cacheable in 4178 * this map. No need to flush the cache. 4179 */ 4180 if (npv->pv_flags & PVF_NC) { 4181#ifdef DIAGNOSTIC 4182 if (cache_needs_cleaning) 4183 panic("pmap_clean_page: " 4184 "cache inconsistency"); 4185#endif 4186 break; 4187 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4188 continue; 4189 if (cache_needs_cleaning) { 4190 page_to_clean = 0; 4191 break; 4192 } else { 4193 page_to_clean = npv->pv_va; 4194 pm_to_clean = npv->pv_pmap; 4195 } 4196 cache_needs_cleaning = 1; 4197 } 4198 } 4199 if (page_to_clean) { 4200 if (PV_BEEN_EXECD(flags)) 4201 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4202 PAGE_SIZE); 4203 else 4204 pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4205 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4206 } else if (cache_needs_cleaning) { 4207 if (PV_BEEN_EXECD(flags)) 4208 pmap_idcache_wbinv_all(pm); 4209 else 4210 pmap_dcache_wbinv_all(pm); 4211 return (1); 4212 } 4213 return (0); 4214} 4215#endif 4216 4217/* 4218 * pmap_copy_page copies the specified (machine independent) 4219 * page by mapping the page into virtual memory and using 4220 * bcopy to copy the page, one machine dependent page at a 4221 * time. 4222 */ 4223 4224/* 4225 * pmap_copy_page() 4226 * 4227 * Copy one physical page into another, by mapping the pages into 4228 * hook points. The same comment regarding cachability as in 4229 * pmap_zero_page also applies here. 4230 */ 4231#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4232void 4233pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4234{ 4235#if 0 4236 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4237#endif 4238#ifdef DEBUG 4239 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4240 4241 if (dst_pg->md.pvh_list != NULL) 4242 panic("pmap_copy_page: dst page has mappings"); 4243#endif 4244 4245 4246 /* 4247 * Clean the source page. Hold the source page's lock for 4248 * the duration of the copy so that no other mappings can 4249 * be created while we have a potentially aliased mapping. 4250 */ 4251#if 0 4252 mtx_lock(&src_pg->md.pvh_mtx); 4253#endif 4254#if 0 4255 /* 4256 * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4257 * pmap_copy_page(). 4258 */ 4259 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4260#endif 4261 /* 4262 * Map the pages into the page hook points, copy them, and purge 4263 * the cache for the appropriate page. Invalidate the TLB 4264 * as required. 4265 */ 4266 *csrc_pte = L2_S_PROTO | src | 4267 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4268 PTE_SYNC(csrc_pte); 4269 *cdst_pte = L2_S_PROTO | dst | 4270 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4271 PTE_SYNC(cdst_pte); 4272 cpu_tlb_flushD_SE(csrcp); 4273 cpu_tlb_flushD_SE(cdstp); 4274 cpu_cpwait(); 4275 bcopy_page(csrcp, cdstp); 4276 cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4277#if 0 4278 mtx_lock(&src_pg->md.pvh_mtx); 4279#endif 4280 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4281} 4282#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4283 4284#if ARM_MMU_XSCALE == 1 4285void 4286pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4287{ 4288#if 0 4289 /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4290 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4291#endif 4292#ifdef DEBUG 4293 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4294 4295 if (dst_pg->md.pvh_list != NULL) 4296 panic("pmap_copy_page: dst page has mappings"); 4297#endif 4298 4299 4300 /* 4301 * Clean the source page. Hold the source page's lock for 4302 * the duration of the copy so that no other mappings can 4303 * be created while we have a potentially aliased mapping. 4304 */ 4305#if 0 4306 /* 4307 * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4308 * pmap_copy_page(). 4309 */ 4310 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4311#endif 4312 /* 4313 * Map the pages into the page hook points, copy them, and purge 4314 * the cache for the appropriate page. Invalidate the TLB 4315 * as required. 4316 */ 4317 *csrc_pte = L2_S_PROTO | src | 4318 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4319 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4320 PTE_SYNC(csrc_pte); 4321 *cdst_pte = L2_S_PROTO | dst | 4322 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4323 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4324 PTE_SYNC(cdst_pte); 4325 cpu_tlb_flushD_SE(csrcp); 4326 cpu_tlb_flushD_SE(cdstp); 4327 cpu_cpwait(); 4328 bcopy_page(csrcp, cdstp); 4329 xscale_cache_clean_minidata(); 4330} 4331#endif /* ARM_MMU_XSCALE == 1 */ 4332 4333void 4334pmap_copy_page(vm_page_t src, vm_page_t dst) 4335{ 4336 cpu_dcache_wbinv_all(); 4337 if (_arm_memcpy && 4338 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4339 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4340 return; 4341 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4342} 4343 4344 4345 4346 4347/* 4348 * this routine returns true if a physical page resides 4349 * in the given pmap. 4350 */ 4351boolean_t 4352pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4353{ 4354 pv_entry_t pv; 4355 int loops = 0; 4356 int s; 4357 4358 if (m->flags & PG_FICTITIOUS) 4359 return (FALSE); 4360 4361 s = splvm(); 4362 4363 /* 4364 * Not found, check current mappings returning immediately 4365 */ 4366 for (pv = TAILQ_FIRST(&m->md.pv_list); 4367 pv; 4368 pv = TAILQ_NEXT(pv, pv_list)) { 4369 if (pv->pv_pmap == pmap) { 4370 splx(s); 4371 return (TRUE); 4372 } 4373 loops++; 4374 if (loops >= 16) 4375 break; 4376 } 4377 splx(s); 4378 return (FALSE); 4379} 4380 4381 4382/* 4383 * pmap_ts_referenced: 4384 * 4385 * Return the count of reference bits for a page, clearing all of them. 4386 */ 4387int 4388pmap_ts_referenced(vm_page_t m) 4389{ 4390 return (pmap_clearbit(m, PVF_REF)); 4391} 4392 4393 4394boolean_t 4395pmap_is_modified(vm_page_t m) 4396{ 4397 4398 if (m->md.pvh_attrs & PVF_MOD) 4399 return (TRUE); 4400 4401 return(FALSE); 4402} 4403 4404 4405/* 4406 * Clear the modify bits on the specified physical page. 4407 */ 4408void 4409pmap_clear_modify(vm_page_t m) 4410{ 4411 4412 if (m->md.pvh_attrs & PVF_MOD) 4413 pmap_clearbit(m, PVF_MOD); 4414} 4415 4416 4417/* 4418 * pmap_clear_reference: 4419 * 4420 * Clear the reference bit on the specified physical page. 4421 */ 4422void 4423pmap_clear_reference(vm_page_t m) 4424{ 4425 4426 if (m->md.pvh_attrs & PVF_REF) 4427 pmap_clearbit(m, PVF_REF); 4428} 4429 4430 4431/* 4432 * perform the pmap work for mincore 4433 */ 4434int 4435pmap_mincore(pmap_t pmap, vm_offset_t addr) 4436{ 4437 printf("pmap_mincore()\n"); 4438 4439 return (0); 4440} 4441 4442 4443vm_offset_t 4444pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 4445{ 4446 4447 return(addr); 4448} 4449 4450 4451/* 4452 * Map a set of physical memory pages into the kernel virtual 4453 * address space. Return a pointer to where it is mapped. This 4454 * routine is intended to be used for mapping device memory, 4455 * NOT real memory. 4456 */ 4457void * 4458pmap_mapdev(vm_offset_t pa, vm_size_t size) 4459{ 4460 vm_offset_t va, tmpva, offset; 4461 4462 offset = pa & PAGE_MASK; 4463 size = roundup(size, PAGE_SIZE); 4464 4465 GIANT_REQUIRED; 4466 4467 va = kmem_alloc_nofault(kernel_map, size); 4468 if (!va) 4469 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4470 for (tmpva = va; size > 0;) { 4471 pmap_kenter_internal(tmpva, pa, 0); 4472 size -= PAGE_SIZE; 4473 tmpva += PAGE_SIZE; 4474 pa += PAGE_SIZE; 4475 } 4476 4477 return ((void *)(va + offset)); 4478} 4479 4480#define BOOTSTRAP_DEBUG 4481 4482/* 4483 * pmap_map_section: 4484 * 4485 * Create a single section mapping. 4486 */ 4487void 4488pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4489 int prot, int cache) 4490{ 4491 pd_entry_t *pde = (pd_entry_t *) l1pt; 4492 pd_entry_t fl; 4493 4494 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4495 4496 switch (cache) { 4497 case PTE_NOCACHE: 4498 default: 4499 fl = 0; 4500 break; 4501 4502 case PTE_CACHE: 4503 fl = pte_l1_s_cache_mode; 4504 break; 4505 4506 case PTE_PAGETABLE: 4507 fl = pte_l1_s_cache_mode_pt; 4508 break; 4509 } 4510 4511 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4512 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4513 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4514 4515} 4516 4517/* 4518 * pmap_link_l2pt: 4519 * 4520 * Link the L2 page table specified by "pa" into the L1 4521 * page table at the slot for "va". 4522 */ 4523void 4524pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4525{ 4526 pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4527 u_int slot = va >> L1_S_SHIFT; 4528 4529#ifndef ARM32_NEW_VM_LAYOUT 4530 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0, ("blah")); 4531 KASSERT((l2pv->pv_pa & PAGE_MASK) == 0, ("ouin")); 4532#endif 4533 4534 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4535 4536 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4537#ifdef ARM32_NEW_VM_LAYOUT 4538 PTE_SYNC(&pde[slot]); 4539#else 4540 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4541 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4542 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4543 PTE_SYNC_RANGE(&pde[slot + 0], 4); 4544#endif 4545 4546 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4547 4548 4549} 4550 4551/* 4552 * pmap_map_entry 4553 * 4554 * Create a single page mapping. 4555 */ 4556void 4557pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4558 int cache) 4559{ 4560 pd_entry_t *pde = (pd_entry_t *) l1pt; 4561 pt_entry_t fl; 4562 pt_entry_t *pte; 4563 4564 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4565 4566 switch (cache) { 4567 case PTE_NOCACHE: 4568 default: 4569 fl = 0; 4570 break; 4571 4572 case PTE_CACHE: 4573 fl = pte_l2_s_cache_mode; 4574 break; 4575 4576 case PTE_PAGETABLE: 4577 fl = pte_l2_s_cache_mode_pt; 4578 break; 4579 } 4580 4581 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4582 panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4583 4584#ifndef ARM32_NEW_VM_LAYOUT 4585 pte = (pt_entry_t *) 4586 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4587#else 4588 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4589#endif 4590 4591 if (pte == NULL) 4592 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4593 4594#ifndef ARM32_NEW_VM_LAYOUT 4595 pte[(va >> PAGE_SHIFT) & 0x3ff] = 4596 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4597 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]); 4598#else 4599 pte[l2pte_index(va)] = 4600 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4601 PTE_SYNC(&pte[l2pte_index(va)]); 4602#endif 4603} 4604 4605/* 4606 * pmap_map_chunk: 4607 * 4608 * Map a chunk of memory using the most efficient mappings 4609 * possible (section. large page, small page) into the 4610 * provided L1 and L2 tables at the specified virtual address. 4611 */ 4612vm_size_t 4613pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4614 vm_size_t size, int prot, int cache) 4615{ 4616 pd_entry_t *pde = (pd_entry_t *) l1pt; 4617 pt_entry_t *pte, f1, f2s, f2l; 4618 vm_size_t resid; 4619 int i; 4620 4621 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4622 4623 if (l1pt == 0) 4624 panic("pmap_map_chunk: no L1 table provided"); 4625 4626#ifdef VERBOSE_INIT_ARM 4627 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4628 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4629#endif 4630 4631 switch (cache) { 4632 case PTE_NOCACHE: 4633 default: 4634 f1 = 0; 4635 f2l = 0; 4636 f2s = 0; 4637 break; 4638 4639 case PTE_CACHE: 4640 f1 = pte_l1_s_cache_mode; 4641 f2l = pte_l2_l_cache_mode; 4642 f2s = pte_l2_s_cache_mode; 4643 break; 4644 4645 case PTE_PAGETABLE: 4646 f1 = pte_l1_s_cache_mode_pt; 4647 f2l = pte_l2_l_cache_mode_pt; 4648 f2s = pte_l2_s_cache_mode_pt; 4649 break; 4650 } 4651 4652 size = resid; 4653 4654 while (resid > 0) { 4655 /* See if we can use a section mapping. */ 4656 if (L1_S_MAPPABLE_P(va, pa, resid)) { 4657#ifdef VERBOSE_INIT_ARM 4658 printf("S"); 4659#endif 4660 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4661 L1_S_PROT(PTE_KERNEL, prot) | f1 | 4662 L1_S_DOM(PMAP_DOMAIN_KERNEL); 4663 PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4664 va += L1_S_SIZE; 4665 pa += L1_S_SIZE; 4666 resid -= L1_S_SIZE; 4667 continue; 4668 } 4669 4670 /* 4671 * Ok, we're going to use an L2 table. Make sure 4672 * one is actually in the corresponding L1 slot 4673 * for the current VA. 4674 */ 4675 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4676 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4677 4678#ifndef ARM32_NEW_VM_LAYOUT 4679 pte = (pt_entry_t *) 4680 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4681#else 4682 pte = (pt_entry_t *) kernel_pt_lookup( 4683 pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4684#endif 4685 if (pte == NULL) 4686 panic("pmap_map_chunk: can't find L2 table for VA" 4687 "0x%08x", va); 4688 /* See if we can use a L2 large page mapping. */ 4689 if (L2_L_MAPPABLE_P(va, pa, resid)) { 4690#ifdef VERBOSE_INIT_ARM 4691 printf("L"); 4692#endif 4693 for (i = 0; i < 16; i++) { 4694#ifndef ARM32_NEW_VM_LAYOUT 4695 pte[((va >> PAGE_SHIFT) & 0x3f0) + i] = 4696 L2_L_PROTO | pa | 4697 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4698 PTE_SYNC(&pte[((va >> PAGE_SHIFT) & 0x3f0) + i]); 4699#else 4700 pte[l2pte_index(va) + i] = 4701 L2_L_PROTO | pa | 4702 L2_L_PROT(PTE_KERNEL, prot) | f2l; 4703 PTE_SYNC(&pte[l2pte_index(va) + i]); 4704#endif 4705 } 4706 va += L2_L_SIZE; 4707 pa += L2_L_SIZE; 4708 resid -= L2_L_SIZE; 4709 continue; 4710 } 4711 4712 /* Use a small page mapping. */ 4713#ifdef VERBOSE_INIT_ARM 4714 printf("P"); 4715#endif 4716#ifndef ARM32_NEW_VM_LAYOUT 4717 pte[(va >> PAGE_SHIFT) & 0x3ff] = 4718 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4719 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]); 4720#else 4721 pte[l2pte_index(va)] = 4722 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4723 PTE_SYNC(&pte[l2pte_index(va)]); 4724#endif 4725 va += PAGE_SIZE; 4726 pa += PAGE_SIZE; 4727 resid -= PAGE_SIZE; 4728 } 4729#ifdef VERBOSE_INIT_ARM 4730 printf("\n"); 4731#endif 4732 return (size); 4733 4734} 4735 4736/********************** Static device map routines ***************************/ 4737 4738static const struct pmap_devmap *pmap_devmap_table; 4739 4740/* 4741 * Register the devmap table. This is provided in case early console 4742 * initialization needs to register mappings created by bootstrap code 4743 * before pmap_devmap_bootstrap() is called. 4744 */ 4745void 4746pmap_devmap_register(const struct pmap_devmap *table) 4747{ 4748 4749 pmap_devmap_table = table; 4750} 4751 4752/* 4753 * Map all of the static regions in the devmap table, and remember 4754 * the devmap table so other parts of the kernel can look up entries 4755 * later. 4756 */ 4757void 4758pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4759{ 4760 int i; 4761 4762 pmap_devmap_table = table; 4763 4764 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4765#ifdef VERBOSE_INIT_ARM 4766 printf("devmap: %08lx -> %08lx @ %08lx\n", 4767 pmap_devmap_table[i].pd_pa, 4768 pmap_devmap_table[i].pd_pa + 4769 pmap_devmap_table[i].pd_size - 1, 4770 pmap_devmap_table[i].pd_va); 4771#endif 4772 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4773 pmap_devmap_table[i].pd_pa, 4774 pmap_devmap_table[i].pd_size, 4775 pmap_devmap_table[i].pd_prot, 4776 pmap_devmap_table[i].pd_cache); 4777 } 4778} 4779 4780const struct pmap_devmap * 4781pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4782{ 4783 int i; 4784 4785 if (pmap_devmap_table == NULL) 4786 return (NULL); 4787 4788 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4789 if (pa >= pmap_devmap_table[i].pd_pa && 4790 pa + size <= pmap_devmap_table[i].pd_pa + 4791 pmap_devmap_table[i].pd_size) 4792 return (&pmap_devmap_table[i]); 4793 } 4794 4795 return (NULL); 4796} 4797 4798const struct pmap_devmap * 4799pmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4800{ 4801 int i; 4802 4803 if (pmap_devmap_table == NULL) 4804 return (NULL); 4805 4806 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4807 if (va >= pmap_devmap_table[i].pd_va && 4808 va + size <= pmap_devmap_table[i].pd_va + 4809 pmap_devmap_table[i].pd_size) 4810 return (&pmap_devmap_table[i]); 4811 } 4812 4813 return (NULL); 4814} 4815 4816