pmap-v4.c revision 137663
1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2129198Scognet/* 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38129198Scognet/* 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 3. All advertising materials mentioning features or use of this software 81129198Scognet * must display the following acknowledgement: 82129198Scognet * This product includes software developed by the NetBSD 83129198Scognet * Foundation, Inc. and its contributors. 84129198Scognet * 4. Neither the name of The NetBSD Foundation nor the names of its 85129198Scognet * contributors may be used to endorse or promote products derived 86129198Scognet * from this software without specific prior written permission. 87129198Scognet * 88129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 89129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 90129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 91129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 92129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 93129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 94129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 95129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 96129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 97129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 98129198Scognet * POSSIBILITY OF SUCH DAMAGE. 99129198Scognet */ 100129198Scognet 101129198Scognet/* 102129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 103129198Scognet * Copyright (c) 1994 Brini. 104129198Scognet * All rights reserved. 105129198Scognet * 106129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 107129198Scognet * 108129198Scognet * Redistribution and use in source and binary forms, with or without 109129198Scognet * modification, are permitted provided that the following conditions 110129198Scognet * are met: 111129198Scognet * 1. Redistributions of source code must retain the above copyright 112129198Scognet * notice, this list of conditions and the following disclaimer. 113129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 114129198Scognet * notice, this list of conditions and the following disclaimer in the 115129198Scognet * documentation and/or other materials provided with the distribution. 116129198Scognet * 3. All advertising materials mentioning features or use of this software 117129198Scognet * must display the following acknowledgement: 118129198Scognet * This product includes software developed by Mark Brinicombe. 119129198Scognet * 4. The name of the author may not be used to endorse or promote products 120129198Scognet * derived from this software without specific prior written permission. 121129198Scognet * 122129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 123129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 124129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 125129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 126129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 127129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 128129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 129129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 130129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 131129198Scognet * 132129198Scognet * RiscBSD kernel project 133129198Scognet * 134129198Scognet * pmap.c 135129198Scognet * 136129198Scognet * Machine dependant vm stuff 137129198Scognet * 138129198Scognet * Created : 20/09/94 139129198Scognet */ 140129198Scognet 141129198Scognet/* 142129198Scognet * Special compilation symbols 143129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 144129198Scognet */ 145129198Scognet/* Include header files */ 146135641Scognet 147137552Scognet#include "opt_vm.h" 148137552Scognet 149129198Scognet#include <sys/cdefs.h> 150129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/pmap.c 137663 2004-11-13 14:41:27Z cognet $"); 151129198Scognet#include <sys/param.h> 152129198Scognet#include <sys/systm.h> 153129198Scognet#include <sys/kernel.h> 154129198Scognet#include <sys/proc.h> 155129198Scognet#include <sys/malloc.h> 156129198Scognet#include <sys/msgbuf.h> 157129198Scognet#include <sys/vmmeter.h> 158129198Scognet#include <sys/mman.h> 159129198Scognet#include <sys/smp.h> 160129198Scognet#include <sys/sx.h> 161129198Scognet#include <sys/sched.h> 162129198Scognet 163129198Scognet#include <vm/vm.h> 164129198Scognet#include <vm/uma.h> 165129198Scognet#include <vm/pmap.h> 166129198Scognet#include <vm/vm_kern.h> 167129198Scognet#include <vm/vm_object.h> 168129198Scognet#include <vm/vm_map.h> 169129198Scognet#include <vm/vm_page.h> 170129198Scognet#include <vm/vm_pageout.h> 171129198Scognet#include <vm/vm_extern.h> 172129198Scognet#include <sys/lock.h> 173129198Scognet#include <sys/mutex.h> 174129198Scognet#include <machine/md_var.h> 175129198Scognet#include <machine/vmparam.h> 176129198Scognet#include <machine/cpu.h> 177129198Scognet#include <machine/cpufunc.h> 178129198Scognet#include <machine/pcb.h> 179129198Scognet 180129198Scognet#ifdef PMAP_DEBUG 181129198Scognet#define PDEBUG(_lev_,_stat_) \ 182129198Scognet if (pmap_debug_level >= (_lev_)) \ 183129198Scognet ((_stat_)) 184129198Scognet#define dprintf printf 185129198Scognet 186129198Scognetint pmap_debug_level = 0; 187135641Scognet#define PMAP_INLINE 188129198Scognet#else /* PMAP_DEBUG */ 189129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 190129198Scognet#define dprintf(x, arg...) 191135641Scognet#define PMAP_INLINE __inline 192129198Scognet#endif /* PMAP_DEBUG */ 193129198Scognet 194129198Scognetextern struct pv_addr systempage; 195129198Scognet/* 196129198Scognet * Internal function prototypes 197129198Scognet */ 198135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 199129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 200129198Scognet 201129198Scognetstatic void pmap_vac_me_harder(struct vm_page *, pmap_t, 202129198Scognet vm_offset_t); 203129198Scognetstatic void pmap_vac_me_kpmap(struct vm_page *, pmap_t, 204129198Scognet vm_offset_t); 205129198Scognetstatic void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t); 206129198Scognetstatic void pmap_alloc_l1(pmap_t); 207129198Scognetstatic void pmap_free_l1(pmap_t); 208129198Scognetstatic void pmap_use_l1(pmap_t); 209129198Scognet 210135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 211129198Scognet 212129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 213129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 214129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 215129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 216129198Scognet 217129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 218129198Scognet 219129198Scognetvm_offset_t avail_end; /* PA of last available physical page */ 220129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 221129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 222135641Scognetvm_offset_t pmap_curmaxkvaddr; 223129198Scognet 224129198Scognetextern void *end; 225129198Scognetvm_offset_t kernel_vm_end = 0; 226129198Scognet 227129198Scognetstruct pmap kernel_pmap_store; 228129198Scognetpmap_t kernel_pmap; 229129198Scognet 230129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 231129198Scognetstatic vm_offset_t csrcp, cdstp; 232129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 233129198Scognet/* 234129198Scognet * These routines are called when the CPU type is identified to set up 235129198Scognet * the PTE prototypes, cache modes, etc. 236129198Scognet * 237129198Scognet * The variables are always here, just in case LKMs need to reference 238129198Scognet * them (though, they shouldn't). 239129198Scognet */ 240129198Scognet 241129198Scognetpt_entry_t pte_l1_s_cache_mode; 242129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 243129198Scognetpt_entry_t pte_l1_s_cache_mask; 244129198Scognet 245129198Scognetpt_entry_t pte_l2_l_cache_mode; 246129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 247129198Scognetpt_entry_t pte_l2_l_cache_mask; 248129198Scognet 249129198Scognetpt_entry_t pte_l2_s_cache_mode; 250129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 251129198Scognetpt_entry_t pte_l2_s_cache_mask; 252129198Scognet 253129198Scognetpt_entry_t pte_l2_s_prot_u; 254129198Scognetpt_entry_t pte_l2_s_prot_w; 255129198Scognetpt_entry_t pte_l2_s_prot_mask; 256129198Scognet 257129198Scognetpt_entry_t pte_l1_s_proto; 258129198Scognetpt_entry_t pte_l1_c_proto; 259129198Scognetpt_entry_t pte_l2_s_proto; 260129198Scognet 261129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 262129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 263129198Scognet/* 264129198Scognet * Which pmap is currently 'live' in the cache 265129198Scognet * 266129198Scognet * XXXSCW: Fix for SMP ... 267129198Scognet */ 268129198Scognetunion pmap_cache_state *pmap_cache_state; 269129198Scognet 270129198ScognetLIST_HEAD(pmaplist, pmap); 271129198Scognetstruct pmaplist allpmaps; 272129198Scognet 273129198Scognetstatic boolean_t pmap_initialized = FALSE; /* Has pmap_init completed? */ 274129198Scognet 275129198Scognet/* static pt_entry_t *msgbufmap;*/ 276129198Scognetstruct msgbuf *msgbufp = 0; 277129198Scognet 278129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 279129198Scognetextern void bzero_page(vm_offset_t); 280137362Scognet 281137362Scognetchar *_tmppt; 282137362Scognet 283129198Scognet/* 284129198Scognet * Metadata for L1 translation tables. 285129198Scognet */ 286129198Scognetstruct l1_ttable { 287129198Scognet /* Entry on the L1 Table list */ 288129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 289129198Scognet 290129198Scognet /* Entry on the L1 Least Recently Used list */ 291129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 292129198Scognet 293129198Scognet /* Track how many domains are allocated from this L1 */ 294129198Scognet volatile u_int l1_domain_use_count; 295129198Scognet 296129198Scognet /* 297129198Scognet * A free-list of domain numbers for this L1. 298129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 299129198Scognet * is slow on ARM. 300129198Scognet */ 301129198Scognet u_int8_t l1_domain_first; 302129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 303129198Scognet 304129198Scognet /* Physical address of this L1 page table */ 305129198Scognet vm_paddr_t l1_physaddr; 306129198Scognet 307129198Scognet /* KVA of this L1 page table */ 308129198Scognet pd_entry_t *l1_kva; 309129198Scognet}; 310129198Scognet 311129198Scognet/* 312129198Scognet * Convert a virtual address into its L1 table index. That is, the 313129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 314129198Scognet * This is basically used to index l1->l1_kva[]. 315129198Scognet * 316129198Scognet * Each L2 descriptor table represents 1MB of VA space. 317129198Scognet */ 318129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 319129198Scognet 320129198Scognet/* 321129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 322129198Scognet * - New L1s are allocated from the HEAD. 323129198Scognet * - Freed L1s are added to the TAIl. 324129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 325129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 326129198Scognet */ 327129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 328135641Scognet/* 329135641Scognet * A list of all L1 tables 330135641Scognet */ 331135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 332129198Scognetstatic struct mtx l1_lru_lock; 333129198Scognet 334129198Scognet/* 335129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 336129198Scognet * 337129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 338129198Scognet * Reference counts are maintained for L2 descriptors so they can be 339129198Scognet * freed when empty. 340129198Scognet */ 341129198Scognetstruct l2_dtable { 342129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 343129198Scognet u_int l2_occupancy; 344129198Scognet 345129198Scognet /* List of L2 page descriptors */ 346129198Scognet struct l2_bucket { 347129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 348129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 349129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 350129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 351129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 352129198Scognet}; 353129198Scognet 354135641Scognet/* pmap_kenter_internal flags */ 355135641Scognet#define KENTER_CACHE 0x1 356135641Scognet 357129198Scognet/* 358129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 359129198Scognet * and bucket index within the l2_dtable. 360129198Scognet */ 361129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 362129198Scognet (L2_SIZE - 1)) 363129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 364129198Scognet 365129198Scognet/* 366129198Scognet * Given a virtual address, this macro returns the 367129198Scognet * virtual address required to drop into the next L2 bucket. 368129198Scognet */ 369129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 370129198Scognet 371129198Scognet/* 372129198Scognet * L2 allocation. 373129198Scognet */ 374129198Scognet#define pmap_alloc_l2_dtable() \ 375129198Scognet (void*)uma_zalloc(l2table_zone, M_NOWAIT) 376129198Scognet#define pmap_free_l2_dtable(l2) \ 377129198Scognet uma_zfree(l2table_zone, l2) 378129198Scognet 379129198Scognet/* 380129198Scognet * We try to map the page tables write-through, if possible. However, not 381129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 382129198Scognet * the cache when we frob page tables. 383129198Scognet * 384129198Scognet * We try to evaluate this at compile time, if possible. However, it's 385129198Scognet * not always possible to do that, hence this run-time var. 386129198Scognet */ 387129198Scognetint pmap_needs_pte_sync; 388129198Scognet 389129198Scognet/* 390129198Scognet * Macro to determine if a mapping might be resident in the 391129198Scognet * instruction cache and/or TLB 392129198Scognet */ 393129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 394129198Scognet 395129198Scognet/* 396129198Scognet * Macro to determine if a mapping might be resident in the 397129198Scognet * data cache and/or TLB 398129198Scognet */ 399129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 400129198Scognet 401129198Scognet/* 402129198Scognet * Data for the pv entry allocation mechanism 403129198Scognet */ 404129198Scognet#define MINPV 1024 405129198Scognet 406129198Scognet#ifndef PMAP_SHPGPERPROC 407129198Scognet#define PMAP_SHPGPERPROC 200 408129198Scognet#endif 409129198Scognet 410135641Scognet#define pmap_is_current(pm) ((pm) == pmap_kernel() || \ 411135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 412129198Scognetstatic uma_zone_t pvzone; 413129198Scognetstatic uma_zone_t l2zone; 414129198Scognetstatic uma_zone_t l2table_zone; 415135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 416135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 417135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 418129198Scognetstatic struct vm_object pvzone_obj; 419129198Scognetstatic struct vm_object l2zone_obj; 420129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 421129198Scognetint pmap_pagedaemon_waken = 0; 422129198Scognet 423129198Scognetvoid pmap_deactivate(struct thread *); 424129198Scognet 425129198Scognetvoid 426129198Scognetpmap_deactivate(struct thread *td) 427129198Scognet{ 428129198Scognet} 429129198Scognet/* 430129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 431129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 432129198Scognet * find them as necessary. 433129198Scognet * 434129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 435129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 436129198Scognet */ 437129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 438129198Scognet 439129198Scognetstatic void 440129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 441129198Scognet{ 442129198Scognet int i; 443129198Scognet 444129198Scognet l1->l1_kva = l1pt; 445129198Scognet l1->l1_domain_use_count = 0; 446129198Scognet l1->l1_domain_first = 0; 447129198Scognet 448129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 449129198Scognet l1->l1_domain_free[i] = i + 1; 450129198Scognet 451129198Scognet /* 452129198Scognet * Copy the kernel's L1 entries to each new L1. 453129198Scognet */ 454129198Scognet if (pmap_initialized) 455129198Scognet memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE); 456129198Scognet 457129198Scognet if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0) 458129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 459135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 460129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 461129198Scognet} 462129198Scognet 463129198Scognetstatic vm_offset_t 464129198Scognetkernel_pt_lookup(vm_paddr_t pa) 465129198Scognet{ 466129198Scognet struct pv_addr *pv; 467129198Scognet 468129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 469129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 470129198Scognet if (pv->pv_pa == (pa & ~PAGE_MASK)) { 471129198Scognet return (pv->pv_va | (pa & PAGE_MASK)); 472129198Scognet } 473129198Scognet#else 474129198Scognet if (pv->pv_pa == pa) 475129198Scognet return (pv->pv_va); 476129198Scognet#endif 477129198Scognet } 478129198Scognet return (0); 479129198Scognet} 480129198Scognet 481129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 482129198Scognetvoid 483129198Scognetpmap_pte_init_generic(void) 484129198Scognet{ 485129198Scognet 486129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 487129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 488129198Scognet 489129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 490129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 491129198Scognet 492129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 493129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 494129198Scognet 495129198Scognet /* 496129198Scognet * If we have a write-through cache, set B and C. If 497129198Scognet * we have a write-back cache, then we assume setting 498129198Scognet * only C will make those pages write-through. 499129198Scognet */ 500129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 501129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 502129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 503129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 504129198Scognet } else { 505129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 506129198Scognet pte_l2_l_cache_mode_pt = L2_C; 507129198Scognet pte_l2_s_cache_mode_pt = L2_C; 508129198Scognet } 509129198Scognet 510129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 511129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 512129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 513129198Scognet 514129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 515129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 516129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 517129198Scognet 518129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 519129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 520129198Scognet} 521129198Scognet 522129198Scognet#if defined(CPU_ARM8) 523129198Scognetvoid 524129198Scognetpmap_pte_init_arm8(void) 525129198Scognet{ 526129198Scognet 527129198Scognet /* 528129198Scognet * ARM8 is compatible with generic, but we need to use 529129198Scognet * the page tables uncached. 530129198Scognet */ 531129198Scognet pmap_pte_init_generic(); 532129198Scognet 533129198Scognet pte_l1_s_cache_mode_pt = 0; 534129198Scognet pte_l2_l_cache_mode_pt = 0; 535129198Scognet pte_l2_s_cache_mode_pt = 0; 536129198Scognet} 537129198Scognet#endif /* CPU_ARM8 */ 538129198Scognet 539129198Scognet#if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH) 540129198Scognetvoid 541129198Scognetpmap_pte_init_arm9(void) 542129198Scognet{ 543129198Scognet 544129198Scognet /* 545129198Scognet * ARM9 is compatible with generic, but we want to use 546129198Scognet * write-through caching for now. 547129198Scognet */ 548129198Scognet pmap_pte_init_generic(); 549129198Scognet 550129198Scognet pte_l1_s_cache_mode = L1_S_C; 551129198Scognet pte_l2_l_cache_mode = L2_C; 552129198Scognet pte_l2_s_cache_mode = L2_C; 553129198Scognet 554129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 555129198Scognet pte_l2_l_cache_mode_pt = L2_C; 556129198Scognet pte_l2_s_cache_mode_pt = L2_C; 557129198Scognet} 558129198Scognet#endif /* CPU_ARM9 */ 559129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 560129198Scognet 561129198Scognet#if defined(CPU_ARM10) 562129198Scognetvoid 563129198Scognetpmap_pte_init_arm10(void) 564129198Scognet{ 565129198Scognet 566129198Scognet /* 567129198Scognet * ARM10 is compatible with generic, but we want to use 568129198Scognet * write-through caching for now. 569129198Scognet */ 570129198Scognet pmap_pte_init_generic(); 571129198Scognet 572129198Scognet pte_l1_s_cache_mode = L1_S_B | L1_S_C; 573129198Scognet pte_l2_l_cache_mode = L2_B | L2_C; 574129198Scognet pte_l2_s_cache_mode = L2_B | L2_C; 575129198Scognet 576129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 577129198Scognet pte_l2_l_cache_mode_pt = L2_C; 578129198Scognet pte_l2_s_cache_mode_pt = L2_C; 579129198Scognet 580129198Scognet} 581129198Scognet#endif /* CPU_ARM10 */ 582129198Scognet 583129198Scognet#if ARM_MMU_SA1 == 1 584129198Scognetvoid 585129198Scognetpmap_pte_init_sa1(void) 586129198Scognet{ 587129198Scognet 588129198Scognet /* 589129198Scognet * The StrongARM SA-1 cache does not have a write-through 590129198Scognet * mode. So, do the generic initialization, then reset 591129198Scognet * the page table cache mode to B=1,C=1, and note that 592129198Scognet * the PTEs need to be sync'd. 593129198Scognet */ 594129198Scognet pmap_pte_init_generic(); 595129198Scognet 596129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 597129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 598129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 599129198Scognet 600129198Scognet pmap_needs_pte_sync = 1; 601129198Scognet} 602129198Scognet#endif /* ARM_MMU_SA1 == 1*/ 603129198Scognet 604129198Scognet#if ARM_MMU_XSCALE == 1 605129198Scognet#if (ARM_NMMUS > 1) 606129198Scognetstatic u_int xscale_use_minidata; 607129198Scognet#endif 608129198Scognet 609129198Scognetvoid 610129198Scognetpmap_pte_init_xscale(void) 611129198Scognet{ 612129198Scognet uint32_t auxctl; 613129198Scognet int write_through = 0; 614129198Scognet 615135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 616129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 617129198Scognet 618129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 619129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 620129198Scognet 621129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 622129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 623129198Scognet 624129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 625129198Scognet pte_l2_l_cache_mode_pt = L2_C; 626129198Scognet pte_l2_s_cache_mode_pt = L2_C; 627129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 628129198Scognet /* 629129198Scognet * The XScale core has an enhanced mode where writes that 630129198Scognet * miss the cache cause a cache line to be allocated. This 631129198Scognet * is significantly faster than the traditional, write-through 632129198Scognet * behavior of this case. 633129198Scognet */ 634129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 635129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 636129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 637129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 638129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 639129198Scognet /* 640129198Scognet * Some versions of the XScale core have various bugs in 641129198Scognet * their cache units, the work-around for which is to run 642129198Scognet * the cache in write-through mode. Unfortunately, this 643129198Scognet * has a major (negative) impact on performance. So, we 644129198Scognet * go ahead and run fast-and-loose, in the hopes that we 645129198Scognet * don't line up the planets in a way that will trip the 646129198Scognet * bugs. 647129198Scognet * 648129198Scognet * However, we give you the option to be slow-but-correct. 649129198Scognet */ 650129198Scognet write_through = 1; 651129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 652129198Scognet /* force write back cache mode */ 653129198Scognet write_through = 0; 654129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 655129198Scognet /* 656129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 657129198Scognet * write-back cache on revision 4 and earlier (stepping 658129198Scognet * A[01] and B[012]). Fixed for C0 and later. 659129198Scognet */ 660129198Scognet { 661129198Scognet uint32_t id, type; 662129198Scognet 663129198Scognet id = cpufunc_id(); 664129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 665129198Scognet 666129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 667129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 668129198Scognet /* write through for stepping A0-1 and B0-2 */ 669129198Scognet write_through = 1; 670129198Scognet } 671129198Scognet } 672129198Scognet } 673129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 674129198Scognet 675129198Scognet if (write_through) { 676129198Scognet pte_l1_s_cache_mode = L1_S_C; 677129198Scognet pte_l2_l_cache_mode = L2_C; 678129198Scognet pte_l2_s_cache_mode = L2_C; 679129198Scognet } 680129198Scognet 681129198Scognet#if (ARM_NMMUS > 1) 682129198Scognet xscale_use_minidata = 1; 683129198Scognet#endif 684129198Scognet 685129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 686129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 687129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 688129198Scognet 689129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 690129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 691129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 692129198Scognet 693129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 694129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 695129198Scognet 696129198Scognet /* 697129198Scognet * Disable ECC protection of page table access, for now. 698129198Scognet */ 699129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 700129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 701129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 702129198Scognet} 703129198Scognet 704129198Scognet/* 705129198Scognet * xscale_setup_minidata: 706129198Scognet * 707129198Scognet * Set up the mini-data cache clean area. We require the 708129198Scognet * caller to allocate the right amount of physically and 709129198Scognet * virtually contiguous space. 710129198Scognet */ 711129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 712129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 713129198Scognetvoid 714129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 715129198Scognet{ 716129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 717129198Scognet pt_entry_t *pte; 718129198Scognet vm_size_t size; 719129198Scognet uint32_t auxctl; 720129198Scognet 721129198Scognet xscale_minidata_clean_addr = va; 722129198Scognet 723129198Scognet /* Round it to page size. */ 724129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 725129198Scognet 726129198Scognet for (; size != 0; 727129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 728129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 729129198Scognet pte = (pt_entry_t *) 730129198Scognet kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 731129198Scognet#else 732129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 733129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 734129198Scognet#endif 735129198Scognet if (pte == NULL) 736129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 737129198Scognet "VA 0x%08x", (u_int32_t) va); 738129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 739129198Scognet pte[(va >> PAGE_SHIFT) & 0x3ff] = 740129198Scognet#else 741129198Scognet pte[l2pte_index(va)] = 742129198Scognet#endif 743129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 744129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 745129198Scognet } 746129198Scognet 747129198Scognet /* 748129198Scognet * Configure the mini-data cache for write-back with 749129198Scognet * read/write-allocate. 750129198Scognet * 751129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 752129198Scognet * make sure it contains no valid data! In order to do that, 753129198Scognet * we must issue a global data cache invalidate command! 754129198Scognet * 755129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 756129198Scognet * THIS IS VERY IMPORTANT! 757129198Scognet */ 758129198Scognet 759129198Scognet /* Invalidate data and mini-data. */ 760129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 761129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 762129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 763129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 764129198Scognet} 765129198Scognet#endif 766129198Scognet 767129198Scognet/* 768129198Scognet * Allocate an L1 translation table for the specified pmap. 769129198Scognet * This is called at pmap creation time. 770129198Scognet */ 771129198Scognetstatic void 772129198Scognetpmap_alloc_l1(pmap_t pm) 773129198Scognet{ 774129198Scognet struct l1_ttable *l1; 775129198Scognet u_int8_t domain; 776129198Scognet 777129198Scognet /* 778129198Scognet * Remove the L1 at the head of the LRU list 779129198Scognet */ 780129198Scognet mtx_lock(&l1_lru_lock); 781129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 782129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 783129198Scognet 784129198Scognet /* 785129198Scognet * Pick the first available domain number, and update 786129198Scognet * the link to the next number. 787129198Scognet */ 788129198Scognet domain = l1->l1_domain_first; 789129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 790129198Scognet 791129198Scognet /* 792129198Scognet * If there are still free domain numbers in this L1, 793129198Scognet * put it back on the TAIL of the LRU list. 794129198Scognet */ 795129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 796129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 797129198Scognet 798129198Scognet mtx_unlock(&l1_lru_lock); 799129198Scognet 800129198Scognet /* 801129198Scognet * Fix up the relevant bits in the pmap structure 802129198Scognet */ 803129198Scognet pm->pm_l1 = l1; 804129198Scognet pm->pm_domain = domain; 805129198Scognet} 806129198Scognet 807129198Scognet/* 808129198Scognet * Free an L1 translation table. 809129198Scognet * This is called at pmap destruction time. 810129198Scognet */ 811129198Scognetstatic void 812129198Scognetpmap_free_l1(pmap_t pm) 813129198Scognet{ 814129198Scognet struct l1_ttable *l1 = pm->pm_l1; 815129198Scognet 816129198Scognet mtx_lock(&l1_lru_lock); 817129198Scognet 818129198Scognet /* 819129198Scognet * If this L1 is currently on the LRU list, remove it. 820129198Scognet */ 821129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 822129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 823129198Scognet 824129198Scognet /* 825129198Scognet * Free up the domain number which was allocated to the pmap 826129198Scognet */ 827129198Scognet l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first; 828129198Scognet l1->l1_domain_first = pm->pm_domain; 829129198Scognet l1->l1_domain_use_count--; 830129198Scognet 831129198Scognet /* 832129198Scognet * The L1 now must have at least 1 free domain, so add 833129198Scognet * it back to the LRU list. If the use count is zero, 834129198Scognet * put it at the head of the list, otherwise it goes 835129198Scognet * to the tail. 836129198Scognet */ 837129198Scognet if (l1->l1_domain_use_count == 0) { 838129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 839129198Scognet } else 840129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 841129198Scognet 842129198Scognet mtx_unlock(&l1_lru_lock); 843129198Scognet} 844129198Scognet 845129198Scognetstatic PMAP_INLINE void 846129198Scognetpmap_use_l1(pmap_t pm) 847129198Scognet{ 848129198Scognet struct l1_ttable *l1; 849129198Scognet 850129198Scognet /* 851129198Scognet * Do nothing if we're in interrupt context. 852129198Scognet * Access to an L1 by the kernel pmap must not affect 853129198Scognet * the LRU list. 854129198Scognet */ 855129198Scognet if (pm == pmap_kernel()) 856129198Scognet return; 857129198Scognet 858129198Scognet l1 = pm->pm_l1; 859129198Scognet 860129198Scognet /* 861129198Scognet * If the L1 is not currently on the LRU list, just return 862129198Scognet */ 863129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) 864129198Scognet return; 865129198Scognet 866129198Scognet mtx_lock(&l1_lru_lock); 867129198Scognet 868129198Scognet /* 869129198Scognet * Check the use count again, now that we've acquired the lock 870129198Scognet */ 871129198Scognet if (l1->l1_domain_use_count == PMAP_DOMAINS) { 872129198Scognet mtx_unlock(&l1_lru_lock); 873129198Scognet return; 874129198Scognet } 875129198Scognet 876129198Scognet /* 877129198Scognet * Move the L1 to the back of the LRU list 878129198Scognet */ 879129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 880129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 881129198Scognet 882129198Scognet mtx_unlock(&l1_lru_lock); 883129198Scognet} 884129198Scognet 885129198Scognet 886129198Scognet/* 887129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 888129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 889129198Scognet */ 890129198Scognetstatic PMAP_INLINE struct l2_bucket * 891129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 892129198Scognet{ 893129198Scognet struct l2_dtable *l2; 894129198Scognet struct l2_bucket *l2b; 895129198Scognet u_short l1idx; 896129198Scognet 897129198Scognet l1idx = L1_IDX(va); 898129198Scognet 899129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 900129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 901129198Scognet return (NULL); 902129198Scognet 903129198Scognet return (l2b); 904129198Scognet} 905129198Scognet 906129198Scognet/* 907129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 908129198Scognet * and VA. 909129198Scognet * 910129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 911129198Scognet * bucket/page table in place. 912129198Scognet * 913129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 914129198Scognet * increment the bucket occupancy counter appropriately *before* 915129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 916129198Scognet * the bucket/page in the meantime. 917129198Scognet */ 918129198Scognetstatic struct l2_bucket * 919129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 920129198Scognet{ 921129198Scognet struct l2_dtable *l2; 922129198Scognet struct l2_bucket *l2b; 923129198Scognet u_short l1idx; 924129198Scognet 925129198Scognet l1idx = L1_IDX(va); 926129198Scognet 927129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 928129198Scognet /* 929129198Scognet * No mapping at this address, as there is 930129198Scognet * no entry in the L1 table. 931129198Scognet * Need to allocate a new l2_dtable. 932129198Scognet */ 933129198Scognet if ((l2 = pmap_alloc_l2_dtable()) == NULL) { 934129198Scognet return (NULL); 935129198Scognet } 936129198Scognet bzero(l2, sizeof(*l2)); 937129198Scognet /* 938129198Scognet * Link it into the parent pmap 939129198Scognet */ 940129198Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 941129198Scognet } 942129198Scognet 943129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 944129198Scognet 945129198Scognet /* 946129198Scognet * Fetch pointer to the L2 page table associated with the address. 947129198Scognet */ 948129198Scognet if (l2b->l2b_kva == NULL) { 949129198Scognet pt_entry_t *ptep; 950129198Scognet 951129198Scognet /* 952129198Scognet * No L2 page table has been allocated. Chances are, this 953129198Scognet * is because we just allocated the l2_dtable, above. 954129198Scognet */ 955129198Scognet ptep = (void*)uma_zalloc(l2zone, M_NOWAIT); 956129198Scognet l2b->l2b_phys = vtophys(ptep); 957129198Scognet if (ptep == NULL) { 958129198Scognet /* 959129198Scognet * Oops, no more L2 page tables available at this 960129198Scognet * time. We may need to deallocate the l2_dtable 961129198Scognet * if we allocated a new one above. 962129198Scognet */ 963129198Scognet if (l2->l2_occupancy == 0) { 964129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 965129198Scognet pmap_free_l2_dtable(l2); 966129198Scognet } 967129198Scognet return (NULL); 968129198Scognet } 969129198Scognet 970129198Scognet l2->l2_occupancy++; 971129198Scognet l2b->l2b_kva = ptep; 972129198Scognet l2b->l2b_l1idx = l1idx; 973129198Scognet } 974129198Scognet 975129198Scognet return (l2b); 976129198Scognet} 977129198Scognet 978129198Scognetstatic PMAP_INLINE void 979129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 980129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 981129198Scognet#else 982129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 983129198Scognet#endif 984129198Scognet{ 985129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 986129198Scognet /* 987129198Scognet * Note: With a write-back cache, we may need to sync this 988129198Scognet * L2 table before re-using it. 989129198Scognet * This is because it may have belonged to a non-current 990129198Scognet * pmap, in which case the cache syncs would have been 991129198Scognet * skipped when the pages were being unmapped. If the 992129198Scognet * L2 table were then to be immediately re-allocated to 993129198Scognet * the *current* pmap, it may well contain stale mappings 994129198Scognet * which have not yet been cleared by a cache write-back 995129198Scognet * and so would still be visible to the mmu. 996129198Scognet */ 997129198Scognet if (need_sync) 998129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 999129198Scognet#endif 1000129198Scognet uma_zfree(l2zone, l2); 1001129198Scognet} 1002129198Scognet/* 1003129198Scognet * One or more mappings in the specified L2 descriptor table have just been 1004129198Scognet * invalidated. 1005129198Scognet * 1006129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 1007129198Scognet * 1008129198Scognet * The pmap lock must be acquired when this is called (not necessary 1009129198Scognet * for the kernel pmap). 1010129198Scognet */ 1011129198Scognetstatic void 1012129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 1013129198Scognet{ 1014129198Scognet struct l2_dtable *l2; 1015129198Scognet pd_entry_t *pl1pd, l1pd; 1016129198Scognet pt_entry_t *ptep; 1017129198Scognet u_short l1idx; 1018129198Scognet 1019129198Scognet 1020129198Scognet /* 1021129198Scognet * Update the bucket's reference count according to how many 1022129198Scognet * PTEs the caller has just invalidated. 1023129198Scognet */ 1024129198Scognet l2b->l2b_occupancy -= count; 1025129198Scognet 1026129198Scognet /* 1027129198Scognet * Note: 1028129198Scognet * 1029129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 1030129198Scognet * as that would require checking all Level 1 page tables and 1031129198Scognet * removing any references to the Level 2 page table. See also the 1032129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 1033129198Scognet * 1034129198Scognet * We make do with just invalidating the mapping in the L2 table. 1035129198Scognet * 1036129198Scognet * This isn't really a big deal in practice and, in fact, leads 1037129198Scognet * to a performance win over time as we don't need to continually 1038129198Scognet * alloc/free. 1039129198Scognet */ 1040129198Scognet if (l2b->l2b_occupancy > 0 || pm == pmap_kernel()) 1041129198Scognet return; 1042129198Scognet 1043129198Scognet /* 1044129198Scognet * There are no more valid mappings in this level 2 page table. 1045129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 1046129198Scognet * free the page table. 1047129198Scognet */ 1048129198Scognet l1idx = l2b->l2b_l1idx; 1049129198Scognet ptep = l2b->l2b_kva; 1050129198Scognet l2b->l2b_kva = NULL; 1051129198Scognet 1052129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1053129198Scognet 1054129198Scognet /* 1055129198Scognet * If the L1 slot matches the pmap's domain 1056129198Scognet * number, then invalidate it. 1057129198Scognet */ 1058129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 1059129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 1060129198Scognet *pl1pd = 0; 1061129198Scognet PTE_SYNC(pl1pd); 1062129198Scognet } 1063129198Scognet 1064129198Scognet /* 1065129198Scognet * Release the L2 descriptor table back to the pool cache. 1066129198Scognet */ 1067129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1068129198Scognet pmap_free_l2_ptp(ptep); 1069129198Scognet#else 1070135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 1071129198Scognet#endif 1072129198Scognet 1073129198Scognet /* 1074129198Scognet * Update the reference count in the associated l2_dtable 1075129198Scognet */ 1076129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1077129198Scognet if (--l2->l2_occupancy > 0) 1078129198Scognet return; 1079129198Scognet 1080129198Scognet /* 1081129198Scognet * There are no more valid mappings in any of the Level 1 1082129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 1083129198Scognet * the pointer in the parent pmap and free the l2_dtable. 1084129198Scognet */ 1085129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 1086129198Scognet pmap_free_l2_dtable(l2); 1087129198Scognet} 1088129198Scognet 1089129198Scognet/* 1090129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 1091129198Scognet * structures. 1092129198Scognet */ 1093133237Scognetstatic int 1094133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 1095129198Scognet{ 1096129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 1097129198Scognet struct l2_bucket *l2b; 1098129198Scognet pt_entry_t *ptep, pte; 1099129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 1100129198Scognet 1101129198Scognet /* 1102129198Scognet * The mappings for these page tables were initially made using 1103135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1104129198Scognet * mode will not be right for page table mappings. To avoid 1105135641Scognet * polluting the pmap_kenter() code with a special case for 1106129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1107129198Scognet * correct. 1108129198Scognet */ 1109129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 1110129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1111129198Scognet pte = *ptep; 1112129198Scognet 1113129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1114129198Scognet /* 1115129198Scognet * Page tables must have the cache-mode set to Write-Thru. 1116129198Scognet */ 1117129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1118129198Scognet PTE_SYNC(ptep); 1119129198Scognet cpu_tlb_flushD_SE(va); 1120129198Scognet cpu_cpwait(); 1121129198Scognet } 1122135641Scognet 1123129198Scognet#endif 1124129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1125129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1126133237Scognet return (0); 1127129198Scognet} 1128129198Scognet 1129129198Scognet/* 1130129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1131129198Scognet * on whether the specified pmap actually needs to be flushed at any 1132129198Scognet * given time. 1133129198Scognet */ 1134129198Scognetstatic PMAP_INLINE void 1135129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1136129198Scognet{ 1137129198Scognet 1138135641Scognet if (pmap_is_current(pm)) 1139129198Scognet cpu_tlb_flushID_SE(va); 1140129198Scognet} 1141129198Scognet 1142129198Scognetstatic PMAP_INLINE void 1143129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1144129198Scognet{ 1145129198Scognet 1146135641Scognet if (pmap_is_current(pm)) 1147129198Scognet cpu_tlb_flushD_SE(va); 1148129198Scognet} 1149129198Scognet 1150129198Scognetstatic PMAP_INLINE void 1151129198Scognetpmap_tlb_flushID(pmap_t pm) 1152129198Scognet{ 1153129198Scognet 1154135641Scognet if (pmap_is_current(pm)) 1155129198Scognet cpu_tlb_flushID(); 1156129198Scognet} 1157129198Scognetstatic PMAP_INLINE void 1158129198Scognetpmap_tlb_flushD(pmap_t pm) 1159129198Scognet{ 1160129198Scognet 1161135641Scognet if (pmap_is_current(pm)) 1162129198Scognet cpu_tlb_flushD(); 1163129198Scognet} 1164129198Scognet 1165129198Scognetstatic PMAP_INLINE void 1166129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1167129198Scognet{ 1168129198Scognet 1169135641Scognet if (pmap_is_current(pm)) 1170129198Scognet cpu_idcache_wbinv_range(va, len); 1171129198Scognet} 1172129198Scognet 1173129198Scognetstatic PMAP_INLINE void 1174129198Scognetpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, 1175129198Scognet boolean_t do_inv, boolean_t rd_only) 1176129198Scognet{ 1177129198Scognet 1178135641Scognet if (pmap_is_current(pm)) { 1179129198Scognet if (do_inv) { 1180129198Scognet if (rd_only) 1181129198Scognet cpu_dcache_inv_range(va, len); 1182129198Scognet else 1183129198Scognet cpu_dcache_wbinv_range(va, len); 1184129198Scognet } else 1185129198Scognet if (!rd_only) 1186129198Scognet cpu_dcache_wb_range(va, len); 1187129198Scognet } 1188129198Scognet} 1189129198Scognet 1190129198Scognetstatic PMAP_INLINE void 1191129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1192129198Scognet{ 1193129198Scognet 1194135641Scognet if (pmap_is_current(pm)) 1195129198Scognet cpu_idcache_wbinv_all(); 1196129198Scognet} 1197129198Scognet 1198129198Scognetstatic PMAP_INLINE void 1199129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1200129198Scognet{ 1201129198Scognet 1202135641Scognet if (pmap_is_current(pm)) 1203129198Scognet cpu_dcache_wbinv_all(); 1204129198Scognet} 1205129198Scognet 1206129198Scognet/* 1207129198Scognet * PTE_SYNC_CURRENT: 1208129198Scognet * 1209129198Scognet * Make sure the pte is written out to RAM. 1210129198Scognet * We need to do this for one of two cases: 1211129198Scognet * - We're dealing with the kernel pmap 1212129198Scognet * - There is no pmap active in the cache/tlb. 1213129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1214129198Scognet */ 1215129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1216129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1217129198Scognetdo { \ 1218129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1219135641Scognet pmap_is_current(pm)) \ 1220129198Scognet PTE_SYNC(ptep); \ 1221129198Scognet} while (/*CONSTCOND*/0) 1222129198Scognet#else 1223129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1224129198Scognet#endif 1225129198Scognet 1226129198Scognet/* 1227129198Scognet * Since we have a virtually indexed cache, we may need to inhibit caching if 1228129198Scognet * there is more than one mapping and at least one of them is writable. 1229129198Scognet * Since we purge the cache on every context switch, we only need to check for 1230129198Scognet * other mappings within the same pmap, or kernel_pmap. 1231129198Scognet * This function is also called when a page is unmapped, to possibly reenable 1232129198Scognet * caching on any remaining mappings. 1233129198Scognet * 1234129198Scognet * The code implements the following logic, where: 1235129198Scognet * 1236129198Scognet * KW = # of kernel read/write pages 1237129198Scognet * KR = # of kernel read only pages 1238129198Scognet * UW = # of user read/write pages 1239129198Scognet * UR = # of user read only pages 1240129198Scognet * 1241129198Scognet * KC = kernel mapping is cacheable 1242129198Scognet * UC = user mapping is cacheable 1243129198Scognet * 1244129198Scognet * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0 1245129198Scognet * +--------------------------------------------- 1246129198Scognet * UW=0,UR=0 | --- KC=1 KC=1 KC=0 1247129198Scognet * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0 1248129198Scognet * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1249129198Scognet * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0 1250129198Scognet */ 1251129198Scognet 1252129198Scognetstatic const int pmap_vac_flags[4][4] = { 1253129198Scognet {-1, 0, 0, PVF_KNC}, 1254129198Scognet {0, 0, PVF_NC, PVF_NC}, 1255129198Scognet {0, PVF_NC, PVF_NC, PVF_NC}, 1256129198Scognet {PVF_UNC, PVF_NC, PVF_NC, PVF_NC} 1257129198Scognet}; 1258129198Scognet 1259129198Scognetstatic PMAP_INLINE int 1260129198Scognetpmap_get_vac_flags(const struct vm_page *pg) 1261129198Scognet{ 1262129198Scognet int kidx, uidx; 1263129198Scognet 1264129198Scognet kidx = 0; 1265129198Scognet if (pg->md.kro_mappings || pg->md.krw_mappings > 1) 1266129198Scognet kidx |= 1; 1267129198Scognet if (pg->md.krw_mappings) 1268129198Scognet kidx |= 2; 1269129198Scognet 1270129198Scognet uidx = 0; 1271129198Scognet if (pg->md.uro_mappings || pg->md.urw_mappings > 1) 1272129198Scognet uidx |= 1; 1273129198Scognet if (pg->md.urw_mappings) 1274129198Scognet uidx |= 2; 1275129198Scognet 1276129198Scognet return (pmap_vac_flags[uidx][kidx]); 1277129198Scognet} 1278129198Scognet 1279129198Scognetstatic __inline void 1280129198Scognetpmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1281129198Scognet{ 1282129198Scognet int nattr; 1283129198Scognet 1284129198Scognet nattr = pmap_get_vac_flags(pg); 1285129198Scognet 1286129198Scognet if (nattr < 0) { 1287129198Scognet pg->md.pvh_attrs &= ~PVF_NC; 1288129198Scognet return; 1289129198Scognet } 1290129198Scognet 1291129198Scognet if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) { 1292129198Scognet return; 1293129198Scognet } 1294129198Scognet 1295129198Scognet if (pm == pmap_kernel()) 1296129198Scognet pmap_vac_me_kpmap(pg, pm, va); 1297129198Scognet else 1298129198Scognet pmap_vac_me_user(pg, pm, va); 1299129198Scognet 1300129198Scognet pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr; 1301129198Scognet} 1302129198Scognet 1303129198Scognetstatic void 1304129198Scognetpmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1305129198Scognet{ 1306129198Scognet u_int u_cacheable, u_entries; 1307129198Scognet struct pv_entry *pv; 1308129198Scognet pmap_t last_pmap = pm; 1309129198Scognet 1310129198Scognet /* 1311129198Scognet * Pass one, see if there are both kernel and user pmaps for 1312129198Scognet * this page. Calculate whether there are user-writable or 1313129198Scognet * kernel-writable pages. 1314129198Scognet */ 1315129198Scognet u_cacheable = 0; 1316129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1317129198Scognet if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0) 1318129198Scognet u_cacheable++; 1319129198Scognet } 1320129198Scognet 1321129198Scognet u_entries = pg->md.urw_mappings + pg->md.uro_mappings; 1322129198Scognet 1323129198Scognet /* 1324129198Scognet * We know we have just been updating a kernel entry, so if 1325129198Scognet * all user pages are already cacheable, then there is nothing 1326129198Scognet * further to do. 1327129198Scognet */ 1328129198Scognet if (pg->md.k_mappings == 0 && u_cacheable == u_entries) 1329129198Scognet return; 1330129198Scognet 1331129198Scognet if (u_entries) { 1332129198Scognet /* 1333129198Scognet * Scan over the list again, for each entry, if it 1334129198Scognet * might not be set correctly, call pmap_vac_me_user 1335129198Scognet * to recalculate the settings. 1336129198Scognet */ 1337129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1338129198Scognet /* 1339129198Scognet * We know kernel mappings will get set 1340129198Scognet * correctly in other calls. We also know 1341129198Scognet * that if the pmap is the same as last_pmap 1342129198Scognet * then we've just handled this entry. 1343129198Scognet */ 1344129198Scognet if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap) 1345129198Scognet continue; 1346129198Scognet 1347129198Scognet /* 1348129198Scognet * If there are kernel entries and this page 1349129198Scognet * is writable but non-cacheable, then we can 1350129198Scognet * skip this entry also. 1351129198Scognet */ 1352129198Scognet if (pg->md.k_mappings && 1353129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 1354129198Scognet (PVF_NC | PVF_WRITE)) 1355129198Scognet continue; 1356129198Scognet 1357129198Scognet /* 1358129198Scognet * Similarly if there are no kernel-writable 1359129198Scognet * entries and the page is already 1360129198Scognet * read-only/cacheable. 1361129198Scognet */ 1362129198Scognet if (pg->md.krw_mappings == 0 && 1363129198Scognet (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0) 1364129198Scognet continue; 1365129198Scognet 1366129198Scognet /* 1367129198Scognet * For some of the remaining cases, we know 1368129198Scognet * that we must recalculate, but for others we 1369129198Scognet * can't tell if they are correct or not, so 1370129198Scognet * we recalculate anyway. 1371129198Scognet */ 1372129198Scognet pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0); 1373129198Scognet } 1374129198Scognet 1375129198Scognet if (pg->md.k_mappings == 0) 1376129198Scognet return; 1377129198Scognet } 1378129198Scognet 1379129198Scognet pmap_vac_me_user(pg, pm, va); 1380129198Scognet} 1381129198Scognet 1382129198Scognetstatic void 1383129198Scognetpmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1384129198Scognet{ 1385129198Scognet pmap_t kpmap = pmap_kernel(); 1386129198Scognet struct pv_entry *pv, *npv; 1387129198Scognet struct l2_bucket *l2b; 1388129198Scognet pt_entry_t *ptep, pte; 1389129198Scognet u_int entries = 0; 1390129198Scognet u_int writable = 0; 1391129198Scognet u_int cacheable_entries = 0; 1392129198Scognet u_int kern_cacheable = 0; 1393129198Scognet u_int other_writable = 0; 1394129198Scognet 1395129198Scognet /* 1396129198Scognet * Count mappings and writable mappings in this pmap. 1397129198Scognet * Include kernel mappings as part of our own. 1398129198Scognet * Keep a pointer to the first one. 1399129198Scognet */ 1400129198Scognet npv = TAILQ_FIRST(&pg->md.pv_list); 1401129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1402129198Scognet /* Count mappings in the same pmap */ 1403129198Scognet if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) { 1404129198Scognet if (entries++ == 0) 1405129198Scognet npv = pv; 1406129198Scognet 1407129198Scognet /* Cacheable mappings */ 1408129198Scognet if ((pv->pv_flags & PVF_NC) == 0) { 1409129198Scognet cacheable_entries++; 1410129198Scognet if (kpmap == pv->pv_pmap) 1411129198Scognet kern_cacheable++; 1412129198Scognet } 1413129198Scognet 1414129198Scognet /* Writable mappings */ 1415129198Scognet if (pv->pv_flags & PVF_WRITE) 1416129198Scognet ++writable; 1417129198Scognet } else 1418129198Scognet if (pv->pv_flags & PVF_WRITE) 1419129198Scognet other_writable = 1; 1420129198Scognet } 1421129198Scognet 1422129198Scognet /* 1423129198Scognet * Enable or disable caching as necessary. 1424129198Scognet * Note: the first entry might be part of the kernel pmap, 1425129198Scognet * so we can't assume this is indicative of the state of the 1426129198Scognet * other (maybe non-kpmap) entries. 1427129198Scognet */ 1428129198Scognet if ((entries > 1 && writable) || 1429129198Scognet (entries > 0 && pm == kpmap && other_writable)) { 1430129198Scognet if (cacheable_entries == 0) 1431129198Scognet return; 1432129198Scognet 1433129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1434129198Scognet if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) || 1435129198Scognet (pv->pv_flags & PVF_NC)) 1436129198Scognet continue; 1437129198Scognet 1438129198Scognet pv->pv_flags |= PVF_NC; 1439129198Scognet 1440129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1441129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1442129198Scognet pte = *ptep & ~L2_S_CACHE_MASK; 1443129198Scognet 1444129198Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1445129198Scognet l2pte_valid(pte)) { 1446129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1447129198Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1448129198Scognet pv->pv_va, PAGE_SIZE); 1449129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1450129198Scognet pv->pv_va); 1451129198Scognet } else 1452129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1453129198Scognet pmap_dcache_wb_range(pv->pv_pmap, 1454129198Scognet pv->pv_va, PAGE_SIZE, TRUE, 1455129198Scognet (pv->pv_flags & PVF_WRITE) == 0); 1456129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1457129198Scognet pv->pv_va); 1458129198Scognet } 1459129198Scognet } 1460129198Scognet 1461129198Scognet *ptep = pte; 1462129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1463129198Scognet } 1464129198Scognet cpu_cpwait(); 1465129198Scognet } else 1466129198Scognet if (entries > cacheable_entries) { 1467129198Scognet /* 1468129198Scognet * Turn cacheing back on for some pages. If it is a kernel 1469129198Scognet * page, only do so if there are no other writable pages. 1470129198Scognet */ 1471129198Scognet for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) { 1472129198Scognet if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap && 1473129198Scognet (kpmap != pv->pv_pmap || other_writable))) 1474129198Scognet continue; 1475129198Scognet 1476129198Scognet pv->pv_flags &= ~PVF_NC; 1477129198Scognet 1478129198Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1479129198Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1480129198Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1481129198Scognet 1482129198Scognet if (l2pte_valid(pte)) { 1483129198Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1484129198Scognet pmap_tlb_flushID_SE(pv->pv_pmap, 1485129198Scognet pv->pv_va); 1486129198Scognet } else 1487129198Scognet if (PV_BEEN_REFD(pv->pv_flags)) { 1488129198Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1489129198Scognet pv->pv_va); 1490129198Scognet } 1491129198Scognet } 1492129198Scognet 1493129198Scognet *ptep = pte; 1494129198Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1495129198Scognet } 1496129198Scognet } 1497129198Scognet} 1498129198Scognet 1499129198Scognet/* 1500129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1501129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1502129198Scognet * constants and the latter would require an extra inversion at run-time. 1503129198Scognet */ 1504135641Scognetstatic int 1505129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1506129198Scognet{ 1507129198Scognet struct l2_bucket *l2b; 1508129198Scognet struct pv_entry *pv; 1509129198Scognet pt_entry_t *ptep, npte, opte; 1510129198Scognet pmap_t pm; 1511129198Scognet vm_offset_t va; 1512129198Scognet u_int oflags; 1513135641Scognet int count = 0; 1514129198Scognet#if 0 1515129198Scognet PMAP_HEAD_TO_MAP_LOCK(); 1516129198Scognet simple_lock(&pg->mdpage.pvh_slock); 1517129198Scognet#endif 1518129198Scognet 1519129198Scognet /* 1520129198Scognet * Clear saved attributes (modify, reference) 1521129198Scognet */ 1522129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1523129198Scognet 1524129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1525129198Scognet#if 0 1526129198Scognet simple_unlock(&pg->mdpage.pvh_slock); 1527129198Scognet PMAP_HEAD_TO_MAP_UNLOCK(); 1528129198Scognet#endif 1529135641Scognet return (0); 1530129198Scognet } 1531129198Scognet 1532129198Scognet /* 1533129198Scognet * Loop over all current mappings setting/clearing as appropos 1534129198Scognet */ 1535129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1536129198Scognet va = pv->pv_va; 1537129198Scognet pm = pv->pv_pmap; 1538129198Scognet oflags = pv->pv_flags; 1539129198Scognet pv->pv_flags &= ~maskbits; 1540135641Scognet pmap_update(pv->pv_pmap); 1541129198Scognet 1542129198Scognet#if 0 1543129198Scognet pmap_acquire_pmap_lock(pm); 1544129198Scognet#endif 1545129198Scognet 1546129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1547129198Scognet 1548129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1549129198Scognet npte = opte = *ptep; 1550129198Scognet 1551129198Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1552129198Scognet if ((pv->pv_flags & PVF_NC)) { 1553129198Scognet /* 1554129198Scognet * Entry is not cacheable: 1555129198Scognet * 1556129198Scognet * Don't turn caching on again if this is a 1557129198Scognet * modified emulation. This would be 1558129198Scognet * inconsitent with the settings created by 1559129198Scognet * pmap_vac_me_harder(). Otherwise, it's safe 1560129198Scognet * to re-enable cacheing. 1561129198Scognet * 1562129198Scognet * There's no need to call pmap_vac_me_harder() 1563129198Scognet * here: all pages are losing their write 1564129198Scognet * permission. 1565129198Scognet */ 1566129198Scognet if (maskbits & PVF_WRITE) { 1567129198Scognet npte |= pte_l2_s_cache_mode; 1568129198Scognet pv->pv_flags &= ~PVF_NC; 1569129198Scognet } 1570129198Scognet } else 1571129198Scognet if (opte & L2_S_PROT_W) { 1572129198Scognet /* 1573129198Scognet * Entry is writable/cacheable: check if pmap 1574129198Scognet * is current if it is flush it, otherwise it 1575129198Scognet * won't be in the cache 1576129198Scognet */ 1577129198Scognet if (PV_BEEN_EXECD(oflags)) 1578129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1579129198Scognet PAGE_SIZE); 1580129198Scognet else 1581129198Scognet if (PV_BEEN_REFD(oflags)) 1582129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1583129198Scognet PAGE_SIZE, 1584129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1585129198Scognet FALSE); 1586129198Scognet } 1587129198Scognet 1588129198Scognet /* make the pte read only */ 1589129198Scognet npte &= ~L2_S_PROT_W; 1590129198Scognet 1591129198Scognet if (maskbits & PVF_WRITE) { 1592129198Scognet /* 1593129198Scognet * Keep alias accounting up to date 1594129198Scognet */ 1595129198Scognet if (pv->pv_pmap == pmap_kernel()) { 1596129198Scognet if (oflags & PVF_WRITE) { 1597129198Scognet pg->md.krw_mappings--; 1598129198Scognet pg->md.kro_mappings++; 1599129198Scognet } 1600129198Scognet } else 1601129198Scognet if (oflags & PVF_WRITE) { 1602129198Scognet pg->md.urw_mappings--; 1603129198Scognet pg->md.uro_mappings++; 1604129198Scognet } 1605129198Scognet } 1606129198Scognet } 1607129198Scognet 1608129198Scognet if (maskbits & PVF_REF) { 1609129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1610129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1611129198Scognet /* 1612129198Scognet * Check npte here; we may have already 1613129198Scognet * done the wbinv above, and the validity 1614129198Scognet * of the PTE is the same for opte and 1615129198Scognet * npte. 1616129198Scognet */ 1617129198Scognet if (npte & L2_S_PROT_W) { 1618129198Scognet if (PV_BEEN_EXECD(oflags)) 1619129198Scognet pmap_idcache_wbinv_range(pm, 1620129198Scognet pv->pv_va, PAGE_SIZE); 1621129198Scognet else 1622129198Scognet if (PV_BEEN_REFD(oflags)) 1623129198Scognet pmap_dcache_wb_range(pm, 1624129198Scognet pv->pv_va, PAGE_SIZE, 1625129198Scognet TRUE, FALSE); 1626129198Scognet } else 1627129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1628129198Scognet /* XXXJRT need idcache_inv_range */ 1629129198Scognet if (PV_BEEN_EXECD(oflags)) 1630129198Scognet pmap_idcache_wbinv_range(pm, 1631129198Scognet pv->pv_va, PAGE_SIZE); 1632129198Scognet else 1633129198Scognet if (PV_BEEN_REFD(oflags)) 1634129198Scognet pmap_dcache_wb_range(pm, 1635129198Scognet pv->pv_va, PAGE_SIZE, 1636129198Scognet TRUE, TRUE); 1637129198Scognet } 1638129198Scognet } 1639129198Scognet 1640129198Scognet /* 1641129198Scognet * Make the PTE invalid so that we will take a 1642129198Scognet * page fault the next time the mapping is 1643129198Scognet * referenced. 1644129198Scognet */ 1645129198Scognet npte &= ~L2_TYPE_MASK; 1646129198Scognet npte |= L2_TYPE_INV; 1647129198Scognet } 1648129198Scognet 1649129198Scognet if (npte != opte) { 1650135641Scognet count++; 1651129198Scognet *ptep = npte; 1652129198Scognet PTE_SYNC(ptep); 1653129198Scognet /* Flush the TLB entry if a current pmap. */ 1654129198Scognet if (PV_BEEN_EXECD(oflags)) 1655129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1656129198Scognet else 1657129198Scognet if (PV_BEEN_REFD(oflags)) 1658129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1659129198Scognet } 1660129198Scognet 1661129198Scognet#if 0 1662129198Scognet pmap_release_pmap_lock(pm); 1663129198Scognet#endif 1664129198Scognet 1665129198Scognet } 1666129198Scognet 1667129198Scognet#if 0 1668129198Scognet simple_unlock(&pg->mdpage.pvh_slock); 1669129198Scognet PMAP_HEAD_TO_MAP_UNLOCK(); 1670129198Scognet#endif 1671135641Scognet return (count); 1672129198Scognet} 1673129198Scognet 1674129198Scognet/* 1675129198Scognet * main pv_entry manipulation functions: 1676129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1677129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1678129198Scognet * 1679129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1680129198Scognet * pmap_remove_pv expects te caller to lock the pvh before calling 1681129198Scognet */ 1682129198Scognet 1683129198Scognet/* 1684129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page lst 1685129198Scognet * 1686129198Scognet * => caller should hold the proper lock on pmap_main_lock 1687129198Scognet * => caller should have pmap locked 1688129198Scognet * => we will gain the lock on the vm_page and allocate the new pv_entry 1689129198Scognet * => caller should adjust ptp's wire_count before calling 1690129198Scognet * => caller should not adjust pmap's wire_count 1691129198Scognet */ 1692129198Scognetstatic void 1693129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1694129198Scognet vm_offset_t va, u_int flags) 1695129198Scognet{ 1696129198Scognet 1697129198Scognet 1698129198Scognet pve->pv_pmap = pm; 1699129198Scognet pve->pv_va = va; 1700129198Scognet pve->pv_flags = flags; 1701129198Scognet 1702129198Scognet#if 0 1703129198Scognet mtx_lock(&pg->md.pvh_mtx); 1704129198Scognet#endif 1705129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1706129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1707129198Scognet if (pm == pmap_kernel()) { 1708129198Scognet if (flags & PVF_WRITE) 1709129198Scognet pg->md.krw_mappings++; 1710129198Scognet else 1711129198Scognet pg->md.kro_mappings++; 1712129198Scognet } 1713129198Scognet if (flags & PVF_WRITE) 1714129198Scognet pg->md.urw_mappings++; 1715129198Scognet else 1716129198Scognet pg->md.uro_mappings++; 1717135641Scognet pg->md.pv_list_count++; 1718129198Scognet#if 0 1719129198Scognet mtx_unlock(&pg->md.pvh_mtx); 1720129198Scognet#endif 1721129198Scognet if (pve->pv_flags & PVF_WIRED) 1722129198Scognet ++pm->pm_stats.wired_count; 1723129198Scognet} 1724129198Scognet 1725129198Scognet/* 1726129198Scognet * 1727129198Scognet * pmap_find_pv: Find a pv entry 1728129198Scognet * 1729129198Scognet * => caller should hold lock on vm_page 1730129198Scognet */ 1731129198Scognetstatic PMAP_INLINE struct pv_entry * 1732129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1733129198Scognet{ 1734129198Scognet struct pv_entry *pv; 1735129198Scognet 1736129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1737129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1738129198Scognet break; 1739129198Scognet return (pv); 1740129198Scognet} 1741129198Scognet 1742129198Scognet/* 1743129198Scognet * vector_page_setprot: 1744129198Scognet * 1745129198Scognet * Manipulate the protection of the vector page. 1746129198Scognet */ 1747129198Scognetvoid 1748129198Scognetvector_page_setprot(int prot) 1749129198Scognet{ 1750129198Scognet struct l2_bucket *l2b; 1751129198Scognet pt_entry_t *ptep; 1752129198Scognet 1753129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page); 1754129198Scognet 1755129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1756129198Scognet 1757129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1758129198Scognet PTE_SYNC(ptep); 1759129198Scognet cpu_tlb_flushD_SE(vector_page); 1760129198Scognet cpu_cpwait(); 1761129198Scognet} 1762129198Scognet 1763129198Scognet/* 1764129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1765129198Scognet * 1766129198Scognet * => caller should hold proper lock on pmap_main_lock 1767129198Scognet * => pmap should be locked 1768129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1769129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1770129198Scognet * => caller should NOT adjust pmap's wire_count 1771129198Scognet * => we return the removed pve 1772129198Scognet */ 1773135641Scognet 1774135641Scognetstatic void 1775135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1776135641Scognet{ 1777135641Scognet 1778135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1779135641Scognet if (pve->pv_flags & PVF_WIRED) 1780135641Scognet --pm->pm_stats.wired_count; 1781135641Scognet pg->md.pv_list_count--; 1782135641Scognet if (pm == pmap_kernel()) { 1783135641Scognet if (pve->pv_flags & PVF_WRITE) 1784135641Scognet pg->md.krw_mappings--; 1785135641Scognet else 1786135641Scognet pg->md.kro_mappings--; 1787135641Scognet } else 1788135641Scognet if (pve->pv_flags & PVF_WRITE) 1789135641Scognet pg->md.urw_mappings--; 1790135641Scognet else 1791135641Scognet pg->md.uro_mappings--; 1792135641Scognet} 1793135641Scognet 1794129198Scognetstatic struct pv_entry * 1795129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1796129198Scognet{ 1797135641Scognet struct pv_entry *pve; 1798129198Scognet 1799135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1800129198Scognet 1801129198Scognet while (pve) { 1802129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1803135641Scognet pmap_nuke_pv(pg, pm, pve); 1804129198Scognet break; 1805129198Scognet } 1806129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1807129198Scognet } 1808129198Scognet 1809129198Scognet return(pve); /* return removed pve */ 1810129198Scognet} 1811129198Scognet/* 1812129198Scognet * 1813129198Scognet * pmap_modify_pv: Update pv flags 1814129198Scognet * 1815129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1816129198Scognet * => caller should NOT adjust pmap's wire_count 1817129198Scognet * => caller must call pmap_vac_me_harder() if writable status of a page 1818129198Scognet * may have changed. 1819129198Scognet * => we return the old flags 1820129198Scognet * 1821129198Scognet * Modify a physical-virtual mapping in the pv table 1822129198Scognet */ 1823129198Scognetstatic u_int 1824129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1825129198Scognet u_int clr_mask, u_int set_mask) 1826129198Scognet{ 1827129198Scognet struct pv_entry *npv; 1828129198Scognet u_int flags, oflags; 1829129198Scognet 1830129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1831129198Scognet return (0); 1832129198Scognet 1833129198Scognet /* 1834129198Scognet * There is at least one VA mapping this page. 1835129198Scognet */ 1836129198Scognet 1837129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1838129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1839129198Scognet 1840129198Scognet oflags = npv->pv_flags; 1841129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1842129198Scognet 1843129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1844129198Scognet if (flags & PVF_WIRED) 1845129198Scognet ++pm->pm_stats.wired_count; 1846129198Scognet else 1847129198Scognet --pm->pm_stats.wired_count; 1848129198Scognet } 1849129198Scognet 1850129198Scognet if ((flags ^ oflags) & PVF_WRITE) { 1851129198Scognet if (pm == pmap_kernel()) { 1852129198Scognet if (flags & PVF_WRITE) { 1853129198Scognet pg->md.krw_mappings++; 1854129198Scognet pg->md.kro_mappings--; 1855129198Scognet } else { 1856129198Scognet pg->md.kro_mappings++; 1857129198Scognet pg->md.krw_mappings--; 1858129198Scognet } 1859129198Scognet } else 1860129198Scognet if (flags & PVF_WRITE) { 1861129198Scognet pg->md.urw_mappings++; 1862129198Scognet pg->md.uro_mappings--; 1863129198Scognet } else { 1864129198Scognet pg->md.uro_mappings++; 1865129198Scognet pg->md.urw_mappings--; 1866129198Scognet } 1867129198Scognet } 1868129198Scognet 1869129198Scognet return (oflags); 1870129198Scognet} 1871129198Scognet 1872129198Scognet/* Function to set the debug level of the pmap code */ 1873129198Scognet#ifdef PMAP_DEBUG 1874129198Scognetvoid 1875129198Scognetpmap_debug(int level) 1876129198Scognet{ 1877129198Scognet pmap_debug_level = level; 1878129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1879129198Scognet} 1880129198Scognet#endif /* PMAP_DEBUG */ 1881129198Scognet 1882129198Scognetvoid 1883129198Scognetpmap_pinit0(struct pmap *pmap) 1884129198Scognet{ 1885129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1886129198Scognet 1887129198Scognet dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n", 1888129198Scognet (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir); 1889135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1890129198Scognet} 1891129198Scognet 1892129198Scognet 1893129198Scognet/* 1894129198Scognet * Initialize the pmap module. 1895129198Scognet * Called by vm_init, to initialize any structures that the pmap 1896129198Scognet * system needs to map virtual memory. 1897129198Scognet * pmap_init has been enhanced to support in a fairly consistant 1898129198Scognet * way, discontiguous physical memory. 1899129198Scognet */ 1900129198Scognetvoid 1901129198Scognetpmap_init(void) 1902129198Scognet{ 1903129198Scognet int i; 1904129198Scognet 1905129198Scognet PDEBUG(1, printf("pmap_init: phys_start = %08x\n")); 1906129198Scognet /* 1907129198Scognet * Allocate memory for random pmap data structures. Includes the 1908129198Scognet * pv_head_table. 1909129198Scognet */ 1910129198Scognet for(i = 0; i < vm_page_array_size; i++) { 1911129198Scognet vm_page_t m; 1912129198Scognet 1913129198Scognet m = &vm_page_array[i]; 1914129198Scognet TAILQ_INIT(&m->md.pv_list); 1915129198Scognet m->md.pv_list_count = 0; 1916129198Scognet } 1917129198Scognet 1918129198Scognet /* 1919129198Scognet * init the pv free list 1920129198Scognet */ 1921129198Scognet pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1922129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1923129198Scognet uma_prealloc(pvzone, MINPV); 1924129198Scognet /* 1925129198Scognet * Now it is safe to enable pv_table recording. 1926129198Scognet */ 1927129198Scognet pmap_initialized = TRUE; 1928129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1929129198Scognet} 1930129198Scognet 1931129198Scognetint 1932129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1933129198Scognet{ 1934129198Scognet struct l2_dtable *l2; 1935129198Scognet struct l2_bucket *l2b; 1936129198Scognet pd_entry_t *pl1pd, l1pd; 1937129198Scognet pt_entry_t *ptep, pte; 1938129198Scognet vm_paddr_t pa; 1939129198Scognet u_int l1idx; 1940129198Scognet int rv = 0; 1941129198Scognet 1942129198Scognet#if 0 1943129198Scognet PMAP_MAP_TO_HEAD_LOCK(); 1944129198Scognet pmap_acquire_pmap_lock(pm); 1945129198Scognet#endif 1946129198Scognet l1idx = L1_IDX(va); 1947129198Scognet 1948129198Scognet /* 1949129198Scognet * If there is no l2_dtable for this address, then the process 1950129198Scognet * has no business accessing it. 1951129198Scognet * 1952129198Scognet * Note: This will catch userland processes trying to access 1953129198Scognet * kernel addresses. 1954129198Scognet */ 1955129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1956129198Scognet if (l2 == NULL) 1957129198Scognet goto out; 1958129198Scognet 1959129198Scognet /* 1960129198Scognet * Likewise if there is no L2 descriptor table 1961129198Scognet */ 1962129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1963129198Scognet if (l2b->l2b_kva == NULL) 1964129198Scognet goto out; 1965129198Scognet 1966129198Scognet /* 1967129198Scognet * Check the PTE itself. 1968129198Scognet */ 1969129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1970129198Scognet pte = *ptep; 1971129198Scognet if (pte == 0) 1972129198Scognet goto out; 1973129198Scognet 1974129198Scognet /* 1975129198Scognet * Catch a userland access to the vector page mapped at 0x0 1976129198Scognet */ 1977129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 1978129198Scognet goto out; 1979129198Scognet 1980129198Scognet pa = l2pte_pa(pte); 1981129198Scognet 1982129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 1983129198Scognet /* 1984129198Scognet * This looks like a good candidate for "page modified" 1985129198Scognet * emulation... 1986129198Scognet */ 1987129198Scognet struct pv_entry *pv; 1988129198Scognet struct vm_page *pg; 1989129198Scognet 1990129198Scognet /* Extract the physical address of the page */ 1991129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 1992129198Scognet goto out; 1993129198Scognet } 1994129198Scognet /* Get the current flags for this page. */ 1995129198Scognet 1996129198Scognet pv = pmap_find_pv(pg, pm, va); 1997129198Scognet if (pv == NULL) { 1998129198Scognet goto out; 1999129198Scognet } 2000129198Scognet 2001129198Scognet /* 2002129198Scognet * Do the flags say this page is writable? If not then it 2003129198Scognet * is a genuine write fault. If yes then the write fault is 2004129198Scognet * our fault as we did not reflect the write access in the 2005129198Scognet * PTE. Now we know a write has occurred we can correct this 2006129198Scognet * and also set the modified bit 2007129198Scognet */ 2008129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 2009129198Scognet goto out; 2010129198Scognet } 2011129198Scognet 2012129198Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 2013129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 2014129198Scognet 2015129198Scognet /* 2016129198Scognet * Re-enable write permissions for the page. No need to call 2017129198Scognet * pmap_vac_me_harder(), since this is just a 2018129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 2019129198Scognet * changing. We've already set the cacheable bits based on 2020129198Scognet * the assumption that we can write to this page. 2021129198Scognet */ 2022135641Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W | 2023135641Scognet pte_l2_s_cache_mask; 2024129198Scognet PTE_SYNC(ptep); 2025129198Scognet rv = 1; 2026129198Scognet } else 2027129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 2028129198Scognet /* 2029129198Scognet * This looks like a good candidate for "page referenced" 2030129198Scognet * emulation. 2031129198Scognet */ 2032129198Scognet struct pv_entry *pv; 2033129198Scognet struct vm_page *pg; 2034129198Scognet 2035129198Scognet /* Extract the physical address of the page */ 2036129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 2037129198Scognet goto out; 2038129198Scognet 2039129198Scognet /* Get the current flags for this page. */ 2040129198Scognet 2041129198Scognet pv = pmap_find_pv(pg, pm, va); 2042129198Scognet if (pv == NULL) { 2043129198Scognet goto out; 2044129198Scognet } 2045129198Scognet 2046129198Scognet pg->md.pvh_attrs |= PVF_REF; 2047129198Scognet pv->pv_flags |= PVF_REF; 2048129198Scognet 2049129198Scognet 2050129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 2051129198Scognet PTE_SYNC(ptep); 2052129198Scognet rv = 1; 2053129198Scognet } 2054129198Scognet 2055129198Scognet /* 2056129198Scognet * We know there is a valid mapping here, so simply 2057129198Scognet * fix up the L1 if necessary. 2058129198Scognet */ 2059129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2060129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 2061129198Scognet if (*pl1pd != l1pd) { 2062129198Scognet *pl1pd = l1pd; 2063129198Scognet PTE_SYNC(pl1pd); 2064129198Scognet rv = 1; 2065129198Scognet } 2066129198Scognet 2067129198Scognet#ifdef CPU_SA110 2068129198Scognet /* 2069129198Scognet * There are bugs in the rev K SA110. This is a check for one 2070129198Scognet * of them. 2071129198Scognet */ 2072129198Scognet if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 && 2073129198Scognet curcpu()->ci_arm_cpurev < 3) { 2074129198Scognet /* Always current pmap */ 2075129198Scognet if (l2pte_valid(pte)) { 2076129198Scognet extern int kernel_debug; 2077129198Scognet if (kernel_debug & 1) { 2078129198Scognet struct proc *p = curlwp->l_proc; 2079129198Scognet printf("prefetch_abort: page is already " 2080129198Scognet "mapped - pte=%p *pte=%08x\n", ptep, pte); 2081129198Scognet printf("prefetch_abort: pc=%08lx proc=%p " 2082129198Scognet "process=%s\n", va, p, p->p_comm); 2083129198Scognet printf("prefetch_abort: far=%08x fs=%x\n", 2084129198Scognet cpu_faultaddress(), cpu_faultstatus()); 2085129198Scognet } 2086129198Scognet#ifdef DDB 2087129198Scognet if (kernel_debug & 2) 2088129198Scognet Debugger(); 2089129198Scognet#endif 2090129198Scognet rv = 1; 2091129198Scognet } 2092129198Scognet } 2093129198Scognet#endif /* CPU_SA110 */ 2094129198Scognet 2095129198Scognet#ifdef DEBUG 2096129198Scognet /* 2097129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 2098129198Scognet * stale TLB entry for the faulting address. This happens when two or 2099129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 2100129198Scognet * a context switch between such processes, we can take domain faults 2101129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 2102129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 2103129198Scognet * example. 2104129198Scognet * 2105129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 2106129198Scognet * entry for a recently entered mapping. In this case, the TLB is 2107129198Scognet * flushed for the new mapping, but there may still be TLB entries for 2108129198Scognet * other mappings belonging to other processes in the 1MB range 2109129198Scognet * covered by the L1 entry. 2110129198Scognet * 2111129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 2112129198Scognet * value, so the fault must be due to a stale TLB entry. 2113129198Scognet * 2114129198Scognet * Since we always need to flush the TLB anyway in the case where we 2115129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 2116129198Scognet * stale TLB entries dynamically. 2117129198Scognet * 2118129198Scognet * However, the above condition can ONLY happen if the current L1 is 2119129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 2120129198Scognet * that other parts of the pmap are not doing their job WRT managing 2121129198Scognet * the TLB. 2122129198Scognet */ 2123129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 2124129198Scognet extern int last_fault_code; 2125129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 2126129198Scognet pm, va, ftype); 2127129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 2128129198Scognet l2, l2b, ptep, pl1pd); 2129129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 2130129198Scognet pte, l1pd, last_fault_code); 2131129198Scognet#ifdef DDB 2132129198Scognet Debugger(); 2133129198Scognet#endif 2134129198Scognet } 2135129198Scognet#endif 2136129198Scognet 2137129198Scognet cpu_tlb_flushID_SE(va); 2138129198Scognet cpu_cpwait(); 2139129198Scognet 2140129198Scognet rv = 1; 2141129198Scognet 2142129198Scognetout: 2143129198Scognet#if 0 2144129198Scognet pmap_release_pmap_lock(pm); 2145129198Scognet PMAP_MAP_TO_HEAD_UNLOCK(); 2146129198Scognet#endif 2147129198Scognet return (rv); 2148129198Scognet} 2149129198Scognet 2150129198Scognet/* 2151129198Scognet * Initialize the address space (zone) for the pv_entries. Set a 2152129198Scognet * high water mark so that the system can recover from excessive 2153129198Scognet * numbers of pv entries. 2154129198Scognet */ 2155129198Scognetvoid 2156129198Scognetpmap_init2() 2157129198Scognet{ 2158129198Scognet int shpgperproc = PMAP_SHPGPERPROC; 2159129198Scognet struct l2_bucket *l2b; 2160129198Scognet struct l1_ttable *l1; 2161129198Scognet pd_entry_t *pl1pt; 2162129198Scognet pt_entry_t *ptep, pte; 2163129198Scognet vm_offset_t va, eva; 2164129198Scognet u_int loop, needed; 2165129198Scognet 2166129198Scognet TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 2167129198Scognet 2168129198Scognet pv_entry_max = shpgperproc * maxproc + vm_page_array_size; 2169129198Scognet pv_entry_high_water = 9 * (pv_entry_max / 10); 2170129198Scognet l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 2171129198Scognet NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 2172135641Scognet uma_prealloc(l2zone, 4096); 2173137663Scognet l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), 2174137663Scognet NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 2175137663Scognet UMA_ZONE_VM | UMA_ZONE_NOFREE); 2176137663Scognet uma_prealloc(l2table_zone, 1024); 2177137663Scognet 2178129198Scognet uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 2179129198Scognet uma_zone_set_obj(l2zone, &l2zone_obj, pv_entry_max); 2180129198Scognet 2181129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 2182129198Scognet needed -= 1; 2183129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 2184129198Scognet 2185129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 2186129198Scognet /* Allocate a L1 page table */ 2187132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 2188132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 2189129198Scognet 2190129198Scognet if (va == 0) 2191129198Scognet panic("Cannot allocate L1 KVM"); 2192129198Scognet 2193129198Scognet eva = va + L1_TABLE_SIZE; 2194129198Scognet pl1pt = (pd_entry_t *)va; 2195129198Scognet 2196135641Scognet while (va < eva) { 2197129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2198129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2199129198Scognet pte = *ptep; 2200129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 2201129198Scognet *ptep = pte; 2202129198Scognet PTE_SYNC(ptep); 2203129198Scognet cpu_tlb_flushD_SE(va); 2204129198Scognet 2205129198Scognet va += PAGE_SIZE; 2206129198Scognet } 2207129198Scognet pmap_init_l1(l1, pl1pt); 2208129198Scognet } 2209129198Scognet 2210129198Scognet 2211129198Scognet#ifdef DEBUG 2212129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 2213129198Scognet needed); 2214129198Scognet#endif 2215129198Scognet} 2216129198Scognet 2217129198Scognet/* 2218129198Scognet * This is used to stuff certain critical values into the PCB where they 2219129198Scognet * can be accessed quickly from cpu_switch() et al. 2220129198Scognet */ 2221129198Scognetvoid 2222129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2223129198Scognet{ 2224129198Scognet struct l2_bucket *l2b; 2225129198Scognet 2226129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2227129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2228129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2229129198Scognet 2230129198Scognet if (vector_page < KERNBASE) { 2231129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2232129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2233129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2234129198Scognet L1_C_DOM(pm->pm_domain); 2235129198Scognet } else 2236129198Scognet pcb->pcb_pl1vec = NULL; 2237129198Scognet} 2238129198Scognet 2239129198Scognetvoid 2240129198Scognetpmap_activate(struct thread *td) 2241129198Scognet{ 2242129198Scognet pmap_t pm; 2243129198Scognet struct pcb *pcb; 2244129198Scognet int s; 2245129198Scognet 2246135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2247129198Scognet pcb = td->td_pcb; 2248129198Scognet 2249129198Scognet critical_enter(); 2250129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2251129198Scognet 2252129198Scognet if (td == curthread) { 2253129198Scognet u_int cur_dacr, cur_ttb; 2254129198Scognet 2255129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2256129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2257129198Scognet 2258129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2259129198Scognet 2260129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2261129198Scognet cur_dacr == pcb->pcb_dacr) { 2262129198Scognet /* 2263129198Scognet * No need to switch address spaces. 2264129198Scognet */ 2265129198Scognet critical_exit(); 2266129198Scognet return; 2267129198Scognet } 2268129198Scognet 2269129198Scognet 2270129198Scognet /* 2271129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2272129198Scognet * to 'vector_page' in the incoming L1 table before switching 2273129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2274129198Scognet * domain faults!) will jump into hyperspace. 2275129198Scognet */ 2276129198Scognet if (pcb->pcb_pl1vec) { 2277129198Scognet 2278129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2279129198Scognet /* 2280129198Scognet * Don't need to PTE_SYNC() at this point since 2281129198Scognet * cpu_setttb() is about to flush both the cache 2282129198Scognet * and the TLB. 2283129198Scognet */ 2284129198Scognet } 2285129198Scognet 2286129198Scognet cpu_domains(pcb->pcb_dacr); 2287129198Scognet cpu_setttb(pcb->pcb_pagedir); 2288129198Scognet 2289129198Scognet splx(s); 2290129198Scognet } 2291129198Scognet critical_exit(); 2292129198Scognet} 2293129198Scognet 2294129198Scognetstatic int 2295129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2296129198Scognet{ 2297129198Scognet pd_entry_t *pdep, pde; 2298129198Scognet pt_entry_t *ptep, pte; 2299129198Scognet vm_offset_t pa; 2300129198Scognet int rv = 0; 2301129198Scognet 2302129198Scognet /* 2303129198Scognet * Make sure the descriptor itself has the correct cache mode 2304129198Scognet */ 2305129198Scognet pdep = &kl1[L1_IDX(va)]; 2306129198Scognet pde = *pdep; 2307129198Scognet 2308129198Scognet if (l1pte_section_p(pde)) { 2309129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2310129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2311129198Scognet pte_l1_s_cache_mode_pt; 2312129198Scognet PTE_SYNC(pdep); 2313129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2314129198Scognet sizeof(*pdep)); 2315129198Scognet rv = 1; 2316129198Scognet } 2317129198Scognet } else { 2318129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2319129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2320129198Scognet if (ptep == NULL) 2321129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2322129198Scognet 2323129198Scognet ptep = &ptep[l2pte_index(va)]; 2324129198Scognet pte = *ptep; 2325129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2326129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2327129198Scognet pte_l2_s_cache_mode_pt; 2328129198Scognet PTE_SYNC(ptep); 2329129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2330129198Scognet sizeof(*ptep)); 2331129198Scognet rv = 1; 2332129198Scognet } 2333129198Scognet } 2334129198Scognet 2335129198Scognet return (rv); 2336129198Scognet} 2337129198Scognet 2338129198Scognetstatic void 2339129198Scognetpmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2340129198Scognet pt_entry_t **ptep) 2341129198Scognet{ 2342129198Scognet vm_offset_t va = *availp; 2343129198Scognet struct l2_bucket *l2b; 2344129198Scognet 2345129198Scognet if (ptep) { 2346129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2347129198Scognet if (l2b == NULL) 2348129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2349129198Scognet 2350129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2351129198Scognet } 2352129198Scognet 2353129198Scognet *vap = va; 2354129198Scognet *availp = va + (PAGE_SIZE * pages); 2355129198Scognet} 2356129198Scognet 2357129198Scognet/* 2358129198Scognet * Bootstrap the system enough to run with virtual memory. 2359129198Scognet * 2360129198Scognet * On the arm this is called after mapping has already been enabled 2361129198Scognet * and just syncs the pmap module with what has already been done. 2362129198Scognet * [We can't call it easily with mapping off since the kernel is not 2363129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2364129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2365129198Scognet * (physical) address starting relative to 0] 2366129198Scognet */ 2367129198Scognet#define PMAP_STATIC_L2_SIZE 16 2368129198Scognetvoid 2369129198Scognetpmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt) 2370129198Scognet{ 2371129198Scognet static struct l1_ttable static_l1; 2372129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2373129198Scognet struct l1_ttable *l1 = &static_l1; 2374129198Scognet struct l2_dtable *l2; 2375129198Scognet struct l2_bucket *l2b; 2376129198Scognet pd_entry_t pde; 2377129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2378129198Scognet pt_entry_t *ptep; 2379129198Scognet vm_paddr_t pa; 2380129198Scognet vm_offset_t va; 2381135641Scognet vm_size_t size; 2382129198Scognet int l1idx, l2idx, l2next = 0; 2383129198Scognet 2384129198Scognet PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n", 2385129198Scognet firstaddr, loadaddr)); 2386129198Scognet 2387129198Scognet virtual_avail = firstaddr; 2388129198Scognet kernel_pmap = &kernel_pmap_store; 2389129198Scognet kernel_pmap->pm_l1 = l1; 2390129198Scognet/* 2391129198Scognet * Scan the L1 translation table created by initarm() and create 2392129198Scognet * the required metadata for all valid mappings found in it. 2393129198Scognet */ 2394129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2395129198Scognet pde = kernel_l1pt[l1idx]; 2396129198Scognet 2397129198Scognet /* 2398129198Scognet * We're only interested in Coarse mappings. 2399129198Scognet * pmap_extract() can deal with section mappings without 2400129198Scognet * recourse to checking L2 metadata. 2401129198Scognet */ 2402129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2403129198Scognet continue; 2404129198Scognet 2405129198Scognet /* 2406129198Scognet * Lookup the KVA of this L2 descriptor table 2407129198Scognet */ 2408129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2409129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2410129198Scognet 2411129198Scognet if (ptep == NULL) { 2412129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2413129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2414129198Scognet } 2415129198Scognet 2416129198Scognet /* 2417129198Scognet * Fetch the associated L2 metadata structure. 2418129198Scognet * Allocate a new one if necessary. 2419129198Scognet */ 2420129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2421129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2422129198Scognet panic("pmap_bootstrap: out of static L2s"); 2423129198Scognet kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2424129198Scognet &static_l2[l2next++]; 2425129198Scognet } 2426129198Scognet 2427129198Scognet /* 2428129198Scognet * One more L1 slot tracked... 2429129198Scognet */ 2430129198Scognet l2->l2_occupancy++; 2431129198Scognet 2432129198Scognet /* 2433129198Scognet * Fill in the details of the L2 descriptor in the 2434129198Scognet * appropriate bucket. 2435129198Scognet */ 2436129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2437129198Scognet l2b->l2b_kva = ptep; 2438129198Scognet l2b->l2b_phys = pa; 2439129198Scognet l2b->l2b_l1idx = l1idx; 2440129198Scognet 2441129198Scognet /* 2442129198Scognet * Establish an initial occupancy count for this descriptor 2443129198Scognet */ 2444129198Scognet for (l2idx = 0; 2445129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2446129198Scognet l2idx++) { 2447129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2448129198Scognet l2b->l2b_occupancy++; 2449129198Scognet } 2450129198Scognet } 2451129198Scognet 2452129198Scognet /* 2453129198Scognet * Make sure the descriptor itself has the correct cache mode. 2454129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2455129198Scognet * should consider this a clue to fix up their initarm() 2456129198Scognet * function. :) 2457129198Scognet */ 2458129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2459129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2460129198Scognet "L2 pte @ %p\n", ptep); 2461129198Scognet } 2462129198Scognet } 2463129198Scognet 2464129198Scognet 2465129198Scognet /* 2466129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2467129198Scognet * a page table. Bitch if it is not correctly set. 2468129198Scognet */ 2469129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2470129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2471129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2472129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2473129198Scognet "primary L1 @ 0x%x\n", va); 2474129198Scognet } 2475129198Scognet 2476129198Scognet cpu_dcache_wbinv_all(); 2477129198Scognet cpu_tlb_flushID(); 2478129198Scognet cpu_cpwait(); 2479129198Scognet 2480129198Scognet kernel_pmap->pm_active = -1; 2481129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2482129198Scognet LIST_INIT(&allpmaps); 2483129198Scognet LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 2484129198Scognet 2485129198Scognet /* 2486129198Scognet * Reserve some special page table entries/VA space for temporary 2487129198Scognet * mapping of pages. 2488129198Scognet */ 2489129198Scognet#define SYSMAP(c, p, v, n) \ 2490129198Scognet v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 2491129198Scognet 2492129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2493129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2494129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2495129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2496135641Scognet size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE; 2497135641Scognet pmap_alloc_specials(&virtual_avail, 2498135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2499135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2500135641Scognet 2501135641Scognet size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE; 2502135641Scognet pmap_alloc_specials(&virtual_avail, 2503135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2504135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2505135641Scognet 2506137362Scognet pmap_alloc_specials(&virtual_avail, 2507137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2508135641Scognet SLIST_INIT(&l1_list); 2509129198Scognet TAILQ_INIT(&l1_lru_list); 2510129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2511129198Scognet pmap_init_l1(l1, kernel_l1pt); 2512129198Scognet cpu_dcache_wbinv_all(); 2513129198Scognet 2514129198Scognet virtual_avail = round_page(virtual_avail); 2515129198Scognet virtual_end = lastaddr; 2516135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2517129198Scognet} 2518129198Scognet 2519129198Scognet/*************************************************** 2520129198Scognet * Pmap allocation/deallocation routines. 2521129198Scognet ***************************************************/ 2522129198Scognet 2523129198Scognet/* 2524129198Scognet * Release any resources held by the given physical map. 2525129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2526129198Scognet * Should only be called if the map contains no valid mappings. 2527129198Scognet */ 2528129198Scognetvoid 2529129198Scognetpmap_release(pmap_t pmap) 2530129198Scognet{ 2531135641Scognet struct pcb *pcb; 2532135641Scognet 2533135641Scognet pmap_idcache_wbinv_all(pmap); 2534135641Scognet pmap_tlb_flushID(pmap); 2535135641Scognet cpu_cpwait(); 2536135641Scognet LIST_REMOVE(pmap, pm_list); 2537135641Scognet if (vector_page < KERNBASE) { 2538135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2539135641Scognet pcb = thread0.td_pcb; 2540135641Scognet if (pmap_is_current(pmap)) { 2541135641Scognet /* 2542135641Scognet * Frob the L1 entry corresponding to the vector 2543135641Scognet * page so that it contains the kernel pmap's domain 2544135641Scognet * number. This will ensure pmap_remove() does not 2545135641Scognet * pull the current vector page out from under us. 2546135641Scognet */ 2547135641Scognet critical_enter(); 2548135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2549135641Scognet cpu_domains(pcb->pcb_dacr); 2550135641Scognet cpu_setttb(pcb->pcb_pagedir); 2551135641Scognet critical_exit(); 2552135641Scognet } 2553135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2554135641Scognet /* 2555135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2556135641Scognet * since this process has no remaining mappings of its own. 2557135641Scognet */ 2558135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2559135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2560135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2561135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2562135641Scognet 2563135641Scognet } 2564129198Scognet pmap_free_l1(pmap); 2565135641Scognet 2566129198Scognet dprintf("pmap_release()\n"); 2567129198Scognet} 2568129198Scognet 2569129198Scognet 2570135641Scognet 2571129198Scognet/* 2572135641Scognet * Helper function for pmap_grow_l2_bucket() 2573135641Scognet */ 2574135641Scognetstatic __inline int 2575135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2576135641Scognet{ 2577135641Scognet struct l2_bucket *l2b; 2578135641Scognet pt_entry_t *ptep; 2579135641Scognet vm_paddr_t pa; 2580135641Scognet struct vm_page *pg; 2581135641Scognet 2582135641Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | 2583135641Scognet VM_ALLOC_WIRED); 2584135641Scognet if (pg == NULL) 2585135641Scognet return (1); 2586135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2587135641Scognet 2588135641Scognet if (pap) 2589135641Scognet *pap = pa; 2590135641Scognet 2591135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2592135641Scognet 2593135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2594135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2595135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2596135641Scognet PTE_SYNC(ptep); 2597135641Scognet memset((void *)va, 0, PAGE_SIZE); 2598135641Scognet return (0); 2599135641Scognet} 2600135641Scognet 2601135641Scognet/* 2602135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2603135641Scognet * used by pmap_growkernel(). 2604135641Scognet */ 2605135641Scognetstatic __inline struct l2_bucket * 2606135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2607135641Scognet{ 2608135641Scognet struct l2_dtable *l2; 2609135641Scognet struct l2_bucket *l2b; 2610135641Scognet struct l1_ttable *l1; 2611135641Scognet pd_entry_t *pl1pd; 2612135641Scognet u_short l1idx; 2613135641Scognet vm_offset_t nva; 2614135641Scognet 2615135641Scognet l1idx = L1_IDX(va); 2616135641Scognet 2617135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2618135641Scognet /* 2619135641Scognet * No mapping at this address, as there is 2620135641Scognet * no entry in the L1 table. 2621135641Scognet * Need to allocate a new l2_dtable. 2622135641Scognet */ 2623135641Scognet nva = pmap_kernel_l2dtable_kva; 2624135641Scognet if ((nva & PAGE_MASK) == 0) { 2625135641Scognet /* 2626135641Scognet * Need to allocate a backing page 2627135641Scognet */ 2628135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2629135641Scognet return (NULL); 2630135641Scognet } 2631135641Scognet 2632135641Scognet l2 = (struct l2_dtable *)nva; 2633135641Scognet nva += sizeof(struct l2_dtable); 2634135641Scognet 2635135641Scognet if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2636135641Scognet PAGE_MASK)) { 2637135641Scognet /* 2638135641Scognet * The new l2_dtable straddles a page boundary. 2639135641Scognet * Map in another page to cover it. 2640135641Scognet */ 2641135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2642135641Scognet return (NULL); 2643135641Scognet } 2644135641Scognet 2645135641Scognet pmap_kernel_l2dtable_kva = nva; 2646135641Scognet 2647135641Scognet /* 2648135641Scognet * Link it into the parent pmap 2649135641Scognet */ 2650135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2651135641Scognet } 2652135641Scognet 2653135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2654135641Scognet 2655135641Scognet /* 2656135641Scognet * Fetch pointer to the L2 page table associated with the address. 2657135641Scognet */ 2658135641Scognet if (l2b->l2b_kva == NULL) { 2659135641Scognet pt_entry_t *ptep; 2660135641Scognet 2661135641Scognet /* 2662135641Scognet * No L2 page table has been allocated. Chances are, this 2663135641Scognet * is because we just allocated the l2_dtable, above. 2664135641Scognet */ 2665135641Scognet nva = pmap_kernel_l2ptp_kva; 2666135641Scognet ptep = (pt_entry_t *)nva; 2667135641Scognet if ((nva & PAGE_MASK) == 0) { 2668135641Scognet /* 2669135641Scognet * Need to allocate a backing page 2670135641Scognet */ 2671135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2672135641Scognet &pmap_kernel_l2ptp_phys)) 2673135641Scognet return (NULL); 2674135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2675135641Scognet } 2676135641Scognet 2677135641Scognet l2->l2_occupancy++; 2678135641Scognet l2b->l2b_kva = ptep; 2679135641Scognet l2b->l2b_l1idx = l1idx; 2680135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2681135641Scognet 2682135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2683135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2684135641Scognet } 2685135641Scognet 2686135641Scognet /* Distribute new L1 entry to all other L1s */ 2687135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2688135641Scognet pl1pd = &l1->l1_kva[L1_IDX(pmap_curmaxkvaddr)]; 2689135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2690135641Scognet L1_C_PROTO; 2691135641Scognet PTE_SYNC(pl1pd); 2692135641Scognet } 2693135641Scognet 2694135641Scognet return (l2b); 2695135641Scognet} 2696135641Scognet 2697135641Scognet 2698135641Scognet/* 2699129198Scognet * grow the number of kernel page table entries, if needed 2700129198Scognet */ 2701129198Scognetvoid 2702129198Scognetpmap_growkernel(vm_offset_t addr) 2703129198Scognet{ 2704135641Scognet pmap_t kpm = pmap_kernel(); 2705135641Scognet int s; 2706129198Scognet 2707135641Scognet if (addr <= pmap_curmaxkvaddr) 2708135641Scognet return; /* we are OK */ 2709135641Scognet 2710135641Scognet /* 2711135641Scognet * whoops! we need to add kernel PTPs 2712135641Scognet */ 2713135641Scognet 2714135641Scognet s = splhigh(); /* to be safe */ 2715135641Scognet 2716135641Scognet /* Map 1MB at a time */ 2717135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2718135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2719135641Scognet 2720135641Scognet /* 2721135641Scognet * flush out the cache, expensive but growkernel will happen so 2722135641Scognet * rarely 2723135641Scognet */ 2724135641Scognet cpu_dcache_wbinv_all(); 2725135641Scognet cpu_tlb_flushD(); 2726135641Scognet cpu_cpwait(); 2727135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2728135641Scognet 2729129198Scognet} 2730129198Scognet 2731129198Scognet 2732129198Scognet/* 2733129198Scognet * pmap_page_protect: 2734129198Scognet * 2735129198Scognet * Lower the permission for all mappings to a given page. 2736129198Scognet */ 2737129198Scognetvoid 2738129198Scognetpmap_page_protect(vm_page_t m, vm_prot_t prot) 2739129198Scognet{ 2740135641Scognet switch(prot) { 2741135641Scognet case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE: 2742135641Scognet case VM_PROT_READ|VM_PROT_WRITE: 2743135641Scognet return; 2744135641Scognet 2745135641Scognet case VM_PROT_READ: 2746135641Scognet case VM_PROT_READ|VM_PROT_EXECUTE: 2747135641Scognet pmap_clearbit(m, PVF_WRITE); 2748135641Scognet break; 2749135641Scognet 2750135641Scognet default: 2751135641Scognet pmap_remove_all(m); 2752135641Scognet break; 2753129198Scognet } 2754135641Scognet 2755129198Scognet} 2756129198Scognet 2757129198Scognet 2758129198Scognet/* 2759129198Scognet * Remove all pages from specified address space 2760129198Scognet * this aids process exit speeds. Also, this code 2761129198Scognet * is special cased for current process only, but 2762129198Scognet * can have the more generic (and slightly slower) 2763129198Scognet * mode enabled. This is much faster than pmap_remove 2764129198Scognet * in the case of running down an entire address space. 2765129198Scognet */ 2766129198Scognetvoid 2767129198Scognetpmap_remove_pages(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2768129198Scognet{ 2769129198Scognet 2770135641Scognet cpu_idcache_wbinv_all(); 2771135641Scognet cpu_tlb_flushID(); 2772135641Scognet cpu_cpwait(); 2773129198Scognet} 2774129198Scognet 2775129198Scognet 2776129198Scognet/*************************************************** 2777129198Scognet * Low level mapping routines..... 2778129198Scognet ***************************************************/ 2779129198Scognet 2780129198Scognet/* 2781129198Scognet * add a wired page to the kva 2782129198Scognet * note that in order for the mapping to take effect -- you 2783129198Scognet * should do a invltlb after doing the pmap_kenter... 2784129198Scognet */ 2785135641Scognetstatic PMAP_INLINE void 2786135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2787129198Scognet{ 2788129198Scognet struct l2_bucket *l2b; 2789129198Scognet pt_entry_t *pte; 2790129198Scognet pt_entry_t opte; 2791129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2792129198Scognet (uint32_t) va, (uint32_t) pa)); 2793129198Scognet 2794129198Scognet 2795129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2796135641Scognet if (l2b == NULL) 2797135641Scognet l2b = pmap_grow_l2_bucket(pmap_kernel(), va); 2798129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2799129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2800129198Scognet opte = *pte; 2801129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2802129198Scognet (uint32_t) pte, opte, *pte)); 2803129198Scognet if (l2pte_valid(opte)) { 2804135641Scognet#if 0 2805129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2806135641Scognet#endif 2807129198Scognet cpu_tlb_flushD_SE(va); 2808129198Scognet cpu_cpwait(); 2809135641Scognet } else { 2810129198Scognet if (opte == 0) 2811129198Scognet l2b->l2b_occupancy++; 2812135641Scognet } 2813129198Scognet *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2814135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2815135641Scognet if (flags & KENTER_CACHE) 2816135641Scognet *pte |= pte_l2_s_cache_mode; 2817129198Scognet PTE_SYNC(pte); 2818135641Scognet} 2819129198Scognet 2820135641Scognetvoid 2821135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2822135641Scognet{ 2823135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2824129198Scognet} 2825129198Scognet 2826129198Scognet 2827135641Scognet 2828129198Scognet/* 2829135641Scognet * remove a page rom the kernel pagetables 2830129198Scognet */ 2831129198ScognetPMAP_INLINE void 2832129198Scognetpmap_kremove(vm_offset_t va) 2833129198Scognet{ 2834135641Scognet struct l2_bucket *l2b; 2835135641Scognet pt_entry_t *pte, opte; 2836135641Scognet 2837135641Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 2838135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2839135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2840135641Scognet opte = *pte; 2841135641Scognet if (l2pte_valid(opte)) { 2842135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2843135641Scognet cpu_tlb_flushD_SE(va); 2844135641Scognet cpu_cpwait(); 2845135641Scognet } 2846135641Scognet if (opte) 2847135641Scognet *pte = 0; 2848129198Scognet} 2849129198Scognet 2850129198Scognet 2851129198Scognet/* 2852129198Scognet * Used to map a range of physical addresses into kernel 2853129198Scognet * virtual address space. 2854129198Scognet * 2855129198Scognet * The value passed in '*virt' is a suggested virtual address for 2856129198Scognet * the mapping. Architectures which can support a direct-mapped 2857129198Scognet * physical to virtual region can return the appropriate address 2858129198Scognet * within that region, leaving '*virt' unchanged. Other 2859129198Scognet * architectures should map the pages starting at '*virt' and 2860129198Scognet * update '*virt' with the first usable address after the mapped 2861129198Scognet * region. 2862129198Scognet */ 2863129198Scognetvm_offset_t 2864129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2865129198Scognet{ 2866129198Scognet vm_offset_t sva = *virt; 2867129198Scognet vm_offset_t va = sva; 2868129198Scognet 2869129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2870129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2871129198Scognet prot)); 2872129198Scognet 2873129198Scognet while (start < end) { 2874129198Scognet pmap_kenter(va, start); 2875129198Scognet va += PAGE_SIZE; 2876129198Scognet start += PAGE_SIZE; 2877129198Scognet } 2878129198Scognet *virt = va; 2879129198Scognet return (sva); 2880129198Scognet} 2881129198Scognet 2882129198Scognet 2883129198Scognet/* 2884129198Scognet * Add a list of wired pages to the kva 2885129198Scognet * this routine is only used for temporary 2886129198Scognet * kernel mappings that do not need to have 2887129198Scognet * page modification or references recorded. 2888129198Scognet * Note that old mappings are simply written 2889129198Scognet * over. The page *must* be wired. 2890129198Scognet */ 2891129198Scognetvoid 2892129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2893129198Scognet{ 2894129198Scognet int i; 2895129198Scognet 2896129198Scognet for (i = 0; i < count; i++) { 2897135641Scognet pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2898135641Scognet KENTER_CACHE); 2899129198Scognet va += PAGE_SIZE; 2900129198Scognet } 2901137549Scognet cpu_dcache_wbinv_all(); /* XXX: shouldn't be needed */ 2902129198Scognet} 2903129198Scognet 2904129198Scognet 2905129198Scognet/* 2906129198Scognet * this routine jerks page mappings from the 2907129198Scognet * kernel -- it is meant only for temporary mappings. 2908129198Scognet */ 2909129198Scognetvoid 2910129198Scognetpmap_qremove(vm_offset_t va, int count) 2911129198Scognet{ 2912129198Scognet int i; 2913129198Scognet 2914129198Scognet for (i = 0; i < count; i++) { 2915129198Scognet pmap_kremove(va); 2916129198Scognet va += PAGE_SIZE; 2917129198Scognet } 2918129198Scognet} 2919129198Scognet 2920129198Scognet 2921129198Scognet/* 2922129198Scognet * pmap_object_init_pt preloads the ptes for a given object 2923129198Scognet * into the specified pmap. This eliminates the blast of soft 2924129198Scognet * faults on process startup and immediately after an mmap. 2925129198Scognet */ 2926129198Scognetvoid 2927129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 2928129198Scognet vm_pindex_t pindex, vm_size_t size) 2929129198Scognet{ 2930129198Scognet printf("pmap_object_init_pt()\n"); 2931129198Scognet} 2932129198Scognet 2933129198Scognet 2934129198Scognet/* 2935129198Scognet * pmap_is_prefaultable: 2936129198Scognet * 2937129198Scognet * Return whether or not the specified virtual address is elgible 2938129198Scognet * for prefault. 2939129198Scognet */ 2940129198Scognetboolean_t 2941129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2942129198Scognet{ 2943135641Scognet pd_entry_t *pde; 2944129198Scognet pt_entry_t *pte; 2945129198Scognet 2946135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 2947135641Scognet return (FALSE); 2948135641Scognet if (*pte == 0) 2949135641Scognet return (TRUE); 2950135641Scognet return (FALSE); 2951129198Scognet} 2952129198Scognet 2953129198Scognet/* 2954129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 2955129198Scognet * Returns TRUE if the mapping exists, else FALSE. 2956129198Scognet * 2957129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 2958129198Scognet * It is not safe to take any pmap locks here, since we could be right 2959129198Scognet * in the middle of debugging the pmap anyway... 2960129198Scognet * 2961129198Scognet * It is possible for this routine to return FALSE even though a valid 2962129198Scognet * mapping does exist. This is because we don't lock, so the metadata 2963129198Scognet * state may be inconsistent. 2964129198Scognet * 2965129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 2966129198Scognet * a "section" mapping. 2967129198Scognet */ 2968129198Scognetboolean_t 2969129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 2970129198Scognet{ 2971129198Scognet struct l2_dtable *l2; 2972129198Scognet pd_entry_t *pl1pd, l1pd; 2973129198Scognet pt_entry_t *ptep; 2974129198Scognet u_short l1idx; 2975129198Scognet 2976129198Scognet if (pm->pm_l1 == NULL) 2977129198Scognet return (FALSE); 2978129198Scognet 2979129198Scognet l1idx = L1_IDX(va); 2980129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2981129198Scognet l1pd = *pl1pd; 2982129198Scognet 2983129198Scognet if (l1pte_section_p(l1pd)) { 2984129198Scognet *ptp = NULL; 2985129198Scognet return (TRUE); 2986129198Scognet } 2987129198Scognet 2988129198Scognet if (pm->pm_l2 == NULL) 2989129198Scognet return (FALSE); 2990129198Scognet 2991129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 2992129198Scognet 2993129198Scognet if (l2 == NULL || 2994129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2995129198Scognet return (FALSE); 2996129198Scognet } 2997129198Scognet 2998129198Scognet *ptp = &ptep[l2pte_index(va)]; 2999129198Scognet return (TRUE); 3000129198Scognet} 3001129198Scognet 3002129198Scognet/* 3003129198Scognet * Routine: pmap_remove_all 3004129198Scognet * Function: 3005129198Scognet * Removes this physical page from 3006129198Scognet * all physical maps in which it resides. 3007129198Scognet * Reflects back modify bits to the pager. 3008129198Scognet * 3009129198Scognet * Notes: 3010129198Scognet * Original versions of this routine were very 3011129198Scognet * inefficient because they iteratively called 3012129198Scognet * pmap_remove (slow...) 3013129198Scognet */ 3014129198Scognetvoid 3015129198Scognetpmap_remove_all(vm_page_t m) 3016129198Scognet{ 3017129198Scognet pv_entry_t pv; 3018135641Scognet pt_entry_t *ptep, pte; 3019135641Scognet struct l2_bucket *l2b; 3020135641Scognet boolean_t flush = FALSE; 3021135641Scognet pmap_t curpm; 3022135641Scognet int flags = 0; 3023129198Scognet 3024129198Scognet#if defined(PMAP_DEBUG) 3025129198Scognet /* 3026129198Scognet * XXX this makes pmap_page_protect(NONE) illegal for non-managed 3027129198Scognet * pages! 3028129198Scognet */ 3029129198Scognet if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) { 3030129198Scognet panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m)); 3031129198Scognet } 3032129198Scognet#endif 3033129198Scognet 3034135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3035135641Scognet return; 3036135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3037135641Scognet pmap_update(curpm); 3038129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3039135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3040135641Scognet pv->pv_pmap == pmap_kernel())) 3041135641Scognet flush = TRUE; 3042135641Scognet pmap_update(pv->pv_pmap); 3043135641Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3044135641Scognet KASSERT(l2b != NULL, ("No l2 bucket")); 3045135641Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3046135641Scognet pte = *ptep; 3047135641Scognet *ptep = 0; 3048135641Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3049135641Scognet pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3050135641Scognet if (pv->pv_flags & PVF_WIRED) 3051135641Scognet pv->pv_pmap->pm_stats.wired_count--; 3052129198Scognet pv->pv_pmap->pm_stats.resident_count--; 3053135641Scognet flags |= pv->pv_flags; 3054135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3055129198Scognet pmap_free_pv_entry(pv); 3056129198Scognet } 3057129198Scognet 3058135641Scognet if (flush) { 3059135641Scognet if (PV_BEEN_EXECD(flags)) 3060135641Scognet pmap_tlb_flushID(curpm); 3061135641Scognet else 3062135641Scognet pmap_tlb_flushD(curpm); 3063135641Scognet } 3064135641Scognet 3065129198Scognet} 3066129198Scognet 3067129198Scognet 3068129198Scognet/* 3069129198Scognet * Set the physical protection on the 3070129198Scognet * specified range of this map as requested. 3071129198Scognet */ 3072129198Scognetvoid 3073129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3074129198Scognet{ 3075129198Scognet struct l2_bucket *l2b; 3076129198Scognet pt_entry_t *ptep, pte; 3077129198Scognet vm_offset_t next_bucket; 3078129198Scognet u_int flags; 3079129198Scognet int flush; 3080129198Scognet 3081129198Scognet if ((prot & VM_PROT_READ) == 0) { 3082132899Salc mtx_lock(&Giant); 3083129198Scognet pmap_remove(pm, sva, eva); 3084132899Salc mtx_unlock(&Giant); 3085129198Scognet return; 3086129198Scognet } 3087129198Scognet 3088129198Scognet if (prot & VM_PROT_WRITE) { 3089129198Scognet /* 3090129198Scognet * If this is a read->write transition, just ignore it and let 3091135641Scognet * vm_fault() take care of it later. 3092129198Scognet */ 3093129198Scognet return; 3094129198Scognet } 3095129198Scognet 3096132899Salc mtx_lock(&Giant); 3097129198Scognet 3098135641Scognet pmap_update(pm); 3099129198Scognet /* 3100129198Scognet * OK, at this point, we know we're doing write-protect operation. 3101129198Scognet * If the pmap is active, write-back the range. 3102129198Scognet */ 3103129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3104129198Scognet 3105129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3106129198Scognet flags = 0; 3107129198Scognet 3108129198Scognet while (sva < eva) { 3109129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3110129198Scognet if (next_bucket > eva) 3111129198Scognet next_bucket = eva; 3112129198Scognet 3113129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3114129198Scognet if (l2b == NULL) { 3115129198Scognet sva = next_bucket; 3116129198Scognet continue; 3117129198Scognet } 3118129198Scognet 3119129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3120129198Scognet 3121129198Scognet while (sva < next_bucket) { 3122129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3123129198Scognet struct vm_page *pg; 3124129198Scognet u_int f; 3125129198Scognet 3126129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3127129198Scognet pte &= ~L2_S_PROT_W; 3128129198Scognet *ptep = pte; 3129129198Scognet PTE_SYNC(ptep); 3130129198Scognet 3131129198Scognet if (pg != NULL) { 3132129198Scognet f = pmap_modify_pv(pg, pm, sva, 3133129198Scognet PVF_WRITE, 0); 3134129198Scognet pmap_vac_me_harder(pg, pm, sva); 3135129198Scognet } else 3136129198Scognet f = PVF_REF | PVF_EXEC; 3137129198Scognet 3138129198Scognet if (flush >= 0) { 3139129198Scognet flush++; 3140129198Scognet flags |= f; 3141129198Scognet } else 3142129198Scognet if (PV_BEEN_EXECD(f)) 3143129198Scognet pmap_tlb_flushID_SE(pm, sva); 3144129198Scognet else 3145129198Scognet if (PV_BEEN_REFD(f)) 3146129198Scognet pmap_tlb_flushD_SE(pm, sva); 3147129198Scognet } 3148129198Scognet 3149129198Scognet sva += PAGE_SIZE; 3150129198Scognet ptep++; 3151129198Scognet } 3152129198Scognet } 3153129198Scognet 3154129198Scognet 3155129198Scognet if (flush) { 3156129198Scognet if (PV_BEEN_EXECD(flags)) 3157129198Scognet pmap_tlb_flushID(pm); 3158129198Scognet else 3159129198Scognet if (PV_BEEN_REFD(flags)) 3160129198Scognet pmap_tlb_flushD(pm); 3161129198Scognet } 3162129198Scognet 3163132899Salc mtx_unlock(&Giant); 3164129198Scognet} 3165129198Scognet 3166129198Scognet 3167129198Scognet/* 3168129198Scognet * Insert the given physical page (p) at 3169129198Scognet * the specified virtual address (v) in the 3170129198Scognet * target physical map with the protection requested. 3171129198Scognet * 3172129198Scognet * If specified, the page will be wired down, meaning 3173129198Scognet * that the related pte can not be reclaimed. 3174129198Scognet * 3175129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3176129198Scognet * or lose information. That is, this routine must actually 3177129198Scognet * insert this page into the given map NOW. 3178129198Scognet */ 3179135641Scognet 3180129198Scognetvoid 3181129198Scognetpmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3182129198Scognet boolean_t wired) 3183129198Scognet{ 3184135641Scognet struct l2_bucket *l2b = NULL; 3185129198Scognet struct vm_page *opg; 3186129198Scognet struct pv_entry *pve; 3187129198Scognet pt_entry_t *ptep, npte, opte; 3188129198Scognet u_int nflags; 3189129198Scognet u_int oflags; 3190129198Scognet vm_paddr_t pa; 3191129198Scognet 3192135641Scognet pmap_update(pmap); 3193135641Scognet vm_page_lock_queues(); 3194129198Scognet if (va == vector_page) { 3195129198Scognet pa = systempage.pv_pa; 3196129198Scognet m = NULL; 3197129198Scognet } else 3198129198Scognet pa = VM_PAGE_TO_PHYS(m); 3199129198Scognet nflags = 0; 3200129198Scognet if (prot & VM_PROT_WRITE) 3201129198Scognet nflags |= PVF_WRITE; 3202129198Scognet if (prot & VM_PROT_EXECUTE) 3203129198Scognet nflags |= PVF_EXEC; 3204129198Scognet if (wired) 3205129198Scognet nflags |= PVF_WIRED; 3206129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3207129198Scognet "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired)); 3208129198Scognet 3209135641Scognet if (pmap == pmap_kernel()) { 3210129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3211135641Scognet if (l2b == NULL) 3212135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3213135641Scognet } else 3214129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3215135641Scognet KASSERT(l2b != NULL, 3216135641Scognet ("pmap_enter: failed to allocate l2 bucket")); 3217129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3218129198Scognet 3219135641Scognet opte = *ptep; 3220129198Scognet npte = pa; 3221129198Scognet oflags = 0; 3222129198Scognet if (opte) { 3223129198Scognet /* 3224129198Scognet * There is already a mapping at this address. 3225129198Scognet * If the physical address is different, lookup the 3226129198Scognet * vm_page. 3227129198Scognet */ 3228129198Scognet if (l2pte_pa(opte) != pa) 3229129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3230129198Scognet else 3231129198Scognet opg = m; 3232129198Scognet } else 3233129198Scognet opg = NULL; 3234129198Scognet 3235135641Scognet if ((prot & (VM_PROT_ALL)) || 3236135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3237129198Scognet /* 3238135641Scognet * - The access type indicates that we don't need 3239135641Scognet * to do referenced emulation. 3240135641Scognet * OR 3241135641Scognet * - The physical page has already been referenced 3242135641Scognet * so no need to re-do referenced emulation here. 3243129198Scognet */ 3244135641Scognet npte |= L2_S_PROTO; 3245135641Scognet 3246135641Scognet nflags |= PVF_REF; 3247135641Scognet 3248135641Scognet if (((prot & VM_PROT_WRITE) != 0 && 3249135641Scognet m && ((m->flags & PG_WRITEABLE) || 3250135641Scognet (m->md.pvh_attrs & PVF_MOD) != 0))) { 3251129198Scognet /* 3252135641Scognet * This is a writable mapping, and the 3253135641Scognet * page's mod state indicates it has 3254135641Scognet * already been modified. Make it 3255135641Scognet * writable from the outset. 3256129198Scognet */ 3257135641Scognet nflags |= PVF_MOD; 3258129198Scognet } 3259135641Scognet } else { 3260135641Scognet /* 3261135641Scognet * Need to do page referenced emulation. 3262135641Scognet */ 3263135641Scognet npte |= L2_TYPE_INV; 3264135641Scognet } 3265135641Scognet 3266135641Scognet if (prot & VM_PROT_WRITE) 3267135641Scognet npte |= L2_S_PROT_W; 3268135641Scognet npte |= pte_l2_s_cache_mode; 3269135641Scognet if (m && m == opg) { 3270135641Scognet /* 3271135641Scognet * We're changing the attrs of an existing mapping. 3272135641Scognet */ 3273129198Scognet#if 0 3274135641Scognet simple_lock(&pg->mdpage.pvh_slock); 3275129198Scognet#endif 3276135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3277135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3278135641Scognet PVF_MOD | PVF_REF, nflags); 3279129198Scognet#if 0 3280135641Scognet simple_unlock(&pg->mdpage.pvh_slock); 3281129198Scognet#endif 3282135641Scognet 3283135641Scognet /* 3284135641Scognet * We may need to flush the cache if we're 3285135641Scognet * doing rw-ro... 3286135641Scognet */ 3287135641Scognet if (pmap_is_current(pmap) && 3288135641Scognet (oflags & PVF_NC) == 0 && 3289129198Scognet (opte & L2_S_PROT_W) != 0 && 3290129198Scognet (prot & VM_PROT_WRITE) == 0) 3291135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3292129198Scognet } else { 3293129198Scognet /* 3294135641Scognet * New mapping, or changing the backing page 3295135641Scognet * of an existing mapping. 3296129198Scognet */ 3297129198Scognet if (opg) { 3298129198Scognet /* 3299135641Scognet * Replacing an existing mapping with a new one. 3300135641Scognet * It is part of our managed memory so we 3301135641Scognet * must remove it from the PV list 3302129198Scognet */ 3303129198Scognet#if 0 3304129198Scognet simple_lock(&opg->mdpage.pvh_slock); 3305129198Scognet#endif 3306129198Scognet pve = pmap_remove_pv(opg, pmap, va); 3307135641Scognet if (!m) 3308135641Scognet pmap_free_pv_entry(pve); 3309129198Scognet pmap_vac_me_harder(opg, pmap, 0); 3310135641Scognet KASSERT(pve != NULL, ("No pv")); 3311129198Scognet#if 0 3312129198Scognet simple_unlock(&opg->mdpage.pvh_slock); 3313129198Scognet#endif 3314129198Scognet oflags = pve->pv_flags; 3315135641Scognet 3316135641Scognet /* 3317135641Scognet * If the old mapping was valid (ref/mod 3318135641Scognet * emulation creates 'invalid' mappings 3319135641Scognet * initially) then make sure to frob 3320135641Scognet * the cache. 3321135641Scognet */ 3322135641Scognet if ((oflags & PVF_NC) == 0 && 3323135641Scognet l2pte_valid(opte)) { 3324135641Scognet if (PV_BEEN_EXECD(oflags)) { 3325129198Scognet pmap_idcache_wbinv_range(pmap, va, 3326129198Scognet PAGE_SIZE); 3327135641Scognet } else 3328135641Scognet if (PV_BEEN_REFD(oflags)) { 3329135641Scognet pmap_dcache_wb_range(pmap, va, 3330135641Scognet PAGE_SIZE, TRUE, 3331135641Scognet (oflags & PVF_WRITE) == 0); 3332135641Scognet } 3333129198Scognet } 3334135641Scognet } else if (m) 3335135641Scognet if ((pve = pmap_get_pv_entry()) == NULL) { 3336135641Scognet panic("pmap_enter: no pv entries"); 3337135641Scognet } 3338135641Scognet if (m) 3339135641Scognet pmap_enter_pv(m, pve, pmap, va, nflags); 3340129198Scognet } 3341129198Scognet /* 3342129198Scognet * Make sure userland mappings get the right permissions 3343129198Scognet */ 3344129198Scognet if (pmap != pmap_kernel() && va != vector_page) { 3345129198Scognet npte |= L2_S_PROT_U; 3346129198Scognet } 3347129198Scognet 3348129198Scognet /* 3349129198Scognet * Keep the stats up to date 3350129198Scognet */ 3351129198Scognet if (opte == 0) { 3352129198Scognet l2b->l2b_occupancy++; 3353129198Scognet pmap->pm_stats.resident_count++; 3354129198Scognet } 3355129198Scognet 3356129198Scognet 3357129198Scognet /* 3358129198Scognet * If this is just a wiring change, the two PTEs will be 3359129198Scognet * identical, so there's no need to update the page table. 3360129198Scognet */ 3361129198Scognet if (npte != opte) { 3362135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3363129198Scognet 3364129198Scognet *ptep = npte; 3365129198Scognet if (is_cached) { 3366129198Scognet /* 3367129198Scognet * We only need to frob the cache/tlb if this pmap 3368129198Scognet * is current 3369129198Scognet */ 3370129198Scognet PTE_SYNC(ptep); 3371129198Scognet if (L1_IDX(va) != L1_IDX(vector_page) && 3372129198Scognet l2pte_valid(npte)) { 3373129198Scognet /* 3374129198Scognet * This mapping is likely to be accessed as 3375129198Scognet * soon as we return to userland. Fix up the 3376129198Scognet * L1 entry to avoid taking another 3377129198Scognet * page/domain fault. 3378129198Scognet */ 3379129198Scognet pd_entry_t *pl1pd, l1pd; 3380129198Scognet 3381129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3382129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3383135641Scognet L1_C_PROTO | pte_l1_s_cache_mode_pt; 3384129198Scognet if (*pl1pd != l1pd) { 3385129198Scognet *pl1pd = l1pd; 3386129198Scognet PTE_SYNC(pl1pd); 3387129198Scognet } 3388129198Scognet } 3389129198Scognet } 3390129198Scognet 3391129198Scognet if (PV_BEEN_EXECD(oflags)) 3392129198Scognet pmap_tlb_flushID_SE(pmap, va); 3393135641Scognet else if (PV_BEEN_REFD(oflags)) 3394129198Scognet pmap_tlb_flushD_SE(pmap, va); 3395129198Scognet 3396129198Scognet 3397135641Scognet pmap_vac_me_harder(m, pmap, va); 3398129198Scognet } 3399135641Scognet vm_page_unlock_queues(); 3400129198Scognet} 3401129198Scognet 3402129198Scognet/* 3403129198Scognet * this code makes some *MAJOR* assumptions: 3404129198Scognet * 1. Current pmap & pmap exists. 3405129198Scognet * 2. Not wired. 3406129198Scognet * 3. Read access. 3407129198Scognet * 4. No page table pages. 3408129198Scognet * 5. Tlbflush is deferred to calling procedure. 3409129198Scognet * 6. Page IS managed. 3410129198Scognet * but is *MUCH* faster than pmap_enter... 3411129198Scognet */ 3412129198Scognet 3413129198Scognetvm_page_t 3414129198Scognetpmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t mpte) 3415129198Scognet{ 3416135641Scognet pmap_enter(pmap, va, m, VM_PROT_READ|VM_PROT_EXECUTE, FALSE); 3417137549Scognet pmap_dcache_wbinv_all(pmap); /* XXX: shouldn't be needed */ 3418129198Scognet return (NULL); 3419129198Scognet} 3420129198Scognet 3421129198Scognet/* 3422129198Scognet * Routine: pmap_change_wiring 3423129198Scognet * Function: Change the wiring attribute for a map/virtual-address 3424129198Scognet * pair. 3425129198Scognet * In/out conditions: 3426129198Scognet * The mapping must already exist in the pmap. 3427129198Scognet */ 3428129198Scognetvoid 3429129198Scognetpmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3430129198Scognet{ 3431129198Scognet struct l2_bucket *l2b; 3432129198Scognet pt_entry_t *ptep, pte; 3433129198Scognet vm_page_t pg; 3434129198Scognet 3435129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3436129198Scognet KASSERT(l2b, ("No l2b bucket in pmap_change_wiring")); 3437129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3438129198Scognet pte = *ptep; 3439129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3440129198Scognet if (pg) 3441129198Scognet pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired); 3442129198Scognet} 3443129198Scognet 3444129198Scognet 3445129198Scognet/* 3446129198Scognet * Copy the range specified by src_addr/len 3447129198Scognet * from the source map to the range dst_addr/len 3448129198Scognet * in the destination map. 3449129198Scognet * 3450129198Scognet * This routine is only advisory and need not do anything. 3451129198Scognet */ 3452129198Scognetvoid 3453129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3454129198Scognet vm_size_t len, vm_offset_t src_addr) 3455129198Scognet{ 3456129198Scognet} 3457129198Scognet 3458129198Scognet 3459129198Scognet/* 3460129198Scognet * Routine: pmap_extract 3461129198Scognet * Function: 3462129198Scognet * Extract the physical page address associated 3463129198Scognet * with the given map/virtual_address pair. 3464129198Scognet */ 3465131658Salcvm_paddr_t 3466129198Scognetpmap_extract(pmap_t pm, vm_offset_t va) 3467129198Scognet{ 3468129198Scognet struct l2_dtable *l2; 3469129198Scognet pd_entry_t *pl1pd, l1pd; 3470129198Scognet pt_entry_t *ptep, pte; 3471129198Scognet vm_paddr_t pa; 3472129198Scognet u_int l1idx; 3473129198Scognet l1idx = L1_IDX(va); 3474129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 3475129198Scognet l1pd = *pl1pd; 3476129198Scognet 3477129198Scognet if (l1pte_section_p(l1pd)) { 3478129198Scognet /* 3479129198Scognet * These should only happen for pmap_kernel() 3480129198Scognet */ 3481129198Scognet KASSERT(pm == pmap_kernel(), ("huh")); 3482129198Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3483129198Scognet } else { 3484129198Scognet /* 3485129198Scognet * Note that we can't rely on the validity of the L1 3486129198Scognet * descriptor as an indication that a mapping exists. 3487129198Scognet * We have to look it up in the L2 dtable. 3488129198Scognet */ 3489129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 3490129198Scognet 3491129198Scognet if (l2 == NULL || 3492129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3493129198Scognet return (0); 3494129198Scognet } 3495129198Scognet 3496129198Scognet ptep = &ptep[l2pte_index(va)]; 3497129198Scognet pte = *ptep; 3498129198Scognet 3499129198Scognet if (pte == 0) 3500129198Scognet return (0); 3501129198Scognet 3502129198Scognet switch (pte & L2_TYPE_MASK) { 3503129198Scognet case L2_TYPE_L: 3504129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3505129198Scognet break; 3506129198Scognet 3507129198Scognet default: 3508129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3509129198Scognet break; 3510129198Scognet } 3511129198Scognet } 3512129198Scognet 3513129198Scognet return (pa); 3514129198Scognet} 3515129198Scognet 3516133453Salc/* 3517133453Salc * Atomically extract and hold the physical page with the given 3518133453Salc * pmap and virtual address pair if that mapping permits the given 3519133453Salc * protection. 3520133453Salc * 3521133453Salc */ 3522129198Scognetvm_page_t 3523129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3524129198Scognet{ 3525135641Scognet struct l2_dtable *l2; 3526135641Scognet pd_entry_t *pl1pd, l1pd; 3527135641Scognet pt_entry_t *ptep, pte; 3528129198Scognet vm_paddr_t pa; 3529135641Scognet vm_page_t m = NULL; 3530135641Scognet u_int l1idx; 3531135641Scognet l1idx = L1_IDX(va); 3532135641Scognet pl1pd = &pmap->pm_l1->l1_kva[l1idx]; 3533135641Scognet l1pd = *pl1pd; 3534129198Scognet 3535135641Scognet vm_page_lock_queues(); 3536135641Scognet if (l1pte_section_p(l1pd)) { 3537135641Scognet /* 3538135641Scognet * These should only happen for pmap_kernel() 3539135641Scognet */ 3540135641Scognet KASSERT(pmap == pmap_kernel(), ("huh")); 3541135641Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3542135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3543135641Scognet m = PHYS_TO_VM_PAGE(pa); 3544135641Scognet vm_page_hold(m); 3545135641Scognet } 3546135641Scognet 3547135641Scognet } else { 3548135641Scognet /* 3549135641Scognet * Note that we can't rely on the validity of the L1 3550135641Scognet * descriptor as an indication that a mapping exists. 3551135641Scognet * We have to look it up in the L2 dtable. 3552135641Scognet */ 3553135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3554135641Scognet 3555135641Scognet if (l2 == NULL || 3556135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3557135641Scognet return (NULL); 3558135641Scognet } 3559135641Scognet 3560135641Scognet ptep = &ptep[l2pte_index(va)]; 3561135641Scognet pte = *ptep; 3562135641Scognet 3563135641Scognet if (pte == 0) 3564135641Scognet return (NULL); 3565135641Scognet 3566135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3567135641Scognet switch (pte & L2_TYPE_MASK) { 3568135641Scognet case L2_TYPE_L: 3569135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3570135641Scognet break; 3571135641Scognet 3572135641Scognet default: 3573135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3574135641Scognet break; 3575135641Scognet } 3576135641Scognet m = PHYS_TO_VM_PAGE(pa); 3577135641Scognet vm_page_hold(m); 3578135641Scognet } 3579129198Scognet } 3580135641Scognet 3581135641Scognet vm_page_unlock_queues(); 3582129198Scognet return (m); 3583129198Scognet} 3584129198Scognet 3585129198Scognetvoid 3586129198Scognetpmap_update(pmap_t pm) 3587129198Scognet{ 3588129198Scognet 3589129198Scognet if (pmap_is_current(pm)) { 3590129198Scognet /* 3591129198Scognet * If we're dealing with a current userland pmap, move its L1 3592129198Scognet * to the end of the LRU. 3593129198Scognet */ 3594129198Scognet if (pm != pmap_kernel()) 3595129198Scognet pmap_use_l1(pm); 3596129198Scognet } 3597129198Scognet 3598129198Scognet} 3599129198Scognet 3600129198Scognet 3601129198Scognet/* 3602129198Scognet * Initialize a preallocated and zeroed pmap structure, 3603129198Scognet * such as one in a vmspace structure. 3604129198Scognet */ 3605129198Scognet 3606129198Scognetvoid 3607129198Scognetpmap_pinit(pmap_t pmap) 3608129198Scognet{ 3609129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3610129198Scognet 3611129198Scognet pmap_alloc_l1(pmap); 3612129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3613129198Scognet 3614129198Scognet LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 3615129198Scognet pmap->pm_count = 1; 3616129198Scognet pmap->pm_active = 0; 3617129198Scognet 3618129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3619129198Scognet pmap->pm_stats.resident_count = 1; 3620129198Scognet if (vector_page < KERNBASE) { 3621129198Scognet pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3622129198Scognet VM_PROT_READ, 1); 3623129198Scognet pmap_update(pmap); 3624129198Scognet } 3625129198Scognet} 3626129198Scognet 3627129198Scognet 3628129198Scognet/*************************************************** 3629129198Scognet * page management routines. 3630129198Scognet ***************************************************/ 3631129198Scognet 3632129198Scognet 3633135641Scognetstatic void 3634129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3635129198Scognet{ 3636129198Scognet pv_entry_count--; 3637129198Scognet uma_zfree(pvzone, pv); 3638129198Scognet} 3639129198Scognet 3640129198Scognet 3641129198Scognet/* 3642129198Scognet * get a new pv_entry, allocating a block from the system 3643129198Scognet * when needed. 3644129198Scognet * the memory allocation is performed bypassing the malloc code 3645129198Scognet * because of the possibility of allocations at interrupt time. 3646129198Scognet */ 3647129198Scognetstatic pv_entry_t 3648129198Scognetpmap_get_pv_entry(void) 3649129198Scognet{ 3650129198Scognet pv_entry_t ret_value; 3651129198Scognet 3652129198Scognet pv_entry_count++; 3653129198Scognet if (pv_entry_high_water && 3654129198Scognet (pv_entry_count > pv_entry_high_water) && 3655129198Scognet (pmap_pagedaemon_waken == 0)) { 3656129198Scognet pmap_pagedaemon_waken = 1; 3657129198Scognet wakeup (&vm_pages_needed); 3658129198Scognet } 3659129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3660129198Scognet return ret_value; 3661129198Scognet} 3662129198Scognet 3663129198Scognet 3664129198Scognet/* 3665129198Scognet * Remove the given range of addresses from the specified map. 3666129198Scognet * 3667129198Scognet * It is assumed that the start and end are properly 3668129198Scognet * rounded to the page size. 3669129198Scognet */ 3670129198Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3671129198Scognetvoid 3672129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3673129198Scognet{ 3674129198Scognet struct l2_bucket *l2b; 3675129198Scognet vm_offset_t next_bucket; 3676129198Scognet pt_entry_t *ptep; 3677129198Scognet u_int cleanlist_idx, total, cnt; 3678129198Scognet struct { 3679129198Scognet vm_offset_t va; 3680129198Scognet pt_entry_t *pte; 3681129198Scognet } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE]; 3682129198Scognet u_int mappings, is_exec, is_refd; 3683135641Scognet int flushall = 0; 3684129198Scognet 3685129198Scognet 3686129198Scognet /* 3687129198Scognet * we lock in the pmap => pv_head direction 3688129198Scognet */ 3689129198Scognet#if 0 3690129198Scognet PMAP_MAP_TO_HEAD_LOCK(); 3691129198Scognet pmap_acquire_pmap_lock(pm); 3692129198Scognet#endif 3693129198Scognet 3694135641Scognet pmap_update(pm); 3695135641Scognet if (!pmap_is_current(pm)) { 3696129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3697129198Scognet } else 3698129198Scognet cleanlist_idx = 0; 3699129198Scognet 3700129198Scognet total = 0; 3701129198Scognet while (sva < eva) { 3702129198Scognet /* 3703129198Scognet * Do one L2 bucket's worth at a time. 3704129198Scognet */ 3705129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3706129198Scognet if (next_bucket > eva) 3707129198Scognet next_bucket = eva; 3708129198Scognet 3709129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3710129198Scognet if (l2b == NULL) { 3711129198Scognet sva = next_bucket; 3712129198Scognet continue; 3713129198Scognet } 3714129198Scognet 3715129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3716129198Scognet mappings = 0; 3717129198Scognet 3718129198Scognet while (sva < next_bucket) { 3719129198Scognet struct vm_page *pg; 3720129198Scognet pt_entry_t pte; 3721129198Scognet vm_paddr_t pa; 3722129198Scognet 3723129198Scognet pte = *ptep; 3724129198Scognet 3725129198Scognet if (pte == 0) { 3726129198Scognet /* 3727129198Scognet * Nothing here, move along 3728129198Scognet */ 3729129198Scognet sva += PAGE_SIZE; 3730129198Scognet ptep++; 3731129198Scognet continue; 3732129198Scognet } 3733129198Scognet 3734129198Scognet pm->pm_stats.resident_count--; 3735129198Scognet pa = l2pte_pa(pte); 3736129198Scognet is_exec = 0; 3737129198Scognet is_refd = 1; 3738129198Scognet 3739129198Scognet /* 3740129198Scognet * Update flags. In a number of circumstances, 3741129198Scognet * we could cluster a lot of these and do a 3742129198Scognet * number of sequential pages in one go. 3743129198Scognet */ 3744129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3745129198Scognet struct pv_entry *pve; 3746129198Scognet#if 0 3747129198Scognet simple_lock(&pg->mdpage.pvh_slock); 3748129198Scognet#endif 3749129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3750135641Scognet if (pve) { 3751129198Scognet#if 0 3752129198Scognet simple_unlock(&pg->mdpage.pvh_slock); 3753129198Scognet#endif 3754129198Scognet is_exec = 3755129198Scognet PV_BEEN_EXECD(pve->pv_flags); 3756129198Scognet is_refd = 3757129198Scognet PV_BEEN_REFD(pve->pv_flags); 3758129198Scognet pmap_free_pv_entry(pve); 3759129198Scognet } 3760129198Scognet } 3761129198Scognet 3762129198Scognet if (!l2pte_valid(pte)) { 3763129198Scognet *ptep = 0; 3764129198Scognet PTE_SYNC_CURRENT(pm, ptep); 3765129198Scognet sva += PAGE_SIZE; 3766129198Scognet ptep++; 3767129198Scognet mappings++; 3768129198Scognet continue; 3769129198Scognet } 3770129198Scognet 3771129198Scognet if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3772129198Scognet /* Add to the clean list. */ 3773129198Scognet cleanlist[cleanlist_idx].pte = ptep; 3774129198Scognet cleanlist[cleanlist_idx].va = 3775129198Scognet sva | (is_exec & 1); 3776129198Scognet cleanlist_idx++; 3777129198Scognet } else 3778129198Scognet if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3779129198Scognet /* Nuke everything if needed. */ 3780129198Scognet pmap_idcache_wbinv_all(pm); 3781129198Scognet pmap_tlb_flushID(pm); 3782129198Scognet 3783129198Scognet /* 3784129198Scognet * Roll back the previous PTE list, 3785129198Scognet * and zero out the current PTE. 3786129198Scognet */ 3787129198Scognet for (cnt = 0; 3788129198Scognet cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) { 3789129198Scognet *cleanlist[cnt].pte = 0; 3790129198Scognet } 3791129198Scognet *ptep = 0; 3792129198Scognet PTE_SYNC(ptep); 3793129198Scognet cleanlist_idx++; 3794135641Scognet flushall = 1; 3795129198Scognet } else { 3796129198Scognet *ptep = 0; 3797129198Scognet PTE_SYNC(ptep); 3798129198Scognet if (is_exec) 3799129198Scognet pmap_tlb_flushID_SE(pm, sva); 3800129198Scognet else 3801129198Scognet if (is_refd) 3802129198Scognet pmap_tlb_flushD_SE(pm, sva); 3803129198Scognet } 3804129198Scognet 3805129198Scognet sva += PAGE_SIZE; 3806129198Scognet ptep++; 3807129198Scognet mappings++; 3808129198Scognet } 3809129198Scognet 3810129198Scognet /* 3811129198Scognet * Deal with any left overs 3812129198Scognet */ 3813129198Scognet if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) { 3814129198Scognet total += cleanlist_idx; 3815129198Scognet for (cnt = 0; cnt < cleanlist_idx; cnt++) { 3816135641Scognet vm_offset_t clva = 3817135641Scognet cleanlist[cnt].va & ~1; 3818135641Scognet if (cleanlist[cnt].va & 1) { 3819135641Scognet pmap_idcache_wbinv_range(pm, 3820135641Scognet clva, PAGE_SIZE); 3821135641Scognet pmap_tlb_flushID_SE(pm, clva); 3822135641Scognet } else { 3823135641Scognet pmap_dcache_wb_range(pm, 3824135641Scognet clva, PAGE_SIZE, TRUE, 3825135641Scognet FALSE); 3826135641Scognet pmap_tlb_flushD_SE(pm, clva); 3827129198Scognet } 3828129198Scognet *cleanlist[cnt].pte = 0; 3829129198Scognet PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte); 3830129198Scognet } 3831129198Scognet 3832129198Scognet /* 3833129198Scognet * If it looks like we're removing a whole bunch 3834129198Scognet * of mappings, it's faster to just write-back 3835129198Scognet * the whole cache now and defer TLB flushes until 3836129198Scognet * pmap_update() is called. 3837129198Scognet */ 3838129198Scognet if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE) 3839129198Scognet cleanlist_idx = 0; 3840129198Scognet else { 3841129198Scognet cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1; 3842129198Scognet pmap_idcache_wbinv_all(pm); 3843135641Scognet flushall = 1; 3844129198Scognet } 3845129198Scognet } 3846129198Scognet 3847129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 3848129198Scognet } 3849129198Scognet 3850135641Scognet if (flushall) 3851135641Scognet cpu_tlb_flushID(); 3852129198Scognet#if 0 3853129198Scognet pmap_release_pmap_lock(pm); 3854129198Scognet PMAP_MAP_TO_HEAD_UNLOCK(); 3855129198Scognet#endif 3856129198Scognet} 3857129198Scognet 3858129198Scognet 3859129198Scognet 3860129198Scognet 3861129198Scognet/* 3862129198Scognet * pmap_zero_page() 3863129198Scognet * 3864129198Scognet * Zero a given physical page by mapping it at a page hook point. 3865129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 3866129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 3867129198Scognet * _any_ bulk data very slow. 3868129198Scognet */ 3869129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 3870129198Scognetvoid 3871129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 3872129198Scognet{ 3873129198Scognet#ifdef DEBUG 3874129198Scognet struct vm_page *pg = PHYS_TO_VM_PAGE(phys); 3875129198Scognet 3876129198Scognet if (pg->md.pvh_list != NULL) 3877129198Scognet panic("pmap_zero_page: page has mappings"); 3878129198Scognet#endif 3879129198Scognet 3880129198Scognet 3881129198Scognet /* 3882129198Scognet * Hook in the page, zero it, and purge the cache for that 3883129198Scognet * zeroed page. Invalidate the TLB as needed. 3884129198Scognet */ 3885129198Scognet *cdst_pte = L2_S_PROTO | phys | 3886129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 3887129198Scognet PTE_SYNC(cdst_pte); 3888129198Scognet cpu_tlb_flushD_SE(cdstp); 3889129198Scognet cpu_cpwait(); 3890135641Scognet if (off || size != PAGE_SIZE) 3891129198Scognet bzero((void *)(cdstp + off), size); 3892129198Scognet else 3893129198Scognet bzero_page(cdstp); 3894129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 3895129198Scognet} 3896129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 3897129198Scognet 3898129198Scognet#if ARM_MMU_XSCALE == 1 3899129198Scognetvoid 3900129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 3901129198Scognet{ 3902129198Scognet /* 3903129198Scognet * Hook in the page, zero it, and purge the cache for that 3904129198Scognet * zeroed page. Invalidate the TLB as needed. 3905129198Scognet */ 3906129198Scognet *cdst_pte = L2_S_PROTO | phys | 3907129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 3908129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 3909129198Scognet PTE_SYNC(cdst_pte); 3910129198Scognet cpu_tlb_flushD_SE(cdstp); 3911129198Scognet cpu_cpwait(); 3912135641Scognet if (off || size != PAGE_SIZE) 3913129198Scognet bzero((void *)(cdstp + off), size); 3914129198Scognet else 3915129198Scognet bzero_page(cdstp); 3916129198Scognet xscale_cache_clean_minidata(); 3917129198Scognet} 3918129198Scognet 3919129198Scognet/* 3920129198Scognet * Change the PTEs for the specified kernel mappings such that they 3921129198Scognet * will use the mini data cache instead of the main data cache. 3922129198Scognet */ 3923129198Scognetvoid 3924135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 3925129198Scognet{ 3926129198Scognet struct l2_bucket *l2b; 3927129198Scognet pt_entry_t *ptep, *sptep, pte; 3928129198Scognet vm_offset_t next_bucket, eva; 3929129198Scognet 3930129198Scognet#if (ARM_NMMUS > 1) 3931129198Scognet if (xscale_use_minidata == 0) 3932129198Scognet return; 3933129198Scognet#endif 3934129198Scognet 3935135641Scognet return; 3936135641Scognet eva = va + size; 3937129198Scognet 3938129198Scognet while (va < eva) { 3939129198Scognet next_bucket = L2_NEXT_BUCKET(va); 3940129198Scognet if (next_bucket > eva) 3941129198Scognet next_bucket = eva; 3942129198Scognet 3943129198Scognet l2b = pmap_get_l2_bucket(pmap_kernel(), va); 3944129198Scognet 3945129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 3946129198Scognet 3947129198Scognet while (va < next_bucket) { 3948129198Scognet pte = *ptep; 3949129198Scognet if (!l2pte_minidata(pte)) { 3950129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 3951129198Scognet cpu_tlb_flushD_SE(va); 3952129198Scognet *ptep = pte & ~L2_B; 3953129198Scognet } 3954129198Scognet ptep++; 3955129198Scognet va += PAGE_SIZE; 3956129198Scognet } 3957129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 3958129198Scognet } 3959129198Scognet cpu_cpwait(); 3960129198Scognet} 3961129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 3962129198Scognet 3963129198Scognet/* 3964129198Scognet * pmap_zero_page zeros the specified hardware page by mapping 3965129198Scognet * the page into KVM and using bzero to clear its contents. 3966129198Scognet */ 3967129198Scognetvoid 3968129198Scognetpmap_zero_page(vm_page_t m) 3969129198Scognet{ 3970135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 3971129198Scognet} 3972129198Scognet 3973129198Scognet 3974129198Scognet/* 3975129198Scognet * pmap_zero_page_area zeros the specified hardware page by mapping 3976129198Scognet * the page into KVM and using bzero to clear its contents. 3977129198Scognet * 3978129198Scognet * off and size may not cover an area beyond a single hardware page. 3979129198Scognet */ 3980129198Scognetvoid 3981129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 3982129198Scognet{ 3983129198Scognet 3984129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 3985129198Scognet} 3986129198Scognet 3987129198Scognet 3988129198Scognet/* 3989129198Scognet * pmap_zero_page_idle zeros the specified hardware page by mapping 3990129198Scognet * the page into KVM and using bzero to clear its contents. This 3991129198Scognet * is intended to be called from the vm_pagezero process only and 3992129198Scognet * outside of Giant. 3993129198Scognet */ 3994129198Scognetvoid 3995129198Scognetpmap_zero_page_idle(vm_page_t m) 3996129198Scognet{ 3997129198Scognet 3998129198Scognet pmap_zero_page(m); 3999129198Scognet} 4000129198Scognet 4001129198Scognet/* 4002129198Scognet * pmap_clean_page() 4003129198Scognet * 4004129198Scognet * This is a local function used to work out the best strategy to clean 4005129198Scognet * a single page referenced by its entry in the PV table. It's used by 4006129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4007129198Scognet * 4008129198Scognet * Its policy is effectively: 4009129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4010129198Scognet * o If there is one mapping, we clean just that page. 4011129198Scognet * o If there are multiple mappings, we clean the entire cache. 4012129198Scognet * 4013129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4014129198Scognet * clean the entire cache, or 1 if it did. 4015129198Scognet * 4016129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4017129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4018129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4019129198Scognet * it will just result in not the most efficient clean for the page. 4020129198Scognet */ 4021129198Scognetstatic int 4022129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4023129198Scognet{ 4024129198Scognet pmap_t pm, pm_to_clean = NULL; 4025129198Scognet struct pv_entry *npv; 4026129198Scognet u_int cache_needs_cleaning = 0; 4027129198Scognet u_int flags = 0; 4028129198Scognet vm_offset_t page_to_clean = 0; 4029129198Scognet 4030129198Scognet if (pv == NULL) { 4031129198Scognet /* nothing mapped in so nothing to flush */ 4032129198Scognet return (0); 4033129198Scognet } 4034129198Scognet 4035129198Scognet /* 4036129198Scognet * Since we flush the cache each time we change to a different 4037129198Scognet * user vmspace, we only need to flush the page if it is in the 4038129198Scognet * current pmap. 4039129198Scognet */ 4040135641Scognet if (curthread) 4041135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4042129198Scognet else 4043129198Scognet pm = pmap_kernel(); 4044129198Scognet 4045129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4046129198Scognet if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) { 4047129198Scognet flags |= npv->pv_flags; 4048135641Scognet pmap_update(npv->pv_pmap); 4049129198Scognet /* 4050129198Scognet * The page is mapped non-cacheable in 4051129198Scognet * this map. No need to flush the cache. 4052129198Scognet */ 4053129198Scognet if (npv->pv_flags & PVF_NC) { 4054129198Scognet#ifdef DIAGNOSTIC 4055129198Scognet if (cache_needs_cleaning) 4056129198Scognet panic("pmap_clean_page: " 4057129198Scognet "cache inconsistency"); 4058129198Scognet#endif 4059129198Scognet break; 4060129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4061129198Scognet continue; 4062129198Scognet if (cache_needs_cleaning) { 4063129198Scognet page_to_clean = 0; 4064129198Scognet break; 4065129198Scognet } else { 4066129198Scognet page_to_clean = npv->pv_va; 4067129198Scognet pm_to_clean = npv->pv_pmap; 4068129198Scognet } 4069129198Scognet cache_needs_cleaning = 1; 4070129198Scognet } 4071129198Scognet } 4072129198Scognet if (page_to_clean) { 4073129198Scognet if (PV_BEEN_EXECD(flags)) 4074129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4075129198Scognet PAGE_SIZE); 4076129198Scognet else 4077129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4078129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4079129198Scognet } else if (cache_needs_cleaning) { 4080129198Scognet if (PV_BEEN_EXECD(flags)) 4081129198Scognet pmap_idcache_wbinv_all(pm); 4082129198Scognet else 4083129198Scognet pmap_dcache_wbinv_all(pm); 4084129198Scognet return (1); 4085129198Scognet } 4086129198Scognet return (0); 4087129198Scognet} 4088129198Scognet 4089129198Scognet/* 4090129198Scognet * pmap_copy_page copies the specified (machine independent) 4091129198Scognet * page by mapping the page into virtual memory and using 4092129198Scognet * bcopy to copy the page, one machine dependent page at a 4093129198Scognet * time. 4094129198Scognet */ 4095129198Scognet 4096129198Scognet/* 4097129198Scognet * pmap_copy_page() 4098129198Scognet * 4099129198Scognet * Copy one physical page into another, by mapping the pages into 4100129198Scognet * hook points. The same comment regarding cachability as in 4101129198Scognet * pmap_zero_page also applies here. 4102129198Scognet */ 4103129198Scognet#if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 4104129198Scognetvoid 4105129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4106129198Scognet{ 4107129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4108129198Scognet#ifdef DEBUG 4109129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4110129198Scognet 4111129198Scognet if (dst_pg->md.pvh_list != NULL) 4112129198Scognet panic("pmap_copy_page: dst page has mappings"); 4113129198Scognet#endif 4114129198Scognet 4115129198Scognet 4116129198Scognet /* 4117129198Scognet * Clean the source page. Hold the source page's lock for 4118129198Scognet * the duration of the copy so that no other mappings can 4119129198Scognet * be created while we have a potentially aliased mapping. 4120129198Scognet */ 4121129198Scognet#if 0 4122129198Scognet mtx_lock(&src_pg->md.pvh_mtx); 4123129198Scognet#endif 4124129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4125129198Scognet 4126129198Scognet /* 4127129198Scognet * Map the pages into the page hook points, copy them, and purge 4128129198Scognet * the cache for the appropriate page. Invalidate the TLB 4129129198Scognet * as required. 4130129198Scognet */ 4131129198Scognet *csrc_pte = L2_S_PROTO | src | 4132129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4133129198Scognet PTE_SYNC(csrc_pte); 4134129198Scognet *cdst_pte = L2_S_PROTO | dst | 4135129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4136129198Scognet PTE_SYNC(cdst_pte); 4137129198Scognet cpu_tlb_flushD_SE(csrcp); 4138129198Scognet cpu_tlb_flushD_SE(cdstp); 4139129198Scognet cpu_cpwait(); 4140129198Scognet bcopy_page(csrcp, cdstp); 4141129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4142129198Scognet#if 0 4143129198Scognet mtx_lock(&src_pg->md.pvh_mtx); 4144129198Scognet#endif 4145129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4146129198Scognet} 4147129198Scognet#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 4148129198Scognet 4149129198Scognet#if ARM_MMU_XSCALE == 1 4150129198Scognetvoid 4151129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4152129198Scognet{ 4153129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4154129198Scognet#ifdef DEBUG 4155129198Scognet struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst); 4156129198Scognet 4157129198Scognet if (dst_pg->md.pvh_list != NULL) 4158129198Scognet panic("pmap_copy_page: dst page has mappings"); 4159129198Scognet#endif 4160129198Scognet 4161129198Scognet 4162129198Scognet /* 4163129198Scognet * Clean the source page. Hold the source page's lock for 4164129198Scognet * the duration of the copy so that no other mappings can 4165129198Scognet * be created while we have a potentially aliased mapping. 4166129198Scognet */ 4167130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4168129198Scognet 4169129198Scognet /* 4170129198Scognet * Map the pages into the page hook points, copy them, and purge 4171129198Scognet * the cache for the appropriate page. Invalidate the TLB 4172129198Scognet * as required. 4173129198Scognet */ 4174129198Scognet *csrc_pte = L2_S_PROTO | src | 4175129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4176129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4177129198Scognet PTE_SYNC(csrc_pte); 4178129198Scognet *cdst_pte = L2_S_PROTO | dst | 4179129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4180129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4181129198Scognet PTE_SYNC(cdst_pte); 4182129198Scognet cpu_tlb_flushD_SE(csrcp); 4183129198Scognet cpu_tlb_flushD_SE(cdstp); 4184129198Scognet cpu_cpwait(); 4185129198Scognet bcopy_page(csrcp, cdstp); 4186129198Scognet xscale_cache_clean_minidata(); 4187129198Scognet} 4188129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4189129198Scognet 4190129198Scognetvoid 4191129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4192129198Scognet{ 4193129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4194129198Scognet} 4195129198Scognet 4196129198Scognet 4197129198Scognet 4198129198Scognet 4199129198Scognet/* 4200129198Scognet * this routine returns true if a physical page resides 4201129198Scognet * in the given pmap. 4202129198Scognet */ 4203129198Scognetboolean_t 4204129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4205129198Scognet{ 4206129198Scognet pv_entry_t pv; 4207129198Scognet int loops = 0; 4208129198Scognet int s; 4209129198Scognet 4210129198Scognet if (!pmap_initialized || (m->flags & PG_FICTITIOUS)) 4211129198Scognet return (FALSE); 4212129198Scognet 4213129198Scognet s = splvm(); 4214129198Scognet 4215129198Scognet /* 4216129198Scognet * Not found, check current mappings returning immediately 4217129198Scognet */ 4218129198Scognet for (pv = TAILQ_FIRST(&m->md.pv_list); 4219129198Scognet pv; 4220129198Scognet pv = TAILQ_NEXT(pv, pv_list)) { 4221129198Scognet if (pv->pv_pmap == pmap) { 4222129198Scognet splx(s); 4223129198Scognet return (TRUE); 4224129198Scognet } 4225129198Scognet loops++; 4226129198Scognet if (loops >= 16) 4227129198Scognet break; 4228129198Scognet } 4229129198Scognet splx(s); 4230129198Scognet return (FALSE); 4231129198Scognet} 4232129198Scognet 4233129198Scognet 4234129198Scognet/* 4235129198Scognet * pmap_ts_referenced: 4236129198Scognet * 4237129198Scognet * Return the count of reference bits for a page, clearing all of them. 4238129198Scognet */ 4239129198Scognetint 4240129198Scognetpmap_ts_referenced(vm_page_t m) 4241129198Scognet{ 4242135641Scognet return (pmap_clearbit(m, PVF_REF)); 4243129198Scognet} 4244129198Scognet 4245129198Scognet 4246129198Scognetboolean_t 4247129198Scognetpmap_is_modified(vm_page_t m) 4248129198Scognet{ 4249135641Scognet 4250135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4251135641Scognet return (TRUE); 4252129198Scognet 4253129198Scognet return(FALSE); 4254129198Scognet} 4255129198Scognet 4256129198Scognet 4257129198Scognet/* 4258129198Scognet * Clear the modify bits on the specified physical page. 4259129198Scognet */ 4260129198Scognetvoid 4261129198Scognetpmap_clear_modify(vm_page_t m) 4262129198Scognet{ 4263129198Scognet 4264129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4265129198Scognet pmap_clearbit(m, PVF_MOD); 4266129198Scognet} 4267129198Scognet 4268129198Scognet 4269129198Scognet/* 4270129198Scognet * pmap_clear_reference: 4271129198Scognet * 4272129198Scognet * Clear the reference bit on the specified physical page. 4273129198Scognet */ 4274129198Scognetvoid 4275129198Scognetpmap_clear_reference(vm_page_t m) 4276129198Scognet{ 4277129198Scognet 4278129198Scognet if (m->md.pvh_attrs & PVF_REF) 4279129198Scognet pmap_clearbit(m, PVF_REF); 4280129198Scognet} 4281129198Scognet 4282129198Scognet 4283129198Scognet/* 4284129198Scognet * perform the pmap work for mincore 4285129198Scognet */ 4286129198Scognetint 4287129198Scognetpmap_mincore(pmap_t pmap, vm_offset_t addr) 4288129198Scognet{ 4289129198Scognet printf("pmap_mincore()\n"); 4290129198Scognet 4291129198Scognet return (0); 4292129198Scognet} 4293129198Scognet 4294129198Scognet 4295129198Scognetvm_offset_t 4296129198Scognetpmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 4297129198Scognet{ 4298129198Scognet 4299129198Scognet return(addr); 4300129198Scognet} 4301129198Scognet 4302129198Scognet 4303129198Scognet/* 4304129198Scognet * Map a set of physical memory pages into the kernel virtual 4305129198Scognet * address space. Return a pointer to where it is mapped. This 4306129198Scognet * routine is intended to be used for mapping device memory, 4307129198Scognet * NOT real memory. 4308129198Scognet */ 4309129198Scognetvoid * 4310129198Scognetpmap_mapdev(vm_offset_t pa, vm_size_t size) 4311129198Scognet{ 4312129198Scognet vm_offset_t va, tmpva, offset; 4313129198Scognet 4314129198Scognet offset = pa & PAGE_MASK; 4315135641Scognet size = roundup(size, PAGE_SIZE); 4316129198Scognet 4317129198Scognet GIANT_REQUIRED; 4318129198Scognet 4319132560Salc va = kmem_alloc_nofault(kernel_map, size); 4320129198Scognet if (!va) 4321129198Scognet panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4322129198Scognet for (tmpva = va; size > 0;) { 4323135641Scognet pmap_kenter_internal(tmpva, pa, 0); 4324129198Scognet size -= PAGE_SIZE; 4325129198Scognet tmpva += PAGE_SIZE; 4326129198Scognet pa += PAGE_SIZE; 4327129198Scognet } 4328129198Scognet 4329135641Scognet return ((void *)(va)); 4330129198Scognet} 4331129198Scognet 4332129198Scognet#define BOOTSTRAP_DEBUG 4333129198Scognet 4334129198Scognet/* 4335129198Scognet * pmap_map_section: 4336129198Scognet * 4337129198Scognet * Create a single section mapping. 4338129198Scognet */ 4339129198Scognetvoid 4340129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4341129198Scognet int prot, int cache) 4342129198Scognet{ 4343129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4344129198Scognet pd_entry_t fl; 4345129198Scognet 4346129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4347129198Scognet 4348129198Scognet switch (cache) { 4349129198Scognet case PTE_NOCACHE: 4350129198Scognet default: 4351129198Scognet fl = 0; 4352129198Scognet break; 4353129198Scognet 4354129198Scognet case PTE_CACHE: 4355129198Scognet fl = pte_l1_s_cache_mode; 4356129198Scognet break; 4357129198Scognet 4358129198Scognet case PTE_PAGETABLE: 4359129198Scognet fl = pte_l1_s_cache_mode_pt; 4360129198Scognet break; 4361129198Scognet } 4362129198Scognet 4363129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4364129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4365129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4366129198Scognet 4367129198Scognet} 4368129198Scognet 4369129198Scognet/* 4370129198Scognet * pmap_link_l2pt: 4371129198Scognet * 4372129198Scognet * Link the L2 page table specified by "pa" into the L1 4373129198Scognet * page table at the slot for "va". 4374129198Scognet */ 4375129198Scognetvoid 4376129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4377129198Scognet{ 4378129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4379129198Scognet u_int slot = va >> L1_S_SHIFT; 4380129198Scognet 4381129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 4382129198Scognet KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0, ("blah")); 4383129198Scognet KASSERT((l2pv->pv_pa & PAGE_MASK) == 0, ("ouin")); 4384129198Scognet#endif 4385129198Scognet 4386129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4387129198Scognet 4388129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4389129198Scognet#ifdef ARM32_NEW_VM_LAYOUT 4390129198Scognet PTE_SYNC(&pde[slot]); 4391129198Scognet#else 4392129198Scognet pde[slot + 1] = proto | (l2pv->pv_pa + 0x400); 4393129198Scognet pde[slot + 2] = proto | (l2pv->pv_pa + 0x800); 4394129198Scognet pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00); 4395129198Scognet PTE_SYNC_RANGE(&pde[slot + 0], 4); 4396129198Scognet#endif 4397129198Scognet 4398129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4399129198Scognet 4400129198Scognet 4401129198Scognet} 4402129198Scognet 4403129198Scognet/* 4404129198Scognet * pmap_map_entry 4405129198Scognet * 4406129198Scognet * Create a single page mapping. 4407129198Scognet */ 4408129198Scognetvoid 4409129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4410129198Scognet int cache) 4411129198Scognet{ 4412129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4413129198Scognet pt_entry_t fl; 4414129198Scognet pt_entry_t *pte; 4415129198Scognet 4416129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4417129198Scognet 4418129198Scognet switch (cache) { 4419129198Scognet case PTE_NOCACHE: 4420129198Scognet default: 4421129198Scognet fl = 0; 4422129198Scognet break; 4423129198Scognet 4424129198Scognet case PTE_CACHE: 4425129198Scognet fl = pte_l2_s_cache_mode; 4426129198Scognet break; 4427129198Scognet 4428129198Scognet case PTE_PAGETABLE: 4429129198Scognet fl = pte_l2_s_cache_mode_pt; 4430129198Scognet break; 4431129198Scognet } 4432129198Scognet 4433129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4434129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4435129198Scognet 4436129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 4437129198Scognet pte = (pt_entry_t *) 4438129198Scognet kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4439129198Scognet#else 4440129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4441129198Scognet#endif 4442129198Scognet 4443129198Scognet if (pte == NULL) 4444129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4445129198Scognet 4446129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 4447129198Scognet pte[(va >> PAGE_SHIFT) & 0x3ff] = 4448129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4449129198Scognet PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]); 4450129198Scognet#else 4451129198Scognet pte[l2pte_index(va)] = 4452129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4453129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4454129198Scognet#endif 4455129198Scognet} 4456129198Scognet 4457129198Scognet/* 4458129198Scognet * pmap_map_chunk: 4459129198Scognet * 4460129198Scognet * Map a chunk of memory using the most efficient mappings 4461129198Scognet * possible (section. large page, small page) into the 4462129198Scognet * provided L1 and L2 tables at the specified virtual address. 4463129198Scognet */ 4464129198Scognetvm_size_t 4465129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4466129198Scognet vm_size_t size, int prot, int cache) 4467129198Scognet{ 4468129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4469129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4470129198Scognet vm_size_t resid; 4471129198Scognet int i; 4472129198Scognet 4473129198Scognet resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); 4474129198Scognet 4475129198Scognet if (l1pt == 0) 4476129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4477129198Scognet 4478129198Scognet#ifdef VERBOSE_INIT_ARM 4479129198Scognet printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx " 4480129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4481129198Scognet#endif 4482129198Scognet 4483129198Scognet switch (cache) { 4484129198Scognet case PTE_NOCACHE: 4485129198Scognet default: 4486129198Scognet f1 = 0; 4487129198Scognet f2l = 0; 4488129198Scognet f2s = 0; 4489129198Scognet break; 4490129198Scognet 4491129198Scognet case PTE_CACHE: 4492129198Scognet f1 = pte_l1_s_cache_mode; 4493129198Scognet f2l = pte_l2_l_cache_mode; 4494129198Scognet f2s = pte_l2_s_cache_mode; 4495129198Scognet break; 4496129198Scognet 4497129198Scognet case PTE_PAGETABLE: 4498129198Scognet f1 = pte_l1_s_cache_mode_pt; 4499129198Scognet f2l = pte_l2_l_cache_mode_pt; 4500129198Scognet f2s = pte_l2_s_cache_mode_pt; 4501129198Scognet break; 4502129198Scognet } 4503129198Scognet 4504129198Scognet size = resid; 4505129198Scognet 4506129198Scognet while (resid > 0) { 4507129198Scognet /* See if we can use a section mapping. */ 4508129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4509129198Scognet#ifdef VERBOSE_INIT_ARM 4510129198Scognet printf("S"); 4511129198Scognet#endif 4512129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4513129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4514129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4515129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4516129198Scognet va += L1_S_SIZE; 4517129198Scognet pa += L1_S_SIZE; 4518129198Scognet resid -= L1_S_SIZE; 4519129198Scognet continue; 4520129198Scognet } 4521129198Scognet 4522129198Scognet /* 4523129198Scognet * Ok, we're going to use an L2 table. Make sure 4524129198Scognet * one is actually in the corresponding L1 slot 4525129198Scognet * for the current VA. 4526129198Scognet */ 4527129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4528129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4529129198Scognet 4530129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 4531129198Scognet pte = (pt_entry_t *) 4532129198Scognet kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME); 4533129198Scognet#else 4534129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4535129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4536129198Scognet#endif 4537129198Scognet if (pte == NULL) 4538129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4539129198Scognet "0x%08x", va); 4540129198Scognet /* See if we can use a L2 large page mapping. */ 4541129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4542129198Scognet#ifdef VERBOSE_INIT_ARM 4543129198Scognet printf("L"); 4544129198Scognet#endif 4545129198Scognet for (i = 0; i < 16; i++) { 4546129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 4547129198Scognet pte[((va >> PAGE_SHIFT) & 0x3f0) + i] = 4548129198Scognet L2_L_PROTO | pa | 4549129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4550129198Scognet PTE_SYNC(&pte[((va >> PAGE_SHIFT) & 0x3f0) + i]); 4551129198Scognet#else 4552129198Scognet pte[l2pte_index(va) + i] = 4553129198Scognet L2_L_PROTO | pa | 4554129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4555129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4556129198Scognet#endif 4557129198Scognet } 4558129198Scognet va += L2_L_SIZE; 4559129198Scognet pa += L2_L_SIZE; 4560129198Scognet resid -= L2_L_SIZE; 4561129198Scognet continue; 4562129198Scognet } 4563129198Scognet 4564129198Scognet /* Use a small page mapping. */ 4565129198Scognet#ifdef VERBOSE_INIT_ARM 4566129198Scognet printf("P"); 4567129198Scognet#endif 4568129198Scognet#ifndef ARM32_NEW_VM_LAYOUT 4569129198Scognet pte[(va >> PAGE_SHIFT) & 0x3ff] = 4570129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4571129198Scognet PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]); 4572129198Scognet#else 4573129198Scognet pte[l2pte_index(va)] = 4574129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4575129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4576129198Scognet#endif 4577129198Scognet va += PAGE_SIZE; 4578129198Scognet pa += PAGE_SIZE; 4579129198Scognet resid -= PAGE_SIZE; 4580129198Scognet } 4581129198Scognet#ifdef VERBOSE_INIT_ARM 4582129198Scognet printf("\n"); 4583129198Scognet#endif 4584129198Scognet return (size); 4585129198Scognet 4586129198Scognet} 4587129198Scognet 4588135641Scognet/********************** Static device map routines ***************************/ 4589135641Scognet 4590135641Scognetstatic const struct pmap_devmap *pmap_devmap_table; 4591135641Scognet 4592135641Scognet/* 4593135641Scognet * Register the devmap table. This is provided in case early console 4594135641Scognet * initialization needs to register mappings created by bootstrap code 4595135641Scognet * before pmap_devmap_bootstrap() is called. 4596135641Scognet */ 4597135641Scognetvoid 4598135641Scognetpmap_devmap_register(const struct pmap_devmap *table) 4599135641Scognet{ 4600135641Scognet 4601135641Scognet pmap_devmap_table = table; 4602135641Scognet} 4603135641Scognet 4604135641Scognet/* 4605135641Scognet * Map all of the static regions in the devmap table, and remember 4606135641Scognet * the devmap table so other parts of the kernel can look up entries 4607135641Scognet * later. 4608135641Scognet */ 4609135641Scognetvoid 4610135641Scognetpmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table) 4611135641Scognet{ 4612135641Scognet int i; 4613135641Scognet 4614135641Scognet pmap_devmap_table = table; 4615135641Scognet 4616135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4617135641Scognet#ifdef VERBOSE_INIT_ARM 4618135641Scognet printf("devmap: %08lx -> %08lx @ %08lx\n", 4619135641Scognet pmap_devmap_table[i].pd_pa, 4620135641Scognet pmap_devmap_table[i].pd_pa + 4621135641Scognet pmap_devmap_table[i].pd_size - 1, 4622135641Scognet pmap_devmap_table[i].pd_va); 4623135641Scognet#endif 4624135641Scognet pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va, 4625135641Scognet pmap_devmap_table[i].pd_pa, 4626135641Scognet pmap_devmap_table[i].pd_size, 4627135641Scognet pmap_devmap_table[i].pd_prot, 4628135641Scognet pmap_devmap_table[i].pd_cache); 4629135641Scognet } 4630135641Scognet} 4631135641Scognet 4632135641Scognetconst struct pmap_devmap * 4633135641Scognetpmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size) 4634135641Scognet{ 4635135641Scognet int i; 4636135641Scognet 4637135641Scognet if (pmap_devmap_table == NULL) 4638135641Scognet return (NULL); 4639135641Scognet 4640135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4641135641Scognet if (pa >= pmap_devmap_table[i].pd_pa && 4642135641Scognet pa + size <= pmap_devmap_table[i].pd_pa + 4643135641Scognet pmap_devmap_table[i].pd_size) 4644135641Scognet return (&pmap_devmap_table[i]); 4645135641Scognet } 4646135641Scognet 4647135641Scognet return (NULL); 4648135641Scognet} 4649135641Scognet 4650135641Scognetconst struct pmap_devmap * 4651135641Scognetpmap_devmap_find_va(vm_offset_t va, vm_size_t size) 4652135641Scognet{ 4653135641Scognet int i; 4654135641Scognet 4655135641Scognet if (pmap_devmap_table == NULL) 4656135641Scognet return (NULL); 4657135641Scognet 4658135641Scognet for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) { 4659135641Scognet if (va >= pmap_devmap_table[i].pd_va && 4660135641Scognet va + size <= pmap_devmap_table[i].pd_va + 4661135641Scognet pmap_devmap_table[i].pd_size) 4662135641Scognet return (&pmap_devmap_table[i]); 4663135641Scognet } 4664135641Scognet 4665135641Scognet return (NULL); 4666135641Scognet} 4667135641Scognet 4668