1129198Scognet/* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */ 2139735Simp/*- 3129198Scognet * Copyright 2004 Olivier Houchard. 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37129198Scognet 38139735Simp/*- 39129198Scognet * Copyright (c) 2002-2003 Wasabi Systems, Inc. 40129198Scognet * Copyright (c) 2001 Richard Earnshaw 41129198Scognet * Copyright (c) 2001-2002 Christopher Gilbert 42129198Scognet * All rights reserved. 43129198Scognet * 44129198Scognet * 1. Redistributions of source code must retain the above copyright 45129198Scognet * notice, this list of conditions and the following disclaimer. 46129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 47129198Scognet * notice, this list of conditions and the following disclaimer in the 48129198Scognet * documentation and/or other materials provided with the distribution. 49129198Scognet * 3. The name of the company nor the name of the author may be used to 50129198Scognet * endorse or promote products derived from this software without specific 51129198Scognet * prior written permission. 52129198Scognet * 53129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56129198Scognet * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63129198Scognet * SUCH DAMAGE. 64129198Scognet */ 65129198Scognet/*- 66129198Scognet * Copyright (c) 1999 The NetBSD Foundation, Inc. 67129198Scognet * All rights reserved. 68129198Scognet * 69129198Scognet * This code is derived from software contributed to The NetBSD Foundation 70129198Scognet * by Charles M. Hannum. 71129198Scognet * 72129198Scognet * Redistribution and use in source and binary forms, with or without 73129198Scognet * modification, are permitted provided that the following conditions 74129198Scognet * are met: 75129198Scognet * 1. Redistributions of source code must retain the above copyright 76129198Scognet * notice, this list of conditions and the following disclaimer. 77129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 78129198Scognet * notice, this list of conditions and the following disclaimer in the 79129198Scognet * documentation and/or other materials provided with the distribution. 80129198Scognet * 81129198Scognet * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 82129198Scognet * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 83129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 84129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 85129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 86129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 87129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 88129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 89129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 90129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 91129198Scognet * POSSIBILITY OF SUCH DAMAGE. 92129198Scognet */ 93129198Scognet 94139735Simp/*- 95129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 96129198Scognet * Copyright (c) 1994 Brini. 97129198Scognet * All rights reserved. 98139735Simp * 99129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 100129198Scognet * 101129198Scognet * Redistribution and use in source and binary forms, with or without 102129198Scognet * modification, are permitted provided that the following conditions 103129198Scognet * are met: 104129198Scognet * 1. Redistributions of source code must retain the above copyright 105129198Scognet * notice, this list of conditions and the following disclaimer. 106129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 107129198Scognet * notice, this list of conditions and the following disclaimer in the 108129198Scognet * documentation and/or other materials provided with the distribution. 109129198Scognet * 3. All advertising materials mentioning features or use of this software 110129198Scognet * must display the following acknowledgement: 111129198Scognet * This product includes software developed by Mark Brinicombe. 112129198Scognet * 4. The name of the author may not be used to endorse or promote products 113129198Scognet * derived from this software without specific prior written permission. 114129198Scognet * 115129198Scognet * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 116129198Scognet * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 117129198Scognet * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 118129198Scognet * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 119129198Scognet * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 120129198Scognet * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 121129198Scognet * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 122129198Scognet * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 123129198Scognet * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 124129198Scognet * 125129198Scognet * RiscBSD kernel project 126129198Scognet * 127129198Scognet * pmap.c 128129198Scognet * 129299069Spfg * Machine dependent vm stuff 130129198Scognet * 131129198Scognet * Created : 20/09/94 132129198Scognet */ 133129198Scognet 134129198Scognet/* 135129198Scognet * Special compilation symbols 136129198Scognet * PMAP_DEBUG - Build in pmap_debug_level code 137257648Sian * 138257648Sian * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c 139129198Scognet */ 140129198Scognet/* Include header files */ 141135641Scognet 142137552Scognet#include "opt_vm.h" 143137552Scognet 144129198Scognet#include <sys/cdefs.h> 145129198Scognet__FBSDID("$FreeBSD: stable/11/sys/arm/arm/pmap-v4.c 331520 2018-03-25 01:47:57Z ian $"); 146129198Scognet#include <sys/param.h> 147129198Scognet#include <sys/systm.h> 148129198Scognet#include <sys/kernel.h> 149183838Sraj#include <sys/ktr.h> 150240983Salc#include <sys/lock.h> 151129198Scognet#include <sys/proc.h> 152129198Scognet#include <sys/malloc.h> 153129198Scognet#include <sys/msgbuf.h> 154240983Salc#include <sys/mutex.h> 155129198Scognet#include <sys/vmmeter.h> 156129198Scognet#include <sys/mman.h> 157239934Salc#include <sys/rwlock.h> 158129198Scognet#include <sys/smp.h> 159129198Scognet#include <sys/sched.h> 160129198Scognet 161129198Scognet#include <vm/vm.h> 162239065Skib#include <vm/vm_param.h> 163129198Scognet#include <vm/uma.h> 164129198Scognet#include <vm/pmap.h> 165129198Scognet#include <vm/vm_kern.h> 166129198Scognet#include <vm/vm_object.h> 167129198Scognet#include <vm/vm_map.h> 168129198Scognet#include <vm/vm_page.h> 169129198Scognet#include <vm/vm_pageout.h> 170243132Skib#include <vm/vm_phys.h> 171129198Scognet#include <vm/vm_extern.h> 172240983Salc 173129198Scognet#include <machine/md_var.h> 174129198Scognet#include <machine/cpu.h> 175129198Scognet#include <machine/cpufunc.h> 176129198Scognet#include <machine/pcb.h> 177129198Scognet 178129198Scognet#ifdef PMAP_DEBUG 179129198Scognet#define PDEBUG(_lev_,_stat_) \ 180129198Scognet if (pmap_debug_level >= (_lev_)) \ 181129198Scognet ((_stat_)) 182129198Scognet#define dprintf printf 183129198Scognet 184129198Scognetint pmap_debug_level = 0; 185236991Simp#define PMAP_INLINE 186129198Scognet#else /* PMAP_DEBUG */ 187129198Scognet#define PDEBUG(_lev_,_stat_) /* Nothing */ 188129198Scognet#define dprintf(x, arg...) 189135641Scognet#define PMAP_INLINE __inline 190129198Scognet#endif /* PMAP_DEBUG */ 191129198Scognet 192129198Scognetextern struct pv_addr systempage; 193225988Smarcel 194225988Smarcelextern int last_fault_code; 195225988Smarcel 196129198Scognet/* 197129198Scognet * Internal function prototypes 198129198Scognet */ 199135641Scognetstatic void pmap_free_pv_entry (pv_entry_t); 200129198Scognetstatic pv_entry_t pmap_get_pv_entry(void); 201129198Scognet 202269728Skibstatic int pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t, 203269728Skib vm_prot_t, u_int); 204240983Salcstatic vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va); 205194459Sthompsastatic void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t); 206129198Scognetstatic void pmap_alloc_l1(pmap_t); 207129198Scognetstatic void pmap_free_l1(pmap_t); 208129198Scognet 209135641Scognetstatic int pmap_clearbit(struct vm_page *, u_int); 210129198Scognet 211129198Scognetstatic struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t); 212129198Scognetstatic struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t); 213129198Scognetstatic void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int); 214129198Scognetstatic vm_offset_t kernel_pt_lookup(vm_paddr_t); 215129198Scognet 216129198Scognetstatic MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1"); 217129198Scognet 218129198Scognetvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 219129198Scognetvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 220135641Scognetvm_offset_t pmap_curmaxkvaddr; 221150865Scognetvm_paddr_t kernel_l1pa; 222129198Scognet 223129198Scognetvm_offset_t kernel_vm_end = 0; 224129198Scognet 225246926Salcvm_offset_t vm_max_kernel_address; 226246926Salc 227129198Scognetstruct pmap kernel_pmap_store; 228129198Scognet 229129198Scognetstatic pt_entry_t *csrc_pte, *cdst_pte; 230286296Sjahstatic vm_offset_t csrcp, cdstp, qmap_addr; 231286296Sjahstatic struct mtx cmtx, qmap_mtx; 232159088Scognet 233129198Scognetstatic void pmap_init_l1(struct l1_ttable *, pd_entry_t *); 234129198Scognet/* 235129198Scognet * These routines are called when the CPU type is identified to set up 236129198Scognet * the PTE prototypes, cache modes, etc. 237129198Scognet * 238129198Scognet * The variables are always here, just in case LKMs need to reference 239129198Scognet * them (though, they shouldn't). 240129198Scognet */ 241129198Scognet 242129198Scognetpt_entry_t pte_l1_s_cache_mode; 243129198Scognetpt_entry_t pte_l1_s_cache_mode_pt; 244129198Scognetpt_entry_t pte_l1_s_cache_mask; 245129198Scognet 246129198Scognetpt_entry_t pte_l2_l_cache_mode; 247129198Scognetpt_entry_t pte_l2_l_cache_mode_pt; 248129198Scognetpt_entry_t pte_l2_l_cache_mask; 249129198Scognet 250129198Scognetpt_entry_t pte_l2_s_cache_mode; 251129198Scognetpt_entry_t pte_l2_s_cache_mode_pt; 252129198Scognetpt_entry_t pte_l2_s_cache_mask; 253129198Scognet 254129198Scognetpt_entry_t pte_l2_s_prot_u; 255129198Scognetpt_entry_t pte_l2_s_prot_w; 256129198Scognetpt_entry_t pte_l2_s_prot_mask; 257129198Scognet 258129198Scognetpt_entry_t pte_l1_s_proto; 259129198Scognetpt_entry_t pte_l1_c_proto; 260129198Scognetpt_entry_t pte_l2_s_proto; 261129198Scognet 262129198Scognetvoid (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 263248280Skibvoid (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 264248280Skib vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, 265248280Skib int cnt); 266129198Scognetvoid (*pmap_zero_page_func)(vm_paddr_t, int, int); 267129198Scognet 268298055Spfgstruct msgbuf *msgbufp = NULL; 269129198Scognet 270184728Sraj/* 271184728Sraj * Crashdump maps. 272184728Sraj */ 273184728Srajstatic caddr_t crashdumpmap; 274184728Sraj 275129198Scognetextern void bcopy_page(vm_offset_t, vm_offset_t); 276129198Scognetextern void bzero_page(vm_offset_t); 277137362Scognet 278164079Scognetextern vm_offset_t alloc_firstaddr; 279164079Scognet 280137362Scognetchar *_tmppt; 281137362Scognet 282129198Scognet/* 283129198Scognet * Metadata for L1 translation tables. 284129198Scognet */ 285129198Scognetstruct l1_ttable { 286129198Scognet /* Entry on the L1 Table list */ 287129198Scognet SLIST_ENTRY(l1_ttable) l1_link; 288129198Scognet 289129198Scognet /* Entry on the L1 Least Recently Used list */ 290129198Scognet TAILQ_ENTRY(l1_ttable) l1_lru; 291129198Scognet 292129198Scognet /* Track how many domains are allocated from this L1 */ 293129198Scognet volatile u_int l1_domain_use_count; 294129198Scognet 295129198Scognet /* 296129198Scognet * A free-list of domain numbers for this L1. 297129198Scognet * We avoid using ffs() and a bitmap to track domains since ffs() 298129198Scognet * is slow on ARM. 299129198Scognet */ 300129198Scognet u_int8_t l1_domain_first; 301129198Scognet u_int8_t l1_domain_free[PMAP_DOMAINS]; 302129198Scognet 303129198Scognet /* Physical address of this L1 page table */ 304129198Scognet vm_paddr_t l1_physaddr; 305129198Scognet 306129198Scognet /* KVA of this L1 page table */ 307129198Scognet pd_entry_t *l1_kva; 308129198Scognet}; 309129198Scognet 310129198Scognet/* 311129198Scognet * Convert a virtual address into its L1 table index. That is, the 312129198Scognet * index used to locate the L2 descriptor table pointer in an L1 table. 313129198Scognet * This is basically used to index l1->l1_kva[]. 314129198Scognet * 315129198Scognet * Each L2 descriptor table represents 1MB of VA space. 316129198Scognet */ 317129198Scognet#define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT) 318129198Scognet 319129198Scognet/* 320129198Scognet * L1 Page Tables are tracked using a Least Recently Used list. 321129198Scognet * - New L1s are allocated from the HEAD. 322129198Scognet * - Freed L1s are added to the TAIl. 323129198Scognet * - Recently accessed L1s (where an 'access' is some change to one of 324129198Scognet * the userland pmaps which owns this L1) are moved to the TAIL. 325129198Scognet */ 326129198Scognetstatic TAILQ_HEAD(, l1_ttable) l1_lru_list; 327135641Scognet/* 328135641Scognet * A list of all L1 tables 329135641Scognet */ 330135641Scognetstatic SLIST_HEAD(, l1_ttable) l1_list; 331129198Scognetstatic struct mtx l1_lru_lock; 332129198Scognet 333129198Scognet/* 334129198Scognet * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots. 335129198Scognet * 336129198Scognet * This is normally 16MB worth L2 page descriptors for any given pmap. 337129198Scognet * Reference counts are maintained for L2 descriptors so they can be 338129198Scognet * freed when empty. 339129198Scognet */ 340129198Scognetstruct l2_dtable { 341129198Scognet /* The number of L2 page descriptors allocated to this l2_dtable */ 342129198Scognet u_int l2_occupancy; 343129198Scognet 344129198Scognet /* List of L2 page descriptors */ 345129198Scognet struct l2_bucket { 346129198Scognet pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */ 347129198Scognet vm_paddr_t l2b_phys; /* Physical address of same */ 348129198Scognet u_short l2b_l1idx; /* This L2 table's L1 index */ 349129198Scognet u_short l2b_occupancy; /* How many active descriptors */ 350129198Scognet } l2_bucket[L2_BUCKET_SIZE]; 351129198Scognet}; 352129198Scognet 353135641Scognet/* pmap_kenter_internal flags */ 354135641Scognet#define KENTER_CACHE 0x1 355142570Scognet#define KENTER_USER 0x2 356135641Scognet 357129198Scognet/* 358129198Scognet * Given an L1 table index, calculate the corresponding l2_dtable index 359129198Scognet * and bucket index within the l2_dtable. 360129198Scognet */ 361129198Scognet#define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \ 362129198Scognet (L2_SIZE - 1)) 363129198Scognet#define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1)) 364129198Scognet 365129198Scognet/* 366129198Scognet * Given a virtual address, this macro returns the 367129198Scognet * virtual address required to drop into the next L2 bucket. 368129198Scognet */ 369129198Scognet#define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE) 370129198Scognet 371129198Scognet/* 372129198Scognet * We try to map the page tables write-through, if possible. However, not 373129198Scognet * all CPUs have a write-through cache mode, so on those we have to sync 374129198Scognet * the cache when we frob page tables. 375129198Scognet * 376129198Scognet * We try to evaluate this at compile time, if possible. However, it's 377129198Scognet * not always possible to do that, hence this run-time var. 378129198Scognet */ 379129198Scognetint pmap_needs_pte_sync; 380129198Scognet 381129198Scognet/* 382129198Scognet * Macro to determine if a mapping might be resident in the 383129198Scognet * instruction cache and/or TLB 384129198Scognet */ 385129198Scognet#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC)) 386129198Scognet 387129198Scognet/* 388129198Scognet * Macro to determine if a mapping might be resident in the 389129198Scognet * data cache and/or TLB 390129198Scognet */ 391129198Scognet#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0) 392129198Scognet 393129198Scognet#ifndef PMAP_SHPGPERPROC 394129198Scognet#define PMAP_SHPGPERPROC 200 395129198Scognet#endif 396129198Scognet 397295042Sskra#define pmap_is_current(pm) ((pm) == kernel_pmap || \ 398135641Scognet curproc->p_vmspace->vm_map.pmap == (pm)) 399194459Sthompsastatic uma_zone_t pvzone = NULL; 400147114Scognetuma_zone_t l2zone; 401129198Scognetstatic uma_zone_t l2table_zone; 402135641Scognetstatic vm_offset_t pmap_kernel_l2dtable_kva; 403135641Scognetstatic vm_offset_t pmap_kernel_l2ptp_kva; 404135641Scognetstatic vm_paddr_t pmap_kernel_l2ptp_phys; 405129198Scognetstatic int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; 406239934Salcstatic struct rwlock pvh_global_lock; 407129198Scognet 408248280Skibvoid pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs, 409248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 410248280Skib#if ARM_MMU_XSCALE == 1 411248280Skibvoid pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs, 412248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 413248280Skib#endif 414248280Skib 415129198Scognet/* 416129198Scognet * This list exists for the benefit of pmap_map_chunk(). It keeps track 417129198Scognet * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can 418129198Scognet * find them as necessary. 419129198Scognet * 420129198Scognet * Note that the data on this list MUST remain valid after initarm() returns, 421129198Scognet * as pmap_bootstrap() uses it to contruct L2 table metadata. 422129198Scognet */ 423129198ScognetSLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list); 424129198Scognet 425129198Scognetstatic void 426129198Scognetpmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt) 427129198Scognet{ 428129198Scognet int i; 429129198Scognet 430129198Scognet l1->l1_kva = l1pt; 431129198Scognet l1->l1_domain_use_count = 0; 432174181Scognet l1->l1_domain_first = 0; 433129198Scognet 434129198Scognet for (i = 0; i < PMAP_DOMAINS; i++) 435174181Scognet l1->l1_domain_free[i] = i + 1; 436129198Scognet 437129198Scognet /* 438129198Scognet * Copy the kernel's L1 entries to each new L1. 439129198Scognet */ 440295042Sskra if (l1pt != kernel_pmap->pm_l1->l1_kva) 441295042Sskra memcpy(l1pt, kernel_pmap->pm_l1->l1_kva, L1_TABLE_SIZE); 442129198Scognet 443295042Sskra if ((l1->l1_physaddr = pmap_extract(kernel_pmap, (vm_offset_t)l1pt)) == 0) 444129198Scognet panic("pmap_init_l1: can't get PA of L1 at %p", l1pt); 445135641Scognet SLIST_INSERT_HEAD(&l1_list, l1, l1_link); 446129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 447129198Scognet} 448129198Scognet 449129198Scognetstatic vm_offset_t 450129198Scognetkernel_pt_lookup(vm_paddr_t pa) 451129198Scognet{ 452129198Scognet struct pv_addr *pv; 453129198Scognet 454129198Scognet SLIST_FOREACH(pv, &kernel_pt_list, pv_list) { 455129198Scognet if (pv->pv_pa == pa) 456129198Scognet return (pv->pv_va); 457129198Scognet } 458129198Scognet return (0); 459129198Scognet} 460129198Scognet 461262958Sian#if ARM_MMU_GENERIC != 0 462129198Scognetvoid 463129198Scognetpmap_pte_init_generic(void) 464129198Scognet{ 465129198Scognet 466129198Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C; 467129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic; 468129198Scognet 469129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 470129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic; 471129198Scognet 472129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 473129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic; 474129198Scognet 475129198Scognet /* 476129198Scognet * If we have a write-through cache, set B and C. If 477129198Scognet * we have a write-back cache, then we assume setting 478129198Scognet * only C will make those pages write-through. 479129198Scognet */ 480129198Scognet if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) { 481129198Scognet pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C; 482129198Scognet pte_l2_l_cache_mode_pt = L2_B|L2_C; 483129198Scognet pte_l2_s_cache_mode_pt = L2_B|L2_C; 484129198Scognet } else { 485129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 486129198Scognet pte_l2_l_cache_mode_pt = L2_C; 487129198Scognet pte_l2_s_cache_mode_pt = L2_C; 488129198Scognet } 489129198Scognet 490129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_generic; 491129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_generic; 492129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; 493129198Scognet 494129198Scognet pte_l1_s_proto = L1_S_PROTO_generic; 495129198Scognet pte_l1_c_proto = L1_C_PROTO_generic; 496129198Scognet pte_l2_s_proto = L2_S_PROTO_generic; 497129198Scognet 498129198Scognet pmap_copy_page_func = pmap_copy_page_generic; 499248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_generic; 500129198Scognet pmap_zero_page_func = pmap_zero_page_generic; 501129198Scognet} 502129198Scognet 503262958Sian#endif /* ARM_MMU_GENERIC != 0 */ 504129198Scognet 505129198Scognet#if ARM_MMU_XSCALE == 1 506164778Scognet#if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3) 507129198Scognetstatic u_int xscale_use_minidata; 508129198Scognet#endif 509129198Scognet 510129198Scognetvoid 511129198Scognetpmap_pte_init_xscale(void) 512129198Scognet{ 513129198Scognet uint32_t auxctl; 514129198Scognet int write_through = 0; 515129198Scognet 516135641Scognet pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P; 517129198Scognet pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale; 518129198Scognet 519129198Scognet pte_l2_l_cache_mode = L2_B|L2_C; 520129198Scognet pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale; 521129198Scognet 522129198Scognet pte_l2_s_cache_mode = L2_B|L2_C; 523129198Scognet pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale; 524129198Scognet 525129198Scognet pte_l1_s_cache_mode_pt = L1_S_C; 526129198Scognet pte_l2_l_cache_mode_pt = L2_C; 527129198Scognet pte_l2_s_cache_mode_pt = L2_C; 528129198Scognet#ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE 529129198Scognet /* 530129198Scognet * The XScale core has an enhanced mode where writes that 531129198Scognet * miss the cache cause a cache line to be allocated. This 532129198Scognet * is significantly faster than the traditional, write-through 533129198Scognet * behavior of this case. 534129198Scognet */ 535129198Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X); 536129198Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X); 537129198Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X); 538129198Scognet#endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */ 539129198Scognet#ifdef XSCALE_CACHE_WRITE_THROUGH 540129198Scognet /* 541129198Scognet * Some versions of the XScale core have various bugs in 542129198Scognet * their cache units, the work-around for which is to run 543129198Scognet * the cache in write-through mode. Unfortunately, this 544129198Scognet * has a major (negative) impact on performance. So, we 545129198Scognet * go ahead and run fast-and-loose, in the hopes that we 546129198Scognet * don't line up the planets in a way that will trip the 547129198Scognet * bugs. 548129198Scognet * 549129198Scognet * However, we give you the option to be slow-but-correct. 550129198Scognet */ 551129198Scognet write_through = 1; 552129198Scognet#elif defined(XSCALE_CACHE_WRITE_BACK) 553129198Scognet /* force write back cache mode */ 554129198Scognet write_through = 0; 555129198Scognet#elif defined(CPU_XSCALE_PXA2X0) 556129198Scognet /* 557129198Scognet * Intel PXA2[15]0 processors are known to have a bug in 558129198Scognet * write-back cache on revision 4 and earlier (stepping 559129198Scognet * A[01] and B[012]). Fixed for C0 and later. 560129198Scognet */ 561129198Scognet { 562129198Scognet uint32_t id, type; 563129198Scognet 564295123Smmel id = cpu_ident(); 565129198Scognet type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK); 566129198Scognet 567129198Scognet if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) { 568129198Scognet if ((id & CPU_ID_REVISION_MASK) < 5) { 569129198Scognet /* write through for stepping A0-1 and B0-2 */ 570129198Scognet write_through = 1; 571129198Scognet } 572129198Scognet } 573129198Scognet } 574129198Scognet#endif /* XSCALE_CACHE_WRITE_THROUGH */ 575129198Scognet 576129198Scognet if (write_through) { 577129198Scognet pte_l1_s_cache_mode = L1_S_C; 578129198Scognet pte_l2_l_cache_mode = L2_C; 579129198Scognet pte_l2_s_cache_mode = L2_C; 580129198Scognet } 581129198Scognet 582129198Scognet#if (ARM_NMMUS > 1) 583129198Scognet xscale_use_minidata = 1; 584129198Scognet#endif 585129198Scognet 586129198Scognet pte_l2_s_prot_u = L2_S_PROT_U_xscale; 587129198Scognet pte_l2_s_prot_w = L2_S_PROT_W_xscale; 588129198Scognet pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale; 589129198Scognet 590129198Scognet pte_l1_s_proto = L1_S_PROTO_xscale; 591129198Scognet pte_l1_c_proto = L1_C_PROTO_xscale; 592129198Scognet pte_l2_s_proto = L2_S_PROTO_xscale; 593129198Scognet 594164778Scognet#ifdef CPU_XSCALE_CORE3 595164778Scognet pmap_copy_page_func = pmap_copy_page_generic; 596248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_generic; 597164778Scognet pmap_zero_page_func = pmap_zero_page_generic; 598164778Scognet xscale_use_minidata = 0; 599171620Scognet /* Make sure it is L2-cachable */ 600171620Scognet pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T); 601171620Scognet pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P; 602171620Scognet pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ; 603171620Scognet pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode; 604171620Scognet pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T); 605171620Scognet pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode; 606171620Scognet 607164778Scognet#else 608129198Scognet pmap_copy_page_func = pmap_copy_page_xscale; 609248280Skib pmap_copy_page_offs_func = pmap_copy_page_offs_xscale; 610129198Scognet pmap_zero_page_func = pmap_zero_page_xscale; 611164778Scognet#endif 612129198Scognet 613129198Scognet /* 614129198Scognet * Disable ECC protection of page table access, for now. 615129198Scognet */ 616129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 617129198Scognet auxctl &= ~XSCALE_AUXCTL_P; 618129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 619129198Scognet} 620129198Scognet 621129198Scognet/* 622129198Scognet * xscale_setup_minidata: 623129198Scognet * 624129198Scognet * Set up the mini-data cache clean area. We require the 625129198Scognet * caller to allocate the right amount of physically and 626129198Scognet * virtually contiguous space. 627129198Scognet */ 628129198Scognetextern vm_offset_t xscale_minidata_clean_addr; 629129198Scognetextern vm_size_t xscale_minidata_clean_size; /* already initialized */ 630129198Scognetvoid 631129198Scognetxscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa) 632129198Scognet{ 633129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 634129198Scognet pt_entry_t *pte; 635129198Scognet vm_size_t size; 636129198Scognet uint32_t auxctl; 637129198Scognet 638129198Scognet xscale_minidata_clean_addr = va; 639129198Scognet 640129198Scognet /* Round it to page size. */ 641129198Scognet size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME; 642129198Scognet 643129198Scognet for (; size != 0; 644129198Scognet va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) { 645129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 646129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 647129198Scognet if (pte == NULL) 648129198Scognet panic("xscale_setup_minidata: can't find L2 table for " 649129198Scognet "VA 0x%08x", (u_int32_t) va); 650129198Scognet pte[l2pte_index(va)] = 651129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 652129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 653129198Scognet } 654129198Scognet 655129198Scognet /* 656129198Scognet * Configure the mini-data cache for write-back with 657129198Scognet * read/write-allocate. 658129198Scognet * 659129198Scognet * NOTE: In order to reconfigure the mini-data cache, we must 660129198Scognet * make sure it contains no valid data! In order to do that, 661129198Scognet * we must issue a global data cache invalidate command! 662129198Scognet * 663129198Scognet * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED! 664129198Scognet * THIS IS VERY IMPORTANT! 665129198Scognet */ 666129198Scognet 667129198Scognet /* Invalidate data and mini-data. */ 668129198Scognet __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); 669129198Scognet __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl)); 670129198Scognet auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA; 671129198Scognet __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); 672129198Scognet} 673129198Scognet#endif 674129198Scognet 675129198Scognet/* 676129198Scognet * Allocate an L1 translation table for the specified pmap. 677129198Scognet * This is called at pmap creation time. 678129198Scognet */ 679129198Scognetstatic void 680129198Scognetpmap_alloc_l1(pmap_t pm) 681129198Scognet{ 682129198Scognet struct l1_ttable *l1; 683129198Scognet u_int8_t domain; 684129198Scognet 685129198Scognet /* 686129198Scognet * Remove the L1 at the head of the LRU list 687129198Scognet */ 688129198Scognet mtx_lock(&l1_lru_lock); 689129198Scognet l1 = TAILQ_FIRST(&l1_lru_list); 690129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 691129198Scognet 692129198Scognet /* 693129198Scognet * Pick the first available domain number, and update 694129198Scognet * the link to the next number. 695129198Scognet */ 696129198Scognet domain = l1->l1_domain_first; 697129198Scognet l1->l1_domain_first = l1->l1_domain_free[domain]; 698129198Scognet 699129198Scognet /* 700129198Scognet * If there are still free domain numbers in this L1, 701129198Scognet * put it back on the TAIL of the LRU list. 702129198Scognet */ 703129198Scognet if (++l1->l1_domain_use_count < PMAP_DOMAINS) 704129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 705129198Scognet 706129198Scognet mtx_unlock(&l1_lru_lock); 707129198Scognet 708129198Scognet /* 709129198Scognet * Fix up the relevant bits in the pmap structure 710129198Scognet */ 711129198Scognet pm->pm_l1 = l1; 712174181Scognet pm->pm_domain = domain + 1; 713129198Scognet} 714129198Scognet 715129198Scognet/* 716129198Scognet * Free an L1 translation table. 717129198Scognet * This is called at pmap destruction time. 718129198Scognet */ 719129198Scognetstatic void 720129198Scognetpmap_free_l1(pmap_t pm) 721129198Scognet{ 722129198Scognet struct l1_ttable *l1 = pm->pm_l1; 723129198Scognet 724129198Scognet mtx_lock(&l1_lru_lock); 725129198Scognet 726129198Scognet /* 727129198Scognet * If this L1 is currently on the LRU list, remove it. 728129198Scognet */ 729129198Scognet if (l1->l1_domain_use_count < PMAP_DOMAINS) 730129198Scognet TAILQ_REMOVE(&l1_lru_list, l1, l1_lru); 731129198Scognet 732129198Scognet /* 733129198Scognet * Free up the domain number which was allocated to the pmap 734129198Scognet */ 735174181Scognet l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first; 736174181Scognet l1->l1_domain_first = pm->pm_domain - 1; 737129198Scognet l1->l1_domain_use_count--; 738129198Scognet 739129198Scognet /* 740129198Scognet * The L1 now must have at least 1 free domain, so add 741129198Scognet * it back to the LRU list. If the use count is zero, 742129198Scognet * put it at the head of the list, otherwise it goes 743129198Scognet * to the tail. 744129198Scognet */ 745129198Scognet if (l1->l1_domain_use_count == 0) { 746129198Scognet TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru); 747129198Scognet } else 748129198Scognet TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru); 749129198Scognet 750129198Scognet mtx_unlock(&l1_lru_lock); 751129198Scognet} 752129198Scognet 753129198Scognet/* 754129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 755129198Scognet * and VA, or NULL if no L2 bucket exists for the address. 756129198Scognet */ 757129198Scognetstatic PMAP_INLINE struct l2_bucket * 758129198Scognetpmap_get_l2_bucket(pmap_t pm, vm_offset_t va) 759129198Scognet{ 760129198Scognet struct l2_dtable *l2; 761129198Scognet struct l2_bucket *l2b; 762129198Scognet u_short l1idx; 763129198Scognet 764129198Scognet l1idx = L1_IDX(va); 765129198Scognet 766129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL || 767129198Scognet (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL) 768129198Scognet return (NULL); 769129198Scognet 770129198Scognet return (l2b); 771129198Scognet} 772129198Scognet 773129198Scognet/* 774129198Scognet * Returns a pointer to the L2 bucket associated with the specified pmap 775129198Scognet * and VA. 776129198Scognet * 777129198Scognet * If no L2 bucket exists, perform the necessary allocations to put an L2 778129198Scognet * bucket/page table in place. 779129198Scognet * 780129198Scognet * Note that if a new L2 bucket/page was allocated, the caller *must* 781236991Simp * increment the bucket occupancy counter appropriately *before* 782129198Scognet * releasing the pmap's lock to ensure no other thread or cpu deallocates 783129198Scognet * the bucket/page in the meantime. 784129198Scognet */ 785129198Scognetstatic struct l2_bucket * 786129198Scognetpmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va) 787129198Scognet{ 788129198Scognet struct l2_dtable *l2; 789129198Scognet struct l2_bucket *l2b; 790129198Scognet u_short l1idx; 791129198Scognet 792129198Scognet l1idx = L1_IDX(va); 793129198Scognet 794159352Salc PMAP_ASSERT_LOCKED(pm); 795239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 796129198Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 797129198Scognet /* 798129198Scognet * No mapping at this address, as there is 799129198Scognet * no entry in the L1 table. 800129198Scognet * Need to allocate a new l2_dtable. 801129198Scognet */ 802159352Salc PMAP_UNLOCK(pm); 803239934Salc rw_wunlock(&pvh_global_lock); 804240803Salc if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) { 805239934Salc rw_wlock(&pvh_global_lock); 806159352Salc PMAP_LOCK(pm); 807129198Scognet return (NULL); 808129198Scognet } 809239934Salc rw_wlock(&pvh_global_lock); 810159352Salc PMAP_LOCK(pm); 811159108Scognet if (pm->pm_l2[L2_IDX(l1idx)] != NULL) { 812159108Scognet /* 813159108Scognet * Someone already allocated the l2_dtable while 814159108Scognet * we were doing the same. 815159108Scognet */ 816240803Salc uma_zfree(l2table_zone, l2); 817240803Salc l2 = pm->pm_l2[L2_IDX(l1idx)]; 818159108Scognet } else { 819159108Scognet bzero(l2, sizeof(*l2)); 820159108Scognet /* 821159108Scognet * Link it into the parent pmap 822159108Scognet */ 823159108Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 824159108Scognet } 825236991Simp } 826129198Scognet 827129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 828129198Scognet 829129198Scognet /* 830129198Scognet * Fetch pointer to the L2 page table associated with the address. 831129198Scognet */ 832129198Scognet if (l2b->l2b_kva == NULL) { 833129198Scognet pt_entry_t *ptep; 834129198Scognet 835129198Scognet /* 836129198Scognet * No L2 page table has been allocated. Chances are, this 837129198Scognet * is because we just allocated the l2_dtable, above. 838129198Scognet */ 839280324Scognet l2->l2_occupancy++; 840159352Salc PMAP_UNLOCK(pm); 841239934Salc rw_wunlock(&pvh_global_lock); 842240803Salc ptep = uma_zalloc(l2zone, M_NOWAIT); 843239934Salc rw_wlock(&pvh_global_lock); 844159352Salc PMAP_LOCK(pm); 845298055Spfg if (l2b->l2b_kva != NULL) { 846159108Scognet /* We lost the race. */ 847280324Scognet l2->l2_occupancy--; 848159108Scognet uma_zfree(l2zone, ptep); 849159108Scognet return (l2b); 850159108Scognet } 851129198Scognet l2b->l2b_phys = vtophys(ptep); 852129198Scognet if (ptep == NULL) { 853129198Scognet /* 854129198Scognet * Oops, no more L2 page tables available at this 855129198Scognet * time. We may need to deallocate the l2_dtable 856129198Scognet * if we allocated a new one above. 857129198Scognet */ 858280324Scognet l2->l2_occupancy--; 859129198Scognet if (l2->l2_occupancy == 0) { 860129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 861240803Salc uma_zfree(l2table_zone, l2); 862129198Scognet } 863129198Scognet return (NULL); 864129198Scognet } 865129198Scognet 866129198Scognet l2b->l2b_kva = ptep; 867129198Scognet l2b->l2b_l1idx = l1idx; 868129198Scognet } 869129198Scognet 870129198Scognet return (l2b); 871129198Scognet} 872129198Scognet 873129198Scognetstatic PMAP_INLINE void 874129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 875129198Scognetpmap_free_l2_ptp(pt_entry_t *l2) 876129198Scognet#else 877129198Scognetpmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2) 878129198Scognet#endif 879129198Scognet{ 880129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 881129198Scognet /* 882129198Scognet * Note: With a write-back cache, we may need to sync this 883129198Scognet * L2 table before re-using it. 884129198Scognet * This is because it may have belonged to a non-current 885129198Scognet * pmap, in which case the cache syncs would have been 886129198Scognet * skipped when the pages were being unmapped. If the 887129198Scognet * L2 table were then to be immediately re-allocated to 888129198Scognet * the *current* pmap, it may well contain stale mappings 889129198Scognet * which have not yet been cleared by a cache write-back 890129198Scognet * and so would still be visible to the mmu. 891129198Scognet */ 892129198Scognet if (need_sync) 893129198Scognet PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 894129198Scognet#endif 895129198Scognet uma_zfree(l2zone, l2); 896129198Scognet} 897129198Scognet/* 898129198Scognet * One or more mappings in the specified L2 descriptor table have just been 899129198Scognet * invalidated. 900129198Scognet * 901129198Scognet * Garbage collect the metadata and descriptor table itself if necessary. 902129198Scognet * 903129198Scognet * The pmap lock must be acquired when this is called (not necessary 904129198Scognet * for the kernel pmap). 905129198Scognet */ 906129198Scognetstatic void 907129198Scognetpmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count) 908129198Scognet{ 909129198Scognet struct l2_dtable *l2; 910129198Scognet pd_entry_t *pl1pd, l1pd; 911129198Scognet pt_entry_t *ptep; 912129198Scognet u_short l1idx; 913129198Scognet 914129198Scognet 915129198Scognet /* 916129198Scognet * Update the bucket's reference count according to how many 917129198Scognet * PTEs the caller has just invalidated. 918129198Scognet */ 919129198Scognet l2b->l2b_occupancy -= count; 920129198Scognet 921129198Scognet /* 922129198Scognet * Note: 923129198Scognet * 924129198Scognet * Level 2 page tables allocated to the kernel pmap are never freed 925129198Scognet * as that would require checking all Level 1 page tables and 926129198Scognet * removing any references to the Level 2 page table. See also the 927129198Scognet * comment elsewhere about never freeing bootstrap L2 descriptors. 928129198Scognet * 929129198Scognet * We make do with just invalidating the mapping in the L2 table. 930129198Scognet * 931129198Scognet * This isn't really a big deal in practice and, in fact, leads 932129198Scognet * to a performance win over time as we don't need to continually 933129198Scognet * alloc/free. 934129198Scognet */ 935295042Sskra if (l2b->l2b_occupancy > 0 || pm == kernel_pmap) 936129198Scognet return; 937129198Scognet 938129198Scognet /* 939129198Scognet * There are no more valid mappings in this level 2 page table. 940129198Scognet * Go ahead and NULL-out the pointer in the bucket, then 941129198Scognet * free the page table. 942129198Scognet */ 943129198Scognet l1idx = l2b->l2b_l1idx; 944129198Scognet ptep = l2b->l2b_kva; 945129198Scognet l2b->l2b_kva = NULL; 946129198Scognet 947129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 948129198Scognet 949129198Scognet /* 950129198Scognet * If the L1 slot matches the pmap's domain 951129198Scognet * number, then invalidate it. 952129198Scognet */ 953129198Scognet l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK); 954129198Scognet if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) { 955129198Scognet *pl1pd = 0; 956129198Scognet PTE_SYNC(pl1pd); 957129198Scognet } 958129198Scognet 959129198Scognet /* 960129198Scognet * Release the L2 descriptor table back to the pool cache. 961129198Scognet */ 962129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 963129198Scognet pmap_free_l2_ptp(ptep); 964129198Scognet#else 965135641Scognet pmap_free_l2_ptp(!pmap_is_current(pm), ptep); 966129198Scognet#endif 967129198Scognet 968129198Scognet /* 969129198Scognet * Update the reference count in the associated l2_dtable 970129198Scognet */ 971129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 972129198Scognet if (--l2->l2_occupancy > 0) 973129198Scognet return; 974129198Scognet 975129198Scognet /* 976129198Scognet * There are no more valid mappings in any of the Level 1 977129198Scognet * slots managed by this l2_dtable. Go ahead and NULL-out 978129198Scognet * the pointer in the parent pmap and free the l2_dtable. 979129198Scognet */ 980129198Scognet pm->pm_l2[L2_IDX(l1idx)] = NULL; 981240803Salc uma_zfree(l2table_zone, l2); 982129198Scognet} 983129198Scognet 984129198Scognet/* 985129198Scognet * Pool cache constructors for L2 descriptor tables, metadata and pmap 986129198Scognet * structures. 987129198Scognet */ 988133237Scognetstatic int 989133237Scognetpmap_l2ptp_ctor(void *mem, int size, void *arg, int flags) 990129198Scognet{ 991129198Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 992129198Scognet struct l2_bucket *l2b; 993129198Scognet pt_entry_t *ptep, pte; 994261642Sian 995129198Scognet vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK; 996129198Scognet 997129198Scognet /* 998129198Scognet * The mappings for these page tables were initially made using 999135641Scognet * pmap_kenter() by the pool subsystem. Therefore, the cache- 1000129198Scognet * mode will not be right for page table mappings. To avoid 1001135641Scognet * polluting the pmap_kenter() code with a special case for 1002129198Scognet * page tables, we simply fix up the cache-mode here if it's not 1003129198Scognet * correct. 1004129198Scognet */ 1005295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, va); 1006147114Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1007147114Scognet pte = *ptep; 1008283366Sandrew 1009147114Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 1010147114Scognet /* 1011236991Simp * Page tables must have the cache-mode set to 1012147114Scognet * Write-Thru. 1013147114Scognet */ 1014147114Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1015147114Scognet PTE_SYNC(ptep); 1016147114Scognet cpu_tlb_flushD_SE(va); 1017147114Scognet cpu_cpwait(); 1018147114Scognet } 1019129198Scognet#endif 1020129198Scognet memset(mem, 0, L2_TABLE_SIZE_REAL); 1021129198Scognet PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 1022133237Scognet return (0); 1023129198Scognet} 1024129198Scognet 1025129198Scognet/* 1026129198Scognet * A bunch of routines to conditionally flush the caches/TLB depending 1027129198Scognet * on whether the specified pmap actually needs to be flushed at any 1028129198Scognet * given time. 1029129198Scognet */ 1030129198Scognetstatic PMAP_INLINE void 1031129198Scognetpmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va) 1032129198Scognet{ 1033129198Scognet 1034135641Scognet if (pmap_is_current(pm)) 1035129198Scognet cpu_tlb_flushID_SE(va); 1036129198Scognet} 1037129198Scognet 1038129198Scognetstatic PMAP_INLINE void 1039129198Scognetpmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va) 1040129198Scognet{ 1041129198Scognet 1042135641Scognet if (pmap_is_current(pm)) 1043129198Scognet cpu_tlb_flushD_SE(va); 1044129198Scognet} 1045129198Scognet 1046129198Scognetstatic PMAP_INLINE void 1047129198Scognetpmap_tlb_flushID(pmap_t pm) 1048129198Scognet{ 1049129198Scognet 1050135641Scognet if (pmap_is_current(pm)) 1051129198Scognet cpu_tlb_flushID(); 1052129198Scognet} 1053129198Scognetstatic PMAP_INLINE void 1054129198Scognetpmap_tlb_flushD(pmap_t pm) 1055129198Scognet{ 1056129198Scognet 1057135641Scognet if (pmap_is_current(pm)) 1058129198Scognet cpu_tlb_flushD(); 1059129198Scognet} 1060129198Scognet 1061203637Srajstatic int 1062203637Srajpmap_has_valid_mapping(pmap_t pm, vm_offset_t va) 1063183838Sraj{ 1064183838Sraj pd_entry_t *pde; 1065183838Sraj pt_entry_t *ptep; 1066183838Sraj 1067203637Sraj if (pmap_get_pde_pte(pm, va, &pde, &ptep) && 1068203637Sraj ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV)) 1069203637Sraj return (1); 1070183838Sraj 1071203637Sraj return (0); 1072183838Sraj} 1073183838Sraj 1074183838Srajstatic PMAP_INLINE void 1075129198Scognetpmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) 1076129198Scognet{ 1077183838Sraj vm_size_t rest; 1078129198Scognet 1079203637Sraj CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x" 1080295042Sskra " len 0x%x ", pm, pm == kernel_pmap, va, len); 1081183838Sraj 1082295042Sskra if (pmap_is_current(pm) || pm == kernel_pmap) { 1083203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1084203637Sraj while (len > 0) { 1085203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1086203637Sraj cpu_idcache_wbinv_range(va, rest); 1087203637Sraj cpu_l2cache_wbinv_range(va, rest); 1088203637Sraj } 1089203637Sraj len -= rest; 1090203637Sraj va += rest; 1091203637Sraj rest = MIN(PAGE_SIZE, len); 1092203637Sraj } 1093183838Sraj } 1094183838Sraj} 1095183838Sraj 1096183838Srajstatic PMAP_INLINE void 1097183838Srajpmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv, 1098183838Sraj boolean_t rd_only) 1099183838Sraj{ 1100203637Sraj vm_size_t rest; 1101184730Sraj 1102183838Sraj CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x " 1103295042Sskra "len 0x%x ", pm, pm == kernel_pmap, va, len); 1104183838Sraj CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only); 1105183838Sraj 1106135641Scognet if (pmap_is_current(pm)) { 1107203637Sraj rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); 1108203637Sraj while (len > 0) { 1109203637Sraj if (pmap_has_valid_mapping(pm, va)) { 1110203637Sraj if (do_inv && rd_only) { 1111203637Sraj cpu_dcache_inv_range(va, rest); 1112203637Sraj cpu_l2cache_inv_range(va, rest); 1113203637Sraj } else if (do_inv) { 1114203637Sraj cpu_dcache_wbinv_range(va, rest); 1115203637Sraj cpu_l2cache_wbinv_range(va, rest); 1116203637Sraj } else if (!rd_only) { 1117203637Sraj cpu_dcache_wb_range(va, rest); 1118203637Sraj cpu_l2cache_wb_range(va, rest); 1119203637Sraj } 1120183838Sraj } 1121203637Sraj len -= rest; 1122203637Sraj va += rest; 1123203637Sraj 1124203637Sraj rest = MIN(PAGE_SIZE, len); 1125183838Sraj } 1126129198Scognet } 1127129198Scognet} 1128129198Scognet 1129129198Scognetstatic PMAP_INLINE void 1130129198Scognetpmap_idcache_wbinv_all(pmap_t pm) 1131129198Scognet{ 1132129198Scognet 1133183838Sraj if (pmap_is_current(pm)) { 1134129198Scognet cpu_idcache_wbinv_all(); 1135183838Sraj cpu_l2cache_wbinv_all(); 1136183838Sraj } 1137129198Scognet} 1138129198Scognet 1139197770Sstas#ifdef notyet 1140129198Scognetstatic PMAP_INLINE void 1141129198Scognetpmap_dcache_wbinv_all(pmap_t pm) 1142129198Scognet{ 1143129198Scognet 1144183838Sraj if (pmap_is_current(pm)) { 1145129198Scognet cpu_dcache_wbinv_all(); 1146183838Sraj cpu_l2cache_wbinv_all(); 1147183838Sraj } 1148129198Scognet} 1149197770Sstas#endif 1150129198Scognet 1151129198Scognet/* 1152129198Scognet * PTE_SYNC_CURRENT: 1153129198Scognet * 1154129198Scognet * Make sure the pte is written out to RAM. 1155129198Scognet * We need to do this for one of two cases: 1156129198Scognet * - We're dealing with the kernel pmap 1157129198Scognet * - There is no pmap active in the cache/tlb. 1158129198Scognet * - The specified pmap is 'active' in the cache/tlb. 1159129198Scognet */ 1160129198Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 1161129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) \ 1162129198Scognetdo { \ 1163129198Scognet if (PMAP_NEEDS_PTE_SYNC && \ 1164135641Scognet pmap_is_current(pm)) \ 1165129198Scognet PTE_SYNC(ptep); \ 1166129198Scognet} while (/*CONSTCOND*/0) 1167129198Scognet#else 1168129198Scognet#define PTE_SYNC_CURRENT(pm, ptep) /* nothing */ 1169129198Scognet#endif 1170129198Scognet 1171129198Scognet/* 1172175840Scognet * cacheable == -1 means we must make the entry uncacheable, 1 means 1173175840Scognet * cacheable; 1174129198Scognet */ 1175129198Scognetstatic __inline void 1176175840Scognetpmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable) 1177129198Scognet{ 1178175840Scognet struct l2_bucket *l2b; 1179175840Scognet pt_entry_t *ptep, pte; 1180129198Scognet 1181175840Scognet l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 1182175840Scognet ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 1183129198Scognet 1184175840Scognet if (cacheable == 1) { 1185175840Scognet pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode; 1186175840Scognet if (l2pte_valid(pte)) { 1187175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1188175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1189175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1190175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va); 1191175840Scognet } 1192175840Scognet } 1193175840Scognet } else { 1194175840Scognet pte = *ptep &~ L2_S_CACHE_MASK; 1195175840Scognet if ((va != pv->pv_va || pm != pv->pv_pmap) && 1196175840Scognet l2pte_valid(pte)) { 1197175840Scognet if (PV_BEEN_EXECD(pv->pv_flags)) { 1198175840Scognet pmap_idcache_wbinv_range(pv->pv_pmap, 1199175840Scognet pv->pv_va, PAGE_SIZE); 1200175840Scognet pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va); 1201175840Scognet } else if (PV_BEEN_REFD(pv->pv_flags)) { 1202175840Scognet pmap_dcache_wb_range(pv->pv_pmap, 1203175840Scognet pv->pv_va, PAGE_SIZE, TRUE, 1204175840Scognet (pv->pv_flags & PVF_WRITE) == 0); 1205175840Scognet pmap_tlb_flushD_SE(pv->pv_pmap, 1206175840Scognet pv->pv_va); 1207175840Scognet } 1208175840Scognet } 1209129198Scognet } 1210175840Scognet *ptep = pte; 1211175840Scognet PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 1212129198Scognet} 1213129198Scognet 1214129198Scognetstatic void 1215175840Scognetpmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1216129198Scognet{ 1217175840Scognet int pmwc = 0; 1218175840Scognet int writable = 0, kwritable = 0, uwritable = 0; 1219175840Scognet int entries = 0, kentries = 0, uentries = 0; 1220129198Scognet struct pv_entry *pv; 1221129198Scognet 1222239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1223129198Scognet 1224175840Scognet /* the cache gets written back/invalidated on context switch. 1225175840Scognet * therefore, if a user page shares an entry in the same page or 1226175840Scognet * with the kernel map and at least one is writable, then the 1227175840Scognet * cache entry must be set write-through. 1228129198Scognet */ 1229129198Scognet 1230175840Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1231175840Scognet /* generate a count of the pv_entry uses */ 1232175840Scognet if (pv->pv_flags & PVF_WRITE) { 1233295042Sskra if (pv->pv_pmap == kernel_pmap) 1234175840Scognet kwritable++; 1235175840Scognet else if (pv->pv_pmap == pm) 1236175840Scognet uwritable++; 1237175840Scognet writable++; 1238129198Scognet } 1239295042Sskra if (pv->pv_pmap == kernel_pmap) 1240175840Scognet kentries++; 1241175840Scognet else { 1242175840Scognet if (pv->pv_pmap == pm) 1243175840Scognet uentries++; 1244175840Scognet entries++; 1245175840Scognet } 1246129198Scognet } 1247175840Scognet /* 1248175840Scognet * check if the user duplicate mapping has 1249175840Scognet * been removed. 1250175840Scognet */ 1251295042Sskra if ((pm != kernel_pmap) && (((uentries > 1) && uwritable) || 1252175840Scognet (uwritable > 1))) 1253175840Scognet pmwc = 1; 1254129198Scognet 1255129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1256175840Scognet /* check for user uncachable conditions - order is important */ 1257295042Sskra if (pm != kernel_pmap && 1258295042Sskra (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap)) { 1259129198Scognet 1260175840Scognet if ((uentries > 1 && uwritable) || uwritable > 1) { 1261129198Scognet 1262175840Scognet /* user duplicate mapping */ 1263295042Sskra if (pv->pv_pmap != kernel_pmap) 1264175840Scognet pv->pv_flags |= PVF_MWC; 1265129198Scognet 1266175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1267175840Scognet pv->pv_flags |= PVF_NC; 1268175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1269175840Scognet } 1270129198Scognet continue; 1271175840Scognet } else /* no longer a duplicate user */ 1272175840Scognet pv->pv_flags &= ~PVF_MWC; 1273175840Scognet } 1274129198Scognet 1275175840Scognet /* 1276175840Scognet * check for kernel uncachable conditions 1277175840Scognet * kernel writable or kernel readable with writable user entry 1278175840Scognet */ 1279209223Scognet if ((kwritable && (entries || kentries > 1)) || 1280194459Sthompsa (kwritable > 1) || 1281175840Scognet ((kwritable != writable) && kentries && 1282295042Sskra (pv->pv_pmap == kernel_pmap || 1283175840Scognet (pv->pv_flags & PVF_WRITE) || 1284175840Scognet (pv->pv_flags & PVF_MWC)))) { 1285129198Scognet 1286175840Scognet if (!(pv->pv_flags & PVF_NC)) { 1287175840Scognet pv->pv_flags |= PVF_NC; 1288175840Scognet pmap_set_cache_entry(pv, pm, va, -1); 1289129198Scognet } 1290175840Scognet continue; 1291129198Scognet } 1292129198Scognet 1293175840Scognet /* kernel and user are cachable */ 1294295042Sskra if ((pm == kernel_pmap) && !(pv->pv_flags & PVF_MWC) && 1295175840Scognet (pv->pv_flags & PVF_NC)) { 1296175840Scognet 1297129198Scognet pv->pv_flags &= ~PVF_NC; 1298244574Scognet if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 1299244414Scognet pmap_set_cache_entry(pv, pm, va, 1); 1300175840Scognet continue; 1301175840Scognet } 1302175840Scognet /* user is no longer sharable and writable */ 1303295042Sskra if (pm != kernel_pmap && 1304295042Sskra (pv->pv_pmap == pm || pv->pv_pmap == kernel_pmap) && 1305175840Scognet !pmwc && (pv->pv_flags & PVF_NC)) { 1306129198Scognet 1307175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1308244574Scognet if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 1309244414Scognet pmap_set_cache_entry(pv, pm, va, 1); 1310129198Scognet } 1311129198Scognet } 1312175840Scognet 1313175840Scognet if ((kwritable == 0) && (writable == 0)) { 1314175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1315225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1316175840Scognet return; 1317175840Scognet } 1318129198Scognet} 1319129198Scognet 1320129198Scognet/* 1321129198Scognet * Modify pte bits for all ptes corresponding to the given physical address. 1322129198Scognet * We use `maskbits' rather than `clearbits' because we're always passing 1323129198Scognet * constants and the latter would require an extra inversion at run-time. 1324129198Scognet */ 1325236991Simpstatic int 1326129198Scognetpmap_clearbit(struct vm_page *pg, u_int maskbits) 1327129198Scognet{ 1328129198Scognet struct l2_bucket *l2b; 1329129198Scognet struct pv_entry *pv; 1330129198Scognet pt_entry_t *ptep, npte, opte; 1331129198Scognet pmap_t pm; 1332129198Scognet vm_offset_t va; 1333129198Scognet u_int oflags; 1334135641Scognet int count = 0; 1335129198Scognet 1336239934Salc rw_wlock(&pvh_global_lock); 1337159352Salc 1338175840Scognet if (maskbits & PVF_WRITE) 1339175840Scognet maskbits |= PVF_MOD; 1340129198Scognet /* 1341129198Scognet * Clear saved attributes (modify, reference) 1342129198Scognet */ 1343129198Scognet pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF)); 1344129198Scognet 1345129198Scognet if (TAILQ_EMPTY(&pg->md.pv_list)) { 1346239934Salc rw_wunlock(&pvh_global_lock); 1347135641Scognet return (0); 1348129198Scognet } 1349129198Scognet 1350129198Scognet /* 1351129198Scognet * Loop over all current mappings setting/clearing as appropos 1352129198Scognet */ 1353129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) { 1354129198Scognet va = pv->pv_va; 1355129198Scognet pm = pv->pv_pmap; 1356129198Scognet oflags = pv->pv_flags; 1357175840Scognet 1358175840Scognet if (!(oflags & maskbits)) { 1359175840Scognet if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) { 1360283366Sandrew if (pg->md.pv_memattr != 1361244574Scognet VM_MEMATTR_UNCACHEABLE) { 1362244414Scognet PMAP_LOCK(pm); 1363244414Scognet l2b = pmap_get_l2_bucket(pm, va); 1364244414Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1365244414Scognet *ptep |= pte_l2_s_cache_mode; 1366244414Scognet PTE_SYNC(ptep); 1367244414Scognet PMAP_UNLOCK(pm); 1368244414Scognet } 1369175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1370175840Scognet } 1371175840Scognet continue; 1372175840Scognet } 1373129198Scognet pv->pv_flags &= ~maskbits; 1374129198Scognet 1375159352Salc PMAP_LOCK(pm); 1376129198Scognet 1377129198Scognet l2b = pmap_get_l2_bucket(pm, va); 1378129198Scognet 1379129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1380129198Scognet npte = opte = *ptep; 1381129198Scognet 1382157970Scognet if (maskbits & (PVF_WRITE|PVF_MOD)) { 1383129198Scognet if ((pv->pv_flags & PVF_NC)) { 1384236991Simp /* 1385129198Scognet * Entry is not cacheable: 1386129198Scognet * 1387236991Simp * Don't turn caching on again if this is a 1388129198Scognet * modified emulation. This would be 1389299069Spfg * inconsistent with the settings created by 1390175840Scognet * pmap_fix_cache(). Otherwise, it's safe 1391299069Spfg * to re-enable caching. 1392129198Scognet * 1393175840Scognet * There's no need to call pmap_fix_cache() 1394129198Scognet * here: all pages are losing their write 1395129198Scognet * permission. 1396129198Scognet */ 1397129198Scognet if (maskbits & PVF_WRITE) { 1398244574Scognet if (pg->md.pv_memattr != 1399244574Scognet VM_MEMATTR_UNCACHEABLE) 1400244414Scognet npte |= pte_l2_s_cache_mode; 1401175840Scognet pv->pv_flags &= ~(PVF_NC | PVF_MWC); 1402129198Scognet } 1403129198Scognet } else 1404129198Scognet if (opte & L2_S_PROT_W) { 1405144760Scognet vm_page_dirty(pg); 1406236991Simp /* 1407129198Scognet * Entry is writable/cacheable: check if pmap 1408129198Scognet * is current if it is flush it, otherwise it 1409129198Scognet * won't be in the cache 1410129198Scognet */ 1411129198Scognet if (PV_BEEN_EXECD(oflags)) 1412129198Scognet pmap_idcache_wbinv_range(pm, pv->pv_va, 1413129198Scognet PAGE_SIZE); 1414129198Scognet else 1415129198Scognet if (PV_BEEN_REFD(oflags)) 1416129198Scognet pmap_dcache_wb_range(pm, pv->pv_va, 1417129198Scognet PAGE_SIZE, 1418129198Scognet (maskbits & PVF_REF) ? TRUE : FALSE, 1419129198Scognet FALSE); 1420129198Scognet } 1421129198Scognet 1422129198Scognet /* make the pte read only */ 1423129198Scognet npte &= ~L2_S_PROT_W; 1424129198Scognet } 1425129198Scognet 1426157970Scognet if (maskbits & PVF_REF) { 1427129198Scognet if ((pv->pv_flags & PVF_NC) == 0 && 1428129198Scognet (maskbits & (PVF_WRITE|PVF_MOD)) == 0) { 1429129198Scognet /* 1430129198Scognet * Check npte here; we may have already 1431129198Scognet * done the wbinv above, and the validity 1432129198Scognet * of the PTE is the same for opte and 1433129198Scognet * npte. 1434129198Scognet */ 1435129198Scognet if (npte & L2_S_PROT_W) { 1436129198Scognet if (PV_BEEN_EXECD(oflags)) 1437129198Scognet pmap_idcache_wbinv_range(pm, 1438129198Scognet pv->pv_va, PAGE_SIZE); 1439129198Scognet else 1440129198Scognet if (PV_BEEN_REFD(oflags)) 1441129198Scognet pmap_dcache_wb_range(pm, 1442129198Scognet pv->pv_va, PAGE_SIZE, 1443129198Scognet TRUE, FALSE); 1444129198Scognet } else 1445129198Scognet if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) { 1446129198Scognet /* XXXJRT need idcache_inv_range */ 1447129198Scognet if (PV_BEEN_EXECD(oflags)) 1448129198Scognet pmap_idcache_wbinv_range(pm, 1449129198Scognet pv->pv_va, PAGE_SIZE); 1450129198Scognet else 1451129198Scognet if (PV_BEEN_REFD(oflags)) 1452129198Scognet pmap_dcache_wb_range(pm, 1453129198Scognet pv->pv_va, PAGE_SIZE, 1454129198Scognet TRUE, TRUE); 1455129198Scognet } 1456129198Scognet } 1457129198Scognet 1458129198Scognet /* 1459129198Scognet * Make the PTE invalid so that we will take a 1460129198Scognet * page fault the next time the mapping is 1461129198Scognet * referenced. 1462129198Scognet */ 1463129198Scognet npte &= ~L2_TYPE_MASK; 1464129198Scognet npte |= L2_TYPE_INV; 1465129198Scognet } 1466129198Scognet 1467129198Scognet if (npte != opte) { 1468135641Scognet count++; 1469129198Scognet *ptep = npte; 1470129198Scognet PTE_SYNC(ptep); 1471129198Scognet /* Flush the TLB entry if a current pmap. */ 1472129198Scognet if (PV_BEEN_EXECD(oflags)) 1473129198Scognet pmap_tlb_flushID_SE(pm, pv->pv_va); 1474129198Scognet else 1475129198Scognet if (PV_BEEN_REFD(oflags)) 1476129198Scognet pmap_tlb_flushD_SE(pm, pv->pv_va); 1477129198Scognet } 1478129198Scognet 1479159352Salc PMAP_UNLOCK(pm); 1480129198Scognet 1481129198Scognet } 1482129198Scognet 1483137664Scognet if (maskbits & PVF_WRITE) 1484225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1485239934Salc rw_wunlock(&pvh_global_lock); 1486135641Scognet return (count); 1487129198Scognet} 1488129198Scognet 1489129198Scognet/* 1490129198Scognet * main pv_entry manipulation functions: 1491129198Scognet * pmap_enter_pv: enter a mapping onto a vm_page list 1492129198Scognet * pmap_remove_pv: remove a mappiing from a vm_page list 1493129198Scognet * 1494129198Scognet * NOTE: pmap_enter_pv expects to lock the pvh itself 1495240166Salc * pmap_remove_pv expects the caller to lock the pvh before calling 1496129198Scognet */ 1497129198Scognet 1498129198Scognet/* 1499240442Salc * pmap_enter_pv: enter a mapping onto a vm_page's PV list 1500129198Scognet * 1501240166Salc * => caller should hold the proper lock on pvh_global_lock 1502129198Scognet * => caller should have pmap locked 1503240442Salc * => we will (someday) gain the lock on the vm_page's PV list 1504129198Scognet * => caller should adjust ptp's wire_count before calling 1505129198Scognet * => caller should not adjust pmap's wire_count 1506129198Scognet */ 1507129198Scognetstatic void 1508129198Scognetpmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm, 1509129198Scognet vm_offset_t va, u_int flags) 1510129198Scognet{ 1511194459Sthompsa 1512239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1513240442Salc PMAP_ASSERT_LOCKED(pm); 1514240166Salc if (pg->md.pv_kva != 0) { 1515240442Salc pve->pv_pmap = kernel_pmap; 1516194459Sthompsa pve->pv_va = pg->md.pv_kva; 1517194459Sthompsa pve->pv_flags = PVF_WRITE | PVF_UNMAN; 1518240442Salc if (pm != kernel_pmap) 1519240442Salc PMAP_LOCK(kernel_pmap); 1520240442Salc TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1521240442Salc TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist); 1522240442Salc if (pm != kernel_pmap) 1523240442Salc PMAP_UNLOCK(kernel_pmap); 1524194459Sthompsa pg->md.pv_kva = 0; 1525194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 1526240166Salc panic("pmap_kenter_pv: no pv entries"); 1527194459Sthompsa } 1528129198Scognet pve->pv_pmap = pm; 1529129198Scognet pve->pv_va = va; 1530129198Scognet pve->pv_flags = flags; 1531129198Scognet TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list); 1532144760Scognet TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist); 1533129198Scognet pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD); 1534129198Scognet if (pve->pv_flags & PVF_WIRED) 1535129198Scognet ++pm->pm_stats.wired_count; 1536225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1537129198Scognet} 1538129198Scognet 1539129198Scognet/* 1540129198Scognet * 1541129198Scognet * pmap_find_pv: Find a pv entry 1542129198Scognet * 1543129198Scognet * => caller should hold lock on vm_page 1544129198Scognet */ 1545129198Scognetstatic PMAP_INLINE struct pv_entry * 1546129198Scognetpmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1547129198Scognet{ 1548129198Scognet struct pv_entry *pv; 1549129198Scognet 1550239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1551129198Scognet TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) 1552129198Scognet if (pm == pv->pv_pmap && va == pv->pv_va) 1553129198Scognet break; 1554129198Scognet return (pv); 1555129198Scognet} 1556129198Scognet 1557129198Scognet/* 1558129198Scognet * vector_page_setprot: 1559129198Scognet * 1560129198Scognet * Manipulate the protection of the vector page. 1561129198Scognet */ 1562129198Scognetvoid 1563129198Scognetvector_page_setprot(int prot) 1564129198Scognet{ 1565129198Scognet struct l2_bucket *l2b; 1566129198Scognet pt_entry_t *ptep; 1567129198Scognet 1568295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, vector_page); 1569129198Scognet 1570129198Scognet ptep = &l2b->l2b_kva[l2pte_index(vector_page)]; 1571129198Scognet 1572129198Scognet *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot); 1573129198Scognet PTE_SYNC(ptep); 1574129198Scognet cpu_tlb_flushD_SE(vector_page); 1575129198Scognet cpu_cpwait(); 1576129198Scognet} 1577129198Scognet 1578129198Scognet/* 1579129198Scognet * pmap_remove_pv: try to remove a mapping from a pv_list 1580129198Scognet * 1581129198Scognet * => caller should hold proper lock on pmap_main_lock 1582129198Scognet * => pmap should be locked 1583129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1584129198Scognet * => caller should adjust ptp's wire_count and free PTP if needed 1585129198Scognet * => caller should NOT adjust pmap's wire_count 1586129198Scognet * => we return the removed pve 1587129198Scognet */ 1588135641Scognet 1589135641Scognetstatic void 1590135641Scognetpmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve) 1591135641Scognet{ 1592135641Scognet 1593194459Sthompsa struct pv_entry *pv; 1594239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1595159352Salc PMAP_ASSERT_LOCKED(pm); 1596135641Scognet TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list); 1597144760Scognet TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist); 1598135641Scognet if (pve->pv_flags & PVF_WIRED) 1599135641Scognet --pm->pm_stats.wired_count; 1600144760Scognet if (pg->md.pvh_attrs & PVF_MOD) 1601144760Scognet vm_page_dirty(pg); 1602175840Scognet if (TAILQ_FIRST(&pg->md.pv_list) == NULL) 1603175840Scognet pg->md.pvh_attrs &= ~PVF_REF; 1604175840Scognet else 1605225418Skib vm_page_aflag_set(pg, PGA_REFERENCED); 1606295042Sskra if ((pve->pv_flags & PVF_NC) && ((pm == kernel_pmap) || 1607175840Scognet (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC))) 1608175840Scognet pmap_fix_cache(pg, pm, 0); 1609175840Scognet else if (pve->pv_flags & PVF_WRITE) { 1610175840Scognet TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list) 1611175840Scognet if (pve->pv_flags & PVF_WRITE) 1612175840Scognet break; 1613175840Scognet if (!pve) { 1614175840Scognet pg->md.pvh_attrs &= ~PVF_MOD; 1615225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1616175840Scognet } 1617146647Scognet } 1618194459Sthompsa pv = TAILQ_FIRST(&pg->md.pv_list); 1619194459Sthompsa if (pv != NULL && (pv->pv_flags & PVF_UNMAN) && 1620194459Sthompsa TAILQ_NEXT(pv, pv_list) == NULL) { 1621205425Scognet pm = kernel_pmap; 1622194459Sthompsa pg->md.pv_kva = pv->pv_va; 1623194459Sthompsa /* a recursive pmap_nuke_pv */ 1624194459Sthompsa TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list); 1625194459Sthompsa TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist); 1626194459Sthompsa if (pv->pv_flags & PVF_WIRED) 1627194459Sthompsa --pm->pm_stats.wired_count; 1628194459Sthompsa pg->md.pvh_attrs &= ~PVF_REF; 1629194459Sthompsa pg->md.pvh_attrs &= ~PVF_MOD; 1630225418Skib vm_page_aflag_clear(pg, PGA_WRITEABLE); 1631194459Sthompsa pmap_free_pv_entry(pv); 1632194459Sthompsa } 1633135641Scognet} 1634135641Scognet 1635129198Scognetstatic struct pv_entry * 1636129198Scognetpmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va) 1637129198Scognet{ 1638135641Scognet struct pv_entry *pve; 1639129198Scognet 1640239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1641135641Scognet pve = TAILQ_FIRST(&pg->md.pv_list); 1642129198Scognet 1643129198Scognet while (pve) { 1644129198Scognet if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */ 1645135641Scognet pmap_nuke_pv(pg, pm, pve); 1646129198Scognet break; 1647129198Scognet } 1648129198Scognet pve = TAILQ_NEXT(pve, pv_list); 1649129198Scognet } 1650129198Scognet 1651194459Sthompsa if (pve == NULL && pg->md.pv_kva == va) 1652194459Sthompsa pg->md.pv_kva = 0; 1653194459Sthompsa 1654129198Scognet return(pve); /* return removed pve */ 1655129198Scognet} 1656129198Scognet/* 1657129198Scognet * 1658129198Scognet * pmap_modify_pv: Update pv flags 1659129198Scognet * 1660129198Scognet * => caller should hold lock on vm_page [so that attrs can be adjusted] 1661129198Scognet * => caller should NOT adjust pmap's wire_count 1662129198Scognet * => we return the old flags 1663236991Simp * 1664129198Scognet * Modify a physical-virtual mapping in the pv table 1665129198Scognet */ 1666129198Scognetstatic u_int 1667129198Scognetpmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va, 1668129198Scognet u_int clr_mask, u_int set_mask) 1669129198Scognet{ 1670129198Scognet struct pv_entry *npv; 1671129198Scognet u_int flags, oflags; 1672129198Scognet 1673159352Salc PMAP_ASSERT_LOCKED(pm); 1674239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 1675129198Scognet if ((npv = pmap_find_pv(pg, pm, va)) == NULL) 1676129198Scognet return (0); 1677129198Scognet 1678129198Scognet /* 1679129198Scognet * There is at least one VA mapping this page. 1680129198Scognet */ 1681129198Scognet 1682129198Scognet if (clr_mask & (PVF_REF | PVF_MOD)) 1683129198Scognet pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD); 1684129198Scognet 1685129198Scognet oflags = npv->pv_flags; 1686129198Scognet npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask; 1687129198Scognet 1688129198Scognet if ((flags ^ oflags) & PVF_WIRED) { 1689129198Scognet if (flags & PVF_WIRED) 1690129198Scognet ++pm->pm_stats.wired_count; 1691129198Scognet else 1692129198Scognet --pm->pm_stats.wired_count; 1693129198Scognet } 1694129198Scognet 1695175840Scognet if ((flags ^ oflags) & PVF_WRITE) 1696175840Scognet pmap_fix_cache(pg, pm, 0); 1697129198Scognet 1698129198Scognet return (oflags); 1699129198Scognet} 1700129198Scognet 1701129198Scognet/* Function to set the debug level of the pmap code */ 1702129198Scognet#ifdef PMAP_DEBUG 1703129198Scognetvoid 1704129198Scognetpmap_debug(int level) 1705129198Scognet{ 1706129198Scognet pmap_debug_level = level; 1707129198Scognet dprintf("pmap_debug: level=%d\n", pmap_debug_level); 1708129198Scognet} 1709129198Scognet#endif /* PMAP_DEBUG */ 1710129198Scognet 1711129198Scognetvoid 1712129198Scognetpmap_pinit0(struct pmap *pmap) 1713129198Scognet{ 1714129198Scognet PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap)); 1715129198Scognet 1716135641Scognet bcopy(kernel_pmap, pmap, sizeof(*pmap)); 1717159325Salc bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx)); 1718159325Salc PMAP_LOCK_INIT(pmap); 1719129198Scognet} 1720129198Scognet 1721147217Salc/* 1722147217Salc * Initialize a vm_page's machine-dependent fields. 1723147217Salc */ 1724147217Salcvoid 1725147217Salcpmap_page_init(vm_page_t m) 1726147217Salc{ 1727129198Scognet 1728147217Salc TAILQ_INIT(&m->md.pv_list); 1729244414Scognet m->md.pv_memattr = VM_MEMATTR_DEFAULT; 1730331520Sian m->md.pvh_attrs = 0; 1731331520Sian m->md.pv_kva = 0; 1732147217Salc} 1733147217Salc 1734129198Scognet/* 1735129198Scognet * Initialize the pmap module. 1736129198Scognet * Called by vm_init, to initialize any structures that the pmap 1737129198Scognet * system needs to map virtual memory. 1738129198Scognet */ 1739129198Scognetvoid 1740129198Scognetpmap_init(void) 1741129198Scognet{ 1742152128Scognet int shpgperproc = PMAP_SHPGPERPROC; 1743129198Scognet 1744240803Salc l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor, 1745240803Salc NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1746240803Salc l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL, 1747240803Salc NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1748240803Salc 1749129198Scognet /* 1750240803Salc * Initialize the PV entry allocator. 1751129198Scognet */ 1752236991Simp pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL, 1753129198Scognet NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1754240803Salc TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1755263620Sbdrewery pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1756247360Sattilio uma_zone_reserve_kva(pvzone, pv_entry_max); 1757240803Salc pv_entry_high_water = 9 * (pv_entry_max / 10); 1758240803Salc 1759129198Scognet /* 1760129198Scognet * Now it is safe to enable pv_table recording. 1761129198Scognet */ 1762129198Scognet PDEBUG(1, printf("pmap_init: done!\n")); 1763129198Scognet} 1764129198Scognet 1765129198Scognetint 1766129198Scognetpmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user) 1767129198Scognet{ 1768129198Scognet struct l2_dtable *l2; 1769129198Scognet struct l2_bucket *l2b; 1770129198Scognet pd_entry_t *pl1pd, l1pd; 1771129198Scognet pt_entry_t *ptep, pte; 1772129198Scognet vm_paddr_t pa; 1773129198Scognet u_int l1idx; 1774129198Scognet int rv = 0; 1775129198Scognet 1776129198Scognet l1idx = L1_IDX(va); 1777239934Salc rw_wlock(&pvh_global_lock); 1778159384Salc PMAP_LOCK(pm); 1779129198Scognet 1780129198Scognet /* 1781129198Scognet * If there is no l2_dtable for this address, then the process 1782129198Scognet * has no business accessing it. 1783129198Scognet * 1784129198Scognet * Note: This will catch userland processes trying to access 1785129198Scognet * kernel addresses. 1786129198Scognet */ 1787129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 1788129198Scognet if (l2 == NULL) 1789129198Scognet goto out; 1790129198Scognet 1791129198Scognet /* 1792129198Scognet * Likewise if there is no L2 descriptor table 1793129198Scognet */ 1794129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 1795129198Scognet if (l2b->l2b_kva == NULL) 1796129198Scognet goto out; 1797129198Scognet 1798129198Scognet /* 1799129198Scognet * Check the PTE itself. 1800129198Scognet */ 1801129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1802129198Scognet pte = *ptep; 1803129198Scognet if (pte == 0) 1804129198Scognet goto out; 1805129198Scognet 1806129198Scognet /* 1807129198Scognet * Catch a userland access to the vector page mapped at 0x0 1808129198Scognet */ 1809129198Scognet if (user && (pte & L2_S_PROT_U) == 0) 1810129198Scognet goto out; 1811157027Scognet if (va == vector_page) 1812157027Scognet goto out; 1813129198Scognet 1814129198Scognet pa = l2pte_pa(pte); 1815129198Scognet 1816129198Scognet if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) { 1817129198Scognet /* 1818129198Scognet * This looks like a good candidate for "page modified" 1819129198Scognet * emulation... 1820129198Scognet */ 1821129198Scognet struct pv_entry *pv; 1822129198Scognet struct vm_page *pg; 1823129198Scognet 1824129198Scognet /* Extract the physical address of the page */ 1825129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) { 1826129198Scognet goto out; 1827129198Scognet } 1828129198Scognet /* Get the current flags for this page. */ 1829129198Scognet 1830129198Scognet pv = pmap_find_pv(pg, pm, va); 1831129198Scognet if (pv == NULL) { 1832129198Scognet goto out; 1833129198Scognet } 1834129198Scognet 1835129198Scognet /* 1836129198Scognet * Do the flags say this page is writable? If not then it 1837129198Scognet * is a genuine write fault. If yes then the write fault is 1838129198Scognet * our fault as we did not reflect the write access in the 1839129198Scognet * PTE. Now we know a write has occurred we can correct this 1840129198Scognet * and also set the modified bit 1841129198Scognet */ 1842129198Scognet if ((pv->pv_flags & PVF_WRITE) == 0) { 1843129198Scognet goto out; 1844129198Scognet } 1845129198Scognet 1846157970Scognet pg->md.pvh_attrs |= PVF_REF | PVF_MOD; 1847157970Scognet vm_page_dirty(pg); 1848129198Scognet pv->pv_flags |= PVF_REF | PVF_MOD; 1849129198Scognet 1850236991Simp /* 1851129198Scognet * Re-enable write permissions for the page. No need to call 1852175840Scognet * pmap_fix_cache(), since this is just a 1853129198Scognet * modified-emulation fault, and the PVF_WRITE bit isn't 1854129198Scognet * changing. We've already set the cacheable bits based on 1855129198Scognet * the assumption that we can write to this page. 1856129198Scognet */ 1857147114Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W; 1858129198Scognet PTE_SYNC(ptep); 1859129198Scognet rv = 1; 1860129198Scognet } else 1861129198Scognet if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) { 1862129198Scognet /* 1863129198Scognet * This looks like a good candidate for "page referenced" 1864129198Scognet * emulation. 1865129198Scognet */ 1866129198Scognet struct pv_entry *pv; 1867129198Scognet struct vm_page *pg; 1868129198Scognet 1869129198Scognet /* Extract the physical address of the page */ 1870159384Salc if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) 1871129198Scognet goto out; 1872129198Scognet /* Get the current flags for this page. */ 1873129198Scognet 1874129198Scognet pv = pmap_find_pv(pg, pm, va); 1875159384Salc if (pv == NULL) 1876129198Scognet goto out; 1877129198Scognet 1878129198Scognet pg->md.pvh_attrs |= PVF_REF; 1879129198Scognet pv->pv_flags |= PVF_REF; 1880129198Scognet 1881129198Scognet 1882129198Scognet *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO; 1883129198Scognet PTE_SYNC(ptep); 1884129198Scognet rv = 1; 1885129198Scognet } 1886129198Scognet 1887129198Scognet /* 1888129198Scognet * We know there is a valid mapping here, so simply 1889129198Scognet * fix up the L1 if necessary. 1890129198Scognet */ 1891129198Scognet pl1pd = &pm->pm_l1->l1_kva[l1idx]; 1892129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO; 1893129198Scognet if (*pl1pd != l1pd) { 1894129198Scognet *pl1pd = l1pd; 1895129198Scognet PTE_SYNC(pl1pd); 1896129198Scognet rv = 1; 1897129198Scognet } 1898129198Scognet 1899129198Scognet#ifdef DEBUG 1900129198Scognet /* 1901129198Scognet * If 'rv == 0' at this point, it generally indicates that there is a 1902129198Scognet * stale TLB entry for the faulting address. This happens when two or 1903129198Scognet * more processes are sharing an L1. Since we don't flush the TLB on 1904129198Scognet * a context switch between such processes, we can take domain faults 1905129198Scognet * for mappings which exist at the same VA in both processes. EVEN IF 1906129198Scognet * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for 1907129198Scognet * example. 1908129198Scognet * 1909129198Scognet * This is extremely likely to happen if pmap_enter() updated the L1 1910129198Scognet * entry for a recently entered mapping. In this case, the TLB is 1911129198Scognet * flushed for the new mapping, but there may still be TLB entries for 1912129198Scognet * other mappings belonging to other processes in the 1MB range 1913129198Scognet * covered by the L1 entry. 1914129198Scognet * 1915129198Scognet * Since 'rv == 0', we know that the L1 already contains the correct 1916129198Scognet * value, so the fault must be due to a stale TLB entry. 1917129198Scognet * 1918129198Scognet * Since we always need to flush the TLB anyway in the case where we 1919129198Scognet * fixed up the L1, or frobbed the L2 PTE, we effectively deal with 1920129198Scognet * stale TLB entries dynamically. 1921129198Scognet * 1922129198Scognet * However, the above condition can ONLY happen if the current L1 is 1923129198Scognet * being shared. If it happens when the L1 is unshared, it indicates 1924129198Scognet * that other parts of the pmap are not doing their job WRT managing 1925129198Scognet * the TLB. 1926129198Scognet */ 1927129198Scognet if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) { 1928129198Scognet printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n", 1929225988Smarcel pm, (u_long)va, ftype); 1930129198Scognet printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n", 1931129198Scognet l2, l2b, ptep, pl1pd); 1932129198Scognet printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n", 1933129198Scognet pte, l1pd, last_fault_code); 1934129198Scognet#ifdef DDB 1935129198Scognet Debugger(); 1936129198Scognet#endif 1937129198Scognet } 1938129198Scognet#endif 1939129198Scognet 1940129198Scognet cpu_tlb_flushID_SE(va); 1941129198Scognet cpu_cpwait(); 1942129198Scognet 1943129198Scognet rv = 1; 1944129198Scognet 1945129198Scognetout: 1946239934Salc rw_wunlock(&pvh_global_lock); 1947159384Salc PMAP_UNLOCK(pm); 1948129198Scognet return (rv); 1949129198Scognet} 1950129198Scognet 1951129198Scognetvoid 1952152128Scognetpmap_postinit(void) 1953152128Scognet{ 1954129198Scognet struct l2_bucket *l2b; 1955129198Scognet struct l1_ttable *l1; 1956129198Scognet pd_entry_t *pl1pt; 1957129198Scognet pt_entry_t *ptep, pte; 1958129198Scognet vm_offset_t va, eva; 1959129198Scognet u_int loop, needed; 1960283366Sandrew 1961129198Scognet needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0); 1962129198Scognet needed -= 1; 1963129198Scognet l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK); 1964129198Scognet 1965129198Scognet for (loop = 0; loop < needed; loop++, l1++) { 1966129198Scognet /* Allocate a L1 page table */ 1967132503Scognet va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0, 1968132503Scognet 0xffffffff, L1_TABLE_SIZE, 0); 1969129198Scognet 1970129198Scognet if (va == 0) 1971129198Scognet panic("Cannot allocate L1 KVM"); 1972129198Scognet 1973129198Scognet eva = va + L1_TABLE_SIZE; 1974129198Scognet pl1pt = (pd_entry_t *)va; 1975283366Sandrew 1976135641Scognet while (va < eva) { 1977295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, va); 1978129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 1979129198Scognet pte = *ptep; 1980129198Scognet pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt; 1981129198Scognet *ptep = pte; 1982129198Scognet PTE_SYNC(ptep); 1983129198Scognet cpu_tlb_flushD_SE(va); 1984283366Sandrew 1985129198Scognet va += PAGE_SIZE; 1986129198Scognet } 1987129198Scognet pmap_init_l1(l1, pl1pt); 1988129198Scognet } 1989129198Scognet 1990129198Scognet 1991129198Scognet#ifdef DEBUG 1992129198Scognet printf("pmap_postinit: Allocated %d static L1 descriptor tables\n", 1993129198Scognet needed); 1994129198Scognet#endif 1995129198Scognet} 1996129198Scognet 1997129198Scognet/* 1998129198Scognet * This is used to stuff certain critical values into the PCB where they 1999129198Scognet * can be accessed quickly from cpu_switch() et al. 2000129198Scognet */ 2001129198Scognetvoid 2002129198Scognetpmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb) 2003129198Scognet{ 2004129198Scognet struct l2_bucket *l2b; 2005129198Scognet 2006129198Scognet pcb->pcb_pagedir = pm->pm_l1->l1_physaddr; 2007129198Scognet pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | 2008129198Scognet (DOMAIN_CLIENT << (pm->pm_domain * 2)); 2009129198Scognet 2010129198Scognet if (vector_page < KERNBASE) { 2011129198Scognet pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)]; 2012129198Scognet l2b = pmap_get_l2_bucket(pm, vector_page); 2013129198Scognet pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO | 2014145071Scognet L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL); 2015129198Scognet } else 2016129198Scognet pcb->pcb_pl1vec = NULL; 2017129198Scognet} 2018129198Scognet 2019129198Scognetvoid 2020129198Scognetpmap_activate(struct thread *td) 2021129198Scognet{ 2022129198Scognet pmap_t pm; 2023129198Scognet struct pcb *pcb; 2024129198Scognet 2025135641Scognet pm = vmspace_pmap(td->td_proc->p_vmspace); 2026129198Scognet pcb = td->td_pcb; 2027129198Scognet 2028129198Scognet critical_enter(); 2029129198Scognet pmap_set_pcb_pagedir(pm, pcb); 2030129198Scognet 2031129198Scognet if (td == curthread) { 2032129198Scognet u_int cur_dacr, cur_ttb; 2033129198Scognet 2034129198Scognet __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb)); 2035129198Scognet __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr)); 2036129198Scognet 2037129198Scognet cur_ttb &= ~(L1_TABLE_SIZE - 1); 2038129198Scognet 2039129198Scognet if (cur_ttb == (u_int)pcb->pcb_pagedir && 2040129198Scognet cur_dacr == pcb->pcb_dacr) { 2041129198Scognet /* 2042129198Scognet * No need to switch address spaces. 2043129198Scognet */ 2044129198Scognet critical_exit(); 2045129198Scognet return; 2046129198Scognet } 2047129198Scognet 2048129198Scognet 2049129198Scognet /* 2050129198Scognet * We MUST, I repeat, MUST fix up the L1 entry corresponding 2051129198Scognet * to 'vector_page' in the incoming L1 table before switching 2052129198Scognet * to it otherwise subsequent interrupts/exceptions (including 2053129198Scognet * domain faults!) will jump into hyperspace. 2054129198Scognet */ 2055129198Scognet if (pcb->pcb_pl1vec) { 2056129198Scognet 2057129198Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2058129198Scognet /* 2059129198Scognet * Don't need to PTE_SYNC() at this point since 2060129198Scognet * cpu_setttb() is about to flush both the cache 2061129198Scognet * and the TLB. 2062129198Scognet */ 2063129198Scognet } 2064129198Scognet 2065129198Scognet cpu_domains(pcb->pcb_dacr); 2066129198Scognet cpu_setttb(pcb->pcb_pagedir); 2067129198Scognet } 2068129198Scognet critical_exit(); 2069129198Scognet} 2070129198Scognet 2071129198Scognetstatic int 2072129198Scognetpmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va) 2073129198Scognet{ 2074129198Scognet pd_entry_t *pdep, pde; 2075129198Scognet pt_entry_t *ptep, pte; 2076129198Scognet vm_offset_t pa; 2077129198Scognet int rv = 0; 2078129198Scognet 2079129198Scognet /* 2080129198Scognet * Make sure the descriptor itself has the correct cache mode 2081129198Scognet */ 2082129198Scognet pdep = &kl1[L1_IDX(va)]; 2083129198Scognet pde = *pdep; 2084129198Scognet 2085129198Scognet if (l1pte_section_p(pde)) { 2086129198Scognet if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) { 2087129198Scognet *pdep = (pde & ~L1_S_CACHE_MASK) | 2088129198Scognet pte_l1_s_cache_mode_pt; 2089129198Scognet PTE_SYNC(pdep); 2090129198Scognet cpu_dcache_wbinv_range((vm_offset_t)pdep, 2091129198Scognet sizeof(*pdep)); 2092183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)pdep, 2093183838Sraj sizeof(*pdep)); 2094129198Scognet rv = 1; 2095129198Scognet } 2096129198Scognet } else { 2097129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2098129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2099129198Scognet if (ptep == NULL) 2100129198Scognet panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep); 2101129198Scognet 2102129198Scognet ptep = &ptep[l2pte_index(va)]; 2103129198Scognet pte = *ptep; 2104129198Scognet if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) { 2105129198Scognet *ptep = (pte & ~L2_S_CACHE_MASK) | 2106129198Scognet pte_l2_s_cache_mode_pt; 2107129198Scognet PTE_SYNC(ptep); 2108129198Scognet cpu_dcache_wbinv_range((vm_offset_t)ptep, 2109129198Scognet sizeof(*ptep)); 2110183838Sraj cpu_l2cache_wbinv_range((vm_offset_t)ptep, 2111183838Sraj sizeof(*ptep)); 2112129198Scognet rv = 1; 2113129198Scognet } 2114129198Scognet } 2115129198Scognet 2116129198Scognet return (rv); 2117129198Scognet} 2118129198Scognet 2119129198Scognetstatic void 2120236991Simppmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap, 2121129198Scognet pt_entry_t **ptep) 2122129198Scognet{ 2123129198Scognet vm_offset_t va = *availp; 2124129198Scognet struct l2_bucket *l2b; 2125129198Scognet 2126129198Scognet if (ptep) { 2127295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, va); 2128129198Scognet if (l2b == NULL) 2129129198Scognet panic("pmap_alloc_specials: no l2b for 0x%x", va); 2130129198Scognet 2131129198Scognet *ptep = &l2b->l2b_kva[l2pte_index(va)]; 2132129198Scognet } 2133129198Scognet 2134129198Scognet *vap = va; 2135129198Scognet *availp = va + (PAGE_SIZE * pages); 2136129198Scognet} 2137129198Scognet 2138129198Scognet/* 2139129198Scognet * Bootstrap the system enough to run with virtual memory. 2140129198Scognet * 2141129198Scognet * On the arm this is called after mapping has already been enabled 2142129198Scognet * and just syncs the pmap module with what has already been done. 2143129198Scognet * [We can't call it easily with mapping off since the kernel is not 2144129198Scognet * mapped with PA == VA, hence we would have to relocate every address 2145129198Scognet * from the linked base (virtual) address "KERNBASE" to the actual 2146129198Scognet * (physical) address starting relative to 0] 2147129198Scognet */ 2148129198Scognet#define PMAP_STATIC_L2_SIZE 16 2149129198Scognetvoid 2150247046Salcpmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt) 2151129198Scognet{ 2152129198Scognet static struct l1_ttable static_l1; 2153129198Scognet static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE]; 2154129198Scognet struct l1_ttable *l1 = &static_l1; 2155129198Scognet struct l2_dtable *l2; 2156129198Scognet struct l2_bucket *l2b; 2157129198Scognet pd_entry_t pde; 2158129198Scognet pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va; 2159129198Scognet pt_entry_t *ptep; 2160286296Sjah pt_entry_t *qmap_pte; 2161129198Scognet vm_paddr_t pa; 2162129198Scognet vm_offset_t va; 2163135641Scognet vm_size_t size; 2164129198Scognet int l1idx, l2idx, l2next = 0; 2165129198Scognet 2166197770Sstas PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n", 2167247046Salc firstaddr, vm_max_kernel_address)); 2168283366Sandrew 2169129198Scognet virtual_avail = firstaddr; 2170129198Scognet kernel_pmap->pm_l1 = l1; 2171150865Scognet kernel_l1pa = l1pt->pv_pa; 2172283366Sandrew 2173143192Scognet /* 2174129198Scognet * Scan the L1 translation table created by initarm() and create 2175129198Scognet * the required metadata for all valid mappings found in it. 2176129198Scognet */ 2177129198Scognet for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) { 2178129198Scognet pde = kernel_l1pt[l1idx]; 2179129198Scognet 2180129198Scognet /* 2181129198Scognet * We're only interested in Coarse mappings. 2182129198Scognet * pmap_extract() can deal with section mappings without 2183129198Scognet * recourse to checking L2 metadata. 2184129198Scognet */ 2185129198Scognet if ((pde & L1_TYPE_MASK) != L1_TYPE_C) 2186129198Scognet continue; 2187129198Scognet 2188129198Scognet /* 2189129198Scognet * Lookup the KVA of this L2 descriptor table 2190129198Scognet */ 2191129198Scognet pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK); 2192129198Scognet ptep = (pt_entry_t *)kernel_pt_lookup(pa); 2193283366Sandrew 2194129198Scognet if (ptep == NULL) { 2195129198Scognet panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx", 2196129198Scognet (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa); 2197129198Scognet } 2198129198Scognet 2199129198Scognet /* 2200129198Scognet * Fetch the associated L2 metadata structure. 2201129198Scognet * Allocate a new one if necessary. 2202129198Scognet */ 2203129198Scognet if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) { 2204129198Scognet if (l2next == PMAP_STATIC_L2_SIZE) 2205129198Scognet panic("pmap_bootstrap: out of static L2s"); 2206236991Simp kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 = 2207129198Scognet &static_l2[l2next++]; 2208129198Scognet } 2209129198Scognet 2210129198Scognet /* 2211129198Scognet * One more L1 slot tracked... 2212129198Scognet */ 2213129198Scognet l2->l2_occupancy++; 2214129198Scognet 2215129198Scognet /* 2216129198Scognet * Fill in the details of the L2 descriptor in the 2217129198Scognet * appropriate bucket. 2218129198Scognet */ 2219129198Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2220129198Scognet l2b->l2b_kva = ptep; 2221129198Scognet l2b->l2b_phys = pa; 2222129198Scognet l2b->l2b_l1idx = l1idx; 2223129198Scognet 2224129198Scognet /* 2225129198Scognet * Establish an initial occupancy count for this descriptor 2226129198Scognet */ 2227129198Scognet for (l2idx = 0; 2228129198Scognet l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)); 2229129198Scognet l2idx++) { 2230129198Scognet if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) { 2231129198Scognet l2b->l2b_occupancy++; 2232129198Scognet } 2233129198Scognet } 2234129198Scognet 2235129198Scognet /* 2236129198Scognet * Make sure the descriptor itself has the correct cache mode. 2237129198Scognet * If not, fix it, but whine about the problem. Port-meisters 2238129198Scognet * should consider this a clue to fix up their initarm() 2239129198Scognet * function. :) 2240129198Scognet */ 2241129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) { 2242129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2243129198Scognet "L2 pte @ %p\n", ptep); 2244129198Scognet } 2245129198Scognet } 2246129198Scognet 2247283366Sandrew 2248129198Scognet /* 2249129198Scognet * Ensure the primary (kernel) L1 has the correct cache mode for 2250129198Scognet * a page table. Bitch if it is not correctly set. 2251129198Scognet */ 2252129198Scognet for (va = (vm_offset_t)kernel_l1pt; 2253129198Scognet va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) { 2254129198Scognet if (pmap_set_pt_cache_mode(kernel_l1pt, va)) 2255129198Scognet printf("pmap_bootstrap: WARNING! wrong cache mode for " 2256129198Scognet "primary L1 @ 0x%x\n", va); 2257129198Scognet } 2258129198Scognet 2259129198Scognet cpu_dcache_wbinv_all(); 2260183838Sraj cpu_l2cache_wbinv_all(); 2261129198Scognet cpu_tlb_flushID(); 2262129198Scognet cpu_cpwait(); 2263129198Scognet 2264159325Salc PMAP_LOCK_INIT(kernel_pmap); 2265222813Sattilio CPU_FILL(&kernel_pmap->pm_active); 2266129198Scognet kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL; 2267144760Scognet TAILQ_INIT(&kernel_pmap->pm_pvlist); 2268239934Salc 2269239934Salc /* 2270239934Salc * Initialize the global pv list lock. 2271239934Salc */ 2272239934Salc rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE); 2273283366Sandrew 2274129198Scognet /* 2275129198Scognet * Reserve some special page table entries/VA space for temporary 2276129198Scognet * mapping of pages. 2277129198Scognet */ 2278129198Scognet pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte); 2279129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte); 2280129198Scognet pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte); 2281129198Scognet pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte); 2282286296Sjah pmap_alloc_specials(&virtual_avail, 1, &qmap_addr, &qmap_pte); 2283286296Sjah pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)qmap_pte); 2284247046Salc size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) / 2285247046Salc L1_S_SIZE; 2286135641Scognet pmap_alloc_specials(&virtual_avail, 2287135641Scognet round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE, 2288135641Scognet &pmap_kernel_l2ptp_kva, NULL); 2289283366Sandrew 2290298643Spfg size = howmany(size, L2_BUCKET_SIZE); 2291135641Scognet pmap_alloc_specials(&virtual_avail, 2292135641Scognet round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE, 2293135641Scognet &pmap_kernel_l2dtable_kva, NULL); 2294135641Scognet 2295137362Scognet pmap_alloc_specials(&virtual_avail, 2296137362Scognet 1, (vm_offset_t*)&_tmppt, NULL); 2297184728Sraj pmap_alloc_specials(&virtual_avail, 2298184728Sraj MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL); 2299135641Scognet SLIST_INIT(&l1_list); 2300129198Scognet TAILQ_INIT(&l1_lru_list); 2301129198Scognet mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); 2302129198Scognet pmap_init_l1(l1, kernel_l1pt); 2303129198Scognet cpu_dcache_wbinv_all(); 2304183838Sraj cpu_l2cache_wbinv_all(); 2305129198Scognet 2306129198Scognet virtual_avail = round_page(virtual_avail); 2307247046Salc virtual_end = vm_max_kernel_address; 2308135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2309159088Scognet mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF); 2310286296Sjah mtx_init(&qmap_mtx, "quick mapping mtx", NULL, MTX_DEF); 2311156191Scognet 2312161105Scognet pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb); 2313129198Scognet} 2314129198Scognet 2315129198Scognet/*************************************************** 2316129198Scognet * Pmap allocation/deallocation routines. 2317129198Scognet ***************************************************/ 2318129198Scognet 2319129198Scognet/* 2320129198Scognet * Release any resources held by the given physical map. 2321129198Scognet * Called when a pmap initialized by pmap_pinit is being released. 2322129198Scognet * Should only be called if the map contains no valid mappings. 2323129198Scognet */ 2324129198Scognetvoid 2325129198Scognetpmap_release(pmap_t pmap) 2326129198Scognet{ 2327135641Scognet struct pcb *pcb; 2328283366Sandrew 2329135641Scognet pmap_idcache_wbinv_all(pmap); 2330183838Sraj cpu_l2cache_wbinv_all(); 2331135641Scognet pmap_tlb_flushID(pmap); 2332135641Scognet cpu_cpwait(); 2333135641Scognet if (vector_page < KERNBASE) { 2334135641Scognet struct pcb *curpcb = PCPU_GET(curpcb); 2335135641Scognet pcb = thread0.td_pcb; 2336135641Scognet if (pmap_is_current(pmap)) { 2337135641Scognet /* 2338135641Scognet * Frob the L1 entry corresponding to the vector 2339135641Scognet * page so that it contains the kernel pmap's domain 2340135641Scognet * number. This will ensure pmap_remove() does not 2341135641Scognet * pull the current vector page out from under us. 2342135641Scognet */ 2343135641Scognet critical_enter(); 2344135641Scognet *pcb->pcb_pl1vec = pcb->pcb_l1vec; 2345135641Scognet cpu_domains(pcb->pcb_dacr); 2346135641Scognet cpu_setttb(pcb->pcb_pagedir); 2347135641Scognet critical_exit(); 2348135641Scognet } 2349135641Scognet pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE); 2350135641Scognet /* 2351135641Scognet * Make sure cpu_switch(), et al, DTRT. This is safe to do 2352135641Scognet * since this process has no remaining mappings of its own. 2353135641Scognet */ 2354135641Scognet curpcb->pcb_pl1vec = pcb->pcb_pl1vec; 2355135641Scognet curpcb->pcb_l1vec = pcb->pcb_l1vec; 2356135641Scognet curpcb->pcb_dacr = pcb->pcb_dacr; 2357135641Scognet curpcb->pcb_pagedir = pcb->pcb_pagedir; 2358135641Scognet 2359135641Scognet } 2360129198Scognet pmap_free_l1(pmap); 2361283366Sandrew 2362129198Scognet dprintf("pmap_release()\n"); 2363129198Scognet} 2364129198Scognet 2365129198Scognet 2366135641Scognet 2367129198Scognet/* 2368135641Scognet * Helper function for pmap_grow_l2_bucket() 2369135641Scognet */ 2370135641Scognetstatic __inline int 2371135641Scognetpmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap) 2372135641Scognet{ 2373135641Scognet struct l2_bucket *l2b; 2374135641Scognet pt_entry_t *ptep; 2375135641Scognet vm_paddr_t pa; 2376135641Scognet struct vm_page *pg; 2377283366Sandrew 2378150865Scognet pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 2379135641Scognet if (pg == NULL) 2380135641Scognet return (1); 2381135641Scognet pa = VM_PAGE_TO_PHYS(pg); 2382135641Scognet 2383135641Scognet if (pap) 2384135641Scognet *pap = pa; 2385135641Scognet 2386295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, va); 2387135641Scognet 2388135641Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 2389135641Scognet *ptep = L2_S_PROTO | pa | cache_mode | 2390135641Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 2391135641Scognet PTE_SYNC(ptep); 2392135641Scognet return (0); 2393135641Scognet} 2394135641Scognet 2395135641Scognet/* 2396135641Scognet * This is the same as pmap_alloc_l2_bucket(), except that it is only 2397135641Scognet * used by pmap_growkernel(). 2398135641Scognet */ 2399135641Scognetstatic __inline struct l2_bucket * 2400135641Scognetpmap_grow_l2_bucket(pmap_t pm, vm_offset_t va) 2401135641Scognet{ 2402135641Scognet struct l2_dtable *l2; 2403135641Scognet struct l2_bucket *l2b; 2404135641Scognet struct l1_ttable *l1; 2405135641Scognet pd_entry_t *pl1pd; 2406135641Scognet u_short l1idx; 2407135641Scognet vm_offset_t nva; 2408135641Scognet 2409135641Scognet l1idx = L1_IDX(va); 2410135641Scognet 2411135641Scognet if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) { 2412135641Scognet /* 2413135641Scognet * No mapping at this address, as there is 2414135641Scognet * no entry in the L1 table. 2415135641Scognet * Need to allocate a new l2_dtable. 2416135641Scognet */ 2417135641Scognet nva = pmap_kernel_l2dtable_kva; 2418135641Scognet if ((nva & PAGE_MASK) == 0) { 2419135641Scognet /* 2420135641Scognet * Need to allocate a backing page 2421135641Scognet */ 2422135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2423135641Scognet return (NULL); 2424135641Scognet } 2425135641Scognet 2426135641Scognet l2 = (struct l2_dtable *)nva; 2427135641Scognet nva += sizeof(struct l2_dtable); 2428135641Scognet 2429236991Simp if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva & 2430135641Scognet PAGE_MASK)) { 2431135641Scognet /* 2432135641Scognet * The new l2_dtable straddles a page boundary. 2433135641Scognet * Map in another page to cover it. 2434135641Scognet */ 2435135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL)) 2436135641Scognet return (NULL); 2437135641Scognet } 2438135641Scognet 2439135641Scognet pmap_kernel_l2dtable_kva = nva; 2440135641Scognet 2441135641Scognet /* 2442135641Scognet * Link it into the parent pmap 2443135641Scognet */ 2444135641Scognet pm->pm_l2[L2_IDX(l1idx)] = l2; 2445150865Scognet memset(l2, 0, sizeof(*l2)); 2446135641Scognet } 2447135641Scognet 2448135641Scognet l2b = &l2->l2_bucket[L2_BUCKET(l1idx)]; 2449135641Scognet 2450135641Scognet /* 2451135641Scognet * Fetch pointer to the L2 page table associated with the address. 2452135641Scognet */ 2453135641Scognet if (l2b->l2b_kva == NULL) { 2454135641Scognet pt_entry_t *ptep; 2455135641Scognet 2456135641Scognet /* 2457135641Scognet * No L2 page table has been allocated. Chances are, this 2458135641Scognet * is because we just allocated the l2_dtable, above. 2459135641Scognet */ 2460135641Scognet nva = pmap_kernel_l2ptp_kva; 2461135641Scognet ptep = (pt_entry_t *)nva; 2462135641Scognet if ((nva & PAGE_MASK) == 0) { 2463135641Scognet /* 2464135641Scognet * Need to allocate a backing page 2465135641Scognet */ 2466135641Scognet if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt, 2467135641Scognet &pmap_kernel_l2ptp_phys)) 2468135641Scognet return (NULL); 2469135641Scognet PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t)); 2470135641Scognet } 2471150865Scognet memset(ptep, 0, L2_TABLE_SIZE_REAL); 2472135641Scognet l2->l2_occupancy++; 2473135641Scognet l2b->l2b_kva = ptep; 2474135641Scognet l2b->l2b_l1idx = l1idx; 2475135641Scognet l2b->l2b_phys = pmap_kernel_l2ptp_phys; 2476135641Scognet 2477135641Scognet pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL; 2478135641Scognet pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL; 2479135641Scognet } 2480135641Scognet 2481135641Scognet /* Distribute new L1 entry to all other L1s */ 2482135641Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2483145071Scognet pl1pd = &l1->l1_kva[L1_IDX(va)]; 2484135641Scognet *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) | 2485135641Scognet L1_C_PROTO; 2486135641Scognet PTE_SYNC(pl1pd); 2487135641Scognet } 2488135641Scognet 2489135641Scognet return (l2b); 2490135641Scognet} 2491135641Scognet 2492135641Scognet 2493135641Scognet/* 2494129198Scognet * grow the number of kernel page table entries, if needed 2495129198Scognet */ 2496129198Scognetvoid 2497129198Scognetpmap_growkernel(vm_offset_t addr) 2498129198Scognet{ 2499295042Sskra pmap_t kpm = kernel_pmap; 2500129198Scognet 2501135641Scognet if (addr <= pmap_curmaxkvaddr) 2502135641Scognet return; /* we are OK */ 2503135641Scognet 2504135641Scognet /* 2505135641Scognet * whoops! we need to add kernel PTPs 2506135641Scognet */ 2507135641Scognet 2508135641Scognet /* Map 1MB at a time */ 2509135641Scognet for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE) 2510135641Scognet pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr); 2511135641Scognet 2512135641Scognet /* 2513135641Scognet * flush out the cache, expensive but growkernel will happen so 2514135641Scognet * rarely 2515135641Scognet */ 2516135641Scognet cpu_dcache_wbinv_all(); 2517183838Sraj cpu_l2cache_wbinv_all(); 2518135641Scognet cpu_tlb_flushD(); 2519135641Scognet cpu_cpwait(); 2520135641Scognet kernel_vm_end = pmap_curmaxkvaddr; 2521129198Scognet} 2522129198Scognet 2523129198Scognet 2524129198Scognet/* 2525129198Scognet * Remove all pages from specified address space 2526129198Scognet * this aids process exit speeds. Also, this code 2527129198Scognet * is special cased for current process only, but 2528129198Scognet * can have the more generic (and slightly slower) 2529129198Scognet * mode enabled. This is much faster than pmap_remove 2530129198Scognet * in the case of running down an entire address space. 2531129198Scognet */ 2532129198Scognetvoid 2533157443Speterpmap_remove_pages(pmap_t pmap) 2534129198Scognet{ 2535144760Scognet struct pv_entry *pv, *npv; 2536144760Scognet struct l2_bucket *l2b = NULL; 2537144760Scognet vm_page_t m; 2538144760Scognet pt_entry_t *pt; 2539283366Sandrew 2540239934Salc rw_wlock(&pvh_global_lock); 2541159352Salc PMAP_LOCK(pmap); 2542175840Scognet cpu_idcache_wbinv_all(); 2543183838Sraj cpu_l2cache_wbinv_all(); 2544144760Scognet for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2545194459Sthompsa if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) { 2546194459Sthompsa /* Cannot remove wired or unmanaged pages now. */ 2547144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2548144760Scognet continue; 2549144760Scognet } 2550144760Scognet pmap->pm_stats.resident_count--; 2551144760Scognet l2b = pmap_get_l2_bucket(pmap, pv->pv_va); 2552144760Scognet KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages")); 2553144760Scognet pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 2554295751Sskra m = PHYS_TO_VM_PAGE(*pt & L2_S_FRAME); 2555164079Scognet KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt)); 2556144760Scognet *pt = 0; 2557144760Scognet PTE_SYNC(pt); 2558144760Scognet npv = TAILQ_NEXT(pv, pv_plist); 2559144760Scognet pmap_nuke_pv(m, pmap, pv); 2560150865Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 2561225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2562144760Scognet pmap_free_pv_entry(pv); 2563164874Scognet pmap_free_l2_bucket(pmap, l2b, 1); 2564144760Scognet } 2565239934Salc rw_wunlock(&pvh_global_lock); 2566135641Scognet cpu_tlb_flushID(); 2567135641Scognet cpu_cpwait(); 2568159352Salc PMAP_UNLOCK(pmap); 2569129198Scognet} 2570129198Scognet 2571129198Scognet 2572129198Scognet/*************************************************** 2573129198Scognet * Low level mapping routines..... 2574129198Scognet ***************************************************/ 2575129198Scognet 2576171620Scognet#ifdef ARM_HAVE_SUPERSECTIONS 2577170582Scognet/* Map a super section into the KVA. */ 2578170582Scognet 2579170582Scognetvoid 2580170582Scognetpmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags) 2581170582Scognet{ 2582171620Scognet pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) | 2583171620Scognet (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL, 2584170582Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2585283366Sandrew struct l1_ttable *l1; 2586171620Scognet vm_offset_t va0, va_end; 2587170582Scognet 2588170582Scognet KASSERT(((va | pa) & L1_SUP_OFFSET) == 0, 2589171620Scognet ("Not a valid super section mapping")); 2590170582Scognet if (flags & SECTION_CACHE) 2591170582Scognet pd |= pte_l1_s_cache_mode; 2592170582Scognet else if (flags & SECTION_PT) 2593170582Scognet pd |= pte_l1_s_cache_mode_pt; 2594171620Scognet va0 = va & L1_SUP_FRAME; 2595170582Scognet va_end = va + L1_SUP_SIZE; 2596170582Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2597171620Scognet va = va0; 2598170582Scognet for (; va < va_end; va += L1_S_SIZE) { 2599170582Scognet l1->l1_kva[L1_IDX(va)] = pd; 2600170582Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2601170582Scognet } 2602170582Scognet } 2603170582Scognet} 2604171620Scognet#endif 2605170582Scognet 2606147114Scognet/* Map a section into the KVA. */ 2607147114Scognet 2608147114Scognetvoid 2609147114Scognetpmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags) 2610147114Scognet{ 2611147114Scognet pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL, 2612147114Scognet VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL); 2613147114Scognet struct l1_ttable *l1; 2614147114Scognet 2615147114Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, 2616147114Scognet ("Not a valid section mapping")); 2617147114Scognet if (flags & SECTION_CACHE) 2618147114Scognet pd |= pte_l1_s_cache_mode; 2619147114Scognet else if (flags & SECTION_PT) 2620147114Scognet pd |= pte_l1_s_cache_mode_pt; 2621147114Scognet SLIST_FOREACH(l1, &l1_list, l1_link) { 2622147114Scognet l1->l1_kva[L1_IDX(va)] = pd; 2623147114Scognet PTE_SYNC(&l1->l1_kva[L1_IDX(va)]); 2624147114Scognet } 2625147114Scognet} 2626147114Scognet 2627129198Scognet/* 2628184728Sraj * Make a temporary mapping for a physical address. This is only intended 2629184728Sraj * to be used for panic dumps. 2630184728Sraj */ 2631184728Srajvoid * 2632271422Sandrewpmap_kenter_temporary(vm_paddr_t pa, int i) 2633184728Sraj{ 2634184728Sraj vm_offset_t va; 2635184728Sraj 2636184728Sraj va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 2637184728Sraj pmap_kenter(va, pa); 2638184728Sraj return ((void *)crashdumpmap); 2639184728Sraj} 2640184728Sraj 2641184728Sraj/* 2642129198Scognet * add a wired page to the kva 2643129198Scognet * note that in order for the mapping to take effect -- you 2644129198Scognet * should do a invltlb after doing the pmap_kenter... 2645129198Scognet */ 2646135641Scognetstatic PMAP_INLINE void 2647135641Scognetpmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags) 2648129198Scognet{ 2649129198Scognet struct l2_bucket *l2b; 2650129198Scognet pt_entry_t *pte; 2651129198Scognet pt_entry_t opte; 2652194459Sthompsa struct pv_entry *pve; 2653194459Sthompsa vm_page_t m; 2654194459Sthompsa 2655129198Scognet PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n", 2656129198Scognet (uint32_t) va, (uint32_t) pa)); 2657129198Scognet 2658129198Scognet 2659295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, va); 2660135641Scognet if (l2b == NULL) 2661295042Sskra l2b = pmap_grow_l2_bucket(kernel_pmap, va); 2662129198Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2663129198Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2664129198Scognet opte = *pte; 2665129198Scognet PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n", 2666129198Scognet (uint32_t) pte, opte, *pte)); 2667129198Scognet if (l2pte_valid(opte)) { 2668194459Sthompsa pmap_kremove(va); 2669135641Scognet } else { 2670129198Scognet if (opte == 0) 2671129198Scognet l2b->l2b_occupancy++; 2672135641Scognet } 2673236991Simp *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, 2674135641Scognet VM_PROT_READ | VM_PROT_WRITE); 2675135641Scognet if (flags & KENTER_CACHE) 2676135641Scognet *pte |= pte_l2_s_cache_mode; 2677142570Scognet if (flags & KENTER_USER) 2678142570Scognet *pte |= L2_S_PROT_U; 2679129198Scognet PTE_SYNC(pte); 2680194459Sthompsa 2681240166Salc /* 2682240166Salc * A kernel mapping may not be the page's only mapping, so create a PV 2683240166Salc * entry to ensure proper caching. 2684240166Salc * 2685240166Salc * The existence test for the pvzone is used to delay the recording of 2686240166Salc * kernel mappings until the VM system is fully initialized. 2687240166Salc * 2688240166Salc * This expects the physical memory to have a vm_page_array entry. 2689240166Salc */ 2690240166Salc if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) { 2691239934Salc rw_wlock(&pvh_global_lock); 2692240166Salc if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) { 2693194459Sthompsa if ((pve = pmap_get_pv_entry()) == NULL) 2694283366Sandrew panic("pmap_kenter_internal: no pv entries"); 2695295042Sskra PMAP_LOCK(kernel_pmap); 2696295042Sskra pmap_enter_pv(m, pve, kernel_pmap, va, 2697198341Smarcel PVF_WRITE | PVF_UNMAN); 2698295042Sskra pmap_fix_cache(m, kernel_pmap, va); 2699295042Sskra PMAP_UNLOCK(kernel_pmap); 2700194459Sthompsa } else { 2701194459Sthompsa m->md.pv_kva = va; 2702194459Sthompsa } 2703239934Salc rw_wunlock(&pvh_global_lock); 2704194459Sthompsa } 2705135641Scognet} 2706129198Scognet 2707135641Scognetvoid 2708135641Scognetpmap_kenter(vm_offset_t va, vm_paddr_t pa) 2709135641Scognet{ 2710135641Scognet pmap_kenter_internal(va, pa, KENTER_CACHE); 2711129198Scognet} 2712129198Scognet 2713142570Scognetvoid 2714156191Scognetpmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa) 2715156191Scognet{ 2716156191Scognet 2717156191Scognet pmap_kenter_internal(va, pa, 0); 2718156191Scognet} 2719156191Scognet 2720156191Scognetvoid 2721281369Sianpmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa) 2722257648Sian{ 2723281369Sian vm_offset_t sva; 2724257648Sian 2725283366Sandrew KASSERT((size & PAGE_MASK) == 0, 2726281369Sian ("%s: device mapping not page-sized", __func__)); 2727281369Sian 2728281369Sian sva = va; 2729281369Sian while (size != 0) { 2730281369Sian pmap_kenter_internal(va, pa, 0); 2731281369Sian va += PAGE_SIZE; 2732281369Sian pa += PAGE_SIZE; 2733281369Sian size -= PAGE_SIZE; 2734281369Sian } 2735257648Sian} 2736257648Sian 2737257648Sianvoid 2738281369Sianpmap_kremove_device(vm_offset_t va, vm_size_t size) 2739281369Sian{ 2740281369Sian vm_offset_t sva; 2741281369Sian 2742283366Sandrew KASSERT((size & PAGE_MASK) == 0, 2743281369Sian ("%s: device mapping not page-sized", __func__)); 2744281369Sian 2745281369Sian sva = va; 2746281369Sian while (size != 0) { 2747281369Sian pmap_kremove(va); 2748281369Sian va += PAGE_SIZE; 2749281369Sian size -= PAGE_SIZE; 2750281369Sian } 2751281369Sian} 2752281369Sian 2753281369Sianvoid 2754142570Scognetpmap_kenter_user(vm_offset_t va, vm_paddr_t pa) 2755142570Scognet{ 2756143192Scognet 2757142570Scognet pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER); 2758143192Scognet /* 2759143192Scognet * Call pmap_fault_fixup now, to make sure we'll have no exception 2760143192Scognet * at the first use of the new address, or bad things will happen, 2761143192Scognet * as we use one of these addresses in the exception handlers. 2762143192Scognet */ 2763295042Sskra pmap_fault_fixup(kernel_pmap, va, VM_PROT_READ|VM_PROT_WRITE, 1); 2764142570Scognet} 2765129198Scognet 2766240983Salcvm_paddr_t 2767240983Salcpmap_kextract(vm_offset_t va) 2768240983Salc{ 2769240983Salc 2770240983Salc return (pmap_extract_locked(kernel_pmap, va)); 2771240983Salc} 2772240983Salc 2773129198Scognet/* 2774194908Scognet * remove a page from the kernel pagetables 2775129198Scognet */ 2776169763Scognetvoid 2777129198Scognetpmap_kremove(vm_offset_t va) 2778129198Scognet{ 2779135641Scognet struct l2_bucket *l2b; 2780135641Scognet pt_entry_t *pte, opte; 2781194459Sthompsa struct pv_entry *pve; 2782194459Sthompsa vm_page_t m; 2783194459Sthompsa vm_offset_t pa; 2784283366Sandrew 2785295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, va); 2786145071Scognet if (!l2b) 2787145071Scognet return; 2788135641Scognet KASSERT(l2b != NULL, ("No L2 Bucket")); 2789135641Scognet pte = &l2b->l2b_kva[l2pte_index(va)]; 2790135641Scognet opte = *pte; 2791135641Scognet if (l2pte_valid(opte)) { 2792294789Sskra /* pa = vtophs(va) taken from pmap_extract() */ 2793294789Sskra if ((opte & L2_TYPE_MASK) == L2_TYPE_L) 2794194459Sthompsa pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET); 2795294789Sskra else 2796194459Sthompsa pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET); 2797294789Sskra /* note: should never have to remove an allocation 2798294789Sskra * before the pvzone is initialized. 2799294789Sskra */ 2800239934Salc rw_wlock(&pvh_global_lock); 2801295042Sskra PMAP_LOCK(kernel_pmap); 2802194459Sthompsa if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) && 2803295042Sskra (pve = pmap_remove_pv(m, kernel_pmap, va))) 2804236991Simp pmap_free_pv_entry(pve); 2805295042Sskra PMAP_UNLOCK(kernel_pmap); 2806239934Salc rw_wunlock(&pvh_global_lock); 2807195779Sraj va = va & ~PAGE_MASK; 2808135641Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 2809183838Sraj cpu_l2cache_wbinv_range(va, PAGE_SIZE); 2810135641Scognet cpu_tlb_flushD_SE(va); 2811135641Scognet cpu_cpwait(); 2812144760Scognet *pte = 0; 2813135641Scognet } 2814129198Scognet} 2815129198Scognet 2816129198Scognet 2817129198Scognet/* 2818129198Scognet * Used to map a range of physical addresses into kernel 2819129198Scognet * virtual address space. 2820129198Scognet * 2821129198Scognet * The value passed in '*virt' is a suggested virtual address for 2822129198Scognet * the mapping. Architectures which can support a direct-mapped 2823129198Scognet * physical to virtual region can return the appropriate address 2824129198Scognet * within that region, leaving '*virt' unchanged. Other 2825129198Scognet * architectures should map the pages starting at '*virt' and 2826129198Scognet * update '*virt' with the first usable address after the mapped 2827129198Scognet * region. 2828129198Scognet */ 2829129198Scognetvm_offset_t 2830129198Scognetpmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 2831129198Scognet{ 2832129198Scognet vm_offset_t sva = *virt; 2833129198Scognet vm_offset_t va = sva; 2834129198Scognet 2835129198Scognet PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, " 2836129198Scognet "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end, 2837129198Scognet prot)); 2838236991Simp 2839129198Scognet while (start < end) { 2840129198Scognet pmap_kenter(va, start); 2841129198Scognet va += PAGE_SIZE; 2842129198Scognet start += PAGE_SIZE; 2843129198Scognet } 2844129198Scognet *virt = va; 2845129198Scognet return (sva); 2846129198Scognet} 2847129198Scognet 2848143724Scognetstatic void 2849150865Scognetpmap_wb_page(vm_page_t m) 2850143724Scognet{ 2851143724Scognet struct pv_entry *pv; 2852129198Scognet 2853143724Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2854150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE, 2855144760Scognet (pv->pv_flags & PVF_WRITE) == 0); 2856143724Scognet} 2857143724Scognet 2858150865Scognetstatic void 2859150865Scognetpmap_inv_page(vm_page_t m) 2860150865Scognet{ 2861150865Scognet struct pv_entry *pv; 2862150865Scognet 2863150865Scognet TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2864150865Scognet pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE); 2865150865Scognet} 2866129198Scognet/* 2867129198Scognet * Add a list of wired pages to the kva 2868129198Scognet * this routine is only used for temporary 2869129198Scognet * kernel mappings that do not need to have 2870129198Scognet * page modification or references recorded. 2871129198Scognet * Note that old mappings are simply written 2872129198Scognet * over. The page *must* be wired. 2873129198Scognet */ 2874129198Scognetvoid 2875129198Scognetpmap_qenter(vm_offset_t va, vm_page_t *m, int count) 2876129198Scognet{ 2877129198Scognet int i; 2878129198Scognet 2879129198Scognet for (i = 0; i < count; i++) { 2880150865Scognet pmap_wb_page(m[i]); 2881236991Simp pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]), 2882135641Scognet KENTER_CACHE); 2883129198Scognet va += PAGE_SIZE; 2884129198Scognet } 2885129198Scognet} 2886129198Scognet 2887129198Scognet 2888129198Scognet/* 2889129198Scognet * this routine jerks page mappings from the 2890129198Scognet * kernel -- it is meant only for temporary mappings. 2891129198Scognet */ 2892129198Scognetvoid 2893129198Scognetpmap_qremove(vm_offset_t va, int count) 2894129198Scognet{ 2895146596Scognet vm_paddr_t pa; 2896129198Scognet int i; 2897129198Scognet 2898129198Scognet for (i = 0; i < count; i++) { 2899146596Scognet pa = vtophys(va); 2900146596Scognet if (pa) { 2901150865Scognet pmap_inv_page(PHYS_TO_VM_PAGE(pa)); 2902146596Scognet pmap_kremove(va); 2903146596Scognet } 2904129198Scognet va += PAGE_SIZE; 2905129198Scognet } 2906129198Scognet} 2907129198Scognet 2908129198Scognet 2909129198Scognet/* 2910129198Scognet * pmap_object_init_pt preloads the ptes for a given object 2911129198Scognet * into the specified pmap. This eliminates the blast of soft 2912129198Scognet * faults on process startup and immediately after an mmap. 2913129198Scognet */ 2914129198Scognetvoid 2915129198Scognetpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 2916129198Scognet vm_pindex_t pindex, vm_size_t size) 2917129198Scognet{ 2918157156Scognet 2919248084Sattilio VM_OBJECT_ASSERT_WLOCKED(object); 2920195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2921157156Scognet ("pmap_object_init_pt: non-device object")); 2922129198Scognet} 2923129198Scognet 2924129198Scognet 2925129198Scognet/* 2926129198Scognet * pmap_is_prefaultable: 2927129198Scognet * 2928129198Scognet * Return whether or not the specified virtual address is elgible 2929129198Scognet * for prefault. 2930129198Scognet */ 2931129198Scognetboolean_t 2932129198Scognetpmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2933129198Scognet{ 2934135641Scognet pd_entry_t *pde; 2935129198Scognet pt_entry_t *pte; 2936129198Scognet 2937135641Scognet if (!pmap_get_pde_pte(pmap, addr, &pde, &pte)) 2938135641Scognet return (FALSE); 2939159073Scognet KASSERT(pte != NULL, ("Valid mapping but no pte ?")); 2940135641Scognet if (*pte == 0) 2941135641Scognet return (TRUE); 2942135641Scognet return (FALSE); 2943129198Scognet} 2944129198Scognet 2945129198Scognet/* 2946129198Scognet * Fetch pointers to the PDE/PTE for the given pmap/VA pair. 2947129198Scognet * Returns TRUE if the mapping exists, else FALSE. 2948129198Scognet * 2949129198Scognet * NOTE: This function is only used by a couple of arm-specific modules. 2950129198Scognet * It is not safe to take any pmap locks here, since we could be right 2951129198Scognet * in the middle of debugging the pmap anyway... 2952129198Scognet * 2953129198Scognet * It is possible for this routine to return FALSE even though a valid 2954129198Scognet * mapping does exist. This is because we don't lock, so the metadata 2955129198Scognet * state may be inconsistent. 2956129198Scognet * 2957129198Scognet * NOTE: We can return a NULL *ptp in the case where the L1 pde is 2958129198Scognet * a "section" mapping. 2959129198Scognet */ 2960129198Scognetboolean_t 2961129198Scognetpmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp) 2962129198Scognet{ 2963129198Scognet struct l2_dtable *l2; 2964129198Scognet pd_entry_t *pl1pd, l1pd; 2965129198Scognet pt_entry_t *ptep; 2966129198Scognet u_short l1idx; 2967129198Scognet 2968129198Scognet if (pm->pm_l1 == NULL) 2969129198Scognet return (FALSE); 2970129198Scognet 2971129198Scognet l1idx = L1_IDX(va); 2972129198Scognet *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx]; 2973129198Scognet l1pd = *pl1pd; 2974129198Scognet 2975129198Scognet if (l1pte_section_p(l1pd)) { 2976129198Scognet *ptp = NULL; 2977129198Scognet return (TRUE); 2978129198Scognet } 2979129198Scognet 2980129198Scognet if (pm->pm_l2 == NULL) 2981129198Scognet return (FALSE); 2982129198Scognet 2983129198Scognet l2 = pm->pm_l2[L2_IDX(l1idx)]; 2984129198Scognet 2985129198Scognet if (l2 == NULL || 2986129198Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 2987129198Scognet return (FALSE); 2988129198Scognet } 2989129198Scognet 2990129198Scognet *ptp = &ptep[l2pte_index(va)]; 2991129198Scognet return (TRUE); 2992129198Scognet} 2993129198Scognet 2994129198Scognet/* 2995129198Scognet * Routine: pmap_remove_all 2996129198Scognet * Function: 2997129198Scognet * Removes this physical page from 2998129198Scognet * all physical maps in which it resides. 2999129198Scognet * Reflects back modify bits to the pager. 3000129198Scognet * 3001129198Scognet * Notes: 3002129198Scognet * Original versions of this routine were very 3003129198Scognet * inefficient because they iteratively called 3004129198Scognet * pmap_remove (slow...) 3005129198Scognet */ 3006129198Scognetvoid 3007129198Scognetpmap_remove_all(vm_page_t m) 3008129198Scognet{ 3009129198Scognet pv_entry_t pv; 3010188019Scognet pt_entry_t *ptep; 3011135641Scognet struct l2_bucket *l2b; 3012135641Scognet boolean_t flush = FALSE; 3013135641Scognet pmap_t curpm; 3014135641Scognet int flags = 0; 3015129198Scognet 3016224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3017223677Salc ("pmap_remove_all: page %p is not managed", m)); 3018135641Scognet if (TAILQ_EMPTY(&m->md.pv_list)) 3019135641Scognet return; 3020239934Salc rw_wlock(&pvh_global_lock); 3021267408Sjmg 3022267408Sjmg /* 3023267408Sjmg * XXX This call shouldn't exist. Iterating over the PV list twice, 3024267408Sjmg * once in pmap_clearbit() and again below, is both unnecessary and 3025267408Sjmg * inefficient. The below code should itself write back the cache 3026267408Sjmg * entry before it destroys the mapping. 3027267408Sjmg */ 3028267408Sjmg pmap_clearbit(m, PVF_WRITE); 3029135641Scognet curpm = vmspace_pmap(curproc->p_vmspace); 3030129198Scognet while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3031135641Scognet if (flush == FALSE && (pv->pv_pmap == curpm || 3032295042Sskra pv->pv_pmap == kernel_pmap)) 3033135641Scognet flush = TRUE; 3034193712Sraj 3035159352Salc PMAP_LOCK(pv->pv_pmap); 3036193712Sraj /* 3037267408Sjmg * Cached contents were written-back in pmap_clearbit(), 3038193712Sraj * but we still have to invalidate the cache entry to make 3039193712Sraj * sure stale data are not retrieved when another page will be 3040193712Sraj * mapped under this virtual address. 3041193712Sraj */ 3042193712Sraj if (pmap_is_current(pv->pv_pmap)) { 3043193712Sraj cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE); 3044203637Sraj if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va)) 3045203637Sraj cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE); 3046193712Sraj } 3047193712Sraj 3048194459Sthompsa if (pv->pv_flags & PVF_UNMAN) { 3049194459Sthompsa /* remove the pv entry, but do not remove the mapping 3050194459Sthompsa * and remember this is a kernel mapped page 3051194459Sthompsa */ 3052194459Sthompsa m->md.pv_kva = pv->pv_va; 3053194459Sthompsa } else { 3054194459Sthompsa /* remove the mapping and pv entry */ 3055194459Sthompsa l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va); 3056194459Sthompsa KASSERT(l2b != NULL, ("No l2 bucket")); 3057194459Sthompsa ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)]; 3058194459Sthompsa *ptep = 0; 3059194459Sthompsa PTE_SYNC_CURRENT(pv->pv_pmap, ptep); 3060194459Sthompsa pmap_free_l2_bucket(pv->pv_pmap, l2b, 1); 3061194459Sthompsa pv->pv_pmap->pm_stats.resident_count--; 3062194459Sthompsa flags |= pv->pv_flags; 3063194459Sthompsa } 3064135641Scognet pmap_nuke_pv(m, pv->pv_pmap, pv); 3065159352Salc PMAP_UNLOCK(pv->pv_pmap); 3066129198Scognet pmap_free_pv_entry(pv); 3067129198Scognet } 3068129198Scognet 3069135641Scognet if (flush) { 3070135641Scognet if (PV_BEEN_EXECD(flags)) 3071135641Scognet pmap_tlb_flushID(curpm); 3072135641Scognet else 3073135641Scognet pmap_tlb_flushD(curpm); 3074135641Scognet } 3075225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3076239934Salc rw_wunlock(&pvh_global_lock); 3077129198Scognet} 3078129198Scognet 3079129198Scognet 3080129198Scognet/* 3081129198Scognet * Set the physical protection on the 3082129198Scognet * specified range of this map as requested. 3083129198Scognet */ 3084129198Scognetvoid 3085129198Scognetpmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3086129198Scognet{ 3087129198Scognet struct l2_bucket *l2b; 3088129198Scognet pt_entry_t *ptep, pte; 3089129198Scognet vm_offset_t next_bucket; 3090129198Scognet u_int flags; 3091129198Scognet int flush; 3092129198Scognet 3093183838Sraj CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x", 3094183838Sraj pm, sva, eva, prot); 3095183838Sraj 3096129198Scognet if ((prot & VM_PROT_READ) == 0) { 3097129198Scognet pmap_remove(pm, sva, eva); 3098129198Scognet return; 3099129198Scognet } 3100129198Scognet 3101129198Scognet if (prot & VM_PROT_WRITE) { 3102129198Scognet /* 3103129198Scognet * If this is a read->write transition, just ignore it and let 3104135641Scognet * vm_fault() take care of it later. 3105129198Scognet */ 3106129198Scognet return; 3107129198Scognet } 3108129198Scognet 3109239934Salc rw_wlock(&pvh_global_lock); 3110159352Salc PMAP_LOCK(pm); 3111129198Scognet 3112129198Scognet /* 3113129198Scognet * OK, at this point, we know we're doing write-protect operation. 3114129198Scognet * If the pmap is active, write-back the range. 3115129198Scognet */ 3116129198Scognet pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE); 3117129198Scognet 3118129198Scognet flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1; 3119129198Scognet flags = 0; 3120129198Scognet 3121129198Scognet while (sva < eva) { 3122129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3123129198Scognet if (next_bucket > eva) 3124129198Scognet next_bucket = eva; 3125129198Scognet 3126129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3127129198Scognet if (l2b == NULL) { 3128129198Scognet sva = next_bucket; 3129129198Scognet continue; 3130129198Scognet } 3131129198Scognet 3132129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3133129198Scognet 3134129198Scognet while (sva < next_bucket) { 3135129198Scognet if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) { 3136129198Scognet struct vm_page *pg; 3137129198Scognet u_int f; 3138129198Scognet 3139129198Scognet pg = PHYS_TO_VM_PAGE(l2pte_pa(pte)); 3140129198Scognet pte &= ~L2_S_PROT_W; 3141129198Scognet *ptep = pte; 3142129198Scognet PTE_SYNC(ptep); 3143129198Scognet 3144239268Sgonzo if (!(pg->oflags & VPO_UNMANAGED)) { 3145239268Sgonzo f = pmap_modify_pv(pg, pm, sva, 3146239268Sgonzo PVF_WRITE, 0); 3147239268Sgonzo if (f & PVF_WRITE) 3148224049Smarcel vm_page_dirty(pg); 3149129198Scognet } else 3150239268Sgonzo f = 0; 3151129198Scognet 3152129198Scognet if (flush >= 0) { 3153129198Scognet flush++; 3154129198Scognet flags |= f; 3155129198Scognet } else 3156129198Scognet if (PV_BEEN_EXECD(f)) 3157129198Scognet pmap_tlb_flushID_SE(pm, sva); 3158129198Scognet else 3159129198Scognet if (PV_BEEN_REFD(f)) 3160129198Scognet pmap_tlb_flushD_SE(pm, sva); 3161129198Scognet } 3162129198Scognet 3163129198Scognet sva += PAGE_SIZE; 3164129198Scognet ptep++; 3165129198Scognet } 3166129198Scognet } 3167129198Scognet 3168129198Scognet 3169129198Scognet if (flush) { 3170129198Scognet if (PV_BEEN_EXECD(flags)) 3171129198Scognet pmap_tlb_flushID(pm); 3172129198Scognet else 3173129198Scognet if (PV_BEEN_REFD(flags)) 3174129198Scognet pmap_tlb_flushD(pm); 3175129198Scognet } 3176239934Salc rw_wunlock(&pvh_global_lock); 3177129198Scognet 3178159352Salc PMAP_UNLOCK(pm); 3179129198Scognet} 3180129198Scognet 3181129198Scognet 3182129198Scognet/* 3183129198Scognet * Insert the given physical page (p) at 3184129198Scognet * the specified virtual address (v) in the 3185129198Scognet * target physical map with the protection requested. 3186129198Scognet * 3187129198Scognet * If specified, the page will be wired down, meaning 3188129198Scognet * that the related pte can not be reclaimed. 3189129198Scognet * 3190129198Scognet * NB: This is the only routine which MAY NOT lazy-evaluate 3191129198Scognet * or lose information. That is, this routine must actually 3192129198Scognet * insert this page into the given map NOW. 3193129198Scognet */ 3194135641Scognet 3195269728Skibint 3196269728Skibpmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3197269728Skib u_int flags, int8_t psind __unused) 3198129198Scognet{ 3199269728Skib int rv; 3200159127Salc 3201239934Salc rw_wlock(&pvh_global_lock); 3202159352Salc PMAP_LOCK(pmap); 3203269728Skib rv = pmap_enter_locked(pmap, va, m, prot, flags); 3204239934Salc rw_wunlock(&pvh_global_lock); 3205159352Salc PMAP_UNLOCK(pmap); 3206269728Skib return (rv); 3207159127Salc} 3208159127Salc 3209159127Salc/* 3210240803Salc * The pvh global and pmap locks must be held. 3211159127Salc */ 3212269728Skibstatic int 3213159127Salcpmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 3214269728Skib u_int flags) 3215159127Salc{ 3216135641Scognet struct l2_bucket *l2b = NULL; 3217129198Scognet struct vm_page *opg; 3218144760Scognet struct pv_entry *pve = NULL; 3219129198Scognet pt_entry_t *ptep, npte, opte; 3220129198Scognet u_int nflags; 3221129198Scognet u_int oflags; 3222129198Scognet vm_paddr_t pa; 3223129198Scognet 3224159325Salc PMAP_ASSERT_LOCKED(pmap); 3225239934Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 3226129198Scognet if (va == vector_page) { 3227129198Scognet pa = systempage.pv_pa; 3228129198Scognet m = NULL; 3229208688Salc } else { 3230269728Skib if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 3231269728Skib VM_OBJECT_ASSERT_LOCKED(m->object); 3232129198Scognet pa = VM_PAGE_TO_PHYS(m); 3233208688Salc } 3234129198Scognet nflags = 0; 3235129198Scognet if (prot & VM_PROT_WRITE) 3236129198Scognet nflags |= PVF_WRITE; 3237129198Scognet if (prot & VM_PROT_EXECUTE) 3238129198Scognet nflags |= PVF_EXEC; 3239269728Skib if ((flags & PMAP_ENTER_WIRED) != 0) 3240129198Scognet nflags |= PVF_WIRED; 3241129198Scognet PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, " 3242269728Skib "flags = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, flags)); 3243236991Simp 3244295042Sskra if (pmap == kernel_pmap) { 3245129198Scognet l2b = pmap_get_l2_bucket(pmap, va); 3246135641Scognet if (l2b == NULL) 3247135641Scognet l2b = pmap_grow_l2_bucket(pmap, va); 3248160260Scognet } else { 3249160260Scognetdo_l2b_alloc: 3250129198Scognet l2b = pmap_alloc_l2_bucket(pmap, va); 3251160260Scognet if (l2b == NULL) { 3252269728Skib if ((flags & PMAP_ENTER_NOSLEEP) == 0) { 3253160260Scognet PMAP_UNLOCK(pmap); 3254239934Salc rw_wunlock(&pvh_global_lock); 3255160260Scognet VM_WAIT; 3256239934Salc rw_wlock(&pvh_global_lock); 3257160260Scognet PMAP_LOCK(pmap); 3258160260Scognet goto do_l2b_alloc; 3259160260Scognet } 3260269728Skib return (KERN_RESOURCE_SHORTAGE); 3261160260Scognet } 3262160260Scognet } 3263160260Scognet 3264129198Scognet ptep = &l2b->l2b_kva[l2pte_index(va)]; 3265236991Simp 3266135641Scognet opte = *ptep; 3267129198Scognet npte = pa; 3268129198Scognet oflags = 0; 3269129198Scognet if (opte) { 3270129198Scognet /* 3271129198Scognet * There is already a mapping at this address. 3272129198Scognet * If the physical address is different, lookup the 3273129198Scognet * vm_page. 3274129198Scognet */ 3275129198Scognet if (l2pte_pa(opte) != pa) 3276129198Scognet opg = PHYS_TO_VM_PAGE(l2pte_pa(opte)); 3277129198Scognet else 3278129198Scognet opg = m; 3279129198Scognet } else 3280129198Scognet opg = NULL; 3281129198Scognet 3282135641Scognet if ((prot & (VM_PROT_ALL)) || 3283135641Scognet (!m || m->md.pvh_attrs & PVF_REF)) { 3284129198Scognet /* 3285135641Scognet * - The access type indicates that we don't need 3286135641Scognet * to do referenced emulation. 3287135641Scognet * OR 3288135641Scognet * - The physical page has already been referenced 3289135641Scognet * so no need to re-do referenced emulation here. 3290129198Scognet */ 3291135641Scognet npte |= L2_S_PROTO; 3292283366Sandrew 3293135641Scognet nflags |= PVF_REF; 3294283366Sandrew 3295144760Scognet if (m && ((prot & VM_PROT_WRITE) != 0 || 3296144760Scognet (m->md.pvh_attrs & PVF_MOD))) { 3297129198Scognet /* 3298135641Scognet * This is a writable mapping, and the 3299135641Scognet * page's mod state indicates it has 3300135641Scognet * already been modified. Make it 3301135641Scognet * writable from the outset. 3302129198Scognet */ 3303135641Scognet nflags |= PVF_MOD; 3304157970Scognet if (!(m->md.pvh_attrs & PVF_MOD)) 3305144760Scognet vm_page_dirty(m); 3306129198Scognet } 3307144760Scognet if (m && opte) 3308225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 3309135641Scognet } else { 3310135641Scognet /* 3311135641Scognet * Need to do page referenced emulation. 3312135641Scognet */ 3313135641Scognet npte |= L2_TYPE_INV; 3314135641Scognet } 3315283366Sandrew 3316164229Salc if (prot & VM_PROT_WRITE) { 3317135641Scognet npte |= L2_S_PROT_W; 3318208846Salc if (m != NULL && 3319224746Skib (m->oflags & VPO_UNMANAGED) == 0) 3320225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 3321164229Salc } 3322244574Scognet if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE) 3323244414Scognet npte |= pte_l2_s_cache_mode; 3324135641Scognet if (m && m == opg) { 3325135641Scognet /* 3326135641Scognet * We're changing the attrs of an existing mapping. 3327135641Scognet */ 3328135641Scognet oflags = pmap_modify_pv(m, pmap, va, 3329135641Scognet PVF_WRITE | PVF_EXEC | PVF_WIRED | 3330135641Scognet PVF_MOD | PVF_REF, nflags); 3331283366Sandrew 3332135641Scognet /* 3333135641Scognet * We may need to flush the cache if we're 3334135641Scognet * doing rw-ro... 3335135641Scognet */ 3336135641Scognet if (pmap_is_current(pmap) && 3337135641Scognet (oflags & PVF_NC) == 0 && 3338183838Sraj (opte & L2_S_PROT_W) != 0 && 3339203637Sraj (prot & VM_PROT_WRITE) == 0 && 3340203637Sraj (opte & L2_TYPE_MASK) != L2_TYPE_INV) { 3341135641Scognet cpu_dcache_wb_range(va, PAGE_SIZE); 3342203637Sraj cpu_l2cache_wb_range(va, PAGE_SIZE); 3343183838Sraj } 3344129198Scognet } else { 3345129198Scognet /* 3346135641Scognet * New mapping, or changing the backing page 3347135641Scognet * of an existing mapping. 3348129198Scognet */ 3349129198Scognet if (opg) { 3350129198Scognet /* 3351135641Scognet * Replacing an existing mapping with a new one. 3352135641Scognet * It is part of our managed memory so we 3353135641Scognet * must remove it from the PV list 3354129198Scognet */ 3355194459Sthompsa if ((pve = pmap_remove_pv(opg, pmap, va))) { 3356194459Sthompsa 3357194459Sthompsa /* note for patch: the oflags/invalidation was moved 3358194459Sthompsa * because PG_FICTITIOUS pages could free the pve 3359194459Sthompsa */ 3360194459Sthompsa oflags = pve->pv_flags; 3361135641Scognet /* 3362135641Scognet * If the old mapping was valid (ref/mod 3363135641Scognet * emulation creates 'invalid' mappings 3364135641Scognet * initially) then make sure to frob 3365135641Scognet * the cache. 3366135641Scognet */ 3367194459Sthompsa if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) { 3368135641Scognet if (PV_BEEN_EXECD(oflags)) { 3369129198Scognet pmap_idcache_wbinv_range(pmap, va, 3370129198Scognet PAGE_SIZE); 3371135641Scognet } else 3372135641Scognet if (PV_BEEN_REFD(oflags)) { 3373135641Scognet pmap_dcache_wb_range(pmap, va, 3374135641Scognet PAGE_SIZE, TRUE, 3375135641Scognet (oflags & PVF_WRITE) == 0); 3376135641Scognet } 3377194459Sthompsa } 3378194459Sthompsa 3379194459Sthompsa /* free/allocate a pv_entry for UNMANAGED pages if 3380194459Sthompsa * this physical page is not/is already mapped. 3381194459Sthompsa */ 3382194459Sthompsa 3383224746Skib if (m && (m->oflags & VPO_UNMANAGED) && 3384194459Sthompsa !m->md.pv_kva && 3385224746Skib TAILQ_EMPTY(&m->md.pv_list)) { 3386194459Sthompsa pmap_free_pv_entry(pve); 3387194459Sthompsa pve = NULL; 3388194459Sthompsa } 3389224746Skib } else if (m && 3390224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3391194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3392194459Sthompsa pve = pmap_get_pv_entry(); 3393224746Skib } else if (m && 3394224746Skib (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva || 3395194459Sthompsa !TAILQ_EMPTY(&m->md.pv_list))) 3396194459Sthompsa pve = pmap_get_pv_entry(); 3397194459Sthompsa 3398224746Skib if (m) { 3399224746Skib if ((m->oflags & VPO_UNMANAGED)) { 3400194459Sthompsa if (!TAILQ_EMPTY(&m->md.pv_list) || 3401224746Skib m->md.pv_kva) { 3402194459Sthompsa KASSERT(pve != NULL, ("No pv")); 3403194459Sthompsa nflags |= PVF_UNMAN; 3404194459Sthompsa pmap_enter_pv(m, pve, pmap, va, nflags); 3405194459Sthompsa } else 3406194459Sthompsa m->md.pv_kva = va; 3407194459Sthompsa } else { 3408224746Skib KASSERT(va < kmi.clean_sva || 3409224746Skib va >= kmi.clean_eva, 3410224746Skib ("pmap_enter: managed mapping within the clean submap")); 3411224746Skib KASSERT(pve != NULL, ("No pv")); 3412224746Skib pmap_enter_pv(m, pve, pmap, va, nflags); 3413129198Scognet } 3414157970Scognet } 3415129198Scognet } 3416129198Scognet /* 3417129198Scognet * Make sure userland mappings get the right permissions 3418129198Scognet */ 3419295042Sskra if (pmap != kernel_pmap && va != vector_page) { 3420129198Scognet npte |= L2_S_PROT_U; 3421129198Scognet } 3422129198Scognet 3423129198Scognet /* 3424129198Scognet * Keep the stats up to date 3425129198Scognet */ 3426129198Scognet if (opte == 0) { 3427129198Scognet l2b->l2b_occupancy++; 3428129198Scognet pmap->pm_stats.resident_count++; 3429236991Simp } 3430129198Scognet 3431129198Scognet /* 3432129198Scognet * If this is just a wiring change, the two PTEs will be 3433129198Scognet * identical, so there's no need to update the page table. 3434129198Scognet */ 3435129198Scognet if (npte != opte) { 3436135641Scognet boolean_t is_cached = pmap_is_current(pmap); 3437129198Scognet 3438129198Scognet *ptep = npte; 3439129198Scognet if (is_cached) { 3440129198Scognet /* 3441129198Scognet * We only need to frob the cache/tlb if this pmap 3442129198Scognet * is current 3443129198Scognet */ 3444129198Scognet PTE_SYNC(ptep); 3445236991Simp if (L1_IDX(va) != L1_IDX(vector_page) && 3446129198Scognet l2pte_valid(npte)) { 3447129198Scognet /* 3448129198Scognet * This mapping is likely to be accessed as 3449129198Scognet * soon as we return to userland. Fix up the 3450129198Scognet * L1 entry to avoid taking another 3451129198Scognet * page/domain fault. 3452129198Scognet */ 3453129198Scognet pd_entry_t *pl1pd, l1pd; 3454129198Scognet 3455129198Scognet pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)]; 3456129198Scognet l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) | 3457144760Scognet L1_C_PROTO; 3458129198Scognet if (*pl1pd != l1pd) { 3459129198Scognet *pl1pd = l1pd; 3460129198Scognet PTE_SYNC(pl1pd); 3461129198Scognet } 3462129198Scognet } 3463129198Scognet } 3464129198Scognet 3465129198Scognet if (PV_BEEN_EXECD(oflags)) 3466129198Scognet pmap_tlb_flushID_SE(pmap, va); 3467135641Scognet else if (PV_BEEN_REFD(oflags)) 3468129198Scognet pmap_tlb_flushD_SE(pmap, va); 3469129198Scognet 3470129198Scognet 3471157025Scognet if (m) 3472175840Scognet pmap_fix_cache(m, pmap, va); 3473129198Scognet } 3474269728Skib return (KERN_SUCCESS); 3475129198Scognet} 3476129198Scognet 3477129198Scognet/* 3478159303Salc * Maps a sequence of resident pages belonging to the same object. 3479159303Salc * The sequence begins with the given page m_start. This page is 3480159303Salc * mapped at the given virtual address start. Each subsequent page is 3481159303Salc * mapped at a virtual address that is offset from start by the same 3482159303Salc * amount as the page is offset from m_start within the object. The 3483159303Salc * last page in the sequence is the page with the largest offset from 3484159303Salc * m_start that can be mapped at a virtual address less than the given 3485159303Salc * virtual address end. Not every virtual page between start and end 3486159303Salc * is mapped; only those for which a resident page exists with the 3487159303Salc * corresponding offset from m_start are mapped. 3488159303Salc */ 3489159303Salcvoid 3490159303Salcpmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3491159303Salc vm_page_t m_start, vm_prot_t prot) 3492159303Salc{ 3493159303Salc vm_page_t m; 3494159303Salc vm_pindex_t diff, psize; 3495159303Salc 3496250884Sattilio VM_OBJECT_ASSERT_LOCKED(m_start->object); 3497250884Sattilio 3498159303Salc psize = atop(end - start); 3499159303Salc m = m_start; 3500239934Salc rw_wlock(&pvh_global_lock); 3501159325Salc PMAP_LOCK(pmap); 3502159303Salc while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3503159303Salc pmap_enter_locked(pmap, start + ptoa(diff), m, prot & 3504269728Skib (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP); 3505159303Salc m = TAILQ_NEXT(m, listq); 3506159303Salc } 3507239934Salc rw_wunlock(&pvh_global_lock); 3508159325Salc PMAP_UNLOCK(pmap); 3509159303Salc} 3510159303Salc 3511159303Salc/* 3512129198Scognet * this code makes some *MAJOR* assumptions: 3513129198Scognet * 1. Current pmap & pmap exists. 3514129198Scognet * 2. Not wired. 3515129198Scognet * 3. Read access. 3516129198Scognet * 4. No page table pages. 3517129198Scognet * but is *MUCH* faster than pmap_enter... 3518129198Scognet */ 3519129198Scognet 3520159627Supsvoid 3521159627Supspmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3522129198Scognet{ 3523138897Salc 3524239934Salc rw_wlock(&pvh_global_lock); 3525159325Salc PMAP_LOCK(pmap); 3526159127Salc pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 3527269728Skib PMAP_ENTER_NOSLEEP); 3528239934Salc rw_wunlock(&pvh_global_lock); 3529159325Salc PMAP_UNLOCK(pmap); 3530129198Scognet} 3531129198Scognet 3532129198Scognet/* 3533268776Salc * Clear the wired attribute from the mappings for the specified range of 3534268776Salc * addresses in the given pmap. Every valid mapping within that range 3535268776Salc * must have the wired attribute set. In contrast, invalid mappings 3536268776Salc * cannot have the wired attribute set, so they are ignored. 3537268776Salc * 3538268776Salc * XXX Wired mappings of unmanaged pages cannot be counted by this pmap 3539268776Salc * implementation. 3540268776Salc */ 3541268776Salcvoid 3542268776Salcpmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3543268776Salc{ 3544268776Salc struct l2_bucket *l2b; 3545268776Salc pt_entry_t *ptep, pte; 3546268776Salc pv_entry_t pv; 3547268776Salc vm_offset_t next_bucket; 3548268776Salc vm_page_t m; 3549283366Sandrew 3550268776Salc rw_wlock(&pvh_global_lock); 3551268776Salc PMAP_LOCK(pmap); 3552268776Salc while (sva < eva) { 3553268776Salc next_bucket = L2_NEXT_BUCKET(sva); 3554268776Salc if (next_bucket > eva) 3555268776Salc next_bucket = eva; 3556268776Salc l2b = pmap_get_l2_bucket(pmap, sva); 3557268776Salc if (l2b == NULL) { 3558268776Salc sva = next_bucket; 3559268776Salc continue; 3560268776Salc } 3561268776Salc for (ptep = &l2b->l2b_kva[l2pte_index(sva)]; sva < next_bucket; 3562268776Salc sva += PAGE_SIZE, ptep++) { 3563268776Salc if ((pte = *ptep) == 0 || 3564268776Salc (m = PHYS_TO_VM_PAGE(l2pte_pa(pte))) == NULL || 3565268776Salc (m->oflags & VPO_UNMANAGED) != 0) 3566268776Salc continue; 3567268776Salc pv = pmap_find_pv(m, pmap, sva); 3568268776Salc if ((pv->pv_flags & PVF_WIRED) == 0) 3569268776Salc panic("pmap_unwire: pv %p isn't wired", pv); 3570268776Salc pv->pv_flags &= ~PVF_WIRED; 3571268776Salc pmap->pm_stats.wired_count--; 3572268776Salc } 3573268776Salc } 3574268776Salc rw_wunlock(&pvh_global_lock); 3575268776Salc PMAP_UNLOCK(pmap); 3576268776Salc} 3577129198Scognet 3578268776Salc 3579129198Scognet/* 3580129198Scognet * Copy the range specified by src_addr/len 3581129198Scognet * from the source map to the range dst_addr/len 3582129198Scognet * in the destination map. 3583129198Scognet * 3584129198Scognet * This routine is only advisory and need not do anything. 3585129198Scognet */ 3586129198Scognetvoid 3587129198Scognetpmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 3588129198Scognet vm_size_t len, vm_offset_t src_addr) 3589129198Scognet{ 3590129198Scognet} 3591129198Scognet 3592129198Scognet 3593129198Scognet/* 3594129198Scognet * Routine: pmap_extract 3595129198Scognet * Function: 3596129198Scognet * Extract the physical page address associated 3597129198Scognet * with the given map/virtual_address pair. 3598129198Scognet */ 3599131658Salcvm_paddr_t 3600240983Salcpmap_extract(pmap_t pmap, vm_offset_t va) 3601129198Scognet{ 3602240983Salc vm_paddr_t pa; 3603240983Salc 3604240983Salc PMAP_LOCK(pmap); 3605240983Salc pa = pmap_extract_locked(pmap, va); 3606240983Salc PMAP_UNLOCK(pmap); 3607240983Salc return (pa); 3608240983Salc} 3609240983Salc 3610240983Salcstatic vm_paddr_t 3611240983Salcpmap_extract_locked(pmap_t pmap, vm_offset_t va) 3612240983Salc{ 3613129198Scognet struct l2_dtable *l2; 3614159450Salc pd_entry_t l1pd; 3615129198Scognet pt_entry_t *ptep, pte; 3616129198Scognet vm_paddr_t pa; 3617129198Scognet u_int l1idx; 3618240983Salc 3619240983Salc if (pmap != kernel_pmap) 3620240983Salc PMAP_ASSERT_LOCKED(pmap); 3621129198Scognet l1idx = L1_IDX(va); 3622240983Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3623129198Scognet if (l1pte_section_p(l1pd)) { 3624129198Scognet /* 3625240983Salc * These should only happen for the kernel pmap. 3626129198Scognet */ 3627240983Salc KASSERT(pmap == kernel_pmap, ("unexpected section")); 3628171620Scognet /* XXX: what to do about the bits > 32 ? */ 3629236991Simp if (l1pd & L1_S_SUPERSEC) 3630171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3631171620Scognet else 3632171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3633129198Scognet } else { 3634129198Scognet /* 3635129198Scognet * Note that we can't rely on the validity of the L1 3636129198Scognet * descriptor as an indication that a mapping exists. 3637129198Scognet * We have to look it up in the L2 dtable. 3638129198Scognet */ 3639240983Salc l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3640129198Scognet if (l2 == NULL || 3641240983Salc (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) 3642129198Scognet return (0); 3643240983Salc pte = ptep[l2pte_index(va)]; 3644240983Salc if (pte == 0) 3645129198Scognet return (0); 3646294789Sskra if ((pte & L2_TYPE_MASK) == L2_TYPE_L) 3647129198Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3648294789Sskra else 3649129198Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3650129198Scognet } 3651129198Scognet return (pa); 3652129198Scognet} 3653129198Scognet 3654133453Salc/* 3655133453Salc * Atomically extract and hold the physical page with the given 3656133453Salc * pmap and virtual address pair if that mapping permits the given 3657133453Salc * protection. 3658133453Salc * 3659133453Salc */ 3660129198Scognetvm_page_t 3661129198Scognetpmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 3662129198Scognet{ 3663135641Scognet struct l2_dtable *l2; 3664159378Salc pd_entry_t l1pd; 3665135641Scognet pt_entry_t *ptep, pte; 3666207410Skmacy vm_paddr_t pa, paddr; 3667135641Scognet vm_page_t m = NULL; 3668135641Scognet u_int l1idx; 3669135641Scognet l1idx = L1_IDX(va); 3670207410Skmacy paddr = 0; 3671129198Scognet 3672159325Salc PMAP_LOCK(pmap); 3673207410Skmacyretry: 3674159378Salc l1pd = pmap->pm_l1->l1_kva[l1idx]; 3675135641Scognet if (l1pte_section_p(l1pd)) { 3676135641Scognet /* 3677295042Sskra * These should only happen for kernel_pmap 3678135641Scognet */ 3679295042Sskra KASSERT(pmap == kernel_pmap, ("huh")); 3680171620Scognet /* XXX: what to do about the bits > 32 ? */ 3681236991Simp if (l1pd & L1_S_SUPERSEC) 3682171620Scognet pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3683171620Scognet else 3684171620Scognet pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3685207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3686207410Skmacy goto retry; 3687135641Scognet if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3688135641Scognet m = PHYS_TO_VM_PAGE(pa); 3689135641Scognet vm_page_hold(m); 3690135641Scognet } 3691283366Sandrew 3692135641Scognet } else { 3693135641Scognet /* 3694135641Scognet * Note that we can't rely on the validity of the L1 3695135641Scognet * descriptor as an indication that a mapping exists. 3696135641Scognet * We have to look it up in the L2 dtable. 3697135641Scognet */ 3698135641Scognet l2 = pmap->pm_l2[L2_IDX(l1idx)]; 3699135641Scognet 3700135641Scognet if (l2 == NULL || 3701135641Scognet (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3702159325Salc PMAP_UNLOCK(pmap); 3703135641Scognet return (NULL); 3704135641Scognet } 3705135641Scognet 3706135641Scognet ptep = &ptep[l2pte_index(va)]; 3707135641Scognet pte = *ptep; 3708135641Scognet 3709150865Scognet if (pte == 0) { 3710159325Salc PMAP_UNLOCK(pmap); 3711135641Scognet return (NULL); 3712150865Scognet } 3713135641Scognet if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) { 3714294789Sskra if ((pte & L2_TYPE_MASK) == L2_TYPE_L) 3715135641Scognet pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3716294789Sskra else 3717135641Scognet pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3718207410Skmacy if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr)) 3719283366Sandrew goto retry; 3720135641Scognet m = PHYS_TO_VM_PAGE(pa); 3721135641Scognet vm_page_hold(m); 3722135641Scognet } 3723129198Scognet } 3724135641Scognet 3725159325Salc PMAP_UNLOCK(pmap); 3726207410Skmacy PA_UNLOCK_COND(paddr); 3727129198Scognet return (m); 3728129198Scognet} 3729129198Scognet 3730294722Sskravm_paddr_t 3731294722Sskrapmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p) 3732294722Sskra{ 3733294722Sskra struct l2_dtable *l2; 3734294722Sskra pd_entry_t l1pd; 3735294722Sskra pt_entry_t *ptep, pte; 3736294722Sskra vm_paddr_t pa; 3737294722Sskra u_int l1idx; 3738294722Sskra 3739294722Sskra l1idx = L1_IDX(va); 3740294722Sskra l1pd = kernel_pmap->pm_l1->l1_kva[l1idx]; 3741294722Sskra if (l1pte_section_p(l1pd)) { 3742294722Sskra if (l1pd & L1_S_SUPERSEC) 3743294722Sskra pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET); 3744294722Sskra else 3745294722Sskra pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET); 3746294722Sskra pte = L2_S_PROTO | pa | 3747294722Sskra L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE); 3748294722Sskra } else { 3749294722Sskra l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]; 3750294722Sskra if (l2 == NULL || 3751294722Sskra (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) { 3752294722Sskra pte = 0; 3753294722Sskra pa = 0; 3754294722Sskra goto out; 3755294722Sskra } 3756294722Sskra pte = ptep[l2pte_index(va)]; 3757294722Sskra if (pte == 0) { 3758294722Sskra pa = 0; 3759294722Sskra goto out; 3760294722Sskra } 3761294789Sskra if ((pte & L2_TYPE_MASK) == L2_TYPE_L) 3762294722Sskra pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET); 3763294789Sskra else 3764294722Sskra pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET); 3765294722Sskra } 3766294722Sskraout: 3767294722Sskra if (pte2p != NULL) 3768294722Sskra *pte2p = pte; 3769294722Sskra return (pa); 3770294722Sskra} 3771294722Sskra 3772129198Scognet/* 3773129198Scognet * Initialize a preallocated and zeroed pmap structure, 3774129198Scognet * such as one in a vmspace structure. 3775129198Scognet */ 3776129198Scognet 3777173361Skibint 3778129198Scognetpmap_pinit(pmap_t pmap) 3779129198Scognet{ 3780129198Scognet PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap)); 3781283366Sandrew 3782129198Scognet pmap_alloc_l1(pmap); 3783129198Scognet bzero(pmap->pm_l2, sizeof(pmap->pm_l2)); 3784129198Scognet 3785222813Sattilio CPU_ZERO(&pmap->pm_active); 3786283366Sandrew 3787144760Scognet TAILQ_INIT(&pmap->pm_pvlist); 3788129198Scognet bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 3789129198Scognet pmap->pm_stats.resident_count = 1; 3790129198Scognet if (vector_page < KERNBASE) { 3791269728Skib pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa), 3792269728Skib VM_PROT_READ, PMAP_ENTER_WIRED | VM_PROT_READ, 0); 3793236991Simp } 3794173361Skib return (1); 3795129198Scognet} 3796129198Scognet 3797129198Scognet 3798129198Scognet/*************************************************** 3799129198Scognet * page management routines. 3800129198Scognet ***************************************************/ 3801129198Scognet 3802129198Scognet 3803135641Scognetstatic void 3804129198Scognetpmap_free_pv_entry(pv_entry_t pv) 3805129198Scognet{ 3806129198Scognet pv_entry_count--; 3807129198Scognet uma_zfree(pvzone, pv); 3808129198Scognet} 3809129198Scognet 3810129198Scognet 3811129198Scognet/* 3812129198Scognet * get a new pv_entry, allocating a block from the system 3813129198Scognet * when needed. 3814129198Scognet * the memory allocation is performed bypassing the malloc code 3815129198Scognet * because of the possibility of allocations at interrupt time. 3816129198Scognet */ 3817129198Scognetstatic pv_entry_t 3818129198Scognetpmap_get_pv_entry(void) 3819129198Scognet{ 3820129198Scognet pv_entry_t ret_value; 3821283366Sandrew 3822129198Scognet pv_entry_count++; 3823159500Salc if (pv_entry_count > pv_entry_high_water) 3824159500Salc pagedaemon_wakeup(); 3825129198Scognet ret_value = uma_zalloc(pvzone, M_NOWAIT); 3826129198Scognet return ret_value; 3827129198Scognet} 3828129198Scognet 3829129198Scognet/* 3830129198Scognet * Remove the given range of addresses from the specified map. 3831129198Scognet * 3832129198Scognet * It is assumed that the start and end are properly 3833129198Scognet * rounded to the page size. 3834129198Scognet */ 3835175840Scognet#define PMAP_REMOVE_CLEAN_LIST_SIZE 3 3836129198Scognetvoid 3837129198Scognetpmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 3838129198Scognet{ 3839129198Scognet struct l2_bucket *l2b; 3840129198Scognet vm_offset_t next_bucket; 3841129198Scognet pt_entry_t *ptep; 3842175840Scognet u_int total; 3843129198Scognet u_int mappings, is_exec, is_refd; 3844135641Scognet int flushall = 0; 3845129198Scognet 3846129198Scognet 3847129198Scognet /* 3848129198Scognet * we lock in the pmap => pv_head direction 3849129198Scognet */ 3850129198Scognet 3851239934Salc rw_wlock(&pvh_global_lock); 3852159352Salc PMAP_LOCK(pm); 3853129198Scognet total = 0; 3854129198Scognet while (sva < eva) { 3855129198Scognet /* 3856129198Scognet * Do one L2 bucket's worth at a time. 3857129198Scognet */ 3858129198Scognet next_bucket = L2_NEXT_BUCKET(sva); 3859129198Scognet if (next_bucket > eva) 3860129198Scognet next_bucket = eva; 3861129198Scognet 3862129198Scognet l2b = pmap_get_l2_bucket(pm, sva); 3863129198Scognet if (l2b == NULL) { 3864129198Scognet sva = next_bucket; 3865129198Scognet continue; 3866129198Scognet } 3867129198Scognet 3868129198Scognet ptep = &l2b->l2b_kva[l2pte_index(sva)]; 3869129198Scognet mappings = 0; 3870129198Scognet 3871129198Scognet while (sva < next_bucket) { 3872129198Scognet struct vm_page *pg; 3873129198Scognet pt_entry_t pte; 3874129198Scognet vm_paddr_t pa; 3875129198Scognet 3876129198Scognet pte = *ptep; 3877129198Scognet 3878129198Scognet if (pte == 0) { 3879129198Scognet /* 3880129198Scognet * Nothing here, move along 3881129198Scognet */ 3882129198Scognet sva += PAGE_SIZE; 3883129198Scognet ptep++; 3884129198Scognet continue; 3885129198Scognet } 3886129198Scognet 3887129198Scognet pm->pm_stats.resident_count--; 3888129198Scognet pa = l2pte_pa(pte); 3889129198Scognet is_exec = 0; 3890129198Scognet is_refd = 1; 3891129198Scognet 3892129198Scognet /* 3893129198Scognet * Update flags. In a number of circumstances, 3894129198Scognet * we could cluster a lot of these and do a 3895129198Scognet * number of sequential pages in one go. 3896129198Scognet */ 3897129198Scognet if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) { 3898129198Scognet struct pv_entry *pve; 3899159474Salc 3900129198Scognet pve = pmap_remove_pv(pg, pm, sva); 3901135641Scognet if (pve) { 3902159474Salc is_exec = PV_BEEN_EXECD(pve->pv_flags); 3903159474Salc is_refd = PV_BEEN_REFD(pve->pv_flags); 3904129198Scognet pmap_free_pv_entry(pve); 3905129198Scognet } 3906129198Scognet } 3907129198Scognet 3908175840Scognet if (l2pte_valid(pte) && pmap_is_current(pm)) { 3909175840Scognet if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) { 3910175840Scognet total++; 3911175840Scognet if (is_exec) { 3912175840Scognet cpu_idcache_wbinv_range(sva, 3913183838Sraj PAGE_SIZE); 3914183838Sraj cpu_l2cache_wbinv_range(sva, 3915183838Sraj PAGE_SIZE); 3916175840Scognet cpu_tlb_flushID_SE(sva); 3917175840Scognet } else if (is_refd) { 3918175840Scognet cpu_dcache_wbinv_range(sva, 3919183838Sraj PAGE_SIZE); 3920183838Sraj cpu_l2cache_wbinv_range(sva, 3921183838Sraj PAGE_SIZE); 3922175840Scognet cpu_tlb_flushD_SE(sva); 3923175840Scognet } 3924175840Scognet } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) { 3925175840Scognet /* flushall will also only get set for 3926175840Scognet * for a current pmap 3927175840Scognet */ 3928175840Scognet cpu_idcache_wbinv_all(); 3929183838Sraj cpu_l2cache_wbinv_all(); 3930175840Scognet flushall = 1; 3931175840Scognet total++; 3932129198Scognet } 3933129198Scognet } 3934175840Scognet *ptep = 0; 3935175840Scognet PTE_SYNC(ptep); 3936129198Scognet 3937129198Scognet sva += PAGE_SIZE; 3938129198Scognet ptep++; 3939129198Scognet mappings++; 3940129198Scognet } 3941129198Scognet 3942129198Scognet pmap_free_l2_bucket(pm, l2b, mappings); 3943129198Scognet } 3944129198Scognet 3945239934Salc rw_wunlock(&pvh_global_lock); 3946135641Scognet if (flushall) 3947135641Scognet cpu_tlb_flushID(); 3948159352Salc PMAP_UNLOCK(pm); 3949129198Scognet} 3950129198Scognet 3951129198Scognet/* 3952129198Scognet * pmap_zero_page() 3953236991Simp * 3954129198Scognet * Zero a given physical page by mapping it at a page hook point. 3955129198Scognet * In doing the zero page op, the page we zero is mapped cachable, as with 3956129198Scognet * StrongARM accesses to non-cached pages are non-burst making writing 3957129198Scognet * _any_ bulk data very slow. 3958129198Scognet */ 3959262958Sian#if ARM_MMU_GENERIC != 0 || defined(CPU_XSCALE_CORE3) 3960129198Scognetvoid 3961129198Scognetpmap_zero_page_generic(vm_paddr_t phys, int off, int size) 3962129198Scognet{ 3963161105Scognet 3964172300Scognet if (_arm_bzero && size >= _min_bzero_size && 3965150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 3966150865Scognet return; 3967129198Scognet 3968159088Scognet mtx_lock(&cmtx); 3969129198Scognet /* 3970183836Sraj * Hook in the page, zero it, invalidate the TLB as needed. 3971183836Sraj * 3972183836Sraj * Note the temporary zero-page mapping must be a non-cached page in 3973184730Sraj * order to work without corruption when write-allocate is enabled. 3974129198Scognet */ 3975183836Sraj *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE); 3976228530Sraj PTE_SYNC(cdst_pte); 3977129198Scognet cpu_tlb_flushD_SE(cdstp); 3978129198Scognet cpu_cpwait(); 3979183836Sraj if (off || size != PAGE_SIZE) 3980129198Scognet bzero((void *)(cdstp + off), size); 3981183836Sraj else 3982129198Scognet bzero_page(cdstp); 3983183836Sraj 3984159088Scognet mtx_unlock(&cmtx); 3985129198Scognet} 3986262958Sian#endif /* ARM_MMU_GENERIC != 0 */ 3987129198Scognet 3988129198Scognet#if ARM_MMU_XSCALE == 1 3989129198Scognetvoid 3990129198Scognetpmap_zero_page_xscale(vm_paddr_t phys, int off, int size) 3991129198Scognet{ 3992172713Scognet 3993172300Scognet if (_arm_bzero && size >= _min_bzero_size && 3994150865Scognet _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0) 3995150865Scognet return; 3996261642Sian 3997159088Scognet mtx_lock(&cmtx); 3998129198Scognet /* 3999129198Scognet * Hook in the page, zero it, and purge the cache for that 4000129198Scognet * zeroed page. Invalidate the TLB as needed. 4001129198Scognet */ 4002129198Scognet *cdst_pte = L2_S_PROTO | phys | 4003129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4004129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4005129198Scognet PTE_SYNC(cdst_pte); 4006129198Scognet cpu_tlb_flushD_SE(cdstp); 4007129198Scognet cpu_cpwait(); 4008135641Scognet if (off || size != PAGE_SIZE) 4009129198Scognet bzero((void *)(cdstp + off), size); 4010129198Scognet else 4011129198Scognet bzero_page(cdstp); 4012159088Scognet mtx_unlock(&cmtx); 4013129198Scognet xscale_cache_clean_minidata(); 4014129198Scognet} 4015129198Scognet 4016129198Scognet/* 4017129198Scognet * Change the PTEs for the specified kernel mappings such that they 4018129198Scognet * will use the mini data cache instead of the main data cache. 4019129198Scognet */ 4020129198Scognetvoid 4021135641Scognetpmap_use_minicache(vm_offset_t va, vm_size_t size) 4022129198Scognet{ 4023129198Scognet struct l2_bucket *l2b; 4024129198Scognet pt_entry_t *ptep, *sptep, pte; 4025129198Scognet vm_offset_t next_bucket, eva; 4026129198Scognet 4027164778Scognet#if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3) 4028129198Scognet if (xscale_use_minidata == 0) 4029129198Scognet return; 4030129198Scognet#endif 4031129198Scognet 4032135641Scognet eva = va + size; 4033129198Scognet 4034129198Scognet while (va < eva) { 4035129198Scognet next_bucket = L2_NEXT_BUCKET(va); 4036129198Scognet if (next_bucket > eva) 4037129198Scognet next_bucket = eva; 4038129198Scognet 4039295042Sskra l2b = pmap_get_l2_bucket(kernel_pmap, va); 4040129198Scognet 4041129198Scognet sptep = ptep = &l2b->l2b_kva[l2pte_index(va)]; 4042129198Scognet 4043129198Scognet while (va < next_bucket) { 4044129198Scognet pte = *ptep; 4045129198Scognet if (!l2pte_minidata(pte)) { 4046129198Scognet cpu_dcache_wbinv_range(va, PAGE_SIZE); 4047129198Scognet cpu_tlb_flushD_SE(va); 4048129198Scognet *ptep = pte & ~L2_B; 4049129198Scognet } 4050129198Scognet ptep++; 4051129198Scognet va += PAGE_SIZE; 4052129198Scognet } 4053129198Scognet PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep)); 4054129198Scognet } 4055129198Scognet cpu_cpwait(); 4056129198Scognet} 4057129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4058129198Scognet 4059129198Scognet/* 4060236991Simp * pmap_zero_page zeros the specified hardware page by mapping 4061129198Scognet * the page into KVM and using bzero to clear its contents. 4062129198Scognet */ 4063129198Scognetvoid 4064129198Scognetpmap_zero_page(vm_page_t m) 4065129198Scognet{ 4066135641Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE); 4067129198Scognet} 4068129198Scognet 4069129198Scognet 4070129198Scognet/* 4071236991Simp * pmap_zero_page_area zeros the specified hardware page by mapping 4072129198Scognet * the page into KVM and using bzero to clear its contents. 4073129198Scognet * 4074129198Scognet * off and size may not cover an area beyond a single hardware page. 4075129198Scognet */ 4076129198Scognetvoid 4077129198Scognetpmap_zero_page_area(vm_page_t m, int off, int size) 4078129198Scognet{ 4079129198Scognet 4080129198Scognet pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size); 4081129198Scognet} 4082129198Scognet 4083129198Scognet 4084129198Scognet/* 4085236991Simp * pmap_zero_page_idle zeros the specified hardware page by mapping 4086129198Scognet * the page into KVM and using bzero to clear its contents. This 4087129198Scognet * is intended to be called from the vm_pagezero process only and 4088129198Scognet * outside of Giant. 4089129198Scognet */ 4090129198Scognetvoid 4091129198Scognetpmap_zero_page_idle(vm_page_t m) 4092129198Scognet{ 4093129198Scognet 4094129198Scognet pmap_zero_page(m); 4095129198Scognet} 4096129198Scognet 4097150865Scognet#if 0 4098129198Scognet/* 4099129198Scognet * pmap_clean_page() 4100129198Scognet * 4101129198Scognet * This is a local function used to work out the best strategy to clean 4102197770Sstas * a single page referenced by its entry in the PV table. It should be used by 4103129198Scognet * pmap_copy_page, pmap_zero page and maybe some others later on. 4104129198Scognet * 4105129198Scognet * Its policy is effectively: 4106129198Scognet * o If there are no mappings, we don't bother doing anything with the cache. 4107129198Scognet * o If there is one mapping, we clean just that page. 4108129198Scognet * o If there are multiple mappings, we clean the entire cache. 4109129198Scognet * 4110129198Scognet * So that some functions can be further optimised, it returns 0 if it didn't 4111129198Scognet * clean the entire cache, or 1 if it did. 4112129198Scognet * 4113129198Scognet * XXX One bug in this routine is that if the pv_entry has a single page 4114129198Scognet * mapped at 0x00000000 a whole cache clean will be performed rather than 4115129198Scognet * just the 1 page. Since this should not occur in everyday use and if it does 4116129198Scognet * it will just result in not the most efficient clean for the page. 4117197770Sstas * 4118197770Sstas * We don't yet use this function but may want to. 4119129198Scognet */ 4120129198Scognetstatic int 4121129198Scognetpmap_clean_page(struct pv_entry *pv, boolean_t is_src) 4122129198Scognet{ 4123129198Scognet pmap_t pm, pm_to_clean = NULL; 4124129198Scognet struct pv_entry *npv; 4125129198Scognet u_int cache_needs_cleaning = 0; 4126129198Scognet u_int flags = 0; 4127129198Scognet vm_offset_t page_to_clean = 0; 4128129198Scognet 4129129198Scognet if (pv == NULL) { 4130129198Scognet /* nothing mapped in so nothing to flush */ 4131129198Scognet return (0); 4132129198Scognet } 4133129198Scognet 4134129198Scognet /* 4135129198Scognet * Since we flush the cache each time we change to a different 4136129198Scognet * user vmspace, we only need to flush the page if it is in the 4137129198Scognet * current pmap. 4138129198Scognet */ 4139135641Scognet if (curthread) 4140135641Scognet pm = vmspace_pmap(curproc->p_vmspace); 4141129198Scognet else 4142295042Sskra pm = kernel_pmap; 4143129198Scognet 4144129198Scognet for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) { 4145295042Sskra if (npv->pv_pmap == kernel_pmap || npv->pv_pmap == pm) { 4146129198Scognet flags |= npv->pv_flags; 4147129198Scognet /* 4148236991Simp * The page is mapped non-cacheable in 4149129198Scognet * this map. No need to flush the cache. 4150129198Scognet */ 4151129198Scognet if (npv->pv_flags & PVF_NC) { 4152129198Scognet#ifdef DIAGNOSTIC 4153129198Scognet if (cache_needs_cleaning) 4154129198Scognet panic("pmap_clean_page: " 4155129198Scognet "cache inconsistency"); 4156129198Scognet#endif 4157129198Scognet break; 4158129198Scognet } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0) 4159129198Scognet continue; 4160129198Scognet if (cache_needs_cleaning) { 4161129198Scognet page_to_clean = 0; 4162129198Scognet break; 4163129198Scognet } else { 4164129198Scognet page_to_clean = npv->pv_va; 4165129198Scognet pm_to_clean = npv->pv_pmap; 4166129198Scognet } 4167129198Scognet cache_needs_cleaning = 1; 4168129198Scognet } 4169129198Scognet } 4170129198Scognet if (page_to_clean) { 4171129198Scognet if (PV_BEEN_EXECD(flags)) 4172129198Scognet pmap_idcache_wbinv_range(pm_to_clean, page_to_clean, 4173129198Scognet PAGE_SIZE); 4174129198Scognet else 4175129198Scognet pmap_dcache_wb_range(pm_to_clean, page_to_clean, 4176129198Scognet PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0); 4177129198Scognet } else if (cache_needs_cleaning) { 4178129198Scognet if (PV_BEEN_EXECD(flags)) 4179129198Scognet pmap_idcache_wbinv_all(pm); 4180129198Scognet else 4181129198Scognet pmap_dcache_wbinv_all(pm); 4182129198Scognet return (1); 4183129198Scognet } 4184129198Scognet return (0); 4185129198Scognet} 4186150865Scognet#endif 4187129198Scognet 4188129198Scognet/* 4189129198Scognet * pmap_copy_page copies the specified (machine independent) 4190129198Scognet * page by mapping the page into virtual memory and using 4191129198Scognet * bcopy to copy the page, one machine dependent page at a 4192129198Scognet * time. 4193129198Scognet */ 4194129198Scognet 4195129198Scognet/* 4196129198Scognet * pmap_copy_page() 4197129198Scognet * 4198129198Scognet * Copy one physical page into another, by mapping the pages into 4199129198Scognet * hook points. The same comment regarding cachability as in 4200129198Scognet * pmap_zero_page also applies here. 4201129198Scognet */ 4202262958Sian#if ARM_MMU_GENERIC != 0 || defined (CPU_XSCALE_CORE3) 4203129198Scognetvoid 4204129198Scognetpmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst) 4205129198Scognet{ 4206151596Scognet#if 0 4207129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4208151596Scognet#endif 4209129198Scognet 4210129198Scognet /* 4211129198Scognet * Clean the source page. Hold the source page's lock for 4212129198Scognet * the duration of the copy so that no other mappings can 4213129198Scognet * be created while we have a potentially aliased mapping. 4214129198Scognet */ 4215129198Scognet#if 0 4216150865Scognet /* 4217150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4218150865Scognet * pmap_copy_page(). 4219150865Scognet */ 4220129198Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4221150865Scognet#endif 4222129198Scognet /* 4223129198Scognet * Map the pages into the page hook points, copy them, and purge 4224129198Scognet * the cache for the appropriate page. Invalidate the TLB 4225129198Scognet * as required. 4226129198Scognet */ 4227159088Scognet mtx_lock(&cmtx); 4228129198Scognet *csrc_pte = L2_S_PROTO | src | 4229129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4230129198Scognet PTE_SYNC(csrc_pte); 4231129198Scognet *cdst_pte = L2_S_PROTO | dst | 4232129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4233129198Scognet PTE_SYNC(cdst_pte); 4234129198Scognet cpu_tlb_flushD_SE(csrcp); 4235129198Scognet cpu_tlb_flushD_SE(cdstp); 4236129198Scognet cpu_cpwait(); 4237129198Scognet bcopy_page(csrcp, cdstp); 4238159088Scognet mtx_unlock(&cmtx); 4239129198Scognet cpu_dcache_inv_range(csrcp, PAGE_SIZE); 4240129198Scognet cpu_dcache_wbinv_range(cdstp, PAGE_SIZE); 4241183838Sraj cpu_l2cache_inv_range(csrcp, PAGE_SIZE); 4242183838Sraj cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE); 4243129198Scognet} 4244248280Skib 4245248280Skibvoid 4246248280Skibpmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs, 4247248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt) 4248248280Skib{ 4249248280Skib 4250248280Skib mtx_lock(&cmtx); 4251248280Skib *csrc_pte = L2_S_PROTO | a_phys | 4252248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode; 4253248280Skib PTE_SYNC(csrc_pte); 4254248280Skib *cdst_pte = L2_S_PROTO | b_phys | 4255248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode; 4256248280Skib PTE_SYNC(cdst_pte); 4257248280Skib cpu_tlb_flushD_SE(csrcp); 4258248280Skib cpu_tlb_flushD_SE(cdstp); 4259248280Skib cpu_cpwait(); 4260248280Skib bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt); 4261248280Skib mtx_unlock(&cmtx); 4262248280Skib cpu_dcache_inv_range(csrcp + a_offs, cnt); 4263248280Skib cpu_dcache_wbinv_range(cdstp + b_offs, cnt); 4264248280Skib cpu_l2cache_inv_range(csrcp + a_offs, cnt); 4265248280Skib cpu_l2cache_wbinv_range(cdstp + b_offs, cnt); 4266248280Skib} 4267262958Sian#endif /* ARM_MMU_GENERIC != 0 */ 4268129198Scognet 4269129198Scognet#if ARM_MMU_XSCALE == 1 4270129198Scognetvoid 4271129198Scognetpmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst) 4272129198Scognet{ 4273150865Scognet#if 0 4274150865Scognet /* XXX: Only needed for pmap_clean_page(), which is commented out. */ 4275129198Scognet struct vm_page *src_pg = PHYS_TO_VM_PAGE(src); 4276150865Scognet#endif 4277129198Scognet 4278129198Scognet /* 4279129198Scognet * Clean the source page. Hold the source page's lock for 4280129198Scognet * the duration of the copy so that no other mappings can 4281129198Scognet * be created while we have a potentially aliased mapping. 4282129198Scognet */ 4283150865Scognet#if 0 4284150865Scognet /* 4285150865Scognet * XXX: Not needed while we call cpu_dcache_wbinv_all() in 4286150865Scognet * pmap_copy_page(). 4287150865Scognet */ 4288130745Scognet (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE); 4289150865Scognet#endif 4290129198Scognet /* 4291129198Scognet * Map the pages into the page hook points, copy them, and purge 4292129198Scognet * the cache for the appropriate page. Invalidate the TLB 4293129198Scognet * as required. 4294129198Scognet */ 4295159088Scognet mtx_lock(&cmtx); 4296129198Scognet *csrc_pte = L2_S_PROTO | src | 4297129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4298129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4299129198Scognet PTE_SYNC(csrc_pte); 4300129198Scognet *cdst_pte = L2_S_PROTO | dst | 4301129198Scognet L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4302129198Scognet L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */ 4303129198Scognet PTE_SYNC(cdst_pte); 4304129198Scognet cpu_tlb_flushD_SE(csrcp); 4305129198Scognet cpu_tlb_flushD_SE(cdstp); 4306129198Scognet cpu_cpwait(); 4307129198Scognet bcopy_page(csrcp, cdstp); 4308159088Scognet mtx_unlock(&cmtx); 4309129198Scognet xscale_cache_clean_minidata(); 4310129198Scognet} 4311248280Skib 4312248280Skibvoid 4313248280Skibpmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs, 4314248280Skib vm_paddr_t b_phys, vm_offset_t b_offs, int cnt) 4315248280Skib{ 4316248280Skib 4317248280Skib mtx_lock(&cmtx); 4318248280Skib *csrc_pte = L2_S_PROTO | a_phys | 4319248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | 4320248280Skib L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4321248280Skib PTE_SYNC(csrc_pte); 4322248280Skib *cdst_pte = L2_S_PROTO | b_phys | 4323248280Skib L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | 4324248280Skib L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); 4325248280Skib PTE_SYNC(cdst_pte); 4326248280Skib cpu_tlb_flushD_SE(csrcp); 4327248280Skib cpu_tlb_flushD_SE(cdstp); 4328248280Skib cpu_cpwait(); 4329248280Skib bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt); 4330248280Skib mtx_unlock(&cmtx); 4331248280Skib xscale_cache_clean_minidata(); 4332248280Skib} 4333129198Scognet#endif /* ARM_MMU_XSCALE == 1 */ 4334129198Scognet 4335129198Scognetvoid 4336129198Scognetpmap_copy_page(vm_page_t src, vm_page_t dst) 4337129198Scognet{ 4338161105Scognet 4339146596Scognet cpu_dcache_wbinv_all(); 4340183838Sraj cpu_l2cache_wbinv_all(); 4341172300Scognet if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size && 4342236991Simp _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst), 4343150865Scognet (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0) 4344150865Scognet return; 4345129198Scognet pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst)); 4346129198Scognet} 4347129198Scognet 4348283014Simp/* 4349283126Simp * We have code to do unmapped I/O. However, it isn't quite right and 4350283126Simp * causes un-page-aligned I/O to devices to fail (most notably newfs 4351283126Simp * or fsck). We give up a little performance to not allow unmapped I/O 4352283126Simp * to gain stability. 4353283014Simp */ 4354283014Simpint unmapped_buf_allowed = 0; 4355248508Skib 4356248280Skibvoid 4357248280Skibpmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4358248280Skib vm_offset_t b_offset, int xfersize) 4359248280Skib{ 4360248280Skib vm_page_t a_pg, b_pg; 4361248280Skib vm_offset_t a_pg_offset, b_pg_offset; 4362248280Skib int cnt; 4363129198Scognet 4364248280Skib cpu_dcache_wbinv_all(); 4365248280Skib cpu_l2cache_wbinv_all(); 4366248280Skib while (xfersize > 0) { 4367248280Skib a_pg = ma[a_offset >> PAGE_SHIFT]; 4368248280Skib a_pg_offset = a_offset & PAGE_MASK; 4369248280Skib cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4370248280Skib b_pg = mb[b_offset >> PAGE_SHIFT]; 4371248280Skib b_pg_offset = b_offset & PAGE_MASK; 4372248280Skib cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4373248280Skib pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset, 4374248280Skib VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt); 4375248280Skib xfersize -= cnt; 4376248280Skib a_offset += cnt; 4377248280Skib b_offset += cnt; 4378248280Skib } 4379248280Skib} 4380129198Scognet 4381286296Sjahvm_offset_t 4382286296Sjahpmap_quick_enter_page(vm_page_t m) 4383286296Sjah{ 4384286296Sjah /* 4385286296Sjah * Don't bother with a PCPU pageframe, since we don't support 4386286296Sjah * SMP for anything pre-armv7. Use pmap_kenter() to ensure 4387286296Sjah * caching is handled correctly for multiple mappings of the 4388286296Sjah * same physical page. 4389286296Sjah */ 4390286296Sjah 4391286296Sjah mtx_assert(&qmap_mtx, MA_NOTOWNED); 4392286296Sjah mtx_lock(&qmap_mtx); 4393286296Sjah 4394286296Sjah pmap_kenter(qmap_addr, VM_PAGE_TO_PHYS(m)); 4395286296Sjah 4396286296Sjah return (qmap_addr); 4397286296Sjah} 4398286296Sjah 4399286296Sjahvoid 4400286296Sjahpmap_quick_remove_page(vm_offset_t addr) 4401286296Sjah{ 4402286296Sjah KASSERT(addr == qmap_addr, 4403286296Sjah ("pmap_quick_remove_page: invalid address")); 4404286296Sjah mtx_assert(&qmap_mtx, MA_OWNED); 4405286296Sjah pmap_kremove(addr); 4406286296Sjah mtx_unlock(&qmap_mtx); 4407286296Sjah} 4408286296Sjah 4409129198Scognet/* 4410129198Scognet * this routine returns true if a physical page resides 4411129198Scognet * in the given pmap. 4412129198Scognet */ 4413129198Scognetboolean_t 4414129198Scognetpmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4415129198Scognet{ 4416129198Scognet pv_entry_t pv; 4417129198Scognet int loops = 0; 4418208990Salc boolean_t rv; 4419283366Sandrew 4420224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4421208990Salc ("pmap_page_exists_quick: page %p is not managed", m)); 4422208990Salc rv = FALSE; 4423239934Salc rw_wlock(&pvh_global_lock); 4424208990Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4425129198Scognet if (pv->pv_pmap == pmap) { 4426208990Salc rv = TRUE; 4427208990Salc break; 4428129198Scognet } 4429129198Scognet loops++; 4430129198Scognet if (loops >= 16) 4431129198Scognet break; 4432129198Scognet } 4433239934Salc rw_wunlock(&pvh_global_lock); 4434208990Salc return (rv); 4435129198Scognet} 4436129198Scognet 4437173708Salc/* 4438173708Salc * pmap_page_wired_mappings: 4439173708Salc * 4440173708Salc * Return the number of managed mappings to the given physical page 4441173708Salc * that are wired. 4442173708Salc */ 4443173708Salcint 4444173708Salcpmap_page_wired_mappings(vm_page_t m) 4445173708Salc{ 4446173708Salc pv_entry_t pv; 4447173708Salc int count; 4448129198Scognet 4449173708Salc count = 0; 4450224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 4451173708Salc return (count); 4452239934Salc rw_wlock(&pvh_global_lock); 4453173708Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 4454173708Salc if ((pv->pv_flags & PVF_WIRED) != 0) 4455173708Salc count++; 4456239934Salc rw_wunlock(&pvh_global_lock); 4457173708Salc return (count); 4458173708Salc} 4459173708Salc 4460129198Scognet/* 4461255028Salc * This function is advisory. 4462255028Salc */ 4463255028Salcvoid 4464255028Salcpmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4465255028Salc{ 4466255028Salc} 4467255028Salc 4468255028Salc/* 4469129198Scognet * pmap_ts_referenced: 4470129198Scognet * 4471129198Scognet * Return the count of reference bits for a page, clearing all of them. 4472129198Scognet */ 4473129198Scognetint 4474129198Scognetpmap_ts_referenced(vm_page_t m) 4475129198Scognet{ 4476164778Scognet 4477224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4478208990Salc ("pmap_ts_referenced: page %p is not managed", m)); 4479135641Scognet return (pmap_clearbit(m, PVF_REF)); 4480129198Scognet} 4481129198Scognet 4482129198Scognet 4483129198Scognetboolean_t 4484129198Scognetpmap_is_modified(vm_page_t m) 4485129198Scognet{ 4486135641Scognet 4487224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4488208504Salc ("pmap_is_modified: page %p is not managed", m)); 4489135641Scognet if (m->md.pvh_attrs & PVF_MOD) 4490135641Scognet return (TRUE); 4491283366Sandrew 4492129198Scognet return(FALSE); 4493129198Scognet} 4494129198Scognet 4495129198Scognet 4496129198Scognet/* 4497129198Scognet * Clear the modify bits on the specified physical page. 4498129198Scognet */ 4499129198Scognetvoid 4500129198Scognetpmap_clear_modify(vm_page_t m) 4501129198Scognet{ 4502129198Scognet 4503224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4504208504Salc ("pmap_clear_modify: page %p is not managed", m)); 4505248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 4506254138Sattilio KASSERT(!vm_page_xbusied(m), 4507254138Sattilio ("pmap_clear_modify: page %p is exclusive busied", m)); 4508208504Salc 4509208504Salc /* 4510225418Skib * If the page is not PGA_WRITEABLE, then no mappings can be modified. 4511208504Salc * If the object containing the page is locked and the page is not 4512254138Sattilio * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4513208504Salc */ 4514225418Skib if ((m->aflags & PGA_WRITEABLE) == 0) 4515208504Salc return; 4516129198Scognet if (m->md.pvh_attrs & PVF_MOD) 4517129198Scognet pmap_clearbit(m, PVF_MOD); 4518129198Scognet} 4519129198Scognet 4520129198Scognet 4521129198Scognet/* 4522207155Salc * pmap_is_referenced: 4523207155Salc * 4524207155Salc * Return whether or not the specified physical page was referenced 4525207155Salc * in any physical maps. 4526207155Salc */ 4527207155Salcboolean_t 4528207155Salcpmap_is_referenced(vm_page_t m) 4529207155Salc{ 4530207155Salc 4531224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4532208574Salc ("pmap_is_referenced: page %p is not managed", m)); 4533208574Salc return ((m->md.pvh_attrs & PVF_REF) != 0); 4534207155Salc} 4535207155Salc 4536129198Scognet 4537129198Scognet/* 4538160537Salc * Clear the write and modified bits in each of the given page's mappings. 4539160537Salc */ 4540160537Salcvoid 4541160889Salcpmap_remove_write(vm_page_t m) 4542160537Salc{ 4543160537Salc 4544224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4545208175Salc ("pmap_remove_write: page %p is not managed", m)); 4546208175Salc 4547208175Salc /* 4548254138Sattilio * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4549254138Sattilio * set by another thread while the object is locked. Thus, 4550254138Sattilio * if PGA_WRITEABLE is clear, no page table entries need updating. 4551208175Salc */ 4552248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 4553254138Sattilio if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0) 4554160537Salc pmap_clearbit(m, PVF_WRITE); 4555160537Salc} 4556160537Salc 4557160537Salc 4558160537Salc/* 4559129198Scognet * perform the pmap work for mincore 4560129198Scognet */ 4561129198Scognetint 4562208504Salcpmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4563129198Scognet{ 4564235717Simp struct l2_bucket *l2b; 4565235717Simp pt_entry_t *ptep, pte; 4566235717Simp vm_paddr_t pa; 4567235717Simp vm_page_t m; 4568235717Simp int val; 4569235717Simp boolean_t managed; 4570235717Simp 4571235717Simp PMAP_LOCK(pmap); 4572235717Simpretry: 4573235717Simp l2b = pmap_get_l2_bucket(pmap, addr); 4574235717Simp if (l2b == NULL) { 4575235717Simp val = 0; 4576235717Simp goto out; 4577235717Simp } 4578235717Simp ptep = &l2b->l2b_kva[l2pte_index(addr)]; 4579235717Simp pte = *ptep; 4580235717Simp if (!l2pte_valid(pte)) { 4581235717Simp val = 0; 4582235717Simp goto out; 4583235717Simp } 4584235717Simp val = MINCORE_INCORE; 4585235717Simp if (pte & L2_S_PROT_W) 4586235717Simp val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4587235717Simp managed = false; 4588235717Simp pa = l2pte_pa(pte); 4589235717Simp m = PHYS_TO_VM_PAGE(pa); 4590235717Simp if (m != NULL && !(m->oflags & VPO_UNMANAGED)) 4591235717Simp managed = true; 4592235717Simp if (managed) { 4593235717Simp /* 4594241044Salc * The ARM pmap tries to maintain a per-mapping 4595235717Simp * reference bit. The trouble is that it's kept in 4596235717Simp * the PV entry, not the PTE, so it's costly to access 4597241044Salc * here. You would need to acquire the pvh global 4598235717Simp * lock, call pmap_find_pv(), and introduce a custom 4599235717Simp * version of vm_page_pa_tryrelock() that releases and 4600241044Salc * reacquires the pvh global lock. In the end, I 4601235717Simp * doubt it's worthwhile. This may falsely report 4602235717Simp * the given address as referenced. 4603235717Simp */ 4604235717Simp if ((m->md.pvh_attrs & PVF_REF) != 0) 4605235717Simp val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4606235717Simp } 4607235717Simp if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4608235717Simp (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 4609235717Simp /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4610235717Simp if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4611235717Simp goto retry; 4612235717Simp } else 4613235717Simpout: 4614235717Simp PA_UNLOCK_COND(*locked_pa); 4615235717Simp PMAP_UNLOCK(pmap); 4616235717Simp return (val); 4617129198Scognet} 4618129198Scognet 4619129198Scognet 4620198341Smarcelvoid 4621198341Smarcelpmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4622198341Smarcel{ 4623198341Smarcel} 4624198341Smarcel 4625198341Smarcel 4626178893Salc/* 4627178893Salc * Increase the starting virtual address of the given mapping if a 4628178893Salc * different alignment might result in more superpage mappings. 4629178893Salc */ 4630178893Salcvoid 4631178893Salcpmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4632178893Salc vm_offset_t *addr, vm_size_t size) 4633178893Salc{ 4634178893Salc} 4635129198Scognet 4636129198Scognet#define BOOTSTRAP_DEBUG 4637129198Scognet 4638129198Scognet/* 4639129198Scognet * pmap_map_section: 4640129198Scognet * 4641129198Scognet * Create a single section mapping. 4642129198Scognet */ 4643129198Scognetvoid 4644129198Scognetpmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4645129198Scognet int prot, int cache) 4646129198Scognet{ 4647129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4648129198Scognet pd_entry_t fl; 4649129198Scognet 4650129198Scognet KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2")); 4651129198Scognet 4652129198Scognet switch (cache) { 4653129198Scognet case PTE_NOCACHE: 4654129198Scognet default: 4655129198Scognet fl = 0; 4656129198Scognet break; 4657129198Scognet 4658129198Scognet case PTE_CACHE: 4659129198Scognet fl = pte_l1_s_cache_mode; 4660129198Scognet break; 4661129198Scognet 4662129198Scognet case PTE_PAGETABLE: 4663129198Scognet fl = pte_l1_s_cache_mode_pt; 4664129198Scognet break; 4665129198Scognet } 4666129198Scognet 4667129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4668129198Scognet L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL); 4669129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4670129198Scognet 4671129198Scognet} 4672129198Scognet 4673129198Scognet/* 4674129198Scognet * pmap_link_l2pt: 4675129198Scognet * 4676164079Scognet * Link the L2 page table specified by l2pv.pv_pa into the L1 4677129198Scognet * page table at the slot for "va". 4678129198Scognet */ 4679129198Scognetvoid 4680129198Scognetpmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv) 4681129198Scognet{ 4682129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt, proto; 4683129198Scognet u_int slot = va >> L1_S_SHIFT; 4684129198Scognet 4685129198Scognet proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO; 4686129198Scognet 4687236991Simp#ifdef VERBOSE_INIT_ARM 4688164079Scognet printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va); 4689164079Scognet#endif 4690164079Scognet 4691129198Scognet pde[slot + 0] = proto | (l2pv->pv_pa + 0x000); 4692164079Scognet 4693129198Scognet PTE_SYNC(&pde[slot]); 4694129198Scognet 4695129198Scognet SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list); 4696129198Scognet 4697283366Sandrew 4698129198Scognet} 4699129198Scognet 4700129198Scognet/* 4701129198Scognet * pmap_map_entry 4702129198Scognet * 4703129198Scognet * Create a single page mapping. 4704129198Scognet */ 4705129198Scognetvoid 4706129198Scognetpmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 4707129198Scognet int cache) 4708129198Scognet{ 4709129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4710129198Scognet pt_entry_t fl; 4711129198Scognet pt_entry_t *pte; 4712129198Scognet 4713129198Scognet KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin")); 4714129198Scognet 4715129198Scognet switch (cache) { 4716129198Scognet case PTE_NOCACHE: 4717129198Scognet default: 4718129198Scognet fl = 0; 4719129198Scognet break; 4720129198Scognet 4721129198Scognet case PTE_CACHE: 4722129198Scognet fl = pte_l2_s_cache_mode; 4723129198Scognet break; 4724129198Scognet 4725129198Scognet case PTE_PAGETABLE: 4726129198Scognet fl = pte_l2_s_cache_mode_pt; 4727129198Scognet break; 4728129198Scognet } 4729129198Scognet 4730129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4731129198Scognet panic("pmap_map_entry: no L2 table for VA 0x%08x", va); 4732129198Scognet 4733129198Scognet pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4734129198Scognet 4735129198Scognet if (pte == NULL) 4736129198Scognet panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va); 4737129198Scognet 4738129198Scognet pte[l2pte_index(va)] = 4739129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl; 4740129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4741129198Scognet} 4742129198Scognet 4743129198Scognet/* 4744129198Scognet * pmap_map_chunk: 4745129198Scognet * 4746129198Scognet * Map a chunk of memory using the most efficient mappings 4747129198Scognet * possible (section. large page, small page) into the 4748129198Scognet * provided L1 and L2 tables at the specified virtual address. 4749129198Scognet */ 4750129198Scognetvm_size_t 4751129198Scognetpmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, 4752129198Scognet vm_size_t size, int prot, int cache) 4753129198Scognet{ 4754129198Scognet pd_entry_t *pde = (pd_entry_t *) l1pt; 4755129198Scognet pt_entry_t *pte, f1, f2s, f2l; 4756236991Simp vm_size_t resid; 4757129198Scognet int i; 4758129198Scognet 4759298433Spfg resid = roundup2(size, PAGE_SIZE); 4760129198Scognet 4761129198Scognet if (l1pt == 0) 4762129198Scognet panic("pmap_map_chunk: no L1 table provided"); 4763129198Scognet 4764236991Simp#ifdef VERBOSE_INIT_ARM 4765159322Scognet printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x " 4766129198Scognet "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache); 4767129198Scognet#endif 4768129198Scognet 4769129198Scognet switch (cache) { 4770129198Scognet case PTE_NOCACHE: 4771129198Scognet default: 4772129198Scognet f1 = 0; 4773129198Scognet f2l = 0; 4774129198Scognet f2s = 0; 4775129198Scognet break; 4776129198Scognet 4777129198Scognet case PTE_CACHE: 4778129198Scognet f1 = pte_l1_s_cache_mode; 4779129198Scognet f2l = pte_l2_l_cache_mode; 4780129198Scognet f2s = pte_l2_s_cache_mode; 4781129198Scognet break; 4782129198Scognet 4783129198Scognet case PTE_PAGETABLE: 4784129198Scognet f1 = pte_l1_s_cache_mode_pt; 4785129198Scognet f2l = pte_l2_l_cache_mode_pt; 4786129198Scognet f2s = pte_l2_s_cache_mode_pt; 4787129198Scognet break; 4788129198Scognet } 4789129198Scognet 4790129198Scognet size = resid; 4791129198Scognet 4792129198Scognet while (resid > 0) { 4793129198Scognet /* See if we can use a section mapping. */ 4794129198Scognet if (L1_S_MAPPABLE_P(va, pa, resid)) { 4795129198Scognet#ifdef VERBOSE_INIT_ARM 4796129198Scognet printf("S"); 4797129198Scognet#endif 4798129198Scognet pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa | 4799129198Scognet L1_S_PROT(PTE_KERNEL, prot) | f1 | 4800129198Scognet L1_S_DOM(PMAP_DOMAIN_KERNEL); 4801129198Scognet PTE_SYNC(&pde[va >> L1_S_SHIFT]); 4802129198Scognet va += L1_S_SIZE; 4803129198Scognet pa += L1_S_SIZE; 4804129198Scognet resid -= L1_S_SIZE; 4805129198Scognet continue; 4806129198Scognet } 4807129198Scognet 4808129198Scognet /* 4809129198Scognet * Ok, we're going to use an L2 table. Make sure 4810129198Scognet * one is actually in the corresponding L1 slot 4811129198Scognet * for the current VA. 4812129198Scognet */ 4813129198Scognet if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C) 4814129198Scognet panic("pmap_map_chunk: no L2 table for VA 0x%08x", va); 4815129198Scognet 4816129198Scognet pte = (pt_entry_t *) kernel_pt_lookup( 4817129198Scognet pde[L1_IDX(va)] & L1_C_ADDR_MASK); 4818129198Scognet if (pte == NULL) 4819129198Scognet panic("pmap_map_chunk: can't find L2 table for VA" 4820129198Scognet "0x%08x", va); 4821129198Scognet /* See if we can use a L2 large page mapping. */ 4822129198Scognet if (L2_L_MAPPABLE_P(va, pa, resid)) { 4823129198Scognet#ifdef VERBOSE_INIT_ARM 4824129198Scognet printf("L"); 4825129198Scognet#endif 4826129198Scognet for (i = 0; i < 16; i++) { 4827129198Scognet pte[l2pte_index(va) + i] = 4828129198Scognet L2_L_PROTO | pa | 4829129198Scognet L2_L_PROT(PTE_KERNEL, prot) | f2l; 4830129198Scognet PTE_SYNC(&pte[l2pte_index(va) + i]); 4831129198Scognet } 4832129198Scognet va += L2_L_SIZE; 4833129198Scognet pa += L2_L_SIZE; 4834129198Scognet resid -= L2_L_SIZE; 4835129198Scognet continue; 4836129198Scognet } 4837129198Scognet 4838129198Scognet /* Use a small page mapping. */ 4839129198Scognet#ifdef VERBOSE_INIT_ARM 4840129198Scognet printf("P"); 4841129198Scognet#endif 4842129198Scognet pte[l2pte_index(va)] = 4843129198Scognet L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s; 4844129198Scognet PTE_SYNC(&pte[l2pte_index(va)]); 4845129198Scognet va += PAGE_SIZE; 4846129198Scognet pa += PAGE_SIZE; 4847129198Scognet resid -= PAGE_SIZE; 4848129198Scognet } 4849129198Scognet#ifdef VERBOSE_INIT_ARM 4850129198Scognet printf("\n"); 4851129198Scognet#endif 4852129198Scognet return (size); 4853129198Scognet 4854129198Scognet} 4855129198Scognet 4856135641Scognetvoid 4857244414Scognetpmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4858244414Scognet{ 4859283366Sandrew /* 4860244414Scognet * Remember the memattr in a field that gets used to set the appropriate 4861244414Scognet * bits in the PTEs as mappings are established. 4862244414Scognet */ 4863244414Scognet m->md.pv_memattr = ma; 4864244414Scognet 4865244414Scognet /* 4866244414Scognet * It appears that this function can only be called before any mappings 4867244414Scognet * for the page are established on ARM. If this ever changes, this code 4868244414Scognet * will need to walk the pv_list and make each of the existing mappings 4869244414Scognet * uncacheable, being careful to sync caches and PTEs (and maybe 4870244414Scognet * invalidate TLB?) for any current mapping it modifies. 4871244414Scognet */ 4872244414Scognet if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL) 4873244414Scognet panic("Can't change memattr on page with existing mappings"); 4874244414Scognet} 4875244414Scognet 4876244414Scognet 4877