1/*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Developed by Ben Gray <ben.r.gray@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company nor the name of the author may be used to 16 * endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32/** 33 * The ARM Cortex-A9 core can support a global timer plus a private and 34 * watchdog timer per core. This driver reserves memory and interrupt 35 * resources for accessing both timer register sets, these resources are 36 * stored globally and used to setup the timecount and eventtimer. 37 * 38 * The timecount timer uses the global 64-bit counter, whereas the 39 * per-CPU eventtimer uses the private 32-bit counters. 40 * 41 * 42 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2) 43 */ 44 45#include <sys/cdefs.h> 46__FBSDID("$FreeBSD: stable/11/sys/arm/arm/mpcore_timer.c 346551 2019-04-22 13:58:28Z ian $"); 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/bus.h> 51#include <sys/kernel.h> 52#include <sys/module.h> 53#include <sys/malloc.h> 54#include <sys/rman.h> 55#include <sys/timeet.h> 56#include <sys/timetc.h> 57#include <sys/watchdog.h> 58#include <machine/bus.h> 59#include <machine/cpu.h> 60#include <machine/intr.h> 61 62#include <dev/fdt/fdt_common.h> 63#include <dev/ofw/openfirm.h> 64#include <dev/ofw/ofw_bus.h> 65#include <dev/ofw/ofw_bus_subr.h> 66 67#include <machine/bus.h> 68 69#include <arm/arm/mpcore_timervar.h> 70 71/* Private (per-CPU) timer register map */ 72#define PRV_TIMER_LOAD 0x0000 73#define PRV_TIMER_COUNT 0x0004 74#define PRV_TIMER_CTRL 0x0008 75#define PRV_TIMER_INTR 0x000C 76 77#define PRV_TIMER_CTR_PRESCALER_SHIFT 8 78#define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 79#define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) 80#define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 81 82#define PRV_TIMER_INTR_EVENT (1UL << 0) 83 84/* Global timer register map */ 85#define GBL_TIMER_COUNT_LOW 0x0000 86#define GBL_TIMER_COUNT_HIGH 0x0004 87#define GBL_TIMER_CTRL 0x0008 88#define GBL_TIMER_INTR 0x000C 89 90#define GBL_TIMER_CTR_PRESCALER_SHIFT 8 91#define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) 92#define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) 93#define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) 94#define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) 95 96#define GBL_TIMER_INTR_EVENT (1UL << 0) 97 98struct arm_tmr_softc { 99 device_t dev; 100 int irqrid; 101 int memrid; 102 struct resource * gbl_mem; 103 struct resource * prv_mem; 104 struct resource * prv_irq; 105 uint64_t clkfreq; 106 struct eventtimer et; 107}; 108 109static struct eventtimer *arm_tmr_et; 110static struct timecounter *arm_tmr_tc; 111static uint64_t arm_tmr_freq; 112static boolean_t arm_tmr_freq_varies; 113 114#define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg) 115#define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val) 116#define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg) 117#define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val) 118 119static timecounter_get_t arm_tmr_get_timecount; 120 121static struct timecounter arm_tmr_timecount = { 122 .tc_name = "MPCore", 123 .tc_get_timecount = arm_tmr_get_timecount, 124 .tc_poll_pps = NULL, 125 .tc_counter_mask = ~0u, 126 .tc_frequency = 0, 127 .tc_quality = 800, 128}; 129 130#define TMR_GBL 0x01 131#define TMR_PRV 0x02 132#define TMR_BOTH (TMR_GBL | TMR_PRV) 133#define TMR_NONE 0 134 135static struct ofw_compat_data compat_data[] = { 136 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */ 137 {"arm,cortex-a9-global-timer", TMR_GBL}, 138 {"arm,cortex-a5-global-timer", TMR_GBL}, 139 {"arm,cortex-a9-twd-timer", TMR_PRV}, 140 {"arm,cortex-a5-twd-timer", TMR_PRV}, 141 {"arm,arm11mp-twd-timer", TMR_PRV}, 142 {NULL, TMR_NONE} 143}; 144 145/** 146 * arm_tmr_get_timecount - reads the timecount (global) timer 147 * @tc: pointer to arm_tmr_timecount struct 148 * 149 * We only read the lower 32-bits, the timecount stuff only uses 32-bits 150 * so (for now?) ignore the upper 32-bits. 151 * 152 * RETURNS 153 * The lower 32-bits of the counter. 154 */ 155static unsigned 156arm_tmr_get_timecount(struct timecounter *tc) 157{ 158 struct arm_tmr_softc *sc; 159 160 sc = tc->tc_priv; 161 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW)); 162} 163 164/** 165 * arm_tmr_start - starts the eventtimer (private) timer 166 * @et: pointer to eventtimer struct 167 * @first: the number of seconds and fractional sections to trigger in 168 * @period: the period (in seconds and fractional sections) to set 169 * 170 * If the eventtimer is required to be in oneshot mode, period will be 171 * NULL and first will point to the time to trigger. If in periodic mode 172 * period will contain the time period and first may optionally contain 173 * the time for the first period. 174 * 175 * RETURNS 176 * Always returns 0 177 */ 178static int 179arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 180{ 181 struct arm_tmr_softc *sc; 182 uint32_t load, count; 183 uint32_t ctrl; 184 185 sc = et->et_priv; 186 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 187 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 188 189 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE; 190 191 if (period != 0) { 192 load = ((uint32_t)et->et_frequency * period) >> 32; 193 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD; 194 } else 195 load = 0; 196 197 if (first != 0) 198 count = (uint32_t)((et->et_frequency * first) >> 32); 199 else 200 count = load; 201 202 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load); 203 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count); 204 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl); 205 206 return (0); 207} 208 209/** 210 * arm_tmr_stop - stops the eventtimer (private) timer 211 * @et: pointer to eventtimer struct 212 * 213 * Simply stops the private timer by clearing all bits in the ctrl register. 214 * 215 * RETURNS 216 * Always returns 0 217 */ 218static int 219arm_tmr_stop(struct eventtimer *et) 220{ 221 struct arm_tmr_softc *sc; 222 223 sc = et->et_priv; 224 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0); 225 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 226 return (0); 227} 228 229/** 230 * arm_tmr_intr - ISR for the eventtimer (private) timer 231 * @arg: pointer to arm_tmr_softc struct 232 * 233 * Clears the event register and then calls the eventtimer callback. 234 * 235 * RETURNS 236 * Always returns FILTER_HANDLED 237 */ 238static int 239arm_tmr_intr(void *arg) 240{ 241 struct arm_tmr_softc *sc; 242 243 sc = arg; 244 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); 245 if (sc->et.et_active) 246 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 247 return (FILTER_HANDLED); 248} 249 250 251 252 253/** 254 * arm_tmr_probe - timer probe routine 255 * @dev: new device 256 * 257 * The probe function returns success when probed with the fdt compatible 258 * string set to "arm,mpcore-timers". 259 * 260 * RETURNS 261 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO. 262 */ 263static int 264arm_tmr_probe(device_t dev) 265{ 266 267 if (!ofw_bus_status_okay(dev)) 268 return (ENXIO); 269 270 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE) 271 return (ENXIO); 272 273 device_set_desc(dev, "ARM MPCore Timers"); 274 return (BUS_PROBE_DEFAULT); 275} 276 277static int 278attach_tc(struct arm_tmr_softc *sc) 279{ 280 int rid; 281 282 if (arm_tmr_tc != NULL) 283 return (EBUSY); 284 285 rid = sc->memrid; 286 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, 287 RF_ACTIVE); 288 if (sc->gbl_mem == NULL) { 289 device_printf(sc->dev, "could not allocate gbl mem resources\n"); 290 return (ENXIO); 291 } 292 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000); 293 294 arm_tmr_timecount.tc_frequency = sc->clkfreq; 295 arm_tmr_timecount.tc_priv = sc; 296 tc_init(&arm_tmr_timecount); 297 arm_tmr_tc = &arm_tmr_timecount; 298 299 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE); 300 301 return (0); 302} 303 304static int 305attach_et(struct arm_tmr_softc *sc) 306{ 307 void *ihl; 308 int irid, mrid; 309 310 if (arm_tmr_et != NULL) 311 return (EBUSY); 312 313 mrid = sc->memrid; 314 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid, 315 RF_ACTIVE); 316 if (sc->prv_mem == NULL) { 317 device_printf(sc->dev, "could not allocate prv mem resources\n"); 318 return (ENXIO); 319 } 320 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000); 321 322 irid = sc->irqrid; 323 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE); 324 if (sc->prv_irq == NULL) { 325 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 326 device_printf(sc->dev, "could not allocate prv irq resources\n"); 327 return (ENXIO); 328 } 329 330 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr, 331 NULL, sc, &ihl) != 0) { 332 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem); 333 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq); 334 device_printf(sc->dev, "unable to setup the et irq handler.\n"); 335 return (ENXIO); 336 } 337 338 /* 339 * Setup and register the eventtimer. Most event timers set their min 340 * and max period values to some value calculated from the clock 341 * frequency. We might not know yet what our runtime clock frequency 342 * will be, so we just use some safe values. A max of 2 seconds ensures 343 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU), 344 * we won't overflow our 32-bit timer count register. A min of 20 345 * nanoseconds is pretty much completely arbitrary. 346 */ 347 sc->et.et_name = "MPCore"; 348 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 349 sc->et.et_quality = 1000; 350 sc->et.et_frequency = sc->clkfreq; 351 sc->et.et_min_period = nstosbt(20); 352 sc->et.et_max_period = 2 * SBT_1S; 353 sc->et.et_start = arm_tmr_start; 354 sc->et.et_stop = arm_tmr_stop; 355 sc->et.et_priv = sc; 356 et_register(&sc->et); 357 arm_tmr_et = &sc->et; 358 359 return (0); 360} 361 362/** 363 * arm_tmr_attach - attaches the timer to the simplebus 364 * @dev: new device 365 * 366 * Reserves memory and interrupt resources, stores the softc structure 367 * globally and registers both the timecount and eventtimer objects. 368 * 369 * RETURNS 370 * Zero on success or ENXIO if an error occuried. 371 */ 372static int 373arm_tmr_attach(device_t dev) 374{ 375 struct arm_tmr_softc *sc; 376 phandle_t node; 377 pcell_t clock; 378 int et_err, tc_err, tmrtype; 379 380 sc = device_get_softc(dev); 381 sc->dev = dev; 382 383 if (arm_tmr_freq_varies) { 384 sc->clkfreq = arm_tmr_freq; 385 } else { 386 if (arm_tmr_freq != 0) { 387 sc->clkfreq = arm_tmr_freq; 388 } else { 389 /* Get the base clock frequency */ 390 node = ofw_bus_get_node(dev); 391 if ((OF_getencprop(node, "clock-frequency", &clock, 392 sizeof(clock))) <= 0) { 393 device_printf(dev, "missing clock-frequency " 394 "attribute in FDT\n"); 395 return (ENXIO); 396 } 397 sc->clkfreq = clock; 398 } 399 } 400 401 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 402 tc_err = ENXIO; 403 et_err = ENXIO; 404 405 /* 406 * If we're handling the global timer and it is fixed-frequency, set it 407 * up to use as a timecounter. If it's variable frequency it won't work 408 * as a timecounter. We also can't use it for DELAY(), so hopefully the 409 * platform provides its own implementation. If it doesn't, ours will 410 * get used, but since the frequency isn't set, it will only use the 411 * bogus loop counter. 412 */ 413 if (tmrtype & TMR_GBL) { 414 if (!arm_tmr_freq_varies) 415 tc_err = attach_tc(sc); 416 else if (bootverbose) 417 device_printf(sc->dev, 418 "not using variable-frequency device as timecounter\n"); 419 sc->memrid++; 420 sc->irqrid++; 421 } 422 423 /* If we are handling the private timer, set it up as an eventtimer. */ 424 if (tmrtype & TMR_PRV) { 425 et_err = attach_et(sc); 426 } 427 428 /* 429 * If we didn't successfully set up a timecounter or eventtimer then we 430 * didn't actually attach at all, return error. 431 */ 432 if (tc_err != 0 && et_err != 0) { 433 return (ENXIO); 434 } 435 return (0); 436} 437 438static device_method_t arm_tmr_methods[] = { 439 DEVMETHOD(device_probe, arm_tmr_probe), 440 DEVMETHOD(device_attach, arm_tmr_attach), 441 { 0, 0 } 442}; 443 444static driver_t arm_tmr_driver = { 445 "mp_tmr", 446 arm_tmr_methods, 447 sizeof(struct arm_tmr_softc), 448}; 449 450static devclass_t arm_tmr_devclass; 451 452EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 453 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 454EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0, 455 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 456 457/* 458 * Handle a change in clock frequency. The mpcore timer runs at half the CPU 459 * frequency. When the CPU frequency changes due to power-saving or thermal 460 * management, the platform-specific code that causes the frequency change calls 461 * this routine to inform the clock driver, and we in turn inform the event 462 * timer system, which actually updates the value in et->frequency for us and 463 * reschedules the current event(s) in a way that's atomic with respect to 464 * start/stop/intr code that may be running on various CPUs at the time of the 465 * call. 466 * 467 * This routine can also be called by a platform's early init code. If the 468 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code 469 * to register as an eventtimer, but not a timecounter. If the value passed in 470 * is any other non-zero value it is used as the fixed frequency for the timer. 471 */ 472void 473arm_tmr_change_frequency(uint64_t newfreq) 474{ 475 476 if (newfreq == ARM_TMR_FREQUENCY_VARIES) { 477 arm_tmr_freq_varies = true; 478 return; 479 } 480 481 arm_tmr_freq = newfreq; 482 if (arm_tmr_et != NULL) 483 et_change_frequency(arm_tmr_et, newfreq); 484} 485 486/** 487 * DELAY - Delay for at least usec microseconds. 488 * @usec: number of microseconds to delay by 489 * 490 * This function is called all over the kernel and is suppose to provide a 491 * consistent delay. This function may also be called before the console 492 * is setup so no printf's can be called here. 493 * 494 * RETURNS: 495 * nothing 496 */ 497static void __used /* Must emit function code for the weak ref below. */ 498arm_tmr_DELAY(int usec) 499{ 500 struct arm_tmr_softc *sc; 501 int32_t counts_per_usec; 502 int32_t counts; 503 uint32_t first, last; 504 505 /* Check the timers are setup, if not just use a for loop for the meantime */ 506 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) { 507 for (; usec > 0; usec--) 508 for (counts = 200; counts > 0; counts--) 509 cpufunc_nullop(); /* Prevent gcc from optimizing 510 * out the loop 511 */ 512 return; 513 } 514 515 sc = arm_tmr_tc->tc_priv; 516 517 /* Get the number of times to count */ 518 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 519 520 /* 521 * Clamp the timeout at a maximum value (about 32 seconds with 522 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 523 * near that length of time and if they are, they should be hung 524 * out to dry. 525 */ 526 if (usec >= (0x80000000U / counts_per_usec)) 527 counts = (0x80000000U / counts_per_usec) - 1; 528 else 529 counts = usec * counts_per_usec; 530 531 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 532 533 while (counts > 0) { 534 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW); 535 counts -= (int32_t)(last - first); 536 first = last; 537 } 538} 539 540/* 541 * Supply a DELAY() implementation via weak linkage. A platform may want to use 542 * the mpcore per-cpu eventtimers but provide its own DELAY() routine, 543 * especially when the core frequency can change on the fly. 544 */ 545__weak_reference(arm_tmr_DELAY, DELAY); 546 547