identcpu-v6.c revision 235062
1129198Scognet/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1995 Mark Brinicombe. 5129198Scognet * Copyright (c) 1995 Brini. 6129198Scognet * All rights reserved. 7129198Scognet * 8129198Scognet * Redistribution and use in source and binary forms, with or without 9129198Scognet * modification, are permitted provided that the following conditions 10129198Scognet * are met: 11129198Scognet * 1. Redistributions of source code must retain the above copyright 12129198Scognet * notice, this list of conditions and the following disclaimer. 13129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 14129198Scognet * notice, this list of conditions and the following disclaimer in the 15129198Scognet * documentation and/or other materials provided with the distribution. 16129198Scognet * 3. All advertising materials mentioning features or use of this software 17129198Scognet * must display the following acknowledgement: 18129198Scognet * This product includes software developed by Brini. 19129198Scognet * 4. The name of the company nor the name of the author may be used to 20129198Scognet * endorse or promote products derived from this software without specific 21129198Scognet * prior written permission. 22129198Scognet * 23129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33129198Scognet * SUCH DAMAGE. 34129198Scognet * 35129198Scognet * RiscBSD kernel project 36129198Scognet * 37129198Scognet * cpu.c 38129198Scognet * 39129198Scognet * Probing and configuration for the master CPU 40129198Scognet * 41129198Scognet * Created : 10/10/95 42129198Scognet */ 43129198Scognet 44129198Scognet#include <sys/cdefs.h> 45129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/identcpu.c 235062 2012-05-05 17:20:12Z imp $"); 46129198Scognet#include <sys/systm.h> 47129198Scognet#include <sys/param.h> 48129198Scognet#include <sys/malloc.h> 49129198Scognet#include <sys/time.h> 50129198Scognet#include <sys/proc.h> 51129198Scognet#include <sys/conf.h> 52135652Scognet#include <sys/kernel.h> 53135652Scognet#include <sys/sysctl.h> 54129198Scognet#include <machine/cpu.h> 55235050Simp#include <machine/endian.h> 56129198Scognet 57129198Scognet#include <machine/cpuconf.h> 58197523Srpaulo#include <machine/md_var.h> 59129198Scognet 60129198Scognetchar machine[] = "arm"; 61129198Scognet 62135652ScognetSYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 63235062Simp machine, 0, "Machine class"); 64129198Scognet 65129198Scognetstatic const char * const generic_steppings[16] = { 66129198Scognet "rev 0", "rev 1", "rev 2", "rev 3", 67129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 68129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 69129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 70129198Scognet}; 71129198Scognet 72129198Scognetstatic const char * const sa110_steppings[16] = { 73129198Scognet "rev 0", "step J", "step K", "step S", 74129198Scognet "step T", "rev 5", "rev 6", "rev 7", 75129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 76129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 77129198Scognet}; 78129198Scognet 79129198Scognetstatic const char * const sa1100_steppings[16] = { 80129198Scognet "rev 0", "step B", "step C", "rev 3", 81129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 82129198Scognet "step D", "step E", "rev 10" "step G", 83129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 84129198Scognet}; 85129198Scognet 86129198Scognetstatic const char * const sa1110_steppings[16] = { 87129198Scognet "step A-0", "rev 1", "rev 2", "rev 3", 88129198Scognet "step B-0", "step B-1", "step B-2", "step B-3", 89129198Scognet "step B-4", "step B-5", "rev 10", "rev 11", 90129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 91129198Scognet}; 92129198Scognet 93129198Scognetstatic const char * const ixp12x0_steppings[16] = { 94129198Scognet "(IXP1200 step A)", "(IXP1200 step B)", 95129198Scognet "rev 2", "(IXP1200 step C)", 96129198Scognet "(IXP1200 step D)", "(IXP1240/1250 step A)", 97129198Scognet "(IXP1240 step B)", "(IXP1250 step B)", 98129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 99129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 100129198Scognet}; 101129198Scognet 102129198Scognetstatic const char * const xscale_steppings[16] = { 103129198Scognet "step A-0", "step A-1", "step B-0", "step C-0", 104129198Scognet "step D-0", "rev 5", "rev 6", "rev 7", 105129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 106129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 107129198Scognet}; 108129198Scognet 109172738Simpstatic const char * const i80219_steppings[16] = { 110172738Simp "step A-0", "rev 1", "rev 2", "rev 3", 111172738Simp "rev 4", "rev 5", "rev 6", "rev 7", 112172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 113172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 114172738Simp}; 115172738Simp 116129198Scognetstatic const char * const i80321_steppings[16] = { 117129198Scognet "step A-0", "step B-0", "rev 2", "rev 3", 118129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 119129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 120129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 121129198Scognet}; 122129198Scognet 123164080Scognetstatic const char * const i81342_steppings[16] = { 124164080Scognet "step A-0", "rev 1", "rev 2", "rev 3", 125164080Scognet "rev 4", "rev 5", "rev 6", "rev 7", 126164080Scognet "rev 8", "rev 9", "rev 10", "rev 11", 127164080Scognet "rev 12", "rev 13", "rev 14", "rev 15", 128164080Scognet}; 129164080Scognet 130172738Simp/* Steppings for PXA2[15]0 */ 131129198Scognetstatic const char * const pxa2x0_steppings[16] = { 132129198Scognet "step A-0", "step A-1", "step B-0", "step B-1", 133129198Scognet "step B-2", "step C-0", "rev 6", "rev 7", 134129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 135129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 136129198Scognet}; 137129198Scognet 138172738Simp/* Steppings for PXA255/26x. 139235062Simp * rev 5: PXA26x B0, rev 6: PXA255 A0 140172738Simp */ 141172738Simpstatic const char * const pxa255_steppings[16] = { 142172738Simp "rev 0", "rev 1", "rev 2", "step A-0", 143172738Simp "rev 4", "step B-0", "step A-0", "rev 7", 144172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 145172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 146172738Simp}; 147172738Simp 148172738Simp/* Stepping for PXA27x */ 149172738Simpstatic const char * const pxa27x_steppings[16] = { 150172738Simp "step A-0", "step A-1", "step B-0", "step B-1", 151172738Simp "step C-0", "rev 5", "rev 6", "rev 7", 152172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 153172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 154172738Simp}; 155172738Simp 156129198Scognetstatic const char * const ixp425_steppings[16] = { 157164423Ssam "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", 158129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 159129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 160129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 161129198Scognet}; 162129198Scognet 163129198Scognetstruct cpuidtab { 164129198Scognet u_int32_t cpuid; 165129198Scognet enum cpu_class cpu_class; 166129198Scognet const char *cpu_name; 167129198Scognet const char * const *cpu_steppings; 168129198Scognet}; 169129198Scognet 170129198Scognetconst struct cpuidtab cpuids[] = { 171129198Scognet { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 172129198Scognet generic_steppings }, 173129198Scognet { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 174129198Scognet generic_steppings }, 175129198Scognet 176129198Scognet { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 177129198Scognet generic_steppings }, 178129198Scognet 179129198Scognet { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 180129198Scognet generic_steppings }, 181129198Scognet { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 182129198Scognet generic_steppings }, 183129198Scognet { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 184129198Scognet generic_steppings }, 185129198Scognet 186129198Scognet { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 187129198Scognet generic_steppings }, 188129198Scognet { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 189129198Scognet generic_steppings }, 190129198Scognet { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 191129198Scognet generic_steppings }, 192129198Scognet { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 193129198Scognet generic_steppings }, 194129198Scognet { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 195129198Scognet generic_steppings }, 196129198Scognet { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 197129198Scognet generic_steppings }, 198129198Scognet { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 199129198Scognet generic_steppings }, 200129198Scognet { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 201129198Scognet generic_steppings }, 202129198Scognet { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 203129198Scognet generic_steppings }, 204129198Scognet 205129198Scognet { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 206129198Scognet generic_steppings }, 207129198Scognet 208129198Scognet { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 209129198Scognet generic_steppings }, 210152653Scognet { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", 211152653Scognet generic_steppings }, 212129198Scognet { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 213129198Scognet generic_steppings }, 214172738Simp { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 215172738Simp generic_steppings }, 216129198Scognet { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 217129198Scognet generic_steppings }, 218129198Scognet { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 219129198Scognet generic_steppings }, 220129198Scognet { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 221129198Scognet generic_steppings }, 222129198Scognet { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 223129198Scognet generic_steppings }, 224207954Skevlo { CPU_ID_FA526, CPU_CLASS_ARM9TDMI, "FA526", 225204122Skevlo generic_steppings }, 226207611Skevlo { CPU_ID_FA626TE, CPU_CLASS_ARM9ES, "FA626TE", 227207611Skevlo generic_steppings }, 228204122Skevlo 229129198Scognet { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 230129198Scognet generic_steppings }, 231129198Scognet 232129198Scognet { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 233129198Scognet generic_steppings }, 234129198Scognet { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 235129198Scognet generic_steppings }, 236172738Simp { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 237172738Simp generic_steppings }, 238129198Scognet 239129198Scognet { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 240129198Scognet sa110_steppings }, 241129198Scognet { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 242129198Scognet sa1100_steppings }, 243129198Scognet { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 244129198Scognet sa1110_steppings }, 245129198Scognet 246129198Scognet { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 247129198Scognet ixp12x0_steppings }, 248129198Scognet 249129198Scognet { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 250129198Scognet xscale_steppings }, 251129198Scognet 252129198Scognet { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 253129198Scognet i80321_steppings }, 254129198Scognet { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 255129198Scognet i80321_steppings }, 256129198Scognet { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 257129198Scognet i80321_steppings }, 258129198Scognet { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 259129198Scognet i80321_steppings }, 260129198Scognet 261164080Scognet { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342", 262164080Scognet i81342_steppings }, 263164080Scognet 264161592Scognet { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 265172738Simp i80219_steppings }, 266161592Scognet { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 267172738Simp i80219_steppings }, 268161592Scognet 269172738Simp { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 270172738Simp pxa27x_steppings }, 271129198Scognet { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 272129198Scognet pxa2x0_steppings }, 273129198Scognet { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 274129198Scognet pxa2x0_steppings }, 275129198Scognet { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 276129198Scognet pxa2x0_steppings }, 277129198Scognet { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 278129198Scognet pxa2x0_steppings }, 279172738Simp { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255", 280172738Simp pxa255_steppings }, 281129198Scognet { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 282129198Scognet pxa2x0_steppings }, 283129198Scognet 284129198Scognet { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 285129198Scognet ixp425_steppings }, 286129198Scognet { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 287129198Scognet ixp425_steppings }, 288129198Scognet { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 289129198Scognet ixp425_steppings }, 290129198Scognet 291186352Ssam /* XXX ixp435 steppings? */ 292186352Ssam { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", 293186352Ssam ixp425_steppings }, 294186352Ssam 295172738Simp { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 296172738Simp generic_steppings }, 297172738Simp { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 298172738Simp generic_steppings }, 299172738Simp 300183835Sraj { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", 301183835Sraj generic_steppings }, 302183835Sraj 303183835Sraj { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", 304183835Sraj generic_steppings }, 305183835Sraj 306183835Sraj { CPU_ID_MV88FR571_41, CPU_CLASS_MARVELL, "Early Feroceon 88FR571", 307183835Sraj generic_steppings }, 308183835Sraj 309129198Scognet { 0, CPU_CLASS_NONE, NULL, NULL } 310129198Scognet}; 311129198Scognet 312129198Scognetstruct cpu_classtab { 313129198Scognet const char *class_name; 314129198Scognet const char *class_option; 315129198Scognet}; 316129198Scognet 317129198Scognetconst struct cpu_classtab cpu_classes[] = { 318129198Scognet { "unknown", NULL }, /* CPU_CLASS_NONE */ 319129198Scognet { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 320129198Scognet { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 321129198Scognet { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 322129198Scognet { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 323129198Scognet { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 324129198Scognet { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 325129198Scognet { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 326155242Simp { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ 327172738Simp { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ 328172738Simp { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ 329129198Scognet { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 330172738Simp { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 331129198Scognet { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 332129198Scognet { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 333172738Simp { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 334205027Sraj { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ 335129198Scognet}; 336129198Scognet 337129198Scognet/* 338129198Scognet * Report the type of the specified arm processor. This uses the generic and 339129198Scognet * arm specific information in the cpu structure to identify the processor. 340129198Scognet * The remaining fields in the cpu structure are filled in appropriately. 341129198Scognet */ 342129198Scognet 343129198Scognetstatic const char * const wtnames[] = { 344129198Scognet "write-through", 345129198Scognet "write-back", 346129198Scognet "write-back", 347129198Scognet "**unknown 3**", 348129198Scognet "**unknown 4**", 349129198Scognet "write-back-locking", /* XXX XScale-specific? */ 350129198Scognet "write-back-locking-A", 351129198Scognet "write-back-locking-B", 352129198Scognet "**unknown 8**", 353129198Scognet "**unknown 9**", 354129198Scognet "**unknown 10**", 355129198Scognet "**unknown 11**", 356129198Scognet "**unknown 12**", 357129198Scognet "**unknown 13**", 358172738Simp "write-back-locking-C", 359129198Scognet "**unknown 15**", 360129198Scognet}; 361129198Scognet 362153940Snetchild 363129198Scognetextern int ctrl; 364197523Srpauloenum cpu_class cpu_class = CPU_CLASS_NONE; 365129198Scognetvoid 366129198Scognetidentify_arm_cpu(void) 367129198Scognet{ 368129198Scognet u_int cpuid; 369129198Scognet int i; 370129198Scognet 371129198Scognet cpuid = cpu_id(); 372129198Scognet 373129198Scognet if (cpuid == 0) { 374129198Scognet printf("Processor failed probe - no CPU ID\n"); 375129198Scognet return; 376129198Scognet } 377129198Scognet 378129198Scognet for (i = 0; cpuids[i].cpuid != 0; i++) 379129198Scognet if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 380129198Scognet cpu_class = cpuids[i].cpu_class; 381155242Simp printf("CPU: %s %s (%s core)\n", 382129198Scognet cpuids[i].cpu_name, 383129198Scognet cpuids[i].cpu_steppings[cpuid & 384129198Scognet CPU_ID_REVISION_MASK], 385129198Scognet cpu_classes[cpu_class].class_name); 386129198Scognet break; 387129198Scognet } 388129198Scognet if (cpuids[i].cpuid == 0) 389129198Scognet printf("unknown CPU (ID = 0x%x)\n", cpuid); 390129198Scognet 391155242Simp printf(" "); 392129198Scognet switch (cpu_class) { 393129198Scognet case CPU_CLASS_ARM6: 394129198Scognet case CPU_CLASS_ARM7: 395129198Scognet case CPU_CLASS_ARM7TDMI: 396129198Scognet case CPU_CLASS_ARM8: 397129198Scognet if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 398129198Scognet printf(" IDC disabled"); 399129198Scognet else 400129198Scognet printf(" IDC enabled"); 401129198Scognet break; 402129198Scognet case CPU_CLASS_ARM9TDMI: 403172738Simp case CPU_CLASS_ARM9ES: 404172738Simp case CPU_CLASS_ARM9EJS: 405129198Scognet case CPU_CLASS_ARM10E: 406172738Simp case CPU_CLASS_ARM10EJ: 407129198Scognet case CPU_CLASS_SA1: 408129198Scognet case CPU_CLASS_XSCALE: 409172738Simp case CPU_CLASS_ARM11J: 410205027Sraj case CPU_CLASS_MARVELL: 411129198Scognet if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0) 412129198Scognet printf(" DC disabled"); 413129198Scognet else 414129198Scognet printf(" DC enabled"); 415129198Scognet if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0) 416129198Scognet printf(" IC disabled"); 417129198Scognet else 418129198Scognet printf(" IC enabled"); 419171625Scognet#ifdef CPU_XSCALE_81342 420171625Scognet if ((ctrl & CPU_CONTROL_L2_ENABLE) == 0) 421171625Scognet printf(" L2 disabled"); 422171625Scognet else 423171625Scognet printf(" L2 enabled"); 424171625Scognet#endif 425129198Scognet break; 426129198Scognet default: 427129198Scognet break; 428129198Scognet } 429129198Scognet if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 430129198Scognet printf(" WB disabled"); 431129198Scognet else 432129198Scognet printf(" WB enabled"); 433129198Scognet 434129198Scognet if (ctrl & CPU_CONTROL_LABT_ENABLE) 435129198Scognet printf(" LABT"); 436129198Scognet else 437129198Scognet printf(" EABT"); 438129198Scognet 439129198Scognet if (ctrl & CPU_CONTROL_BPRD_ENABLE) 440129198Scognet printf(" branch prediction enabled"); 441129198Scognet 442155242Simp printf("\n"); 443137272Scognet /* Print cache info. */ 444137272Scognet if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 445137272Scognet return; 446137272Scognet 447137272Scognet if (arm_pcache_unified) { 448155242Simp printf(" %dKB/%dB %d-way %s unified cache\n", 449137272Scognet arm_pdcache_size / 1024, 450137272Scognet arm_pdcache_line_size, arm_pdcache_ways, 451137272Scognet wtnames[arm_pcache_type]); 452137272Scognet } else { 453155242Simp printf(" %dKB/%dB %d-way Instruction cache\n", 454137272Scognet arm_picache_size / 1024, 455137272Scognet arm_picache_line_size, arm_picache_ways); 456155242Simp printf(" %dKB/%dB %d-way %s Data cache\n", 457137272Scognet arm_pdcache_size / 1024, 458137272Scognet arm_pdcache_line_size, arm_pdcache_ways, 459235062Simp wtnames[arm_pcache_type]); 460137272Scognet } 461129198Scognet} 462129198Scognet 463