1/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ 2 3/*- 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44#include <sys/cdefs.h> 45__FBSDID("$FreeBSD: stable/11/sys/arm/arm/identcpu-v6.c 358591 2020-03-03 18:01:03Z dim $"); 46#include <sys/param.h> 47#include <sys/systm.h> 48#include <sys/conf.h> 49#include <sys/kernel.h> 50#include <sys/sysctl.h> 51#include <machine/cpu.h> 52#include <machine/md_var.h> 53 54char machine[] = "arm"; 55 56SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 57 machine, 0, "Machine class"); 58 59static char cpu_model[64]; 60SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 61 cpu_model, sizeof(cpu_model), "Machine model"); 62 63static char hw_buf[81]; 64static int hw_buf_idx; 65static bool hw_buf_newline; 66 67static struct { 68 int implementer; 69 int part_number; 70 char *impl_name; 71 char *core_name; 72} cpu_names[] = { 73 {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176"}, 74 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5"}, 75 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7"}, 76 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8"}, 77 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9"}, 78 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12"}, 79 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15"}, 80 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17"}, 81 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53"}, 82 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57"}, 83 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72"}, 84 {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73"}, 85 86 {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marvell", "PJ4 v7"}, 87 {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marvell", "PJ4MP v7"}, 88 89 {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300"}, 90}; 91 92 93static void 94print_v5_cache(void) 95{ 96 uint32_t isize, dsize; 97 uint32_t multiplier; 98 int pcache_type; 99 int pcache_unified; 100 int picache_size; 101 int picache_line_size; 102 int picache_ways; 103 int pdcache_size; 104 int pdcache_line_size; 105 int pdcache_ways; 106 107 pcache_unified = 0; 108 picache_size = 0 ; 109 picache_line_size = 0 ; 110 picache_ways = 0 ; 111 pdcache_size = 0; 112 pdcache_line_size = 0; 113 pdcache_ways = 0; 114 115 if ((cpuinfo.ctr & CPU_CT_S) == 0) 116 pcache_unified = 1; 117 118 /* 119 * If you want to know how this code works, go read the ARM ARM. 120 */ 121 pcache_type = CPU_CT_CTYPE(cpuinfo.ctr); 122 123 if (pcache_unified == 0) { 124 isize = CPU_CT_ISIZE(cpuinfo.ctr); 125 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; 126 picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); 127 if (CPU_CT_xSIZE_ASSOC(isize) == 0) { 128 if (isize & CPU_CT_xSIZE_M) 129 picache_line_size = 0; /* not present */ 130 else 131 picache_ways = 1; 132 } else { 133 picache_ways = multiplier << 134 (CPU_CT_xSIZE_ASSOC(isize) - 1); 135 } 136 picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); 137 } 138 139 dsize = CPU_CT_DSIZE(cpuinfo.ctr); 140 multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; 141 pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); 142 if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { 143 if (dsize & CPU_CT_xSIZE_M) 144 pdcache_line_size = 0; /* not present */ 145 else 146 pdcache_ways = 1; 147 } else { 148 pdcache_ways = multiplier << 149 (CPU_CT_xSIZE_ASSOC(dsize) - 1); 150 } 151 pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); 152 153 154 /* Print cache info. */ 155 if (picache_line_size == 0 && pdcache_line_size == 0) 156 return; 157 158 if (pcache_unified) { 159 printf(" %dKB/%dB %d-way %s unified cache\n", 160 pdcache_size / 1024, 161 pdcache_line_size, pdcache_ways, 162 pcache_type == 0 ? "WT" : "WB"); 163 } else { 164 printf(" %dKB/%dB %d-way instruction cache\n", 165 picache_size / 1024, 166 picache_line_size, picache_ways); 167 printf(" %dKB/%dB %d-way %s data cache\n", 168 pdcache_size / 1024, 169 pdcache_line_size, pdcache_ways, 170 pcache_type == 0 ? "WT" : "WB"); 171 } 172} 173 174static void 175print_v7_cache(void ) 176{ 177 uint32_t type, val, size, sets, ways, linesize; 178 int i; 179 180 printf("LoUU:%d LoC:%d LoUIS:%d \n", 181 CPU_CLIDR_LOUU(cpuinfo.clidr) + 1, 182 CPU_CLIDR_LOC(cpuinfo.clidr) + 1, 183 CPU_CLIDR_LOUIS(cpuinfo.clidr) + 1); 184 185 for (i = 0; i < 7; i++) { 186 type = CPU_CLIDR_CTYPE(cpuinfo.clidr, i); 187 if (type == 0) 188 break; 189 printf("Cache level %d:\n", i + 1); 190 if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE || 191 type == CACHE_SEP_CACHE) { 192 cp15_csselr_set(i << 1); 193 val = cp15_ccsidr_get(); 194 ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; 195 sets = CPUV7_CT_xSIZE_SET(val) + 1; 196 linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); 197 size = (ways * sets * linesize) / 1024; 198 199 if (type == CACHE_UNI_CACHE) 200 printf(" %dKB/%dB %d-way unified cache", 201 size, linesize,ways); 202 else 203 printf(" %dKB/%dB %d-way data cache", 204 size, linesize, ways); 205 if (val & CPUV7_CT_CTYPE_WT) 206 printf(" WT"); 207 if (val & CPUV7_CT_CTYPE_WB) 208 printf(" WB"); 209 if (val & CPUV7_CT_CTYPE_RA) 210 printf(" Read-Alloc"); 211 if (val & CPUV7_CT_CTYPE_WA) 212 printf(" Write-Alloc"); 213 printf("\n"); 214 } 215 216 if (type == CACHE_ICACHE || type == CACHE_SEP_CACHE) { 217 cp15_csselr_set(i << 1 | 1); 218 val = cp15_ccsidr_get(); 219 ways = CPUV7_CT_xSIZE_ASSOC(val) + 1; 220 sets = CPUV7_CT_xSIZE_SET(val) + 1; 221 linesize = 1 << (CPUV7_CT_xSIZE_LEN(val) + 4); 222 size = (ways * sets * linesize) / 1024; 223 printf(" %dKB/%dB %d-way instruction cache", 224 size, linesize, ways); 225 if (val & CPUV7_CT_CTYPE_WT) 226 printf(" WT"); 227 if (val & CPUV7_CT_CTYPE_WB) 228 printf(" WB"); 229 if (val & CPUV7_CT_CTYPE_RA) 230 printf(" Read-Alloc"); 231 if (val & CPUV7_CT_CTYPE_WA) 232 printf(" Write-Alloc"); 233 printf("\n"); 234 } 235 } 236 cp15_csselr_set(0); 237} 238 239static void 240add_cap(char *cap) 241{ 242 int len; 243 244 len = strlen(cap); 245 246 if ((hw_buf_idx + len + 2) >= 79) { 247 printf("%s,\n", hw_buf); 248 hw_buf_idx = 0; 249 hw_buf_newline = true; 250 } 251 if (hw_buf_newline) 252 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, " "); 253 else 254 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, ", "); 255 hw_buf_newline = false; 256 257 258 hw_buf_idx += sprintf(hw_buf + hw_buf_idx, "%s", cap); 259} 260 261void 262identify_arm_cpu(void) 263{ 264 int i; 265 u_int val; 266 267 /* 268 * CPU 269 */ 270 for(i = 0; i < nitems(cpu_names); i++) { 271 if (cpu_names[i].implementer == cpuinfo.implementer && 272 cpu_names[i].part_number == cpuinfo.part_number) { 273 snprintf(cpu_model, sizeof(cpu_model), 274 "%s %s r%dp%d (ECO: 0x%08X)", 275 cpu_names[i].impl_name, cpu_names[i].core_name, 276 cpuinfo.revision, cpuinfo.patch, 277 cpuinfo.midr != cpuinfo.revidr ? 278 cpuinfo.revidr : 0); 279 printf("CPU: %s\n", cpu_model); 280 break; 281 } 282 283 } 284 if (i >= nitems(cpu_names)) 285 printf("unknown CPU (ID = 0x%x)\n", cpuinfo.midr); 286 287 printf("CPU Features: \n"); 288 hw_buf_idx = 0; 289 hw_buf_newline = true; 290 291 val = (cpuinfo.mpidr >> 4)& 0xF; 292 if (cpuinfo.mpidr & (1 << 31U)) 293 add_cap("Multiprocessing"); 294 val = (cpuinfo.id_pfr0 >> 4)& 0xF; 295 if (val == 1) 296 add_cap("Thumb"); 297 else if (val == 3) 298 add_cap("Thumb2"); 299 300 val = (cpuinfo.id_pfr1 >> 4)& 0xF; 301 if (val == 1 || val == 2) 302 add_cap("Security"); 303 304 val = (cpuinfo.id_pfr1 >> 12)& 0xF; 305 if (val == 1) 306 add_cap("Virtualization"); 307 308 val = (cpuinfo.id_pfr1 >> 16)& 0xF; 309 if (val == 1) 310 add_cap("Generic Timer"); 311 312 val = (cpuinfo.id_mmfr0 >> 0)& 0xF; 313 if (val == 2) { 314 add_cap("VMSAv6"); 315 } else if (val >= 3) { 316 add_cap("VMSAv7"); 317 if (val >= 4) 318 add_cap("PXN"); 319 if (val >= 5) 320 add_cap("LPAE"); 321 } 322 323 val = (cpuinfo.id_mmfr3 >> 20)& 0xF; 324 if (val == 1) 325 add_cap("Coherent Walk"); 326 327 if (hw_buf_idx != 0) 328 printf("%s\n", hw_buf); 329 330 printf("Optional instructions: \n"); 331 hw_buf_idx = 0; 332 hw_buf_newline = true; 333 val = (cpuinfo.id_isar0 >> 24)& 0xF; 334 if (val == 1) 335 add_cap("SDIV/UDIV (Thumb)"); 336 else if (val == 2) 337 add_cap("SDIV/UDIV"); 338 339 val = (cpuinfo.id_isar2 >> 20)& 0xF; 340 if (val == 1 || val == 2) 341 add_cap("UMULL"); 342 343 val = (cpuinfo.id_isar2 >> 16)& 0xF; 344 if (val == 1 || val == 2 || val == 3) 345 add_cap("SMULL"); 346 347 val = (cpuinfo.id_isar2 >> 12)& 0xF; 348 if (val == 1) 349 add_cap("MLA"); 350 351 val = (cpuinfo.id_isar3 >> 4)& 0xF; 352 if (val == 1) 353 add_cap("SIMD"); 354 else if (val == 3) 355 add_cap("SIMD(ext)"); 356 if (hw_buf_idx != 0) 357 printf("%s\n", hw_buf); 358 359 /* 360 * Cache 361 */ 362 if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) 363 print_v7_cache(); 364 else 365 print_v5_cache(); 366} 367