identcpu-v6.c revision 235050
1129198Scognet/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1995 Mark Brinicombe. 5129198Scognet * Copyright (c) 1995 Brini. 6129198Scognet * All rights reserved. 7129198Scognet * 8129198Scognet * Redistribution and use in source and binary forms, with or without 9129198Scognet * modification, are permitted provided that the following conditions 10129198Scognet * are met: 11129198Scognet * 1. Redistributions of source code must retain the above copyright 12129198Scognet * notice, this list of conditions and the following disclaimer. 13129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 14129198Scognet * notice, this list of conditions and the following disclaimer in the 15129198Scognet * documentation and/or other materials provided with the distribution. 16129198Scognet * 3. All advertising materials mentioning features or use of this software 17129198Scognet * must display the following acknowledgement: 18129198Scognet * This product includes software developed by Brini. 19129198Scognet * 4. The name of the company nor the name of the author may be used to 20129198Scognet * endorse or promote products derived from this software without specific 21129198Scognet * prior written permission. 22129198Scognet * 23129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33129198Scognet * SUCH DAMAGE. 34129198Scognet * 35129198Scognet * RiscBSD kernel project 36129198Scognet * 37129198Scognet * cpu.c 38129198Scognet * 39129198Scognet * Probing and configuration for the master CPU 40129198Scognet * 41129198Scognet * Created : 10/10/95 42129198Scognet */ 43129198Scognet 44129198Scognet#include <sys/cdefs.h> 45129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/identcpu.c 235050 2012-05-05 07:15:34Z imp $"); 46129198Scognet#include <sys/systm.h> 47129198Scognet#include <sys/param.h> 48129198Scognet#include <sys/malloc.h> 49129198Scognet#include <sys/time.h> 50129198Scognet#include <sys/proc.h> 51129198Scognet#include <sys/conf.h> 52135652Scognet#include <sys/kernel.h> 53135652Scognet#include <sys/sysctl.h> 54129198Scognet#include <machine/cpu.h> 55235050Simp#include <machine/endian.h> 56129198Scognet 57129198Scognet#include <machine/cpuconf.h> 58197523Srpaulo#include <machine/md_var.h> 59129198Scognet 60235050Simp#if _BYTE_ORDER == _LITTLE_ENDIAN 61129198Scognetchar machine[] = "arm"; 62235050Simp#else 63235050Simpchar machine[] = "armeb"; 64235050Simp#endif 65129198Scognet 66135652ScognetSYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 67135652Scognet machine, 0, "Machine class"); 68129198Scognet 69129198Scognetstatic const char * const generic_steppings[16] = { 70129198Scognet "rev 0", "rev 1", "rev 2", "rev 3", 71129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 72129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 73129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 74129198Scognet}; 75129198Scognet 76129198Scognetstatic const char * const sa110_steppings[16] = { 77129198Scognet "rev 0", "step J", "step K", "step S", 78129198Scognet "step T", "rev 5", "rev 6", "rev 7", 79129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 80129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 81129198Scognet}; 82129198Scognet 83129198Scognetstatic const char * const sa1100_steppings[16] = { 84129198Scognet "rev 0", "step B", "step C", "rev 3", 85129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 86129198Scognet "step D", "step E", "rev 10" "step G", 87129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 88129198Scognet}; 89129198Scognet 90129198Scognetstatic const char * const sa1110_steppings[16] = { 91129198Scognet "step A-0", "rev 1", "rev 2", "rev 3", 92129198Scognet "step B-0", "step B-1", "step B-2", "step B-3", 93129198Scognet "step B-4", "step B-5", "rev 10", "rev 11", 94129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 95129198Scognet}; 96129198Scognet 97129198Scognetstatic const char * const ixp12x0_steppings[16] = { 98129198Scognet "(IXP1200 step A)", "(IXP1200 step B)", 99129198Scognet "rev 2", "(IXP1200 step C)", 100129198Scognet "(IXP1200 step D)", "(IXP1240/1250 step A)", 101129198Scognet "(IXP1240 step B)", "(IXP1250 step B)", 102129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 103129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 104129198Scognet}; 105129198Scognet 106129198Scognetstatic const char * const xscale_steppings[16] = { 107129198Scognet "step A-0", "step A-1", "step B-0", "step C-0", 108129198Scognet "step D-0", "rev 5", "rev 6", "rev 7", 109129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 110129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 111129198Scognet}; 112129198Scognet 113172738Simpstatic const char * const i80219_steppings[16] = { 114172738Simp "step A-0", "rev 1", "rev 2", "rev 3", 115172738Simp "rev 4", "rev 5", "rev 6", "rev 7", 116172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 117172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 118172738Simp}; 119172738Simp 120129198Scognetstatic const char * const i80321_steppings[16] = { 121129198Scognet "step A-0", "step B-0", "rev 2", "rev 3", 122129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 123129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 124129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 125129198Scognet}; 126129198Scognet 127164080Scognetstatic const char * const i81342_steppings[16] = { 128164080Scognet "step A-0", "rev 1", "rev 2", "rev 3", 129164080Scognet "rev 4", "rev 5", "rev 6", "rev 7", 130164080Scognet "rev 8", "rev 9", "rev 10", "rev 11", 131164080Scognet "rev 12", "rev 13", "rev 14", "rev 15", 132164080Scognet}; 133164080Scognet 134172738Simp/* Steppings for PXA2[15]0 */ 135129198Scognetstatic const char * const pxa2x0_steppings[16] = { 136129198Scognet "step A-0", "step A-1", "step B-0", "step B-1", 137129198Scognet "step B-2", "step C-0", "rev 6", "rev 7", 138129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 139129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 140129198Scognet}; 141129198Scognet 142172738Simp/* Steppings for PXA255/26x. 143172738Simp * rev 5: PXA26x B0, rev 6: PXA255 A0 144172738Simp */ 145172738Simpstatic const char * const pxa255_steppings[16] = { 146172738Simp "rev 0", "rev 1", "rev 2", "step A-0", 147172738Simp "rev 4", "step B-0", "step A-0", "rev 7", 148172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 149172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 150172738Simp}; 151172738Simp 152172738Simp/* Stepping for PXA27x */ 153172738Simpstatic const char * const pxa27x_steppings[16] = { 154172738Simp "step A-0", "step A-1", "step B-0", "step B-1", 155172738Simp "step C-0", "rev 5", "rev 6", "rev 7", 156172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 157172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 158172738Simp}; 159172738Simp 160129198Scognetstatic const char * const ixp425_steppings[16] = { 161164423Ssam "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", 162129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 163129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 164129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 165129198Scognet}; 166129198Scognet 167129198Scognetstruct cpuidtab { 168129198Scognet u_int32_t cpuid; 169129198Scognet enum cpu_class cpu_class; 170129198Scognet const char *cpu_name; 171129198Scognet const char * const *cpu_steppings; 172129198Scognet}; 173129198Scognet 174129198Scognetconst struct cpuidtab cpuids[] = { 175129198Scognet { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 176129198Scognet generic_steppings }, 177129198Scognet { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 178129198Scognet generic_steppings }, 179129198Scognet 180129198Scognet { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 181129198Scognet generic_steppings }, 182129198Scognet 183129198Scognet { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 184129198Scognet generic_steppings }, 185129198Scognet { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 186129198Scognet generic_steppings }, 187129198Scognet { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 188129198Scognet generic_steppings }, 189129198Scognet 190129198Scognet { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 191129198Scognet generic_steppings }, 192129198Scognet { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 193129198Scognet generic_steppings }, 194129198Scognet { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 195129198Scognet generic_steppings }, 196129198Scognet { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 197129198Scognet generic_steppings }, 198129198Scognet { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 199129198Scognet generic_steppings }, 200129198Scognet { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 201129198Scognet generic_steppings }, 202129198Scognet { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 203129198Scognet generic_steppings }, 204129198Scognet { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 205129198Scognet generic_steppings }, 206129198Scognet { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 207129198Scognet generic_steppings }, 208129198Scognet 209129198Scognet { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 210129198Scognet generic_steppings }, 211129198Scognet 212129198Scognet { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 213129198Scognet generic_steppings }, 214152653Scognet { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", 215152653Scognet generic_steppings }, 216129198Scognet { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 217129198Scognet generic_steppings }, 218172738Simp { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 219172738Simp generic_steppings }, 220129198Scognet { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 221129198Scognet generic_steppings }, 222129198Scognet { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 223129198Scognet generic_steppings }, 224129198Scognet { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 225129198Scognet generic_steppings }, 226129198Scognet { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 227129198Scognet generic_steppings }, 228207954Skevlo { CPU_ID_FA526, CPU_CLASS_ARM9TDMI, "FA526", 229204122Skevlo generic_steppings }, 230207611Skevlo { CPU_ID_FA626TE, CPU_CLASS_ARM9ES, "FA626TE", 231207611Skevlo generic_steppings }, 232204122Skevlo 233129198Scognet { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 234129198Scognet generic_steppings }, 235129198Scognet 236129198Scognet { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 237129198Scognet generic_steppings }, 238129198Scognet { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 239129198Scognet generic_steppings }, 240172738Simp { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 241172738Simp generic_steppings }, 242129198Scognet 243129198Scognet { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 244129198Scognet sa110_steppings }, 245129198Scognet { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 246129198Scognet sa1100_steppings }, 247129198Scognet { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 248129198Scognet sa1110_steppings }, 249129198Scognet 250129198Scognet { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 251129198Scognet ixp12x0_steppings }, 252129198Scognet 253129198Scognet { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 254129198Scognet xscale_steppings }, 255129198Scognet 256129198Scognet { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 257129198Scognet i80321_steppings }, 258129198Scognet { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 259129198Scognet i80321_steppings }, 260129198Scognet { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 261129198Scognet i80321_steppings }, 262129198Scognet { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 263129198Scognet i80321_steppings }, 264129198Scognet 265164080Scognet { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342", 266164080Scognet i81342_steppings }, 267164080Scognet 268161592Scognet { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 269172738Simp i80219_steppings }, 270161592Scognet { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 271172738Simp i80219_steppings }, 272161592Scognet 273172738Simp { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 274172738Simp pxa27x_steppings }, 275129198Scognet { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 276129198Scognet pxa2x0_steppings }, 277129198Scognet { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 278129198Scognet pxa2x0_steppings }, 279129198Scognet { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 280129198Scognet pxa2x0_steppings }, 281129198Scognet { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 282129198Scognet pxa2x0_steppings }, 283172738Simp { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255", 284172738Simp pxa255_steppings }, 285129198Scognet { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 286129198Scognet pxa2x0_steppings }, 287129198Scognet 288129198Scognet { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 289129198Scognet ixp425_steppings }, 290129198Scognet { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 291129198Scognet ixp425_steppings }, 292129198Scognet { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 293129198Scognet ixp425_steppings }, 294129198Scognet 295186352Ssam /* XXX ixp435 steppings? */ 296186352Ssam { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", 297186352Ssam ixp425_steppings }, 298186352Ssam 299172738Simp { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 300172738Simp generic_steppings }, 301172738Simp { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 302172738Simp generic_steppings }, 303172738Simp 304183835Sraj { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", 305183835Sraj generic_steppings }, 306183835Sraj 307183835Sraj { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", 308183835Sraj generic_steppings }, 309183835Sraj 310183835Sraj { CPU_ID_MV88FR571_41, CPU_CLASS_MARVELL, "Early Feroceon 88FR571", 311183835Sraj generic_steppings }, 312183835Sraj 313129198Scognet { 0, CPU_CLASS_NONE, NULL, NULL } 314129198Scognet}; 315129198Scognet 316129198Scognetstruct cpu_classtab { 317129198Scognet const char *class_name; 318129198Scognet const char *class_option; 319129198Scognet}; 320129198Scognet 321129198Scognetconst struct cpu_classtab cpu_classes[] = { 322129198Scognet { "unknown", NULL }, /* CPU_CLASS_NONE */ 323129198Scognet { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 324129198Scognet { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 325129198Scognet { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 326129198Scognet { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 327129198Scognet { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 328129198Scognet { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 329129198Scognet { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 330155242Simp { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ 331172738Simp { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ 332172738Simp { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ 333129198Scognet { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 334172738Simp { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 335129198Scognet { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 336129198Scognet { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 337172738Simp { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 338205027Sraj { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ 339129198Scognet}; 340129198Scognet 341129198Scognet/* 342129198Scognet * Report the type of the specified arm processor. This uses the generic and 343129198Scognet * arm specific information in the cpu structure to identify the processor. 344129198Scognet * The remaining fields in the cpu structure are filled in appropriately. 345129198Scognet */ 346129198Scognet 347129198Scognetstatic const char * const wtnames[] = { 348129198Scognet "write-through", 349129198Scognet "write-back", 350129198Scognet "write-back", 351129198Scognet "**unknown 3**", 352129198Scognet "**unknown 4**", 353129198Scognet "write-back-locking", /* XXX XScale-specific? */ 354129198Scognet "write-back-locking-A", 355129198Scognet "write-back-locking-B", 356129198Scognet "**unknown 8**", 357129198Scognet "**unknown 9**", 358129198Scognet "**unknown 10**", 359129198Scognet "**unknown 11**", 360129198Scognet "**unknown 12**", 361129198Scognet "**unknown 13**", 362172738Simp "write-back-locking-C", 363129198Scognet "**unknown 15**", 364129198Scognet}; 365129198Scognet 366153940Snetchild 367129198Scognetextern int ctrl; 368197523Srpauloenum cpu_class cpu_class = CPU_CLASS_NONE; 369129198Scognetvoid 370129198Scognetidentify_arm_cpu(void) 371129198Scognet{ 372129198Scognet u_int cpuid; 373129198Scognet int i; 374129198Scognet 375129198Scognet cpuid = cpu_id(); 376129198Scognet 377129198Scognet if (cpuid == 0) { 378129198Scognet printf("Processor failed probe - no CPU ID\n"); 379129198Scognet return; 380129198Scognet } 381129198Scognet 382129198Scognet for (i = 0; cpuids[i].cpuid != 0; i++) 383129198Scognet if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 384129198Scognet cpu_class = cpuids[i].cpu_class; 385155242Simp printf("CPU: %s %s (%s core)\n", 386129198Scognet cpuids[i].cpu_name, 387129198Scognet cpuids[i].cpu_steppings[cpuid & 388129198Scognet CPU_ID_REVISION_MASK], 389129198Scognet cpu_classes[cpu_class].class_name); 390129198Scognet break; 391129198Scognet } 392129198Scognet if (cpuids[i].cpuid == 0) 393129198Scognet printf("unknown CPU (ID = 0x%x)\n", cpuid); 394129198Scognet 395155242Simp printf(" "); 396129198Scognet switch (cpu_class) { 397129198Scognet case CPU_CLASS_ARM6: 398129198Scognet case CPU_CLASS_ARM7: 399129198Scognet case CPU_CLASS_ARM7TDMI: 400129198Scognet case CPU_CLASS_ARM8: 401129198Scognet if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 402129198Scognet printf(" IDC disabled"); 403129198Scognet else 404129198Scognet printf(" IDC enabled"); 405129198Scognet break; 406129198Scognet case CPU_CLASS_ARM9TDMI: 407172738Simp case CPU_CLASS_ARM9ES: 408172738Simp case CPU_CLASS_ARM9EJS: 409129198Scognet case CPU_CLASS_ARM10E: 410172738Simp case CPU_CLASS_ARM10EJ: 411129198Scognet case CPU_CLASS_SA1: 412129198Scognet case CPU_CLASS_XSCALE: 413172738Simp case CPU_CLASS_ARM11J: 414205027Sraj case CPU_CLASS_MARVELL: 415129198Scognet if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0) 416129198Scognet printf(" DC disabled"); 417129198Scognet else 418129198Scognet printf(" DC enabled"); 419129198Scognet if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0) 420129198Scognet printf(" IC disabled"); 421129198Scognet else 422129198Scognet printf(" IC enabled"); 423171625Scognet#ifdef CPU_XSCALE_81342 424171625Scognet if ((ctrl & CPU_CONTROL_L2_ENABLE) == 0) 425171625Scognet printf(" L2 disabled"); 426171625Scognet else 427171625Scognet printf(" L2 enabled"); 428171625Scognet#endif 429129198Scognet break; 430129198Scognet default: 431129198Scognet break; 432129198Scognet } 433129198Scognet if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 434129198Scognet printf(" WB disabled"); 435129198Scognet else 436129198Scognet printf(" WB enabled"); 437129198Scognet 438129198Scognet if (ctrl & CPU_CONTROL_LABT_ENABLE) 439129198Scognet printf(" LABT"); 440129198Scognet else 441129198Scognet printf(" EABT"); 442129198Scognet 443129198Scognet if (ctrl & CPU_CONTROL_BPRD_ENABLE) 444129198Scognet printf(" branch prediction enabled"); 445129198Scognet 446155242Simp printf("\n"); 447137272Scognet /* Print cache info. */ 448137272Scognet if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 449137272Scognet return; 450137272Scognet 451137272Scognet if (arm_pcache_unified) { 452155242Simp printf(" %dKB/%dB %d-way %s unified cache\n", 453137272Scognet arm_pdcache_size / 1024, 454137272Scognet arm_pdcache_line_size, arm_pdcache_ways, 455137272Scognet wtnames[arm_pcache_type]); 456137272Scognet } else { 457155242Simp printf(" %dKB/%dB %d-way Instruction cache\n", 458137272Scognet arm_picache_size / 1024, 459137272Scognet arm_picache_line_size, arm_picache_ways); 460155242Simp printf(" %dKB/%dB %d-way %s Data cache\n", 461137272Scognet arm_pdcache_size / 1024, 462137272Scognet arm_pdcache_line_size, arm_pdcache_ways, 463137272Scognet wtnames[arm_pcache_type]); 464137272Scognet } 465129198Scognet} 466129198Scognet 467