identcpu-v6.c revision 205027
1129198Scognet/* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1995 Mark Brinicombe. 5129198Scognet * Copyright (c) 1995 Brini. 6129198Scognet * All rights reserved. 7129198Scognet * 8129198Scognet * Redistribution and use in source and binary forms, with or without 9129198Scognet * modification, are permitted provided that the following conditions 10129198Scognet * are met: 11129198Scognet * 1. Redistributions of source code must retain the above copyright 12129198Scognet * notice, this list of conditions and the following disclaimer. 13129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 14129198Scognet * notice, this list of conditions and the following disclaimer in the 15129198Scognet * documentation and/or other materials provided with the distribution. 16129198Scognet * 3. All advertising materials mentioning features or use of this software 17129198Scognet * must display the following acknowledgement: 18129198Scognet * This product includes software developed by Brini. 19129198Scognet * 4. The name of the company nor the name of the author may be used to 20129198Scognet * endorse or promote products derived from this software without specific 21129198Scognet * prior written permission. 22129198Scognet * 23129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33129198Scognet * SUCH DAMAGE. 34129198Scognet * 35129198Scognet * RiscBSD kernel project 36129198Scognet * 37129198Scognet * cpu.c 38129198Scognet * 39129198Scognet * Probing and configuration for the master CPU 40129198Scognet * 41129198Scognet * Created : 10/10/95 42129198Scognet */ 43129198Scognet 44129198Scognet#include <sys/cdefs.h> 45129198Scognet__FBSDID("$FreeBSD: head/sys/arm/arm/identcpu.c 205027 2010-03-11 21:04:29Z raj $"); 46129198Scognet#include <sys/systm.h> 47129198Scognet#include <sys/param.h> 48129198Scognet#include <sys/malloc.h> 49129198Scognet#include <sys/time.h> 50129198Scognet#include <sys/proc.h> 51129198Scognet#include <sys/conf.h> 52135652Scognet#include <sys/kernel.h> 53135652Scognet#include <sys/sysctl.h> 54129198Scognet#include <machine/cpu.h> 55129198Scognet 56129198Scognet#include <machine/cpuconf.h> 57197523Srpaulo#include <machine/md_var.h> 58129198Scognet 59129198Scognetchar machine[] = "arm"; 60129198Scognet 61135652ScognetSYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 62135652Scognet machine, 0, "Machine class"); 63129198Scognet 64129198Scognetstatic const char * const generic_steppings[16] = { 65129198Scognet "rev 0", "rev 1", "rev 2", "rev 3", 66129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 67129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 68129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 69129198Scognet}; 70129198Scognet 71129198Scognetstatic const char * const sa110_steppings[16] = { 72129198Scognet "rev 0", "step J", "step K", "step S", 73129198Scognet "step T", "rev 5", "rev 6", "rev 7", 74129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 75129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 76129198Scognet}; 77129198Scognet 78129198Scognetstatic const char * const sa1100_steppings[16] = { 79129198Scognet "rev 0", "step B", "step C", "rev 3", 80129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 81129198Scognet "step D", "step E", "rev 10" "step G", 82129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 83129198Scognet}; 84129198Scognet 85129198Scognetstatic const char * const sa1110_steppings[16] = { 86129198Scognet "step A-0", "rev 1", "rev 2", "rev 3", 87129198Scognet "step B-0", "step B-1", "step B-2", "step B-3", 88129198Scognet "step B-4", "step B-5", "rev 10", "rev 11", 89129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 90129198Scognet}; 91129198Scognet 92129198Scognetstatic const char * const ixp12x0_steppings[16] = { 93129198Scognet "(IXP1200 step A)", "(IXP1200 step B)", 94129198Scognet "rev 2", "(IXP1200 step C)", 95129198Scognet "(IXP1200 step D)", "(IXP1240/1250 step A)", 96129198Scognet "(IXP1240 step B)", "(IXP1250 step B)", 97129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 98129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 99129198Scognet}; 100129198Scognet 101129198Scognetstatic const char * const xscale_steppings[16] = { 102129198Scognet "step A-0", "step A-1", "step B-0", "step C-0", 103129198Scognet "step D-0", "rev 5", "rev 6", "rev 7", 104129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 105129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 106129198Scognet}; 107129198Scognet 108172738Simpstatic const char * const i80219_steppings[16] = { 109172738Simp "step A-0", "rev 1", "rev 2", "rev 3", 110172738Simp "rev 4", "rev 5", "rev 6", "rev 7", 111172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 112172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 113172738Simp}; 114172738Simp 115129198Scognetstatic const char * const i80321_steppings[16] = { 116129198Scognet "step A-0", "step B-0", "rev 2", "rev 3", 117129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 118129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 119129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 120129198Scognet}; 121129198Scognet 122164080Scognetstatic const char * const i81342_steppings[16] = { 123164080Scognet "step A-0", "rev 1", "rev 2", "rev 3", 124164080Scognet "rev 4", "rev 5", "rev 6", "rev 7", 125164080Scognet "rev 8", "rev 9", "rev 10", "rev 11", 126164080Scognet "rev 12", "rev 13", "rev 14", "rev 15", 127164080Scognet}; 128164080Scognet 129172738Simp/* Steppings for PXA2[15]0 */ 130129198Scognetstatic const char * const pxa2x0_steppings[16] = { 131129198Scognet "step A-0", "step A-1", "step B-0", "step B-1", 132129198Scognet "step B-2", "step C-0", "rev 6", "rev 7", 133129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 134129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 135129198Scognet}; 136129198Scognet 137172738Simp/* Steppings for PXA255/26x. 138172738Simp * rev 5: PXA26x B0, rev 6: PXA255 A0 139172738Simp */ 140172738Simpstatic const char * const pxa255_steppings[16] = { 141172738Simp "rev 0", "rev 1", "rev 2", "step A-0", 142172738Simp "rev 4", "step B-0", "step A-0", "rev 7", 143172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 144172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 145172738Simp}; 146172738Simp 147172738Simp/* Stepping for PXA27x */ 148172738Simpstatic const char * const pxa27x_steppings[16] = { 149172738Simp "step A-0", "step A-1", "step B-0", "step B-1", 150172738Simp "step C-0", "rev 5", "rev 6", "rev 7", 151172738Simp "rev 8", "rev 9", "rev 10", "rev 11", 152172738Simp "rev 12", "rev 13", "rev 14", "rev 15", 153172738Simp}; 154172738Simp 155129198Scognetstatic const char * const ixp425_steppings[16] = { 156164423Ssam "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", 157129198Scognet "rev 4", "rev 5", "rev 6", "rev 7", 158129198Scognet "rev 8", "rev 9", "rev 10", "rev 11", 159129198Scognet "rev 12", "rev 13", "rev 14", "rev 15", 160129198Scognet}; 161129198Scognet 162129198Scognetstruct cpuidtab { 163129198Scognet u_int32_t cpuid; 164129198Scognet enum cpu_class cpu_class; 165129198Scognet const char *cpu_name; 166129198Scognet const char * const *cpu_steppings; 167129198Scognet}; 168129198Scognet 169129198Scognetconst struct cpuidtab cpuids[] = { 170129198Scognet { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 171129198Scognet generic_steppings }, 172129198Scognet { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 173129198Scognet generic_steppings }, 174129198Scognet 175129198Scognet { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 176129198Scognet generic_steppings }, 177129198Scognet 178129198Scognet { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 179129198Scognet generic_steppings }, 180129198Scognet { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 181129198Scognet generic_steppings }, 182129198Scognet { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 183129198Scognet generic_steppings }, 184129198Scognet 185129198Scognet { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 186129198Scognet generic_steppings }, 187129198Scognet { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 188129198Scognet generic_steppings }, 189129198Scognet { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 190129198Scognet generic_steppings }, 191129198Scognet { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 192129198Scognet generic_steppings }, 193129198Scognet { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 194129198Scognet generic_steppings }, 195129198Scognet { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 196129198Scognet generic_steppings }, 197129198Scognet { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 198129198Scognet generic_steppings }, 199129198Scognet { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 200129198Scognet generic_steppings }, 201129198Scognet { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 202129198Scognet generic_steppings }, 203129198Scognet 204129198Scognet { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 205129198Scognet generic_steppings }, 206129198Scognet 207129198Scognet { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 208129198Scognet generic_steppings }, 209152653Scognet { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", 210152653Scognet generic_steppings }, 211129198Scognet { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 212129198Scognet generic_steppings }, 213172738Simp { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 214172738Simp generic_steppings }, 215129198Scognet { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 216129198Scognet generic_steppings }, 217129198Scognet { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 218129198Scognet generic_steppings }, 219129198Scognet { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 220129198Scognet generic_steppings }, 221129198Scognet { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 222129198Scognet generic_steppings }, 223204122Skevlo { CPU_ID_FA526, CPU_CLASS_ARM9, "FA526", 224204122Skevlo generic_steppings }, 225204122Skevlo 226129198Scognet { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 227129198Scognet generic_steppings }, 228129198Scognet 229129198Scognet { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 230129198Scognet generic_steppings }, 231129198Scognet { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 232129198Scognet generic_steppings }, 233172738Simp { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 234172738Simp generic_steppings }, 235129198Scognet 236129198Scognet { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 237129198Scognet sa110_steppings }, 238129198Scognet { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 239129198Scognet sa1100_steppings }, 240129198Scognet { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 241129198Scognet sa1110_steppings }, 242129198Scognet 243129198Scognet { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 244129198Scognet ixp12x0_steppings }, 245129198Scognet 246129198Scognet { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 247129198Scognet xscale_steppings }, 248129198Scognet 249129198Scognet { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 250129198Scognet i80321_steppings }, 251129198Scognet { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 252129198Scognet i80321_steppings }, 253129198Scognet { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 254129198Scognet i80321_steppings }, 255129198Scognet { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 256129198Scognet i80321_steppings }, 257129198Scognet 258164080Scognet { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342", 259164080Scognet i81342_steppings }, 260164080Scognet 261161592Scognet { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 262172738Simp i80219_steppings }, 263161592Scognet { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 264172738Simp i80219_steppings }, 265161592Scognet 266172738Simp { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 267172738Simp pxa27x_steppings }, 268129198Scognet { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 269129198Scognet pxa2x0_steppings }, 270129198Scognet { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 271129198Scognet pxa2x0_steppings }, 272129198Scognet { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 273129198Scognet pxa2x0_steppings }, 274129198Scognet { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 275129198Scognet pxa2x0_steppings }, 276172738Simp { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255", 277172738Simp pxa255_steppings }, 278129198Scognet { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 279129198Scognet pxa2x0_steppings }, 280129198Scognet 281129198Scognet { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 282129198Scognet ixp425_steppings }, 283129198Scognet { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 284129198Scognet ixp425_steppings }, 285129198Scognet { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 286129198Scognet ixp425_steppings }, 287129198Scognet 288186352Ssam /* XXX ixp435 steppings? */ 289186352Ssam { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", 290186352Ssam ixp425_steppings }, 291186352Ssam 292172738Simp { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 293172738Simp generic_steppings }, 294172738Simp { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 295172738Simp generic_steppings }, 296172738Simp 297183835Sraj { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", 298183835Sraj generic_steppings }, 299183835Sraj 300183835Sraj { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", 301183835Sraj generic_steppings }, 302183835Sraj 303183835Sraj { CPU_ID_MV88FR571_41, CPU_CLASS_MARVELL, "Early Feroceon 88FR571", 304183835Sraj generic_steppings }, 305183835Sraj 306129198Scognet { 0, CPU_CLASS_NONE, NULL, NULL } 307129198Scognet}; 308129198Scognet 309129198Scognetstruct cpu_classtab { 310129198Scognet const char *class_name; 311129198Scognet const char *class_option; 312129198Scognet}; 313129198Scognet 314129198Scognetconst struct cpu_classtab cpu_classes[] = { 315129198Scognet { "unknown", NULL }, /* CPU_CLASS_NONE */ 316129198Scognet { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 317129198Scognet { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 318129198Scognet { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 319129198Scognet { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 320129198Scognet { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 321129198Scognet { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 322129198Scognet { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 323204122Skevlo { "ARM9", "CPU_ARM9" }, /* CPU_CLASS_ARM9 */ 324155242Simp { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ 325172738Simp { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ 326172738Simp { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ 327129198Scognet { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 328172738Simp { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 329129198Scognet { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 330129198Scognet { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 331172738Simp { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 332205027Sraj { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ 333129198Scognet}; 334129198Scognet 335129198Scognet/* 336129198Scognet * Report the type of the specified arm processor. This uses the generic and 337129198Scognet * arm specific information in the cpu structure to identify the processor. 338129198Scognet * The remaining fields in the cpu structure are filled in appropriately. 339129198Scognet */ 340129198Scognet 341129198Scognetstatic const char * const wtnames[] = { 342129198Scognet "write-through", 343129198Scognet "write-back", 344129198Scognet "write-back", 345129198Scognet "**unknown 3**", 346129198Scognet "**unknown 4**", 347129198Scognet "write-back-locking", /* XXX XScale-specific? */ 348129198Scognet "write-back-locking-A", 349129198Scognet "write-back-locking-B", 350129198Scognet "**unknown 8**", 351129198Scognet "**unknown 9**", 352129198Scognet "**unknown 10**", 353129198Scognet "**unknown 11**", 354129198Scognet "**unknown 12**", 355129198Scognet "**unknown 13**", 356172738Simp "write-back-locking-C", 357129198Scognet "**unknown 15**", 358129198Scognet}; 359129198Scognet 360153940Snetchild 361129198Scognetextern int ctrl; 362197523Srpauloenum cpu_class cpu_class = CPU_CLASS_NONE; 363129198Scognetvoid 364129198Scognetidentify_arm_cpu(void) 365129198Scognet{ 366129198Scognet u_int cpuid; 367129198Scognet int i; 368129198Scognet 369129198Scognet cpuid = cpu_id(); 370129198Scognet 371129198Scognet if (cpuid == 0) { 372129198Scognet printf("Processor failed probe - no CPU ID\n"); 373129198Scognet return; 374129198Scognet } 375129198Scognet 376129198Scognet for (i = 0; cpuids[i].cpuid != 0; i++) 377129198Scognet if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 378129198Scognet cpu_class = cpuids[i].cpu_class; 379155242Simp printf("CPU: %s %s (%s core)\n", 380129198Scognet cpuids[i].cpu_name, 381129198Scognet cpuids[i].cpu_steppings[cpuid & 382129198Scognet CPU_ID_REVISION_MASK], 383129198Scognet cpu_classes[cpu_class].class_name); 384129198Scognet break; 385129198Scognet } 386129198Scognet if (cpuids[i].cpuid == 0) 387129198Scognet printf("unknown CPU (ID = 0x%x)\n", cpuid); 388129198Scognet 389155242Simp printf(" "); 390129198Scognet switch (cpu_class) { 391129198Scognet case CPU_CLASS_ARM6: 392129198Scognet case CPU_CLASS_ARM7: 393129198Scognet case CPU_CLASS_ARM7TDMI: 394129198Scognet case CPU_CLASS_ARM8: 395129198Scognet if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 396129198Scognet printf(" IDC disabled"); 397129198Scognet else 398129198Scognet printf(" IDC enabled"); 399129198Scognet break; 400129198Scognet case CPU_CLASS_ARM9TDMI: 401172738Simp case CPU_CLASS_ARM9ES: 402172738Simp case CPU_CLASS_ARM9EJS: 403129198Scognet case CPU_CLASS_ARM10E: 404172738Simp case CPU_CLASS_ARM10EJ: 405129198Scognet case CPU_CLASS_SA1: 406129198Scognet case CPU_CLASS_XSCALE: 407172738Simp case CPU_CLASS_ARM11J: 408205027Sraj case CPU_CLASS_MARVELL: 409129198Scognet if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0) 410129198Scognet printf(" DC disabled"); 411129198Scognet else 412129198Scognet printf(" DC enabled"); 413129198Scognet if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0) 414129198Scognet printf(" IC disabled"); 415129198Scognet else 416129198Scognet printf(" IC enabled"); 417171625Scognet#ifdef CPU_XSCALE_81342 418171625Scognet if ((ctrl & CPU_CONTROL_L2_ENABLE) == 0) 419171625Scognet printf(" L2 disabled"); 420171625Scognet else 421171625Scognet printf(" L2 enabled"); 422171625Scognet#endif 423129198Scognet break; 424129198Scognet default: 425129198Scognet break; 426129198Scognet } 427129198Scognet if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 428129198Scognet printf(" WB disabled"); 429129198Scognet else 430129198Scognet printf(" WB enabled"); 431129198Scognet 432129198Scognet if (ctrl & CPU_CONTROL_LABT_ENABLE) 433129198Scognet printf(" LABT"); 434129198Scognet else 435129198Scognet printf(" EABT"); 436129198Scognet 437129198Scognet if (ctrl & CPU_CONTROL_BPRD_ENABLE) 438129198Scognet printf(" branch prediction enabled"); 439129198Scognet 440155242Simp printf("\n"); 441137272Scognet /* Print cache info. */ 442137272Scognet if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 443137272Scognet return; 444137272Scognet 445137272Scognet if (arm_pcache_unified) { 446155242Simp printf(" %dKB/%dB %d-way %s unified cache\n", 447137272Scognet arm_pdcache_size / 1024, 448137272Scognet arm_pdcache_line_size, arm_pdcache_ways, 449137272Scognet wtnames[arm_pcache_type]); 450137272Scognet } else { 451155242Simp printf(" %dKB/%dB %d-way Instruction cache\n", 452137272Scognet arm_picache_size / 1024, 453137272Scognet arm_picache_line_size, arm_picache_ways); 454155242Simp printf(" %dKB/%dB %d-way %s Data cache\n", 455137272Scognet arm_pdcache_size / 1024, 456137272Scognet arm_pdcache_line_size, arm_pdcache_ways, 457137272Scognet wtnames[arm_pcache_type]); 458137272Scognet } 459129198Scognet} 460129198Scognet 461