1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/11/sys/arm/altera/socfpga/socfpga_mp.c 307344 2016-10-15 08:27:54Z mmel $");
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/kernel.h>
37#include <sys/lock.h>
38#include <sys/mutex.h>
39#include <sys/smp.h>
40
41#include <vm/vm.h>
42#include <vm/pmap.h>
43
44#include <machine/cpu.h>
45#include <machine/smp.h>
46#include <machine/fdt.h>
47#include <machine/intr.h>
48
49#define	SCU_PHYSBASE			0xFFFEC000
50#define	SCU_SIZE			0x100
51
52#define	SCU_CONTROL_REG			0x00
53#define	 SCU_CONTROL_ENABLE		(1 << 0)
54#define	SCU_CONFIG_REG			0x04
55#define	 SCU_CONFIG_REG_NCPU_MASK	0x03
56#define	SCU_CPUPOWER_REG		0x08
57#define	SCU_INV_TAGS_REG		0x0c
58#define	SCU_DIAG_CONTROL		0x30
59#define	 SCU_DIAG_DISABLE_MIGBIT	(1 << 0)
60#define	SCU_FILTER_START_REG		0x40
61#define	SCU_FILTER_END_REG		0x44
62#define	SCU_SECURE_ACCESS_REG		0x50
63#define	SCU_NONSECURE_ACCESS_REG	0x54
64
65#define	RSTMGR_PHYSBASE			0xFFD05000
66#define	RSTMGR_SIZE			0x100
67#define	MPUMODRST			0x10
68#define	 MPUMODRST_CPU1			(1 << 1)
69
70#define	RAM_PHYSBASE			0x0
71#define	 RAM_SIZE			0x1000
72
73extern char	*mpentry_addr;
74static void	socfpga_trampoline(void);
75
76static void
77socfpga_trampoline(void)
78{
79
80	__asm __volatile(
81			"ldr pc, 1f\n"
82			".globl mpentry_addr\n"
83			"mpentry_addr:\n"
84			"1: .space 4\n");
85}
86
87void
88platform_mp_setmaxid(void)
89{
90	int hwcpu, ncpu;
91
92	/* If we've already set this don't bother to do it again. */
93	if (mp_ncpus != 0)
94		return;
95
96	hwcpu = 2;
97
98	ncpu = hwcpu;
99	TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
100	if (ncpu < 1 || ncpu > hwcpu)
101		ncpu = hwcpu;
102
103	mp_ncpus = ncpu;
104	mp_maxid = ncpu - 1;
105}
106
107void
108platform_mp_start_ap(void)
109{
110	bus_space_handle_t scu, rst, ram;
111	int reg;
112
113	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
114					SCU_SIZE, 0, &scu) != 0)
115		panic("Couldn't map the SCU\n");
116	if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
117					RSTMGR_SIZE, 0, &rst) != 0)
118		panic("Couldn't map the reset manager (RSTMGR)\n");
119	if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE,
120					RAM_SIZE, 0, &ram) != 0)
121		panic("Couldn't map the first physram page\n");
122
123	/* Invalidate SCU cache tags */
124	bus_space_write_4(fdtbus_bs_tag, scu,
125		SCU_INV_TAGS_REG, 0x0000ffff);
126
127	/*
128	 * Erratum ARM/MP: 764369 (problems with cache maintenance).
129	 * Setting the "disable-migratory bit" in the undocumented SCU
130	 * Diagnostic Control Register helps work around the problem.
131	 */
132	reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
133	reg |= (SCU_DIAG_DISABLE_MIGBIT);
134	bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
135
136	/* Put CPU1 to reset state */
137	bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, MPUMODRST_CPU1);
138
139	/* Enable the SCU, then clean the cache on this core */
140	reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
141	reg |= (SCU_CONTROL_ENABLE);
142	bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg);
143
144	/* Set up trampoline code */
145	mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
146	bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
147	    (uint32_t *)&socfpga_trampoline, 8);
148
149	dcache_wbinv_poc_all();
150
151	/* Put CPU1 out from reset */
152	bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
153
154	dsb();
155	sev();
156
157	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
158	bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
159	bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
160}
161