1271093Sbr/*- 2271093Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3271093Sbr * All rights reserved. 4271093Sbr * 5271093Sbr * This software was developed by SRI International and the University of 6271093Sbr * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7271093Sbr * ("CTSRD"), as part of the DARPA CRASH research programme. 8271093Sbr * 9271093Sbr * Redistribution and use in source and binary forms, with or without 10271093Sbr * modification, are permitted provided that the following conditions 11271093Sbr * are met: 12271093Sbr * 1. Redistributions of source code must retain the above copyright 13271093Sbr * notice, this list of conditions and the following disclaimer. 14271093Sbr * 2. Redistributions in binary form must reproduce the above copyright 15271093Sbr * notice, this list of conditions and the following disclaimer in the 16271093Sbr * documentation and/or other materials provided with the distribution. 17271093Sbr * 18271093Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19271093Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20271093Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21271093Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22271093Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23271093Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24271093Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25271093Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26271093Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27271093Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28271093Sbr * SUCH DAMAGE. 29271093Sbr */ 30271093Sbr 31271093Sbr#include <sys/cdefs.h> 32271093Sbr__FBSDID("$FreeBSD: stable/11/sys/arm/altera/socfpga/socfpga_common.c 314506 2017-03-01 19:55:04Z ian $"); 33271093Sbr 34271093Sbr#include <sys/param.h> 35271093Sbr#include <sys/systm.h> 36271093Sbr#include <sys/bus.h> 37271093Sbr#include <sys/kernel.h> 38271093Sbr 39271093Sbr#include <dev/ofw/openfirm.h> 40271093Sbr 41271093Sbr#include <machine/bus.h> 42271093Sbr#include <machine/fdt.h> 43271093Sbr 44271431Sbr#include <arm/altera/socfpga/socfpga_rstmgr.h> 45271093Sbr 46271093Sbrvoid 47271093Sbrcpu_reset(void) 48271093Sbr{ 49314503Sian uint32_t paddr; 50271093Sbr bus_addr_t vaddr; 51271431Sbr phandle_t node; 52271093Sbr 53271431Sbr if (rstmgr_warmreset() == 0) 54271431Sbr goto end; 55271431Sbr 56271431Sbr node = OF_finddevice("rstmgr"); 57271431Sbr if (node == -1) 58271431Sbr goto end; 59271431Sbr 60314503Sian if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { 61314503Sian if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) { 62271431Sbr bus_space_write_4(fdtbus_bs_tag, vaddr, 63271431Sbr RSTMGR_CTRL, CTRL_SWWARMRSTREQ); 64271431Sbr } 65271093Sbr } 66271093Sbr 67271431Sbrend: 68271093Sbr while (1); 69271093Sbr} 70271093Sbr 71298068Sandrew#ifndef INTRNG 72271093Sbrstatic int 73271093Sbrfdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 74271093Sbr int *pol) 75271093Sbr{ 76271093Sbr 77271093Sbr if (!fdt_is_compatible(node, "arm,gic")) 78271093Sbr return (ENXIO); 79271093Sbr 80271093Sbr *interrupt = fdt32_to_cpu(intr[0]); 81271093Sbr *trig = INTR_TRIGGER_CONFORM; 82271093Sbr *pol = INTR_POLARITY_CONFORM; 83271093Sbr return (0); 84271093Sbr} 85271093Sbr 86271093Sbrfdt_pic_decode_t fdt_pic_table[] = { 87271093Sbr &fdt_pic_decode_ic, 88271093Sbr NULL 89271093Sbr}; 90295509Sandrew#endif 91