1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/11/sys/arm/altera/socfpga/socfpga_common.c 314506 2017-03-01 19:55:04Z ian $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38
39#include <dev/ofw/openfirm.h>
40
41#include <machine/bus.h>
42#include <machine/fdt.h>
43
44#include <arm/altera/socfpga/socfpga_rstmgr.h>
45
46void
47cpu_reset(void)
48{
49	uint32_t paddr;
50	bus_addr_t vaddr;
51	phandle_t node;
52
53	if (rstmgr_warmreset() == 0)
54		goto end;
55
56	node = OF_finddevice("rstmgr");
57	if (node == -1)
58		goto end;
59
60	if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
61		if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) {
62			bus_space_write_4(fdtbus_bs_tag, vaddr,
63			    RSTMGR_CTRL, CTRL_SWWARMRSTREQ);
64		}
65	}
66
67end:
68	while (1);
69}
70
71#ifndef INTRNG
72static int
73fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
74    int *pol)
75{
76
77	if (!fdt_is_compatible(node, "arm,gic"))
78		return (ENXIO);
79
80	*interrupt = fdt32_to_cpu(intr[0]);
81	*trig = INTR_TRIGGER_CONFORM;
82	*pol = INTR_POLARITY_CONFORM;
83	return (0);
84}
85
86fdt_pic_decode_t fdt_pic_table[] = {
87	&fdt_pic_decode_ic,
88	NULL
89};
90#endif
91