timer.c revision 245876 
1/*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/arm/allwinner/timer.c 245876 2013-01-24 09:36:50Z ganbold $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/malloc.h>
36#include <sys/rman.h>
37#include <sys/timeet.h>
38#include <sys/timetc.h>
39#include <sys/watchdog.h>
40#include <machine/bus.h>
41#include <machine/cpu.h>
42#include <machine/frame.h>
43#include <machine/intr.h>
44
45#include <dev/fdt/fdt_common.h>
46#include <dev/ofw/openfirm.h>
47#include <dev/ofw/ofw_bus.h>
48#include <dev/ofw/ofw_bus_subr.h>
49
50#include <machine/bus.h>
51#include <machine/fdt.h>
52
53#include <sys/kdb.h>
54
55/**
56 * Timer registers addr
57 *
58 */
59#define SW_TIMER_IRQ_EN_REG 	0x00
60#define SW_TIMER_IRQ_STA_REG 	0x04
61#define SW_TIMER0_CTRL_REG 	0x10
62#define SW_TIMER0_INT_VALUE_REG	0x14
63#define SW_TIMER0_CUR_VALUE_REG	0x18
64
65#define SW_COUNTER64LO_REG	0xa4
66#define SW_COUNTER64HI_REG	0xa8
67#define CNT64_CTRL_REG		0xa0
68
69#define CNT64_RL_EN		0x02 /* read latch enable */
70
71#define TIMER_ENABLE		(1<<0)
72#define TIMER_AUTORELOAD	(1<<1)
73#define TIMER_OSC24M		(1<<2) /* oscillator = 24mhz */
74#define TIMER_PRESCALAR		(4<<4) /* prescalar = 16 */
75
76#define SYS_TIMER_CLKSRC	24000000 /* clock source */
77
78struct a10_timer_softc {
79	device_t 	sc_dev;
80	struct resource *res[2];
81	bus_space_tag_t sc_bst;
82	bus_space_handle_t sc_bsh;
83	void 		*sc_ih;		/* interrupt handler */
84	uint32_t 	sc_period;
85	uint32_t 	timer0_freq;
86	struct eventtimer et;
87};
88
89int a10_timer_get_timerfreq(struct a10_timer_softc *);
90
91#define timer_read_4(sc, reg)	\
92	bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
93#define timer_write_4(sc, reg, val)	\
94	bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
95
96static u_int	a10_timer_get_timecount(struct timecounter *);
97static int	a10_timer_timer_start(struct eventtimer *,
98    struct bintime *, struct bintime *);
99static int	a10_timer_timer_stop(struct eventtimer *);
100
101static uint64_t timer_read_counter64(void);
102
103static int a10_timer_initialized = 0;
104static int a10_timer_hardclock(void *);
105static int a10_timer_probe(device_t);
106static int a10_timer_attach(device_t);
107
108static struct timecounter a10_timer_timecounter = {
109	.tc_name           = "a10_timer timer0",
110	.tc_get_timecount  = a10_timer_get_timecount,
111	.tc_counter_mask   = ~0u,
112	.tc_frequency      = 0,
113	.tc_quality        = 1000,
114};
115
116struct a10_timer_softc *a10_timer_sc = NULL;
117
118static struct resource_spec a10_timer_spec[] = {
119	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
120	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
121	{ -1, 0 }
122};
123
124static uint64_t
125timer_read_counter64(void)
126{
127	uint32_t lo, hi;
128
129	/* Latch counter, wait for it to be ready to read. */
130	timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
131	while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
132		continue;
133
134	hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
135	lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
136
137	return (((uint64_t)hi << 32) | lo);
138}
139
140static int
141a10_timer_probe(device_t dev)
142{
143
144	if (!ofw_bus_is_compatible(dev, "a10,timers"))
145		return (ENXIO);
146
147	device_set_desc(dev, "Allwinner A10 timer");
148	return (BUS_PROBE_DEFAULT);
149}
150
151static int
152a10_timer_attach(device_t dev)
153{
154	struct a10_timer_softc *sc;
155	int err;
156	uint32_t val;
157
158	sc = device_get_softc(dev);
159
160	if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
161		device_printf(dev, "could not allocate resources\n");
162		return (ENXIO);
163	}
164
165	sc->sc_dev = dev;
166	sc->sc_bst = rman_get_bustag(sc->res[0]);
167	sc->sc_bsh = rman_get_bushandle(sc->res[0]);
168
169	/* Setup and enable the timer interrupt */
170	err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
171	    NULL, sc, &sc->sc_ih);
172	if (err != 0) {
173		bus_release_resources(dev, a10_timer_spec, sc->res);
174		device_printf(dev, "Unable to setup the clock irq handler, "
175		    "err = %d\n", err);
176		return (ENXIO);
177	}
178
179	/* Set clock source to OSC24M, 16 pre-division */
180	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
181	val |= TIMER_PRESCALAR | TIMER_OSC24M;
182	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
183
184	/* Enable timer0 */
185	val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
186	val |= TIMER_ENABLE;
187	timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
188
189	sc->timer0_freq = SYS_TIMER_CLKSRC;
190
191	/* Set desired frequency in event timer and timecounter */
192	sc->et.et_frequency = sc->timer0_freq;
193	sc->et.et_name = "a10_timer Eventtimer";
194	sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
195	sc->et.et_quality = 1000;
196	sc->et.et_min_period.sec = 0;
197	sc->et.et_min_period.frac =
198	    ((0x00000005LLU << 32) / sc->et.et_frequency) << 32;
199	sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency;
200	sc->et.et_max_period.frac =
201	    ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
202	sc->et.et_start = a10_timer_timer_start;
203	sc->et.et_stop = a10_timer_timer_stop;
204	sc->et.et_priv = sc;
205	et_register(&sc->et);
206
207	if (device_get_unit(dev) == 0)
208		a10_timer_sc = sc;
209
210	a10_timer_timecounter.tc_frequency = sc->timer0_freq;
211	tc_init(&a10_timer_timecounter);
212
213	if (bootverbose) {
214		device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
215
216		device_printf(sc->sc_dev, "event timer clock frequency %u\n",
217		    sc->timer0_freq);
218		device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
219		    a10_timer_timecounter.tc_frequency);
220	}
221
222	a10_timer_initialized = 1;
223
224	return (0);
225}
226
227static int
228a10_timer_timer_start(struct eventtimer *et, struct bintime *first,
229    struct bintime *period)
230{
231	struct a10_timer_softc *sc;
232	uint32_t count;
233	uint32_t val;
234
235	sc = (struct a10_timer_softc *)et->et_priv;
236
237	sc->sc_period = 0;
238
239	if (period != NULL) {
240		sc->sc_period = (sc->et.et_frequency * (period->frac >> 32)) >> 32;
241		sc->sc_period += sc->et.et_frequency * period->sec;
242	}
243	if (first == NULL)
244		count = sc->sc_period;
245	else {
246		count = (sc->et.et_frequency * (first->frac >> 32)) >> 32;
247		if (first->sec != 0)
248			count += sc->et.et_frequency * first->sec;
249	}
250
251	/* Update timer values */
252	timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
253	timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
254
255	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
256	if (first == NULL) {
257		/* periodic */
258		val |= TIMER_AUTORELOAD;
259	} else {
260		/* oneshot */
261		val &= ~TIMER_AUTORELOAD;
262	}
263	/* Enable timer0 */
264	val |= TIMER_ENABLE;
265	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
266
267	return (0);
268}
269
270static int
271a10_timer_timer_stop(struct eventtimer *et)
272{
273	struct a10_timer_softc *sc;
274	uint32_t val;
275
276	sc = (struct a10_timer_softc *)et->et_priv;
277
278	/* Disable timer0 */
279	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
280	val &= ~TIMER_ENABLE;
281	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
282
283	sc->sc_period = 0;
284
285	return (0);
286}
287
288int
289a10_timer_get_timerfreq(struct a10_timer_softc *sc)
290{
291	return (sc->timer0_freq);
292}
293
294void
295cpu_initclocks(void)
296{
297	cpu_initclocks_bsp();
298}
299
300static int
301a10_timer_hardclock(void *arg)
302{
303	struct a10_timer_softc *sc;
304	uint32_t val;
305
306	sc = (struct a10_timer_softc *)arg;
307
308	/* Clear interrupt pending bit. */
309	timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
310
311	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
312	/*
313	 * Disabled autoreload and sc_period > 0 means
314	 * timer_start was called with non NULL first value.
315	 * Now we will set periodic timer with the given period
316	 * value.
317	 */
318	if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
319		/* Update timer */
320		timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
321
322		/* Make periodic and enable */
323		val |= TIMER_AUTORELOAD | TIMER_ENABLE;
324		timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
325	}
326
327	if (sc->et.et_active)
328		sc->et.et_event_cb(&sc->et, sc->et.et_arg);
329
330	return (FILTER_HANDLED);
331}
332
333u_int
334a10_timer_get_timecount(struct timecounter *tc)
335{
336
337	if (a10_timer_sc == NULL)
338		return (0);
339
340	return ((u_int)timer_read_counter64());
341}
342
343static device_method_t a10_timer_methods[] = {
344	DEVMETHOD(device_probe,		a10_timer_probe),
345	DEVMETHOD(device_attach,	a10_timer_attach),
346
347	DEVMETHOD_END
348};
349
350static driver_t a10_timer_driver = {
351	"a10_timer",
352	a10_timer_methods,
353	sizeof(struct a10_timer_softc),
354};
355
356static devclass_t a10_timer_devclass;
357
358DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0);
359
360void
361DELAY(int usec)
362{
363	uint32_t counter;
364	uint64_t end, now;
365
366	if (!a10_timer_initialized) {
367		for (; usec > 0; usec--)
368			for (counter = 50; counter > 0; counter--)
369				cpufunc_nullop();
370		return;
371	}
372
373	now = timer_read_counter64();
374	end = now + (a10_timer_sc->timer0_freq / 1000000) * (usec + 1);
375
376	while (now < end)
377		now = timer_read_counter64();
378}
379
380