1/*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/11/sys/arm/allwinner/timer.c 308274 2016-11-04 00:54:21Z manu $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34#include <sys/module.h>
35#include <sys/malloc.h>
36#include <sys/rman.h>
37#include <sys/timeet.h>
38#include <sys/timetc.h>
39#include <sys/watchdog.h>
40#include <machine/bus.h>
41#include <machine/cpu.h>
42#include <machine/intr.h>
43#include <machine/machdep.h>
44
45#include <dev/fdt/fdt_common.h>
46#include <dev/ofw/openfirm.h>
47#include <dev/ofw/ofw_bus.h>
48#include <dev/ofw/ofw_bus_subr.h>
49
50#include <machine/bus.h>
51
52#include <sys/kdb.h>
53
54#include <arm/allwinner/aw_machdep.h>
55
56/**
57 * Timer registers addr
58 *
59 */
60#define SW_TIMER_IRQ_EN_REG 	0x00
61#define SW_TIMER_IRQ_STA_REG 	0x04
62#define SW_TIMER0_CTRL_REG 	0x10
63#define SW_TIMER0_INT_VALUE_REG	0x14
64#define SW_TIMER0_CUR_VALUE_REG	0x18
65
66#define SW_COUNTER64LO_REG	0xa4
67#define SW_COUNTER64HI_REG	0xa8
68#define CNT64_CTRL_REG		0xa0
69
70#define CNT64_RL_EN		0x02 /* read latch enable */
71
72#define TIMER_ENABLE		(1<<0)
73#define TIMER_AUTORELOAD	(1<<1)
74#define TIMER_OSC24M		(1<<2) /* oscillator = 24mhz */
75#define TIMER_PRESCALAR		(0<<4) /* prescalar = 1 */
76
77#define SYS_TIMER_CLKSRC	24000000 /* clock source */
78
79struct a10_timer_softc {
80	device_t 	sc_dev;
81	struct resource *res[2];
82	bus_space_tag_t sc_bst;
83	bus_space_handle_t sc_bsh;
84	void 		*sc_ih;		/* interrupt handler */
85	uint32_t 	sc_period;
86	uint32_t 	timer0_freq;
87	struct eventtimer et;
88};
89
90int a10_timer_get_timerfreq(struct a10_timer_softc *);
91
92#define timer_read_4(sc, reg)	\
93	bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
94#define timer_write_4(sc, reg, val)	\
95	bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
96
97static u_int	a10_timer_get_timecount(struct timecounter *);
98static int	a10_timer_timer_start(struct eventtimer *,
99    sbintime_t first, sbintime_t period);
100static int	a10_timer_timer_stop(struct eventtimer *);
101
102static uint64_t timer_read_counter64(void);
103
104static int a10_timer_hardclock(void *);
105static int a10_timer_probe(device_t);
106static int a10_timer_attach(device_t);
107
108static delay_func a10_timer_delay;
109
110static struct timecounter a10_timer_timecounter = {
111	.tc_name           = "a10_timer timer0",
112	.tc_get_timecount  = a10_timer_get_timecount,
113	.tc_counter_mask   = ~0u,
114	.tc_frequency      = 0,
115	.tc_quality        = 1000,
116};
117
118struct a10_timer_softc *a10_timer_sc = NULL;
119
120static struct resource_spec a10_timer_spec[] = {
121	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
122	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
123	{ -1, 0 }
124};
125
126static uint64_t
127timer_read_counter64(void)
128{
129	uint32_t lo, hi;
130
131	/* Latch counter, wait for it to be ready to read. */
132	timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
133	while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
134		continue;
135
136	hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
137	lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
138
139	return (((uint64_t)hi << 32) | lo);
140}
141
142static int
143a10_timer_probe(device_t dev)
144{
145	struct a10_timer_softc *sc;
146	u_int soc_family;
147
148	sc = device_get_softc(dev);
149
150	if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-timer"))
151		return (ENXIO);
152
153	soc_family = allwinner_soc_family();
154	if (soc_family != ALLWINNERSOC_SUN4I &&
155	    soc_family != ALLWINNERSOC_SUN5I)
156		return (ENXIO);
157
158	device_set_desc(dev, "Allwinner A10/A20 timer");
159	return (BUS_PROBE_DEFAULT);
160}
161
162static int
163a10_timer_attach(device_t dev)
164{
165	struct a10_timer_softc *sc;
166	int err;
167	uint32_t val;
168
169	sc = device_get_softc(dev);
170
171	if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
172		device_printf(dev, "could not allocate resources\n");
173		return (ENXIO);
174	}
175
176	sc->sc_dev = dev;
177	sc->sc_bst = rman_get_bustag(sc->res[0]);
178	sc->sc_bsh = rman_get_bushandle(sc->res[0]);
179
180	/* Setup and enable the timer interrupt */
181	err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
182	    NULL, sc, &sc->sc_ih);
183	if (err != 0) {
184		bus_release_resources(dev, a10_timer_spec, sc->res);
185		device_printf(dev, "Unable to setup the clock irq handler, "
186		    "err = %d\n", err);
187		return (ENXIO);
188	}
189
190	/* Set clock source to OSC24M, 16 pre-division */
191	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
192	val |= TIMER_PRESCALAR | TIMER_OSC24M;
193	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
194
195	/* Enable timer0 */
196	val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
197	val |= TIMER_ENABLE;
198	timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
199
200	sc->timer0_freq = SYS_TIMER_CLKSRC;
201
202	/* Set desired frequency in event timer and timecounter */
203	sc->et.et_frequency = sc->timer0_freq;
204	sc->et.et_name = "a10_timer Eventtimer";
205	sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
206	sc->et.et_quality = 1000;
207	sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
208	sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
209	sc->et.et_start = a10_timer_timer_start;
210	sc->et.et_stop = a10_timer_timer_stop;
211	sc->et.et_priv = sc;
212	et_register(&sc->et);
213
214	if (device_get_unit(dev) == 0) {
215		arm_set_delay(a10_timer_delay, sc);
216		a10_timer_sc = sc;
217	}
218
219	a10_timer_timecounter.tc_frequency = sc->timer0_freq;
220	tc_init(&a10_timer_timecounter);
221
222	if (bootverbose) {
223		device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
224
225		device_printf(sc->sc_dev, "event timer clock frequency %u\n",
226		    sc->timer0_freq);
227		device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
228		    a10_timer_timecounter.tc_frequency);
229	}
230
231	return (0);
232}
233
234static int
235a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
236    sbintime_t period)
237{
238	struct a10_timer_softc *sc;
239	uint32_t count;
240	uint32_t val;
241
242	sc = (struct a10_timer_softc *)et->et_priv;
243
244	if (period != 0)
245		sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
246	else
247		sc->sc_period = 0;
248	if (first != 0)
249		count = ((uint32_t)et->et_frequency * first) >> 32;
250	else
251		count = sc->sc_period;
252
253	/* Update timer values */
254	timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
255	timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
256
257	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
258	if (period != 0) {
259		/* periodic */
260		val |= TIMER_AUTORELOAD;
261	} else {
262		/* oneshot */
263		val &= ~TIMER_AUTORELOAD;
264	}
265	/* Enable timer0 */
266	val |= TIMER_ENABLE;
267	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
268
269	return (0);
270}
271
272static int
273a10_timer_timer_stop(struct eventtimer *et)
274{
275	struct a10_timer_softc *sc;
276	uint32_t val;
277
278	sc = (struct a10_timer_softc *)et->et_priv;
279
280	/* Disable timer0 */
281	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
282	val &= ~TIMER_ENABLE;
283	timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
284
285	sc->sc_period = 0;
286
287	return (0);
288}
289
290int
291a10_timer_get_timerfreq(struct a10_timer_softc *sc)
292{
293	return (sc->timer0_freq);
294}
295
296static int
297a10_timer_hardclock(void *arg)
298{
299	struct a10_timer_softc *sc;
300	uint32_t val;
301
302	sc = (struct a10_timer_softc *)arg;
303
304	/* Clear interrupt pending bit. */
305	timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
306
307	val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
308	/*
309	 * Disabled autoreload and sc_period > 0 means
310	 * timer_start was called with non NULL first value.
311	 * Now we will set periodic timer with the given period
312	 * value.
313	 */
314	if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
315		/* Update timer */
316		timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
317
318		/* Make periodic and enable */
319		val |= TIMER_AUTORELOAD | TIMER_ENABLE;
320		timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
321	}
322
323	if (sc->et.et_active)
324		sc->et.et_event_cb(&sc->et, sc->et.et_arg);
325
326	return (FILTER_HANDLED);
327}
328
329u_int
330a10_timer_get_timecount(struct timecounter *tc)
331{
332
333	if (a10_timer_sc == NULL)
334		return (0);
335
336	return ((u_int)timer_read_counter64());
337}
338
339static device_method_t a10_timer_methods[] = {
340	DEVMETHOD(device_probe,		a10_timer_probe),
341	DEVMETHOD(device_attach,	a10_timer_attach),
342
343	DEVMETHOD_END
344};
345
346static driver_t a10_timer_driver = {
347	"a10_timer",
348	a10_timer_methods,
349	sizeof(struct a10_timer_softc),
350};
351
352static devclass_t a10_timer_devclass;
353
354EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0,
355    BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
356
357static void
358a10_timer_delay(int usec, void *arg)
359{
360	struct a10_timer_softc *sc = arg;
361	uint64_t end, now;
362
363	now = timer_read_counter64();
364	end = now + (sc->timer0_freq / 1000000) * (usec + 1);
365
366	while (now < end)
367		now = timer_read_counter64();
368}
369