1245450Sganbold/*- 2263711Sganbold * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3245450Sganbold * All rights reserved. 4245450Sganbold * 5245450Sganbold * Redistribution and use in source and binary forms, with or without 6245450Sganbold * modification, are permitted provided that the following conditions 7245450Sganbold * are met: 8245453Sganbold * 1. Redistributions of source code must retain the above copyright 9245453Sganbold * notice, this list of conditions and the following disclaimer. 10245453Sganbold * 2. Redistributions in binary form must reproduce the above copyright 11245453Sganbold * notice, this list of conditions and the following disclaimer in the 12245453Sganbold * documentation and/or other materials provided with the distribution. 13245450Sganbold * 14245450Sganbold * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15245450Sganbold * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16245450Sganbold * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17245454Sganbold * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18245450Sganbold * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19245450Sganbold * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20245450Sganbold * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21245450Sganbold * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22245450Sganbold * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23245450Sganbold * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24245450Sganbold * SUCH DAMAGE. 25245450Sganbold */ 26245450Sganbold 27245450Sganbold#include <sys/cdefs.h> 28245450Sganbold__FBSDID("$FreeBSD: stable/11/sys/arm/allwinner/timer.c 308274 2016-11-04 00:54:21Z manu $"); 29245450Sganbold 30245450Sganbold#include <sys/param.h> 31245450Sganbold#include <sys/systm.h> 32245450Sganbold#include <sys/bus.h> 33245450Sganbold#include <sys/kernel.h> 34245450Sganbold#include <sys/module.h> 35245450Sganbold#include <sys/malloc.h> 36245450Sganbold#include <sys/rman.h> 37245450Sganbold#include <sys/timeet.h> 38245450Sganbold#include <sys/timetc.h> 39245450Sganbold#include <sys/watchdog.h> 40245450Sganbold#include <machine/bus.h> 41245450Sganbold#include <machine/cpu.h> 42245450Sganbold#include <machine/intr.h> 43298854Sandrew#include <machine/machdep.h> 44245450Sganbold 45245450Sganbold#include <dev/fdt/fdt_common.h> 46245450Sganbold#include <dev/ofw/openfirm.h> 47245450Sganbold#include <dev/ofw/ofw_bus.h> 48245450Sganbold#include <dev/ofw/ofw_bus_subr.h> 49245450Sganbold 50245450Sganbold#include <machine/bus.h> 51245450Sganbold 52245450Sganbold#include <sys/kdb.h> 53245450Sganbold 54308274Smanu#include <arm/allwinner/aw_machdep.h> 55254056Sganbold 56245450Sganbold/** 57245450Sganbold * Timer registers addr 58245450Sganbold * 59245450Sganbold */ 60245450Sganbold#define SW_TIMER_IRQ_EN_REG 0x00 61245450Sganbold#define SW_TIMER_IRQ_STA_REG 0x04 62245450Sganbold#define SW_TIMER0_CTRL_REG 0x10 63245450Sganbold#define SW_TIMER0_INT_VALUE_REG 0x14 64245450Sganbold#define SW_TIMER0_CUR_VALUE_REG 0x18 65245450Sganbold 66245876Sganbold#define SW_COUNTER64LO_REG 0xa4 67245876Sganbold#define SW_COUNTER64HI_REG 0xa8 68245876Sganbold#define CNT64_CTRL_REG 0xa0 69245450Sganbold 70245876Sganbold#define CNT64_RL_EN 0x02 /* read latch enable */ 71245450Sganbold 72245876Sganbold#define TIMER_ENABLE (1<<0) 73245876Sganbold#define TIMER_AUTORELOAD (1<<1) 74245876Sganbold#define TIMER_OSC24M (1<<2) /* oscillator = 24mhz */ 75272397Sganbold#define TIMER_PRESCALAR (0<<4) /* prescalar = 1 */ 76245876Sganbold 77245876Sganbold#define SYS_TIMER_CLKSRC 24000000 /* clock source */ 78245876Sganbold 79245450Sganboldstruct a10_timer_softc { 80245450Sganbold device_t sc_dev; 81245450Sganbold struct resource *res[2]; 82245450Sganbold bus_space_tag_t sc_bst; 83245450Sganbold bus_space_handle_t sc_bsh; 84245450Sganbold void *sc_ih; /* interrupt handler */ 85245450Sganbold uint32_t sc_period; 86245876Sganbold uint32_t timer0_freq; 87245450Sganbold struct eventtimer et; 88245450Sganbold}; 89245450Sganbold 90245450Sganboldint a10_timer_get_timerfreq(struct a10_timer_softc *); 91245450Sganbold 92245450Sganbold#define timer_read_4(sc, reg) \ 93245450Sganbold bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg) 94245450Sganbold#define timer_write_4(sc, reg, val) \ 95245450Sganbold bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val) 96245450Sganbold 97245450Sganboldstatic u_int a10_timer_get_timecount(struct timecounter *); 98245450Sganboldstatic int a10_timer_timer_start(struct eventtimer *, 99247463Smav sbintime_t first, sbintime_t period); 100245450Sganboldstatic int a10_timer_timer_stop(struct eventtimer *); 101245450Sganbold 102245876Sganboldstatic uint64_t timer_read_counter64(void); 103245876Sganbold 104245876Sganboldstatic int a10_timer_hardclock(void *); 105245450Sganboldstatic int a10_timer_probe(device_t); 106245450Sganboldstatic int a10_timer_attach(device_t); 107245450Sganbold 108298854Sandrewstatic delay_func a10_timer_delay; 109298854Sandrew 110245450Sganboldstatic struct timecounter a10_timer_timecounter = { 111245450Sganbold .tc_name = "a10_timer timer0", 112245450Sganbold .tc_get_timecount = a10_timer_get_timecount, 113245450Sganbold .tc_counter_mask = ~0u, 114245450Sganbold .tc_frequency = 0, 115245450Sganbold .tc_quality = 1000, 116245450Sganbold}; 117245450Sganbold 118245450Sganboldstruct a10_timer_softc *a10_timer_sc = NULL; 119245450Sganbold 120245450Sganboldstatic struct resource_spec a10_timer_spec[] = { 121245450Sganbold { SYS_RES_MEMORY, 0, RF_ACTIVE }, 122245450Sganbold { SYS_RES_IRQ, 0, RF_ACTIVE }, 123245450Sganbold { -1, 0 } 124245450Sganbold}; 125245450Sganbold 126245876Sganboldstatic uint64_t 127245876Sganboldtimer_read_counter64(void) 128245876Sganbold{ 129245876Sganbold uint32_t lo, hi; 130245876Sganbold 131245876Sganbold /* Latch counter, wait for it to be ready to read. */ 132245876Sganbold timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN); 133245876Sganbold while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN) 134245876Sganbold continue; 135245876Sganbold 136245876Sganbold hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG); 137245876Sganbold lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG); 138245876Sganbold 139245876Sganbold return (((uint64_t)hi << 32) | lo); 140245876Sganbold} 141245876Sganbold 142245450Sganboldstatic int 143245450Sganbolda10_timer_probe(device_t dev) 144245450Sganbold{ 145254056Sganbold struct a10_timer_softc *sc; 146295464Sandrew u_int soc_family; 147245450Sganbold 148254056Sganbold sc = device_get_softc(dev); 149254056Sganbold 150295464Sandrew if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-timer")) 151245450Sganbold return (ENXIO); 152245450Sganbold 153295464Sandrew soc_family = allwinner_soc_family(); 154295464Sandrew if (soc_family != ALLWINNERSOC_SUN4I && 155295464Sandrew soc_family != ALLWINNERSOC_SUN5I) 156295464Sandrew return (ENXIO); 157295464Sandrew 158254056Sganbold device_set_desc(dev, "Allwinner A10/A20 timer"); 159245450Sganbold return (BUS_PROBE_DEFAULT); 160245450Sganbold} 161245450Sganbold 162245450Sganboldstatic int 163245450Sganbolda10_timer_attach(device_t dev) 164245450Sganbold{ 165245450Sganbold struct a10_timer_softc *sc; 166245450Sganbold int err; 167245450Sganbold uint32_t val; 168245450Sganbold 169245450Sganbold sc = device_get_softc(dev); 170245450Sganbold 171245450Sganbold if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) { 172245450Sganbold device_printf(dev, "could not allocate resources\n"); 173245450Sganbold return (ENXIO); 174245450Sganbold } 175245450Sganbold 176245450Sganbold sc->sc_dev = dev; 177245450Sganbold sc->sc_bst = rman_get_bustag(sc->res[0]); 178245450Sganbold sc->sc_bsh = rman_get_bushandle(sc->res[0]); 179245450Sganbold 180245450Sganbold /* Setup and enable the timer interrupt */ 181245876Sganbold err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock, 182245450Sganbold NULL, sc, &sc->sc_ih); 183245450Sganbold if (err != 0) { 184245450Sganbold bus_release_resources(dev, a10_timer_spec, sc->res); 185245450Sganbold device_printf(dev, "Unable to setup the clock irq handler, " 186245450Sganbold "err = %d\n", err); 187245450Sganbold return (ENXIO); 188245450Sganbold } 189245450Sganbold 190245876Sganbold /* Set clock source to OSC24M, 16 pre-division */ 191245876Sganbold val = timer_read_4(sc, SW_TIMER0_CTRL_REG); 192245876Sganbold val |= TIMER_PRESCALAR | TIMER_OSC24M; 193245876Sganbold timer_write_4(sc, SW_TIMER0_CTRL_REG, val); 194245876Sganbold 195245876Sganbold /* Enable timer0 */ 196245876Sganbold val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG); 197245876Sganbold val |= TIMER_ENABLE; 198245876Sganbold timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val); 199245876Sganbold 200245876Sganbold sc->timer0_freq = SYS_TIMER_CLKSRC; 201245876Sganbold 202245876Sganbold /* Set desired frequency in event timer and timecounter */ 203245876Sganbold sc->et.et_frequency = sc->timer0_freq; 204245450Sganbold sc->et.et_name = "a10_timer Eventtimer"; 205245450Sganbold sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 206245450Sganbold sc->et.et_quality = 1000; 207247463Smav sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency; 208247463Smav sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 209245450Sganbold sc->et.et_start = a10_timer_timer_start; 210245450Sganbold sc->et.et_stop = a10_timer_timer_stop; 211245450Sganbold sc->et.et_priv = sc; 212245450Sganbold et_register(&sc->et); 213245450Sganbold 214298854Sandrew if (device_get_unit(dev) == 0) { 215298854Sandrew arm_set_delay(a10_timer_delay, sc); 216245450Sganbold a10_timer_sc = sc; 217298854Sandrew } 218245450Sganbold 219245876Sganbold a10_timer_timecounter.tc_frequency = sc->timer0_freq; 220245450Sganbold tc_init(&a10_timer_timecounter); 221245450Sganbold 222245876Sganbold if (bootverbose) { 223245876Sganbold device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz); 224245450Sganbold 225245876Sganbold device_printf(sc->sc_dev, "event timer clock frequency %u\n", 226245876Sganbold sc->timer0_freq); 227245876Sganbold device_printf(sc->sc_dev, "timecounter clock frequency %lld\n", 228245876Sganbold a10_timer_timecounter.tc_frequency); 229245876Sganbold } 230245450Sganbold 231245450Sganbold return (0); 232245450Sganbold} 233245450Sganbold 234245450Sganboldstatic int 235247463Smava10_timer_timer_start(struct eventtimer *et, sbintime_t first, 236247463Smav sbintime_t period) 237245450Sganbold{ 238245450Sganbold struct a10_timer_softc *sc; 239245876Sganbold uint32_t count; 240245876Sganbold uint32_t val; 241245450Sganbold 242245450Sganbold sc = (struct a10_timer_softc *)et->et_priv; 243245450Sganbold 244247463Smav if (period != 0) 245247463Smav sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 246247463Smav else 247247463Smav sc->sc_period = 0; 248247463Smav if (first != 0) 249247463Smav count = ((uint32_t)et->et_frequency * first) >> 32; 250247463Smav else 251245876Sganbold count = sc->sc_period; 252245450Sganbold 253245876Sganbold /* Update timer values */ 254245876Sganbold timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period); 255245876Sganbold timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count); 256245450Sganbold 257245876Sganbold val = timer_read_4(sc, SW_TIMER0_CTRL_REG); 258247463Smav if (period != 0) { 259245876Sganbold /* periodic */ 260245876Sganbold val |= TIMER_AUTORELOAD; 261245876Sganbold } else { 262245876Sganbold /* oneshot */ 263245876Sganbold val &= ~TIMER_AUTORELOAD; 264245450Sganbold } 265245876Sganbold /* Enable timer0 */ 266245876Sganbold val |= TIMER_ENABLE; 267245876Sganbold timer_write_4(sc, SW_TIMER0_CTRL_REG, val); 268245450Sganbold 269245876Sganbold return (0); 270245450Sganbold} 271245450Sganbold 272245450Sganboldstatic int 273245450Sganbolda10_timer_timer_stop(struct eventtimer *et) 274245450Sganbold{ 275245450Sganbold struct a10_timer_softc *sc; 276245450Sganbold uint32_t val; 277245450Sganbold 278245450Sganbold sc = (struct a10_timer_softc *)et->et_priv; 279245450Sganbold 280245876Sganbold /* Disable timer0 */ 281245450Sganbold val = timer_read_4(sc, SW_TIMER0_CTRL_REG); 282245876Sganbold val &= ~TIMER_ENABLE; 283245450Sganbold timer_write_4(sc, SW_TIMER0_CTRL_REG, val); 284245450Sganbold 285245450Sganbold sc->sc_period = 0; 286245450Sganbold 287245450Sganbold return (0); 288245450Sganbold} 289245450Sganbold 290245450Sganboldint 291245450Sganbolda10_timer_get_timerfreq(struct a10_timer_softc *sc) 292245450Sganbold{ 293245876Sganbold return (sc->timer0_freq); 294245450Sganbold} 295245450Sganbold 296245450Sganboldstatic int 297245876Sganbolda10_timer_hardclock(void *arg) 298245450Sganbold{ 299245450Sganbold struct a10_timer_softc *sc; 300245876Sganbold uint32_t val; 301245450Sganbold 302245450Sganbold sc = (struct a10_timer_softc *)arg; 303245450Sganbold 304245876Sganbold /* Clear interrupt pending bit. */ 305245876Sganbold timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1); 306245876Sganbold 307245876Sganbold val = timer_read_4(sc, SW_TIMER0_CTRL_REG); 308245876Sganbold /* 309245876Sganbold * Disabled autoreload and sc_period > 0 means 310245876Sganbold * timer_start was called with non NULL first value. 311245876Sganbold * Now we will set periodic timer with the given period 312245876Sganbold * value. 313245876Sganbold */ 314245876Sganbold if ((val & (1<<1)) == 0 && sc->sc_period > 0) { 315245876Sganbold /* Update timer */ 316245876Sganbold timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period); 317245876Sganbold 318245876Sganbold /* Make periodic and enable */ 319245876Sganbold val |= TIMER_AUTORELOAD | TIMER_ENABLE; 320245876Sganbold timer_write_4(sc, SW_TIMER0_CTRL_REG, val); 321245876Sganbold } 322245876Sganbold 323245450Sganbold if (sc->et.et_active) 324245450Sganbold sc->et.et_event_cb(&sc->et, sc->et.et_arg); 325245450Sganbold 326245450Sganbold return (FILTER_HANDLED); 327245450Sganbold} 328245450Sganbold 329245450Sganboldu_int 330245450Sganbolda10_timer_get_timecount(struct timecounter *tc) 331245450Sganbold{ 332245450Sganbold 333245450Sganbold if (a10_timer_sc == NULL) 334245450Sganbold return (0); 335245450Sganbold 336245876Sganbold return ((u_int)timer_read_counter64()); 337245450Sganbold} 338245450Sganbold 339245450Sganboldstatic device_method_t a10_timer_methods[] = { 340245450Sganbold DEVMETHOD(device_probe, a10_timer_probe), 341245450Sganbold DEVMETHOD(device_attach, a10_timer_attach), 342245450Sganbold 343245450Sganbold DEVMETHOD_END 344245450Sganbold}; 345245450Sganbold 346245450Sganboldstatic driver_t a10_timer_driver = { 347245450Sganbold "a10_timer", 348245450Sganbold a10_timer_methods, 349245450Sganbold sizeof(struct a10_timer_softc), 350245450Sganbold}; 351245450Sganbold 352245450Sganboldstatic devclass_t a10_timer_devclass; 353245450Sganbold 354295464SandrewEARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0, 355295464Sandrew BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 356245450Sganbold 357298854Sandrewstatic void 358298854Sandrewa10_timer_delay(int usec, void *arg) 359245450Sganbold{ 360298854Sandrew struct a10_timer_softc *sc = arg; 361245876Sganbold uint64_t end, now; 362245450Sganbold 363245876Sganbold now = timer_read_counter64(); 364298854Sandrew end = now + (sc->timer0_freq / 1000000) * (usec + 1); 365245450Sganbold 366245876Sganbold while (now < end) 367245876Sganbold now = timer_read_counter64(); 368245450Sganbold} 369