1/*-
2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/malloc.h>
38#include <sys/rman.h>
39#include <sys/timeet.h>
40#include <sys/timetc.h>
41#include <sys/watchdog.h>
42#include <machine/bus.h>
43#include <machine/cpu.h>
44#include <machine/frame.h>
45#include <machine/intr.h>
46
47#include <dev/fdt/fdt_common.h>
48#include <dev/ofw/openfirm.h>
49#include <dev/ofw/ofw_bus.h>
50#include <dev/ofw/ofw_bus_subr.h>
51
52#include "a10_sramc.h"
53
54#define	SRAM_CTL1_CFG		0x04
55#define	CTL1_CFG_SRAMD_MAP_USB0	(1 << 0)
56
57struct a10_sramc_softc {
58	struct resource		*res;
59	bus_space_tag_t		bst;
60	bus_space_handle_t	bsh;
61};
62
63static struct a10_sramc_softc *a10_sramc_sc;
64
65#define	sramc_read_4(sc, reg)		\
66    bus_space_read_4((sc)->bst, (sc)->bsh, (reg))
67#define	sramc_write_4(sc, reg, val)	\
68    bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val))
69
70
71static int
72a10_sramc_probe(device_t dev)
73{
74
75	if (ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-sram-controller")) {
76		device_set_desc(dev, "Allwinner sramc module");
77		return (BUS_PROBE_DEFAULT);
78	}
79
80	return (ENXIO);
81}
82
83static int
84a10_sramc_attach(device_t dev)
85{
86	struct a10_sramc_softc *sc = device_get_softc(dev);
87	int rid = 0;
88
89	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
90	if (!sc->res) {
91		device_printf(dev, "could not allocate resource\n");
92		return (ENXIO);
93	}
94
95	sc->bst = rman_get_bustag(sc->res);
96	sc->bsh = rman_get_bushandle(sc->res);
97
98	a10_sramc_sc = sc;
99
100	return (0);
101}
102
103static device_method_t a10_sramc_methods[] = {
104	DEVMETHOD(device_probe,		a10_sramc_probe),
105	DEVMETHOD(device_attach,	a10_sramc_attach),
106	{ 0, 0 }
107};
108
109static driver_t a10_sramc_driver = {
110	"a10_sramc",
111	a10_sramc_methods,
112	sizeof(struct a10_sramc_softc),
113};
114
115static devclass_t a10_sramc_devclass;
116
117EARLY_DRIVER_MODULE(a10_sramc, simplebus, a10_sramc_driver, a10_sramc_devclass,
118    0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_EARLY);
119
120int
121a10_map_to_emac(void)
122{
123	struct a10_sramc_softc *sc = a10_sramc_sc;
124	uint32_t reg_value;
125
126	if (sc == NULL)
127		return (ENXIO);
128
129	/* Map SRAM to EMAC, set bit 2 and 4. */
130	reg_value = sramc_read_4(sc, SRAM_CTL1_CFG);
131	reg_value |= 0x5 << 2;
132	sramc_write_4(sc, SRAM_CTL1_CFG, reg_value);
133
134	return (0);
135}
136
137int
138a10_map_to_otg(void)
139{
140	struct a10_sramc_softc *sc = a10_sramc_sc;
141	uint32_t reg_value;
142
143	if (sc == NULL)
144		return (ENXIO);
145
146	/* Map SRAM to OTG */
147	reg_value = sramc_read_4(sc, SRAM_CTL1_CFG);
148	reg_value |= CTL1_CFG_SRAMD_MAP_USB0;
149	sramc_write_4(sc, SRAM_CTL1_CFG, reg_value);
150
151	return (0);
152}
153