a10_ehci.c revision 308324 
1/*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * Allwinner A10 attachment driver for the USB Enhanced Host Controller.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/11/sys/arm/allwinner/a10_ehci.c 308324 2016-11-05 04:17:32Z mmel $");
33
34#include "opt_bus.h"
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/rman.h>
40#include <sys/condvar.h>
41#include <sys/kernel.h>
42#include <sys/module.h>
43
44#include <machine/bus.h>
45#include <dev/ofw/ofw_bus.h>
46#include <dev/ofw/ofw_bus_subr.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50
51#include <dev/usb/usb_core.h>
52#include <dev/usb/usb_busdma.h>
53#include <dev/usb/usb_process.h>
54#include <dev/usb/usb_util.h>
55
56#include <dev/usb/usb_controller.h>
57#include <dev/usb/usb_bus.h>
58#include <dev/usb/controller/ehci.h>
59#include <dev/usb/controller/ehcireg.h>
60
61#include <arm/allwinner/aw_machdep.h>
62#include <dev/extres/clk/clk.h>
63#include <dev/extres/hwreset/hwreset.h>
64#include <dev/extres/phy/phy.h>
65
66#define EHCI_HC_DEVSTR			"Allwinner Integrated USB 2.0 controller"
67
68#define SW_USB_PMU_IRQ_ENABLE		0x800
69
70#define SW_SDRAM_REG_HPCR_USB1		(0x250 + ((1 << 2) * 4))
71#define SW_SDRAM_REG_HPCR_USB2		(0x250 + ((1 << 2) * 5))
72#define SW_SDRAM_BP_HPCR_ACCESS		(1 << 0)
73
74#define SW_ULPI_BYPASS			(1 << 0)
75#define SW_AHB_INCRX_ALIGN		(1 << 8)
76#define SW_AHB_INCR4			(1 << 9)
77#define SW_AHB_INCR8			(1 << 10)
78
79#define	USB_CONF(d)			\
80	(void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
81
82#define A10_READ_4(sc, reg)		\
83	bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
84
85#define A10_WRITE_4(sc, reg, data)	\
86	bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
87
88static device_attach_t a10_ehci_attach;
89static device_detach_t a10_ehci_detach;
90
91bs_r_1_proto(reversed);
92bs_w_1_proto(reversed);
93
94struct aw_ehci_softc {
95	ehci_softc_t	sc;
96	clk_t		clk;
97	hwreset_t	rst;
98	phy_t		phy;
99};
100
101struct aw_ehci_conf {
102	bool		sdram_init;
103};
104
105static const struct aw_ehci_conf a10_ehci_conf = {
106	.sdram_init = true,
107};
108
109static const struct aw_ehci_conf a31_ehci_conf = {
110	.sdram_init = false,
111};
112
113static struct ofw_compat_data compat_data[] = {
114	{ "allwinner,sun4i-a10-ehci",	(uintptr_t)&a10_ehci_conf },
115	{ "allwinner,sun5i-a13-ehci",	(uintptr_t)&a10_ehci_conf },
116	{ "allwinner,sun6i-a31-ehci",	(uintptr_t)&a31_ehci_conf },
117	{ "allwinner,sun7i-a20-ehci",	(uintptr_t)&a10_ehci_conf },
118	{ "allwinner,sun8i-a83t-ehci",	(uintptr_t)&a31_ehci_conf },
119	{ "allwinner,sun8i-h3-ehci",	(uintptr_t)&a31_ehci_conf },
120	{ NULL,				(uintptr_t)NULL }
121};
122
123static int
124a10_ehci_probe(device_t self)
125{
126
127	if (!ofw_bus_status_okay(self))
128		return (ENXIO);
129
130	if (ofw_bus_search_compatible(self, compat_data)->ocd_data == 0)
131		return (ENXIO);
132
133	device_set_desc(self, EHCI_HC_DEVSTR);
134
135	return (BUS_PROBE_DEFAULT);
136}
137
138static int
139a10_ehci_attach(device_t self)
140{
141	struct aw_ehci_softc *aw_sc = device_get_softc(self);
142	ehci_softc_t *sc = &aw_sc->sc;
143	const struct aw_ehci_conf *conf;
144	bus_space_handle_t bsh;
145	int err;
146	int rid;
147	uint32_t reg_value = 0;
148
149	conf = USB_CONF(self);
150
151	/* initialise some bus fields */
152	sc->sc_bus.parent = self;
153	sc->sc_bus.devices = sc->sc_devices;
154	sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
155	sc->sc_bus.dma_bits = 32;
156
157	/* get all DMA memory */
158	if (usb_bus_mem_alloc_all(&sc->sc_bus,
159	    USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
160		return (ENOMEM);
161	}
162
163	sc->sc_bus.usbrev = USB_REV_2_0;
164
165	rid = 0;
166	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
167	if (!sc->sc_io_res) {
168		device_printf(self, "Could not map memory\n");
169		goto error;
170	}
171
172	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
173	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
174	bsh = rman_get_bushandle(sc->sc_io_res);
175
176	sc->sc_io_size = rman_get_size(sc->sc_io_res);
177
178	if (bus_space_subregion(sc->sc_io_tag, bsh, 0x00,
179	    sc->sc_io_size, &sc->sc_io_hdl) != 0)
180		panic("%s: unable to subregion USB host registers",
181		    device_get_name(self));
182
183	rid = 0;
184	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
185	    RF_SHAREABLE | RF_ACTIVE);
186	if (sc->sc_irq_res == NULL) {
187		device_printf(self, "Could not allocate irq\n");
188		goto error;
189	}
190	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
191	if (!sc->sc_bus.bdev) {
192		device_printf(self, "Could not add USB device\n");
193		goto error;
194	}
195	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
196	device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
197
198	sprintf(sc->sc_vendor, "Allwinner");
199
200	err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
201	    NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
202	if (err) {
203		device_printf(self, "Could not setup irq, %d\n", err);
204		sc->sc_intr_hdl = NULL;
205		goto error;
206	}
207
208	sc->sc_flags |= EHCI_SCFLG_DONTRESET;
209
210	/* De-assert reset */
211	if (hwreset_get_by_ofw_idx(self, 0, 0, &aw_sc->rst) == 0) {
212		err = hwreset_deassert(aw_sc->rst);
213		if (err != 0) {
214			device_printf(self, "Could not de-assert reset\n");
215			goto error;
216		}
217	}
218
219	/* Enable clock for USB */
220	err = clk_get_by_ofw_index(self, 0, 0, &aw_sc->clk);
221	if (err != 0) {
222		device_printf(self, "Could not get clock\n");
223		goto error;
224	}
225	err = clk_enable(aw_sc->clk);
226	if (err != 0) {
227		device_printf(self, "Could not enable clock\n");
228		goto error;
229	}
230
231	/* Enable USB PHY */
232	err = phy_get_by_ofw_name(self, 0, "usb", &aw_sc->phy);
233	if (err != 0) {
234		device_printf(self, "Could not get phy\n");
235		goto error;
236	}
237	err = phy_enable(self, aw_sc->phy);
238	if (err != 0) {
239		device_printf(self, "Could not enable phy\n");
240		goto error;
241	}
242
243	/* Enable passby */
244	reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
245	reg_value |= SW_AHB_INCR8; /* AHB INCR8 enable */
246	reg_value |= SW_AHB_INCR4; /* AHB burst type INCR4 enable */
247	reg_value |= SW_AHB_INCRX_ALIGN; /* AHB INCRX align enable */
248	reg_value |= SW_ULPI_BYPASS; /* ULPI bypass enable */
249	A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
250
251	/* Configure port */
252	if (conf->sdram_init) {
253		reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
254		reg_value |= SW_SDRAM_BP_HPCR_ACCESS;
255		A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
256	}
257
258	err = ehci_init(sc);
259	if (!err) {
260		err = device_probe_and_attach(sc->sc_bus.bdev);
261	}
262	if (err) {
263		device_printf(self, "USB init failed err=%d\n", err);
264		goto error;
265	}
266	return (0);
267
268error:
269	if (aw_sc->clk)
270		clk_release(aw_sc->clk);
271	a10_ehci_detach(self);
272	return (ENXIO);
273}
274
275static int
276a10_ehci_detach(device_t self)
277{
278	struct aw_ehci_softc *aw_sc = device_get_softc(self);
279	ehci_softc_t *sc = &aw_sc->sc;
280	const struct aw_ehci_conf *conf;
281	device_t bdev;
282	int err;
283	uint32_t reg_value = 0;
284
285	conf = USB_CONF(self);
286
287	if (sc->sc_bus.bdev) {
288		bdev = sc->sc_bus.bdev;
289		device_detach(bdev);
290		device_delete_child(self, bdev);
291	}
292	/* during module unload there are lots of children leftover */
293	device_delete_children(self);
294
295	if (sc->sc_irq_res && sc->sc_intr_hdl) {
296		/*
297		 * only call ehci_detach() after ehci_init()
298		 */
299		ehci_detach(sc);
300
301		err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
302
303		if (err)
304			/* XXX or should we panic? */
305			device_printf(self, "Could not tear down irq, %d\n",
306			    err);
307		sc->sc_intr_hdl = NULL;
308	}
309
310	if (sc->sc_irq_res) {
311		bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
312		sc->sc_irq_res = NULL;
313	}
314	if (sc->sc_io_res) {
315		bus_release_resource(self, SYS_RES_MEMORY, 0,
316		    sc->sc_io_res);
317		sc->sc_io_res = NULL;
318	}
319	usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
320
321	/* Disable configure port */
322	if (conf->sdram_init) {
323		reg_value = A10_READ_4(sc, SW_SDRAM_REG_HPCR_USB2);
324		reg_value &= ~SW_SDRAM_BP_HPCR_ACCESS;
325		A10_WRITE_4(sc, SW_SDRAM_REG_HPCR_USB2, reg_value);
326	}
327
328	/* Disable passby */
329	reg_value = A10_READ_4(sc, SW_USB_PMU_IRQ_ENABLE);
330	reg_value &= ~SW_AHB_INCR8; /* AHB INCR8 disable */
331	reg_value &= ~SW_AHB_INCR4; /* AHB burst type INCR4 disable */
332	reg_value &= ~SW_AHB_INCRX_ALIGN; /* AHB INCRX align disable */
333	reg_value &= ~SW_ULPI_BYPASS; /* ULPI bypass disable */
334	A10_WRITE_4(sc, SW_USB_PMU_IRQ_ENABLE, reg_value);
335
336	/* Disable clock for USB */
337	clk_disable(aw_sc->clk);
338	clk_release(aw_sc->clk);
339
340	/* Assert reset */
341	if (aw_sc->rst != NULL) {
342		hwreset_assert(aw_sc->rst);
343		hwreset_release(aw_sc->rst);
344	}
345
346	return (0);
347}
348
349static device_method_t ehci_methods[] = {
350	/* Device interface */
351	DEVMETHOD(device_probe, a10_ehci_probe),
352	DEVMETHOD(device_attach, a10_ehci_attach),
353	DEVMETHOD(device_detach, a10_ehci_detach),
354	DEVMETHOD(device_suspend, bus_generic_suspend),
355	DEVMETHOD(device_resume, bus_generic_resume),
356	DEVMETHOD(device_shutdown, bus_generic_shutdown),
357
358	DEVMETHOD_END
359};
360
361static driver_t ehci_driver = {
362	.name = "ehci",
363	.methods = ehci_methods,
364	.size = sizeof(struct aw_ehci_softc),
365};
366
367static devclass_t ehci_devclass;
368
369DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0);
370MODULE_DEPEND(ehci, usb, 1, 1, 1);
371