1/*- 2 * Copyright (c) 2011-2014 Robert N. M. Watson 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: stable/11/stand/mips/beri/common/common.ldscript 329099 2018-02-10 04:37:44Z kevans $ 31 */ 32 33/* 34 * MIPS segment definitions. 35 */ 36__mips_ckseg_cached__ = 0xffffffff80000000; /* BSD kernel here. */ 37__mips64_xkphys_cached__ = 0x9800000000000000; /* Device memory here. */ 38__mips64_xkphys_uncached__ = 0x9000000000000000; /* Device I/O here. */ 39 40/* 41 * Physical addresses of various peripherals. 42 */ 43__cheri_flash_base__ = 0x74000000; 44__cheri_sdcard_base__ = 0x7f008000; 45 46/* 47 * Location of boot2 in flash. 48 */ 49__cheri_flash_boot_loader_base_ = 0x03fe0000; 50__cheri_flash_boot_loader_vaddr__ = __mips64_xkphys_cached__ + 51 __cheri_flash_base__ + __cheri_flash_boot_loader_base_; 52 53/* 54 * Location of boot file system in flash. 55 */ 56__cheri_flash_bootfs_base__ = 0x1820000; 57__cheri_flash_bootfs_len__ = 0x27c0000; 58__cheri_flash_bootfs_vaddr__ = __mips64_xkphys_cached__ + 59 __cheri_flash_base__ + __cheri_flash_bootfs_base__; 60 61/* 62 * Location of SD card controller. 63 */ 64__cheri_sdcard_vaddr__ = __mips64_xkphys_uncached__ + __cheri_sdcard_base__; 65 66/* 67 * Location where the production kernel gets put. This must agree with other 68 * definitions, such as in the kernel's own linker script. 69 * 70 * (As it happens, in the short run, we also place boot2 here, as Miniboot 71 * expects to find an ELF binary there -- but that will change.) 72 */ 73__kernel_base__ = 0x100000; 74__kernel_vaddr__ = __mips64_xkphys_cached__ + __kernel_base__; 75 76OUTPUT_ARCH(mips) 77