fwohci.c revision 298826
1170101Ssimokawa/* 2170101Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3170101Ssimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4170101Ssimokawa * All rights reserved. 5170101Ssimokawa * 6170101Ssimokawa * Redistribution and use in source and binary forms, with or without 7170101Ssimokawa * modification, are permitted provided that the following conditions 8170101Ssimokawa * are met: 9170101Ssimokawa * 1. Redistributions of source code must retain the above copyright 10170101Ssimokawa * notice, this list of conditions and the following disclaimer. 11170101Ssimokawa * 2. Redistributions in binary form must reproduce the above copyright 12170101Ssimokawa * notice, this list of conditions and the following disclaimer in the 13170101Ssimokawa * documentation and/or other materials provided with the distribution. 14170101Ssimokawa * 3. All advertising materials mentioning features or use of this software 15170101Ssimokawa * must display the acknowledgement as bellow: 16170101Ssimokawa * 17170101Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18170101Ssimokawa * 19170101Ssimokawa * 4. The name of the author may not be used to endorse or promote products 20170101Ssimokawa * derived from this software without specific prior written permission. 21170101Ssimokawa * 22170101Ssimokawa * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23170101Ssimokawa * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24170101Ssimokawa * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25170101Ssimokawa * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26170101Ssimokawa * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27170101Ssimokawa * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28170101Ssimokawa * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29170101Ssimokawa * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30170101Ssimokawa * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31170101Ssimokawa * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32170101Ssimokawa * POSSIBILITY OF SUCH DAMAGE. 33170101Ssimokawa * 34170101Ssimokawa * $FreeBSD: head/sys/boot/i386/libfirewire/fwohci.c 298826 2016-04-30 00:26:38Z pfg $ 35170101Ssimokawa * 36170101Ssimokawa */ 37170101Ssimokawa 38170101Ssimokawa#include <stand.h> 39170101Ssimokawa#include <btxv86.h> 40170101Ssimokawa#include <bootstrap.h> 41170101Ssimokawa 42170101Ssimokawa#include "fwohci.h" 43170101Ssimokawa#include "fwohcireg.h" 44170101Ssimokawa#include <dev/firewire/firewire_phy.h> 45170101Ssimokawa 46170101Ssimokawastatic uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 47170101Ssimokawastatic uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 48170101Ssimokawaint firewire_debug=0; 49170101Ssimokawa 50170101Ssimokawa#if 0 51170101Ssimokawa#define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__) 52170101Ssimokawa#else 53170101Ssimokawa#define device_printf(a, x, ...) 54170101Ssimokawa#endif 55170101Ssimokawa 56170101Ssimokawa#define device_t int 57170101Ssimokawa#define DELAY(x) delay(x) 58170101Ssimokawa 59170101Ssimokawa#define MAX_SPEED 3 60170101Ssimokawa#define MAXREC(x) (2 << (x)) 61170101Ssimokawachar *linkspeed[] = { 62170101Ssimokawa "S100", "S200", "S400", "S800", 63170101Ssimokawa "S1600", "S3200", "undef", "undef" 64170101Ssimokawa}; 65170101Ssimokawa 66170101Ssimokawa#define FW_EUI64_BYTE(eui, x) \ 67170101Ssimokawa ((((x)<4)? \ 68170101Ssimokawa ((eui)->hi >> (8*(3-(x)))): \ 69170101Ssimokawa ((eui)->lo >> (8*(7-(x)))) \ 70170101Ssimokawa ) & 0xff) 71170101Ssimokawa 72170101Ssimokawa/* 73170101Ssimokawa * Communication with PHY device 74170101Ssimokawa */ 75170101Ssimokawastatic uint32_t 76170101Ssimokawafwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 77170101Ssimokawa{ 78170101Ssimokawa uint32_t fun; 79170101Ssimokawa 80170101Ssimokawa addr &= 0xf; 81170101Ssimokawa data &= 0xff; 82170101Ssimokawa 83170101Ssimokawa fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 84170101Ssimokawa OWRITE(sc, OHCI_PHYACCESS, fun); 85170101Ssimokawa DELAY(100); 86170101Ssimokawa 87170101Ssimokawa return(fwphy_rddata( sc, addr)); 88170101Ssimokawa} 89170101Ssimokawa 90170101Ssimokawastatic uint32_t 91170101Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 92170101Ssimokawa{ 93170101Ssimokawa uint32_t fun, stat; 94170101Ssimokawa u_int i, retry = 0; 95170101Ssimokawa 96170101Ssimokawa addr &= 0xf; 97170101Ssimokawa#define MAX_RETRY 100 98170101Ssimokawaagain: 99170101Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 100170101Ssimokawa fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 101170101Ssimokawa OWRITE(sc, OHCI_PHYACCESS, fun); 102170101Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 103170101Ssimokawa fun = OREAD(sc, OHCI_PHYACCESS); 104170101Ssimokawa if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 105170101Ssimokawa break; 106170101Ssimokawa DELAY(100); 107170101Ssimokawa } 108170101Ssimokawa if(i >= MAX_RETRY) { 109170101Ssimokawa if (firewire_debug) 110170101Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 111170101Ssimokawa if (++retry < MAX_RETRY) { 112170101Ssimokawa DELAY(100); 113170101Ssimokawa goto again; 114170101Ssimokawa } 115170101Ssimokawa } 116170101Ssimokawa /* Make sure that SCLK is started */ 117170101Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 118170101Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 119170101Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 120170101Ssimokawa if (firewire_debug) 121170101Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 122170101Ssimokawa if (++retry < MAX_RETRY) { 123170101Ssimokawa DELAY(100); 124170101Ssimokawa goto again; 125170101Ssimokawa } 126170101Ssimokawa } 127170101Ssimokawa if (firewire_debug || retry >= MAX_RETRY) 128170101Ssimokawa device_printf(sc->fc.dev, 129170101Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 130170101Ssimokawa#undef MAX_RETRY 131170101Ssimokawa return((fun >> PHYDEV_RDDATA )& 0xff); 132170101Ssimokawa} 133170101Ssimokawa 134170101Ssimokawa 135170101Ssimokawastatic int 136170101Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 137170101Ssimokawa{ 138170101Ssimokawa uint32_t reg, reg2; 139170101Ssimokawa int e1394a = 1; 140170101Ssimokawa int nport, speed; 141170101Ssimokawa/* 142170101Ssimokawa * probe PHY parameters 143170101Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 144170101Ssimokawa * 1. to probe maximum speed supported by the PHY and 145170101Ssimokawa * number of port supported by core-logic. 146170101Ssimokawa * It is not actually available port on your PC . 147170101Ssimokawa */ 148170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 149170101Ssimokawa DELAY(500); 150170101Ssimokawa 151170101Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 152170101Ssimokawa 153170101Ssimokawa if((reg >> 5) != 7 ){ 154170101Ssimokawa nport = reg & FW_PHY_NP; 155170101Ssimokawa speed = reg & FW_PHY_SPD >> 6; 156170101Ssimokawa if (speed > MAX_SPEED) { 157170101Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 158170101Ssimokawa speed, MAX_SPEED); 159170101Ssimokawa speed = MAX_SPEED; 160170101Ssimokawa } 161170101Ssimokawa device_printf(dev, 162170101Ssimokawa "Phy 1394 only %s, %d ports.\n", 163170101Ssimokawa linkspeed[speed], nport); 164170101Ssimokawa }else{ 165170101Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 166170101Ssimokawa nport = reg & FW_PHY_NP; 167170101Ssimokawa speed = (reg2 & FW_PHY_ESPD) >> 5; 168170101Ssimokawa if (speed > MAX_SPEED) { 169170101Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 170170101Ssimokawa speed, MAX_SPEED); 171170101Ssimokawa speed = MAX_SPEED; 172170101Ssimokawa } 173170101Ssimokawa device_printf(dev, 174170101Ssimokawa "Phy 1394a available %s, %d ports.\n", 175170101Ssimokawa linkspeed[speed], nport); 176170101Ssimokawa 177170101Ssimokawa /* check programPhyEnable */ 178170101Ssimokawa reg2 = fwphy_rddata(sc, 5); 179170101Ssimokawa#if 0 180170101Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 181170101Ssimokawa#else /* XXX force to enable 1394a */ 182170101Ssimokawa if (e1394a) { 183170101Ssimokawa#endif 184170101Ssimokawa if (firewire_debug) 185170101Ssimokawa device_printf(dev, 186170101Ssimokawa "Enable 1394a Enhancements\n"); 187170101Ssimokawa /* enable EAA EMC */ 188170101Ssimokawa reg2 |= 0x03; 189170101Ssimokawa /* set aPhyEnhanceEnable */ 190170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 191170101Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 192170101Ssimokawa } else { 193170101Ssimokawa /* for safe */ 194170101Ssimokawa reg2 &= ~0x83; 195170101Ssimokawa } 196170101Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 197170101Ssimokawa } 198170101Ssimokawa sc->speed = speed; 199170101Ssimokawa 200170101Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 201170101Ssimokawa if((reg >> 5) == 7 ){ 202170101Ssimokawa reg = fwphy_rddata(sc, 4); 203170101Ssimokawa reg |= 1 << 6; 204170101Ssimokawa fwphy_wrdata(sc, 4, reg); 205170101Ssimokawa reg = fwphy_rddata(sc, 4); 206170101Ssimokawa } 207170101Ssimokawa return 0; 208170101Ssimokawa} 209170101Ssimokawa 210170101Ssimokawa 211170101Ssimokawavoid 212170101Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 213170101Ssimokawa{ 214170101Ssimokawa int i, max_rec, speed; 215170101Ssimokawa uint32_t reg, reg2; 216170101Ssimokawa 217170101Ssimokawa /* Disable interrupts */ 218170101Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 219170101Ssimokawa 220298826Spfg /* FLUSH FIFO and reset Transmitter/Receiver */ 221170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 222170101Ssimokawa if (firewire_debug) 223170101Ssimokawa device_printf(dev, "resetting OHCI..."); 224170101Ssimokawa i = 0; 225170101Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 226170101Ssimokawa if (i++ > 100) break; 227170101Ssimokawa DELAY(1000); 228170101Ssimokawa } 229170101Ssimokawa if (firewire_debug) 230170101Ssimokawa printf("done (loop=%d)\n", i); 231170101Ssimokawa 232170101Ssimokawa /* Probe phy */ 233170101Ssimokawa fwohci_probe_phy(sc, dev); 234170101Ssimokawa 235170101Ssimokawa /* Probe link */ 236170101Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 237170101Ssimokawa reg2 = reg | OHCI_BUSFNC; 238170101Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 239170101Ssimokawa speed = (reg & 0x00000007); 240170101Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 241170101Ssimokawa linkspeed[speed], MAXREC(max_rec)); 242170101Ssimokawa /* XXX fix max_rec */ 243170101Ssimokawa sc->maxrec = sc->speed + 8; 244170101Ssimokawa if (max_rec != sc->maxrec) { 245170101Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12); 246170101Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 247170101Ssimokawa MAXREC(max_rec), MAXREC(sc->maxrec)); 248170101Ssimokawa } 249170101Ssimokawa if (firewire_debug) 250170101Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 251170101Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 252170101Ssimokawa 253170101Ssimokawa /* Initialize registers */ 254170101Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]); 255170101Ssimokawa OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom)); 256170101Ssimokawa#if 0 257170101Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 258170101Ssimokawa#endif 259170101Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 260170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 261170101Ssimokawa#if 0 262170101Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 263170101Ssimokawa#endif 264170101Ssimokawa 265170101Ssimokawa /* Enable link */ 266170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 267170101Ssimokawa} 268170101Ssimokawa 269170101Ssimokawaint 270170101Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 271170101Ssimokawa{ 272170101Ssimokawa int i, mver; 273170101Ssimokawa uint32_t reg; 274170101Ssimokawa uint8_t ui[8]; 275170101Ssimokawa 276170101Ssimokawa/* OHCI version */ 277170101Ssimokawa reg = OREAD(sc, OHCI_VERSION); 278170101Ssimokawa mver = (reg >> 16) & 0xff; 279170101Ssimokawa device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 280170101Ssimokawa mver, reg & 0xff, (reg>>24) & 1); 281170101Ssimokawa if (mver < 1 || mver > 9) { 282170101Ssimokawa device_printf(dev, "invalid OHCI version\n"); 283170101Ssimokawa return (ENXIO); 284170101Ssimokawa } 285170101Ssimokawa 286170101Ssimokawa/* Available Isochronous DMA channel probe */ 287170101Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 288170101Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 289170101Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 290170101Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 291170101Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 292170101Ssimokawa for (i = 0; i < 0x20; i++) 293170101Ssimokawa if ((reg & (1 << i)) == 0) 294170101Ssimokawa break; 295170101Ssimokawa device_printf(dev, "No. of Isochronous channels is %d.\n", i); 296170101Ssimokawa if (i == 0) 297170101Ssimokawa return (ENXIO); 298170101Ssimokawa 299170101Ssimokawa#if 0 300298826Spfg/* SID receive buffer must align 2^11 */ 301170101Ssimokawa#define OHCI_SIDSIZE (1 << 11) 302170101Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 303170101Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 304170101Ssimokawa if (sc->sid_buf == NULL) { 305170101Ssimokawa device_printf(dev, "sid_buf alloc failed."); 306170101Ssimokawa return ENOMEM; 307170101Ssimokawa } 308170101Ssimokawa#endif 309170101Ssimokawa 310170101Ssimokawa sc->eui.hi = OREAD(sc, FWOHCIGUID_H); 311170101Ssimokawa sc->eui.lo = OREAD(sc, FWOHCIGUID_L); 312170101Ssimokawa for( i = 0 ; i < 8 ; i ++) 313170101Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->eui,i); 314170101Ssimokawa device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 315170101Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 316170101Ssimokawa fwohci_reset(sc, dev); 317170101Ssimokawa 318170101Ssimokawa return 0; 319170101Ssimokawa} 320170101Ssimokawa 321170101Ssimokawavoid 322170101Ssimokawafwohci_ibr(struct fwohci_softc *sc) 323170101Ssimokawa{ 324170101Ssimokawa uint32_t fun; 325170101Ssimokawa 326170101Ssimokawa device_printf(sc->dev, "Initiate bus reset\n"); 327170101Ssimokawa 328170101Ssimokawa /* 329170101Ssimokawa * Make sure our cached values from the config rom are 330170101Ssimokawa * initialised. 331170101Ssimokawa */ 332170101Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); 333170101Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); 334170101Ssimokawa 335170101Ssimokawa /* 336170101Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 337170101Ssimokawa * shouldn't became the root node. 338170101Ssimokawa */ 339170101Ssimokawa#if 1 340170101Ssimokawa fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 341170101Ssimokawa fun |= FW_PHY_IBR; 342170101Ssimokawa fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 343170101Ssimokawa#else /* Short bus reset */ 344170101Ssimokawa fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 345170101Ssimokawa fun |= FW_PHY_ISBR; 346170101Ssimokawa fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 347170101Ssimokawa#endif 348170101Ssimokawa} 349170101Ssimokawa 350170101Ssimokawa 351170101Ssimokawavoid 352170101Ssimokawafwohci_sid(struct fwohci_softc *sc) 353170101Ssimokawa{ 354170101Ssimokawa uint32_t node_id; 355170101Ssimokawa int plen; 356170101Ssimokawa 357170101Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 358170101Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 359170101Ssimokawa#if 0 360170101Ssimokawa printf("Bus reset failure\n"); 361170101Ssimokawa#endif 362170101Ssimokawa return; 363170101Ssimokawa } 364170101Ssimokawa 365170101Ssimokawa /* Enable bus reset interrupt */ 366170101Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 367170101Ssimokawa /* Allow async. request to us */ 368170101Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 369170101Ssimokawa /* XXX insecure ?? */ 370170101Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 371170101Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 372170101Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 373170101Ssimokawa /* Set ATRetries register */ 374170101Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 375170101Ssimokawa/* 376170101Ssimokawa** Checking whether the node is root or not. If root, turn on 377170101Ssimokawa** cycle master. 378170101Ssimokawa*/ 379170101Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 380170101Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 381170101Ssimokawa node_id, (plen >> 16) & 0xff); 382170101Ssimokawa if (node_id & OHCI_NODE_ROOT) { 383170101Ssimokawa device_printf(sc->dev, "CYCLEMASTER mode\n"); 384170101Ssimokawa OWRITE(sc, OHCI_LNKCTL, 385170101Ssimokawa OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 386170101Ssimokawa } else { 387170101Ssimokawa device_printf(sc->dev, "non CYCLEMASTER mode\n"); 388170101Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 389170101Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 390170101Ssimokawa } 391170101Ssimokawa if (plen & OHCI_SID_ERR) { 392170101Ssimokawa device_printf(fc->dev, "SID Error\n"); 393170101Ssimokawa return; 394170101Ssimokawa } 395170101Ssimokawa device_printf(sc->dev, "bus reset phase done\n"); 396170101Ssimokawa sc->state = FWOHCI_STATE_NORMAL; 397170101Ssimokawa} 398170101Ssimokawa 399170101Ssimokawastatic void 400170101Ssimokawafwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 401170101Ssimokawa{ 402170101Ssimokawa#undef OHCI_DEBUG 403170101Ssimokawa#ifdef OHCI_DEBUG 404170101Ssimokawa#if 0 405170101Ssimokawa if(stat & OREAD(sc, FWOHCI_INTMASK)) 406170101Ssimokawa#else 407170101Ssimokawa if (1) 408170101Ssimokawa#endif 409170101Ssimokawa device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 410170101Ssimokawa stat & OHCI_INT_EN ? "DMA_EN ":"", 411170101Ssimokawa stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 412170101Ssimokawa stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 413170101Ssimokawa stat & OHCI_INT_ERR ? "INT_ERR ":"", 414170101Ssimokawa stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 415170101Ssimokawa stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 416170101Ssimokawa stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 417170101Ssimokawa stat & OHCI_INT_CYC_START ? "CYC_START ":"", 418170101Ssimokawa stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 419170101Ssimokawa stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 420170101Ssimokawa stat & OHCI_INT_PHY_SID ? "SID ":"", 421170101Ssimokawa stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 422170101Ssimokawa stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 423170101Ssimokawa stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 424170101Ssimokawa stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 425170101Ssimokawa stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 426170101Ssimokawa stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 427170101Ssimokawa stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 428170101Ssimokawa stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 429170101Ssimokawa stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 430170101Ssimokawa stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 431170101Ssimokawa stat, OREAD(sc, FWOHCI_INTMASK) 432170101Ssimokawa ); 433170101Ssimokawa#endif 434170101Ssimokawa/* Bus reset */ 435170101Ssimokawa if(stat & OHCI_INT_PHY_BUS_R ){ 436170101Ssimokawa device_printf(fc->dev, "BUS reset\n"); 437170101Ssimokawa if (sc->state == FWOHCI_STATE_BUSRESET) 438170101Ssimokawa goto busresetout; 439170101Ssimokawa sc->state = FWOHCI_STATE_BUSRESET; 440170101Ssimokawa /* Disable bus reset interrupt until sid recv. */ 441170101Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 442170101Ssimokawa 443170101Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 444170101Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 445170101Ssimokawa 446170101Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); 447170101Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); 448170101Ssimokawa } else if (sc->state == FWOHCI_STATE_BUSRESET) { 449170101Ssimokawa fwohci_sid(sc); 450170101Ssimokawa } 451170101Ssimokawabusresetout: 452170101Ssimokawa return; 453170101Ssimokawa} 454170101Ssimokawa 455170101Ssimokawastatic uint32_t 456170101Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 457170101Ssimokawa{ 458170101Ssimokawa uint32_t stat; 459170101Ssimokawa 460170101Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 461170101Ssimokawa if (stat == 0xffffffff) { 462170101Ssimokawa device_printf(sc->fc.dev, 463170101Ssimokawa "device physically ejected?\n"); 464170101Ssimokawa return(stat); 465170101Ssimokawa } 466170101Ssimokawa if (stat) 467170101Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 468170101Ssimokawa return(stat); 469170101Ssimokawa} 470170101Ssimokawa 471170101Ssimokawavoid 472170101Ssimokawafwohci_poll(struct fwohci_softc *sc) 473170101Ssimokawa{ 474170101Ssimokawa uint32_t stat; 475170101Ssimokawa 476170101Ssimokawa stat = fwochi_check_stat(sc); 477170101Ssimokawa if (stat != 0xffffffff) 478170101Ssimokawa fwohci_intr_body(sc, stat, 1); 479170101Ssimokawa} 480