1/* 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the acknowledgement as bellow: 16 * 17 * This product includes software developed by K. Kobayashi and H. Shimokawa 18 * 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: stable/11/stand/i386/libfirewire/fwohci.c 332156 2018-04-06 21:50:09Z kevans $ 35 * 36 */ 37 38#include <stand.h> 39#include <btxv86.h> 40#include <bootstrap.h> 41 42#include <dev/firewire/firewire.h> 43#include "fwohci.h" 44#include <dev/firewire/fwohcireg.h> 45#include <dev/firewire/firewire_phy.h> 46 47static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 48static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 49int firewire_debug=0; 50 51#if 0 52#define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__) 53#else 54#define device_printf(a, x, ...) 55#endif 56 57#define device_t int 58#define DELAY(x) delay(x) 59 60#define MAX_SPEED 3 61#define MAXREC(x) (2 << (x)) 62char *linkspeed[] = { 63 "S100", "S200", "S400", "S800", 64 "S1600", "S3200", "undef", "undef" 65}; 66 67/* 68 * Communication with PHY device 69 */ 70static uint32_t 71fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 72{ 73 uint32_t fun; 74 75 addr &= 0xf; 76 data &= 0xff; 77 78 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 79 OWRITE(sc, OHCI_PHYACCESS, fun); 80 DELAY(100); 81 82 return(fwphy_rddata( sc, addr)); 83} 84 85static uint32_t 86fwphy_rddata(struct fwohci_softc *sc, u_int addr) 87{ 88 uint32_t fun, stat; 89 u_int i, retry = 0; 90 91 addr &= 0xf; 92#define MAX_RETRY 100 93again: 94 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 95 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 96 OWRITE(sc, OHCI_PHYACCESS, fun); 97 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 98 fun = OREAD(sc, OHCI_PHYACCESS); 99 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 100 break; 101 DELAY(100); 102 } 103 if(i >= MAX_RETRY) { 104 if (firewire_debug) 105 device_printf(sc->fc.dev, "phy read failed(1).\n"); 106 if (++retry < MAX_RETRY) { 107 DELAY(100); 108 goto again; 109 } 110 } 111 /* Make sure that SCLK is started */ 112 stat = OREAD(sc, FWOHCI_INTSTAT); 113 if ((stat & OHCI_INT_REG_FAIL) != 0 || 114 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 115 if (firewire_debug) 116 device_printf(sc->fc.dev, "phy read failed(2).\n"); 117 if (++retry < MAX_RETRY) { 118 DELAY(100); 119 goto again; 120 } 121 } 122 if (firewire_debug || retry >= MAX_RETRY) 123 device_printf(sc->fc.dev, 124 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 125#undef MAX_RETRY 126 return((fun >> PHYDEV_RDDATA )& 0xff); 127} 128 129 130static int 131fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 132{ 133 uint32_t reg, reg2; 134 int e1394a = 1; 135 int nport, speed; 136/* 137 * probe PHY parameters 138 * 0. to prove PHY version, whether compliance of 1394a. 139 * 1. to probe maximum speed supported by the PHY and 140 * number of port supported by core-logic. 141 * It is not actually available port on your PC . 142 */ 143 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 144 DELAY(500); 145 146 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 147 148 if((reg >> 5) != 7 ){ 149 nport = reg & FW_PHY_NP; 150 speed = reg & FW_PHY_SPD >> 6; 151 if (speed > MAX_SPEED) { 152 device_printf(dev, "invalid speed %d (fixed to %d).\n", 153 speed, MAX_SPEED); 154 speed = MAX_SPEED; 155 } 156 device_printf(dev, 157 "Phy 1394 only %s, %d ports.\n", 158 linkspeed[speed], nport); 159 }else{ 160 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 161 nport = reg & FW_PHY_NP; 162 speed = (reg2 & FW_PHY_ESPD) >> 5; 163 if (speed > MAX_SPEED) { 164 device_printf(dev, "invalid speed %d (fixed to %d).\n", 165 speed, MAX_SPEED); 166 speed = MAX_SPEED; 167 } 168 device_printf(dev, 169 "Phy 1394a available %s, %d ports.\n", 170 linkspeed[speed], nport); 171 172 /* check programPhyEnable */ 173 reg2 = fwphy_rddata(sc, 5); 174#if 0 175 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 176#else /* XXX force to enable 1394a */ 177 if (e1394a) { 178#endif 179 if (firewire_debug) 180 device_printf(dev, 181 "Enable 1394a Enhancements\n"); 182 /* enable EAA EMC */ 183 reg2 |= 0x03; 184 /* set aPhyEnhanceEnable */ 185 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 186 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 187 } else { 188 /* for safe */ 189 reg2 &= ~0x83; 190 } 191 reg2 = fwphy_wrdata(sc, 5, reg2); 192 } 193 sc->speed = speed; 194 195 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 196 if((reg >> 5) == 7 ){ 197 reg = fwphy_rddata(sc, 4); 198 reg |= 1 << 6; 199 fwphy_wrdata(sc, 4, reg); 200 reg = fwphy_rddata(sc, 4); 201 } 202 return 0; 203} 204 205 206void 207fwohci_reset(struct fwohci_softc *sc, device_t dev) 208{ 209 int i, max_rec, speed; 210 uint32_t reg, reg2; 211 212 /* Disable interrupts */ 213 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 214 215 /* FLUSH FIFO and reset Transmitter/Receiver */ 216 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 217 if (firewire_debug) 218 device_printf(dev, "resetting OHCI..."); 219 i = 0; 220 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 221 if (i++ > 100) break; 222 DELAY(1000); 223 } 224 if (firewire_debug) 225 printf("done (loop=%d)\n", i); 226 227 /* Probe phy */ 228 fwohci_probe_phy(sc, dev); 229 230 /* Probe link */ 231 reg = OREAD(sc, OHCI_BUS_OPT); 232 reg2 = reg | OHCI_BUSFNC; 233 max_rec = (reg & 0x0000f000) >> 12; 234 speed = (reg & 0x00000007); 235 device_printf(dev, "Link %s, max_rec %d bytes.\n", 236 linkspeed[speed], MAXREC(max_rec)); 237 /* XXX fix max_rec */ 238 sc->maxrec = sc->speed + 8; 239 if (max_rec != sc->maxrec) { 240 reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12); 241 device_printf(dev, "max_rec %d -> %d\n", 242 MAXREC(max_rec), MAXREC(sc->maxrec)); 243 } 244 if (firewire_debug) 245 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 246 OWRITE(sc, OHCI_BUS_OPT, reg2); 247 248 /* Initialize registers */ 249 OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]); 250 OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom)); 251#if 0 252 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 253#endif 254 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 255 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 256#if 0 257 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 258#endif 259 260 /* Enable link */ 261 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 262} 263 264int 265fwohci_init(struct fwohci_softc *sc, device_t dev) 266{ 267 int i, mver; 268 uint32_t reg; 269 uint8_t ui[8]; 270 271/* OHCI version */ 272 reg = OREAD(sc, OHCI_VERSION); 273 mver = (reg >> 16) & 0xff; 274 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 275 mver, reg & 0xff, (reg>>24) & 1); 276 if (mver < 1 || mver > 9) { 277 device_printf(dev, "invalid OHCI version\n"); 278 return (ENXIO); 279 } 280 281/* Available Isochronous DMA channel probe */ 282 OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 283 OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 284 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 285 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 286 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 287 for (i = 0; i < 0x20; i++) 288 if ((reg & (1 << i)) == 0) 289 break; 290 device_printf(dev, "No. of Isochronous channels is %d.\n", i); 291 if (i == 0) 292 return (ENXIO); 293 294#if 0 295/* SID receive buffer must align 2^11 */ 296#define OHCI_SIDSIZE (1 << 11) 297 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 298 &sc->sid_dma, BUS_DMA_WAITOK); 299 if (sc->sid_buf == NULL) { 300 device_printf(dev, "sid_buf alloc failed."); 301 return ENOMEM; 302 } 303#endif 304 305 sc->eui.hi = OREAD(sc, FWOHCIGUID_H); 306 sc->eui.lo = OREAD(sc, FWOHCIGUID_L); 307 for( i = 0 ; i < 8 ; i ++) 308 ui[i] = FW_EUI64_BYTE(&sc->eui,i); 309 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 310 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 311 fwohci_reset(sc, dev); 312 313 return 0; 314} 315 316void 317fwohci_ibr(struct fwohci_softc *sc) 318{ 319 uint32_t fun; 320 321 device_printf(sc->dev, "Initiate bus reset\n"); 322 323 /* 324 * Make sure our cached values from the config rom are 325 * initialised. 326 */ 327 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); 328 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); 329 330 /* 331 * Set root hold-off bit so that non cyclemaster capable node 332 * shouldn't became the root node. 333 */ 334#if 1 335 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 336 fun |= FW_PHY_IBR; 337 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 338#else /* Short bus reset */ 339 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 340 fun |= FW_PHY_ISBR; 341 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 342#endif 343} 344 345 346void 347fwohci_sid(struct fwohci_softc *sc) 348{ 349 uint32_t node_id; 350 int plen; 351 352 node_id = OREAD(sc, FWOHCI_NODEID); 353 if (!(node_id & OHCI_NODE_VALID)) { 354#if 0 355 printf("Bus reset failure\n"); 356#endif 357 return; 358 } 359 360 /* Enable bus reset interrupt */ 361 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 362 /* Allow async. request to us */ 363 OWRITE(sc, OHCI_AREQHI, 1 << 31); 364 /* XXX insecure ?? */ 365 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 366 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 367 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 368 /* Set ATRetries register */ 369 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 370/* 371** Checking whether the node is root or not. If root, turn on 372** cycle master. 373*/ 374 plen = OREAD(sc, OHCI_SID_CNT); 375 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 376 node_id, (plen >> 16) & 0xff); 377 if (node_id & OHCI_NODE_ROOT) { 378 device_printf(sc->dev, "CYCLEMASTER mode\n"); 379 OWRITE(sc, OHCI_LNKCTL, 380 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 381 } else { 382 device_printf(sc->dev, "non CYCLEMASTER mode\n"); 383 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 384 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 385 } 386 if (plen & OHCI_SID_ERR) { 387 device_printf(fc->dev, "SID Error\n"); 388 return; 389 } 390 device_printf(sc->dev, "bus reset phase done\n"); 391 sc->state = FWOHCI_STATE_NORMAL; 392} 393 394static void 395fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 396{ 397#undef OHCI_DEBUG 398#ifdef OHCI_DEBUG 399#if 0 400 if(stat & OREAD(sc, FWOHCI_INTMASK)) 401#else 402 if (1) 403#endif 404 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 405 stat & OHCI_INT_EN ? "DMA_EN ":"", 406 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 407 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 408 stat & OHCI_INT_ERR ? "INT_ERR ":"", 409 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 410 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 411 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 412 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 413 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 414 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 415 stat & OHCI_INT_PHY_SID ? "SID ":"", 416 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 417 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 418 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 419 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 420 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 421 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 422 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 423 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 424 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 425 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 426 stat, OREAD(sc, FWOHCI_INTMASK) 427 ); 428#endif 429/* Bus reset */ 430 if(stat & OHCI_INT_PHY_BUS_R ){ 431 device_printf(fc->dev, "BUS reset\n"); 432 if (sc->state == FWOHCI_STATE_BUSRESET) 433 goto busresetout; 434 sc->state = FWOHCI_STATE_BUSRESET; 435 /* Disable bus reset interrupt until sid recv. */ 436 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 437 438 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 439 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 440 441 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); 442 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); 443 } else if (sc->state == FWOHCI_STATE_BUSRESET) { 444 fwohci_sid(sc); 445 } 446busresetout: 447 return; 448} 449 450static uint32_t 451fwochi_check_stat(struct fwohci_softc *sc) 452{ 453 uint32_t stat; 454 455 stat = OREAD(sc, FWOHCI_INTSTAT); 456 if (stat == 0xffffffff) { 457 device_printf(sc->fc.dev, 458 "device physically ejected?\n"); 459 return(stat); 460 } 461 if (stat) 462 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 463 return(stat); 464} 465 466void 467fwohci_poll(struct fwohci_softc *sc) 468{ 469 uint32_t stat; 470 471 stat = fwochi_check_stat(sc); 472 if (stat != 0xffffffff) 473 fwohci_intr_body(sc, stat, 1); 474} 475