1170101Ssimokawa/* 2170101Ssimokawa * Copyright (c) 2003 Hidetoshi Shimokawa 3170101Ssimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4170101Ssimokawa * All rights reserved. 5170101Ssimokawa * 6170101Ssimokawa * Redistribution and use in source and binary forms, with or without 7170101Ssimokawa * modification, are permitted provided that the following conditions 8170101Ssimokawa * are met: 9170101Ssimokawa * 1. Redistributions of source code must retain the above copyright 10170101Ssimokawa * notice, this list of conditions and the following disclaimer. 11170101Ssimokawa * 2. Redistributions in binary form must reproduce the above copyright 12170101Ssimokawa * notice, this list of conditions and the following disclaimer in the 13170101Ssimokawa * documentation and/or other materials provided with the distribution. 14170101Ssimokawa * 3. All advertising materials mentioning features or use of this software 15170101Ssimokawa * must display the acknowledgement as bellow: 16170101Ssimokawa * 17170101Ssimokawa * This product includes software developed by K. Kobayashi and H. Shimokawa 18170101Ssimokawa * 19170101Ssimokawa * 4. The name of the author may not be used to endorse or promote products 20170101Ssimokawa * derived from this software without specific prior written permission. 21170101Ssimokawa * 22170101Ssimokawa * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23170101Ssimokawa * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24170101Ssimokawa * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25170101Ssimokawa * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26170101Ssimokawa * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27170101Ssimokawa * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28170101Ssimokawa * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29170101Ssimokawa * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30170101Ssimokawa * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31170101Ssimokawa * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32170101Ssimokawa * POSSIBILITY OF SUCH DAMAGE. 33170101Ssimokawa * 34170101Ssimokawa * $FreeBSD: stable/11/stand/i386/libfirewire/fwohci.c 332156 2018-04-06 21:50:09Z kevans $ 35170101Ssimokawa * 36170101Ssimokawa */ 37170101Ssimokawa 38170101Ssimokawa#include <stand.h> 39170101Ssimokawa#include <btxv86.h> 40170101Ssimokawa#include <bootstrap.h> 41170101Ssimokawa 42332156Skevans#include <dev/firewire/firewire.h> 43170101Ssimokawa#include "fwohci.h" 44332156Skevans#include <dev/firewire/fwohcireg.h> 45170101Ssimokawa#include <dev/firewire/firewire_phy.h> 46170101Ssimokawa 47170101Ssimokawastatic uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t); 48170101Ssimokawastatic uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t); 49170101Ssimokawaint firewire_debug=0; 50170101Ssimokawa 51170101Ssimokawa#if 0 52170101Ssimokawa#define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__) 53170101Ssimokawa#else 54170101Ssimokawa#define device_printf(a, x, ...) 55170101Ssimokawa#endif 56170101Ssimokawa 57170101Ssimokawa#define device_t int 58170101Ssimokawa#define DELAY(x) delay(x) 59170101Ssimokawa 60170101Ssimokawa#define MAX_SPEED 3 61170101Ssimokawa#define MAXREC(x) (2 << (x)) 62170101Ssimokawachar *linkspeed[] = { 63170101Ssimokawa "S100", "S200", "S400", "S800", 64170101Ssimokawa "S1600", "S3200", "undef", "undef" 65170101Ssimokawa}; 66170101Ssimokawa 67170101Ssimokawa/* 68170101Ssimokawa * Communication with PHY device 69170101Ssimokawa */ 70170101Ssimokawastatic uint32_t 71170101Ssimokawafwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data) 72170101Ssimokawa{ 73170101Ssimokawa uint32_t fun; 74170101Ssimokawa 75170101Ssimokawa addr &= 0xf; 76170101Ssimokawa data &= 0xff; 77170101Ssimokawa 78170101Ssimokawa fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 79170101Ssimokawa OWRITE(sc, OHCI_PHYACCESS, fun); 80170101Ssimokawa DELAY(100); 81170101Ssimokawa 82170101Ssimokawa return(fwphy_rddata( sc, addr)); 83170101Ssimokawa} 84170101Ssimokawa 85170101Ssimokawastatic uint32_t 86170101Ssimokawafwphy_rddata(struct fwohci_softc *sc, u_int addr) 87170101Ssimokawa{ 88170101Ssimokawa uint32_t fun, stat; 89170101Ssimokawa u_int i, retry = 0; 90170101Ssimokawa 91170101Ssimokawa addr &= 0xf; 92170101Ssimokawa#define MAX_RETRY 100 93170101Ssimokawaagain: 94170101Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 95170101Ssimokawa fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 96170101Ssimokawa OWRITE(sc, OHCI_PHYACCESS, fun); 97170101Ssimokawa for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 98170101Ssimokawa fun = OREAD(sc, OHCI_PHYACCESS); 99170101Ssimokawa if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 100170101Ssimokawa break; 101170101Ssimokawa DELAY(100); 102170101Ssimokawa } 103170101Ssimokawa if(i >= MAX_RETRY) { 104170101Ssimokawa if (firewire_debug) 105170101Ssimokawa device_printf(sc->fc.dev, "phy read failed(1).\n"); 106170101Ssimokawa if (++retry < MAX_RETRY) { 107170101Ssimokawa DELAY(100); 108170101Ssimokawa goto again; 109170101Ssimokawa } 110170101Ssimokawa } 111170101Ssimokawa /* Make sure that SCLK is started */ 112170101Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 113170101Ssimokawa if ((stat & OHCI_INT_REG_FAIL) != 0 || 114170101Ssimokawa ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 115170101Ssimokawa if (firewire_debug) 116170101Ssimokawa device_printf(sc->fc.dev, "phy read failed(2).\n"); 117170101Ssimokawa if (++retry < MAX_RETRY) { 118170101Ssimokawa DELAY(100); 119170101Ssimokawa goto again; 120170101Ssimokawa } 121170101Ssimokawa } 122170101Ssimokawa if (firewire_debug || retry >= MAX_RETRY) 123170101Ssimokawa device_printf(sc->fc.dev, 124170101Ssimokawa "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); 125170101Ssimokawa#undef MAX_RETRY 126170101Ssimokawa return((fun >> PHYDEV_RDDATA )& 0xff); 127170101Ssimokawa} 128170101Ssimokawa 129170101Ssimokawa 130170101Ssimokawastatic int 131170101Ssimokawafwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 132170101Ssimokawa{ 133170101Ssimokawa uint32_t reg, reg2; 134170101Ssimokawa int e1394a = 1; 135170101Ssimokawa int nport, speed; 136170101Ssimokawa/* 137170101Ssimokawa * probe PHY parameters 138170101Ssimokawa * 0. to prove PHY version, whether compliance of 1394a. 139170101Ssimokawa * 1. to probe maximum speed supported by the PHY and 140170101Ssimokawa * number of port supported by core-logic. 141170101Ssimokawa * It is not actually available port on your PC . 142170101Ssimokawa */ 143170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 144170101Ssimokawa DELAY(500); 145170101Ssimokawa 146170101Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 147170101Ssimokawa 148170101Ssimokawa if((reg >> 5) != 7 ){ 149170101Ssimokawa nport = reg & FW_PHY_NP; 150170101Ssimokawa speed = reg & FW_PHY_SPD >> 6; 151170101Ssimokawa if (speed > MAX_SPEED) { 152170101Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 153170101Ssimokawa speed, MAX_SPEED); 154170101Ssimokawa speed = MAX_SPEED; 155170101Ssimokawa } 156170101Ssimokawa device_printf(dev, 157170101Ssimokawa "Phy 1394 only %s, %d ports.\n", 158170101Ssimokawa linkspeed[speed], nport); 159170101Ssimokawa }else{ 160170101Ssimokawa reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 161170101Ssimokawa nport = reg & FW_PHY_NP; 162170101Ssimokawa speed = (reg2 & FW_PHY_ESPD) >> 5; 163170101Ssimokawa if (speed > MAX_SPEED) { 164170101Ssimokawa device_printf(dev, "invalid speed %d (fixed to %d).\n", 165170101Ssimokawa speed, MAX_SPEED); 166170101Ssimokawa speed = MAX_SPEED; 167170101Ssimokawa } 168170101Ssimokawa device_printf(dev, 169170101Ssimokawa "Phy 1394a available %s, %d ports.\n", 170170101Ssimokawa linkspeed[speed], nport); 171170101Ssimokawa 172170101Ssimokawa /* check programPhyEnable */ 173170101Ssimokawa reg2 = fwphy_rddata(sc, 5); 174170101Ssimokawa#if 0 175170101Ssimokawa if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 176170101Ssimokawa#else /* XXX force to enable 1394a */ 177170101Ssimokawa if (e1394a) { 178170101Ssimokawa#endif 179170101Ssimokawa if (firewire_debug) 180170101Ssimokawa device_printf(dev, 181170101Ssimokawa "Enable 1394a Enhancements\n"); 182170101Ssimokawa /* enable EAA EMC */ 183170101Ssimokawa reg2 |= 0x03; 184170101Ssimokawa /* set aPhyEnhanceEnable */ 185170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 186170101Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 187170101Ssimokawa } else { 188170101Ssimokawa /* for safe */ 189170101Ssimokawa reg2 &= ~0x83; 190170101Ssimokawa } 191170101Ssimokawa reg2 = fwphy_wrdata(sc, 5, reg2); 192170101Ssimokawa } 193170101Ssimokawa sc->speed = speed; 194170101Ssimokawa 195170101Ssimokawa reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 196170101Ssimokawa if((reg >> 5) == 7 ){ 197170101Ssimokawa reg = fwphy_rddata(sc, 4); 198170101Ssimokawa reg |= 1 << 6; 199170101Ssimokawa fwphy_wrdata(sc, 4, reg); 200170101Ssimokawa reg = fwphy_rddata(sc, 4); 201170101Ssimokawa } 202170101Ssimokawa return 0; 203170101Ssimokawa} 204170101Ssimokawa 205170101Ssimokawa 206170101Ssimokawavoid 207170101Ssimokawafwohci_reset(struct fwohci_softc *sc, device_t dev) 208170101Ssimokawa{ 209170101Ssimokawa int i, max_rec, speed; 210170101Ssimokawa uint32_t reg, reg2; 211170101Ssimokawa 212170101Ssimokawa /* Disable interrupts */ 213170101Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 214170101Ssimokawa 215298826Spfg /* FLUSH FIFO and reset Transmitter/Receiver */ 216170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 217170101Ssimokawa if (firewire_debug) 218170101Ssimokawa device_printf(dev, "resetting OHCI..."); 219170101Ssimokawa i = 0; 220170101Ssimokawa while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 221170101Ssimokawa if (i++ > 100) break; 222170101Ssimokawa DELAY(1000); 223170101Ssimokawa } 224170101Ssimokawa if (firewire_debug) 225170101Ssimokawa printf("done (loop=%d)\n", i); 226170101Ssimokawa 227170101Ssimokawa /* Probe phy */ 228170101Ssimokawa fwohci_probe_phy(sc, dev); 229170101Ssimokawa 230170101Ssimokawa /* Probe link */ 231170101Ssimokawa reg = OREAD(sc, OHCI_BUS_OPT); 232170101Ssimokawa reg2 = reg | OHCI_BUSFNC; 233170101Ssimokawa max_rec = (reg & 0x0000f000) >> 12; 234170101Ssimokawa speed = (reg & 0x00000007); 235170101Ssimokawa device_printf(dev, "Link %s, max_rec %d bytes.\n", 236170101Ssimokawa linkspeed[speed], MAXREC(max_rec)); 237170101Ssimokawa /* XXX fix max_rec */ 238170101Ssimokawa sc->maxrec = sc->speed + 8; 239170101Ssimokawa if (max_rec != sc->maxrec) { 240170101Ssimokawa reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12); 241170101Ssimokawa device_printf(dev, "max_rec %d -> %d\n", 242170101Ssimokawa MAXREC(max_rec), MAXREC(sc->maxrec)); 243170101Ssimokawa } 244170101Ssimokawa if (firewire_debug) 245170101Ssimokawa device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 246170101Ssimokawa OWRITE(sc, OHCI_BUS_OPT, reg2); 247170101Ssimokawa 248170101Ssimokawa /* Initialize registers */ 249170101Ssimokawa OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]); 250170101Ssimokawa OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom)); 251170101Ssimokawa#if 0 252170101Ssimokawa OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); 253170101Ssimokawa#endif 254170101Ssimokawa OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 255170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 256170101Ssimokawa#if 0 257170101Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 258170101Ssimokawa#endif 259170101Ssimokawa 260170101Ssimokawa /* Enable link */ 261170101Ssimokawa OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 262170101Ssimokawa} 263170101Ssimokawa 264170101Ssimokawaint 265170101Ssimokawafwohci_init(struct fwohci_softc *sc, device_t dev) 266170101Ssimokawa{ 267170101Ssimokawa int i, mver; 268170101Ssimokawa uint32_t reg; 269170101Ssimokawa uint8_t ui[8]; 270170101Ssimokawa 271170101Ssimokawa/* OHCI version */ 272170101Ssimokawa reg = OREAD(sc, OHCI_VERSION); 273170101Ssimokawa mver = (reg >> 16) & 0xff; 274170101Ssimokawa device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 275170101Ssimokawa mver, reg & 0xff, (reg>>24) & 1); 276170101Ssimokawa if (mver < 1 || mver > 9) { 277170101Ssimokawa device_printf(dev, "invalid OHCI version\n"); 278170101Ssimokawa return (ENXIO); 279170101Ssimokawa } 280170101Ssimokawa 281170101Ssimokawa/* Available Isochronous DMA channel probe */ 282170101Ssimokawa OWRITE(sc, OHCI_IT_MASK, 0xffffffff); 283170101Ssimokawa OWRITE(sc, OHCI_IR_MASK, 0xffffffff); 284170101Ssimokawa reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); 285170101Ssimokawa OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); 286170101Ssimokawa OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); 287170101Ssimokawa for (i = 0; i < 0x20; i++) 288170101Ssimokawa if ((reg & (1 << i)) == 0) 289170101Ssimokawa break; 290170101Ssimokawa device_printf(dev, "No. of Isochronous channels is %d.\n", i); 291170101Ssimokawa if (i == 0) 292170101Ssimokawa return (ENXIO); 293170101Ssimokawa 294170101Ssimokawa#if 0 295298826Spfg/* SID receive buffer must align 2^11 */ 296170101Ssimokawa#define OHCI_SIDSIZE (1 << 11) 297170101Ssimokawa sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, 298170101Ssimokawa &sc->sid_dma, BUS_DMA_WAITOK); 299170101Ssimokawa if (sc->sid_buf == NULL) { 300170101Ssimokawa device_printf(dev, "sid_buf alloc failed."); 301170101Ssimokawa return ENOMEM; 302170101Ssimokawa } 303170101Ssimokawa#endif 304170101Ssimokawa 305170101Ssimokawa sc->eui.hi = OREAD(sc, FWOHCIGUID_H); 306170101Ssimokawa sc->eui.lo = OREAD(sc, FWOHCIGUID_L); 307170101Ssimokawa for( i = 0 ; i < 8 ; i ++) 308170101Ssimokawa ui[i] = FW_EUI64_BYTE(&sc->eui,i); 309170101Ssimokawa device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 310170101Ssimokawa ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); 311170101Ssimokawa fwohci_reset(sc, dev); 312170101Ssimokawa 313170101Ssimokawa return 0; 314170101Ssimokawa} 315170101Ssimokawa 316170101Ssimokawavoid 317170101Ssimokawafwohci_ibr(struct fwohci_softc *sc) 318170101Ssimokawa{ 319170101Ssimokawa uint32_t fun; 320170101Ssimokawa 321170101Ssimokawa device_printf(sc->dev, "Initiate bus reset\n"); 322170101Ssimokawa 323170101Ssimokawa /* 324170101Ssimokawa * Make sure our cached values from the config rom are 325170101Ssimokawa * initialised. 326170101Ssimokawa */ 327170101Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); 328170101Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); 329170101Ssimokawa 330170101Ssimokawa /* 331170101Ssimokawa * Set root hold-off bit so that non cyclemaster capable node 332170101Ssimokawa * shouldn't became the root node. 333170101Ssimokawa */ 334170101Ssimokawa#if 1 335170101Ssimokawa fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 336170101Ssimokawa fun |= FW_PHY_IBR; 337170101Ssimokawa fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 338170101Ssimokawa#else /* Short bus reset */ 339170101Ssimokawa fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 340170101Ssimokawa fun |= FW_PHY_ISBR; 341170101Ssimokawa fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 342170101Ssimokawa#endif 343170101Ssimokawa} 344170101Ssimokawa 345170101Ssimokawa 346170101Ssimokawavoid 347170101Ssimokawafwohci_sid(struct fwohci_softc *sc) 348170101Ssimokawa{ 349170101Ssimokawa uint32_t node_id; 350170101Ssimokawa int plen; 351170101Ssimokawa 352170101Ssimokawa node_id = OREAD(sc, FWOHCI_NODEID); 353170101Ssimokawa if (!(node_id & OHCI_NODE_VALID)) { 354170101Ssimokawa#if 0 355170101Ssimokawa printf("Bus reset failure\n"); 356170101Ssimokawa#endif 357170101Ssimokawa return; 358170101Ssimokawa } 359170101Ssimokawa 360170101Ssimokawa /* Enable bus reset interrupt */ 361170101Ssimokawa OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 362170101Ssimokawa /* Allow async. request to us */ 363170101Ssimokawa OWRITE(sc, OHCI_AREQHI, 1 << 31); 364170101Ssimokawa /* XXX insecure ?? */ 365170101Ssimokawa OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 366170101Ssimokawa OWRITE(sc, OHCI_PREQLO, 0xffffffff); 367170101Ssimokawa OWRITE(sc, OHCI_PREQUPPER, 0x10000); 368170101Ssimokawa /* Set ATRetries register */ 369170101Ssimokawa OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 370170101Ssimokawa/* 371170101Ssimokawa** Checking whether the node is root or not. If root, turn on 372170101Ssimokawa** cycle master. 373170101Ssimokawa*/ 374170101Ssimokawa plen = OREAD(sc, OHCI_SID_CNT); 375170101Ssimokawa device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", 376170101Ssimokawa node_id, (plen >> 16) & 0xff); 377170101Ssimokawa if (node_id & OHCI_NODE_ROOT) { 378170101Ssimokawa device_printf(sc->dev, "CYCLEMASTER mode\n"); 379170101Ssimokawa OWRITE(sc, OHCI_LNKCTL, 380170101Ssimokawa OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 381170101Ssimokawa } else { 382170101Ssimokawa device_printf(sc->dev, "non CYCLEMASTER mode\n"); 383170101Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 384170101Ssimokawa OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 385170101Ssimokawa } 386170101Ssimokawa if (plen & OHCI_SID_ERR) { 387170101Ssimokawa device_printf(fc->dev, "SID Error\n"); 388170101Ssimokawa return; 389170101Ssimokawa } 390170101Ssimokawa device_printf(sc->dev, "bus reset phase done\n"); 391170101Ssimokawa sc->state = FWOHCI_STATE_NORMAL; 392170101Ssimokawa} 393170101Ssimokawa 394170101Ssimokawastatic void 395170101Ssimokawafwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count) 396170101Ssimokawa{ 397170101Ssimokawa#undef OHCI_DEBUG 398170101Ssimokawa#ifdef OHCI_DEBUG 399170101Ssimokawa#if 0 400170101Ssimokawa if(stat & OREAD(sc, FWOHCI_INTMASK)) 401170101Ssimokawa#else 402170101Ssimokawa if (1) 403170101Ssimokawa#endif 404170101Ssimokawa device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 405170101Ssimokawa stat & OHCI_INT_EN ? "DMA_EN ":"", 406170101Ssimokawa stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 407170101Ssimokawa stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 408170101Ssimokawa stat & OHCI_INT_ERR ? "INT_ERR ":"", 409170101Ssimokawa stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 410170101Ssimokawa stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 411170101Ssimokawa stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 412170101Ssimokawa stat & OHCI_INT_CYC_START ? "CYC_START ":"", 413170101Ssimokawa stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 414170101Ssimokawa stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 415170101Ssimokawa stat & OHCI_INT_PHY_SID ? "SID ":"", 416170101Ssimokawa stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 417170101Ssimokawa stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 418170101Ssimokawa stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 419170101Ssimokawa stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 420170101Ssimokawa stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 421170101Ssimokawa stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 422170101Ssimokawa stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 423170101Ssimokawa stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 424170101Ssimokawa stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 425170101Ssimokawa stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 426170101Ssimokawa stat, OREAD(sc, FWOHCI_INTMASK) 427170101Ssimokawa ); 428170101Ssimokawa#endif 429170101Ssimokawa/* Bus reset */ 430170101Ssimokawa if(stat & OHCI_INT_PHY_BUS_R ){ 431170101Ssimokawa device_printf(fc->dev, "BUS reset\n"); 432170101Ssimokawa if (sc->state == FWOHCI_STATE_BUSRESET) 433170101Ssimokawa goto busresetout; 434170101Ssimokawa sc->state = FWOHCI_STATE_BUSRESET; 435170101Ssimokawa /* Disable bus reset interrupt until sid recv. */ 436170101Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); 437170101Ssimokawa 438170101Ssimokawa OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 439170101Ssimokawa OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 440170101Ssimokawa 441170101Ssimokawa OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0])); 442170101Ssimokawa OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2])); 443170101Ssimokawa } else if (sc->state == FWOHCI_STATE_BUSRESET) { 444170101Ssimokawa fwohci_sid(sc); 445170101Ssimokawa } 446170101Ssimokawabusresetout: 447170101Ssimokawa return; 448170101Ssimokawa} 449170101Ssimokawa 450170101Ssimokawastatic uint32_t 451170101Ssimokawafwochi_check_stat(struct fwohci_softc *sc) 452170101Ssimokawa{ 453170101Ssimokawa uint32_t stat; 454170101Ssimokawa 455170101Ssimokawa stat = OREAD(sc, FWOHCI_INTSTAT); 456170101Ssimokawa if (stat == 0xffffffff) { 457170101Ssimokawa device_printf(sc->fc.dev, 458170101Ssimokawa "device physically ejected?\n"); 459170101Ssimokawa return(stat); 460170101Ssimokawa } 461170101Ssimokawa if (stat) 462170101Ssimokawa OWRITE(sc, FWOHCI_INTSTATCLR, stat); 463170101Ssimokawa return(stat); 464170101Ssimokawa} 465170101Ssimokawa 466170101Ssimokawavoid 467170101Ssimokawafwohci_poll(struct fwohci_softc *sc) 468170101Ssimokawa{ 469170101Ssimokawa uint32_t stat; 470170101Ssimokawa 471170101Ssimokawa stat = fwochi_check_stat(sc); 472170101Ssimokawa if (stat != 0xffffffff) 473170101Ssimokawa fwohci_intr_body(sc, stat, 1); 474170101Ssimokawa} 475