sha512-ia64.pl revision 160814
1#!/usr/bin/env perl 2# 3# ==================================================================== 4# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL 5# project. Rights for redistribution and usage in source and binary 6# forms are granted according to the OpenSSL license. 7# ==================================================================== 8# 9# SHA256/512_Transform for Itanium. 10# 11# sha512_block runs in 1003 cycles on Itanium 2, which is almost 50% 12# faster than gcc and >60%(!) faster than code generated by HP-UX 13# compiler (yes, HP-UX is generating slower code, because unlike gcc, 14# it failed to deploy "shift right pair," 'shrp' instruction, which 15# substitutes for 64-bit rotate). 16# 17# 924 cycles long sha256_block outperforms gcc by over factor of 2(!) 18# and HP-UX compiler - by >40% (yes, gcc won sha512_block, but lost 19# this one big time). Note that "formally" 924 is about 100 cycles 20# too much. I mean it's 64 32-bit rounds vs. 80 virtually identical 21# 64-bit ones and 1003*64/80 gives 802. Extra cycles, 2 per round, 22# are spent on extra work to provide for 32-bit rotations. 32-bit 23# rotations are still handled by 'shrp' instruction and for this 24# reason lower 32 bits are deposited to upper half of 64-bit register 25# prior 'shrp' issue. And in order to minimize the amount of such 26# operations, X[16] values are *maintained* with copies of lower 27# halves in upper halves, which is why you'll spot such instructions 28# as custom 'mux2', "parallel 32-bit add," 'padd4' and "parallel 29# 32-bit unsigned right shift," 'pshr4.u' instructions here. 30# 31# Rules of engagement. 32# 33# There is only one integer shifter meaning that if I have two rotate, 34# deposit or extract instructions in adjacent bundles, they shall 35# split [at run-time if they have to]. But note that variable and 36# parallel shifts are performed by multi-media ALU and *are* pairable 37# with rotates [and alike]. On the backside MMALU is rather slow: it 38# takes 2 extra cycles before the result of integer operation is 39# available *to* MMALU and 2(*) extra cycles before the result of MM 40# operation is available "back" *to* integer ALU, not to mention that 41# MMALU itself has 2 cycles latency. However! I explicitly scheduled 42# these MM instructions to avoid MM stalls, so that all these extra 43# latencies get "hidden" in instruction-level parallelism. 44# 45# (*) 2 cycles on Itanium 1 and 1 cycle on Itanium 2. But I schedule 46# for 2 in order to provide for best *overall* performance, 47# because on Itanium 1 stall on MM result is accompanied by 48# pipeline flush, which takes 6 cycles:-( 49# 50# Resulting performance numbers for 900MHz Itanium 2 system: 51# 52# The 'numbers' are in 1000s of bytes per second processed. 53# type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes 54# sha1(*) 6210.14k 20376.30k 52447.83k 85870.05k 105478.12k 55# sha256 7476.45k 20572.05k 41538.34k 56062.29k 62093.18k 56# sha512 4996.56k 20026.28k 47597.20k 85278.79k 111501.31k 57# 58# (*) SHA1 numbers are for HP-UX compiler and are presented purely 59# for reference purposes. I bet it can improved too... 60# 61# To generate code, pass the file name with either 256 or 512 in its 62# name and compiler flags. 63 64$output=shift; 65 66if ($output =~ /512.*\.[s|asm]/) { 67 $SZ=8; 68 $BITS=8*$SZ; 69 $LDW="ld8"; 70 $STW="st8"; 71 $ADD="add"; 72 $SHRU="shr.u"; 73 $TABLE="K512"; 74 $func="sha512_block"; 75 @Sigma0=(28,34,39); 76 @Sigma1=(14,18,41); 77 @sigma0=(1, 8, 7); 78 @sigma1=(19,61, 6); 79 $rounds=80; 80} elsif ($output =~ /256.*\.[s|asm]/) { 81 $SZ=4; 82 $BITS=8*$SZ; 83 $LDW="ld4"; 84 $STW="st4"; 85 $ADD="padd4"; 86 $SHRU="pshr4.u"; 87 $TABLE="K256"; 88 $func="sha256_block"; 89 @Sigma0=( 2,13,22); 90 @Sigma1=( 6,11,25); 91 @sigma0=( 7,18, 3); 92 @sigma1=(17,19,10); 93 $rounds=64; 94} else { die "nonsense $output"; } 95 96open STDOUT,">$output" || die "can't open $output: $!"; 97 98if ($^O eq "hpux") { 99 $ADDP="addp4"; 100 for (@ARGV) { $ADDP="add" if (/[\+DD|\-mlp]64/); } 101} else { $ADDP="add"; } 102for (@ARGV) { $big_endian=1 if (/\-DB_ENDIAN/); 103 $big_endian=0 if (/\-DL_ENDIAN/); } 104if (!defined($big_endian)) 105 { $big_endian=(unpack('L',pack('N',1))==1); } 106 107$code=<<___; 108.ident \"$output, version 1.0\" 109.ident \"IA-64 ISA artwork by Andy Polyakov <appro\@fy.chalmers.se>\" 110.explicit 111.text 112 113prsave=r14; 114K=r15; 115A=r16; B=r17; C=r18; D=r19; 116E=r20; F=r21; G=r22; H=r23; 117T1=r24; T2=r25; 118s0=r26; s1=r27; t0=r28; t1=r29; 119Ktbl=r30; 120ctx=r31; // 1st arg 121input=r48; // 2nd arg 122num=r49; // 3rd arg 123sgm0=r50; sgm1=r51; // small constants 124 125// void $func (SHA_CTX *ctx, const void *in,size_t num[,int host]) 126.global $func# 127.proc $func# 128.align 32 129$func: 130 .prologue 131 .fframe 0 132 .save ar.pfs,r2 133 .save ar.lc,r3 134 .save pr,prsave 135{ .mmi; alloc r2=ar.pfs,3,17,0,16 136 $ADDP ctx=0,r32 // 1st arg 137 mov r3=ar.lc } 138{ .mmi; $ADDP input=0,r33 // 2nd arg 139 addl Ktbl=\@ltoff($TABLE#),gp 140 mov prsave=pr };; 141 142 .body 143{ .mii; ld8 Ktbl=[Ktbl] 144 mov num=r34 };; // 3rd arg 145 146{ .mib; add r8=0*$SZ,ctx 147 add r9=1*$SZ,ctx 148 brp.loop.imp .L_first16,.L_first16_ctop 149 } 150{ .mib; add r10=2*$SZ,ctx 151 add r11=3*$SZ,ctx 152 brp.loop.imp .L_rest,.L_rest_ctop 153 };; 154// load A-H 155{ .mmi; $LDW A=[r8],4*$SZ 156 $LDW B=[r9],4*$SZ 157 mov sgm0=$sigma0[2] } 158{ .mmi; $LDW C=[r10],4*$SZ 159 $LDW D=[r11],4*$SZ 160 mov sgm1=$sigma1[2] };; 161{ .mmi; $LDW E=[r8] 162 $LDW F=[r9] } 163{ .mmi; $LDW G=[r10] 164 $LDW H=[r11] 165 cmp.ne p15,p14=0,r35 };; // used in sha256_block 166 167.L_outer: 168{ .mii; mov ar.lc=15 169 mov ar.ec=1 };; 170.align 32 171.L_first16: 172.rotr X[16] 173___ 174$t0="t0", $t1="t1", $code.=<<___ if ($BITS==32); 175{ .mib; (p14) add r9=1,input 176 (p14) add r10=2,input } 177{ .mib; (p14) add r11=3,input 178 (p15) br.dptk.few .L_host };; 179{ .mmi; (p14) ld1 r8=[input],$SZ 180 (p14) ld1 r9=[r9] } 181{ .mmi; (p14) ld1 r10=[r10] 182 (p14) ld1 r11=[r11] };; 183{ .mii; (p14) dep r9=r8,r9,8,8 184 (p14) dep r11=r10,r11,8,8 };; 185{ .mib; (p14) dep X[15]=r9,r11,16,16 };; 186.L_host: 187{ .mib; (p15) $LDW X[15]=[input],$SZ // X[i]=*input++ 188 dep.z $t1=E,32,32 } 189{ .mib; $LDW K=[Ktbl],$SZ 190 zxt4 E=E };; 191{ .mmi; or $t1=$t1,E 192 and T1=F,E 193 and T2=A,B } 194{ .mmi; andcm r8=G,E 195 and r9=A,C 196 mux2 $t0=A,0x44 };; // copy lower half to upper 197{ .mib; xor T1=T1,r8 // T1=((e & f) ^ (~e & g)) 198 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14) 199{ .mib; and r10=B,C 200 xor T2=T2,r9 };; 201___ 202$t0="A", $t1="E", $code.=<<___ if ($BITS==64); 203{ .mmi; $LDW X[15]=[input],$SZ // X[i]=*input++ 204 and T1=F,E 205 and T2=A,B } 206{ .mmi; $LDW K=[Ktbl],$SZ 207 andcm r8=G,E 208 and r9=A,C };; 209{ .mmi; xor T1=T1,r8 //T1=((e & f) ^ (~e & g)) 210 and r10=B,C 211 _rotr r11=$t1,$Sigma1[0] } // ROTR(e,14) 212{ .mmi; xor T2=T2,r9 213 mux1 X[15]=X[15],\@rev };; // eliminated in big-endian 214___ 215$code.=<<___; 216{ .mib; add T1=T1,H // T1=Ch(e,f,g)+h 217 _rotr r8=$t1,$Sigma1[1] } // ROTR(e,18) 218{ .mib; xor T2=T2,r10 // T2=((a & b) ^ (a & c) ^ (b & c)) 219 mov H=G };; 220{ .mib; xor r11=r8,r11 221 _rotr r9=$t1,$Sigma1[2] } // ROTR(e,41) 222{ .mib; mov G=F 223 mov F=E };; 224{ .mib; xor r9=r9,r11 // r9=Sigma1(e) 225 _rotr r10=$t0,$Sigma0[0] } // ROTR(a,28) 226{ .mib; add T1=T1,K // T1=Ch(e,f,g)+h+K512[i] 227 mov E=D };; 228{ .mib; add T1=T1,r9 // T1+=Sigma1(e) 229 _rotr r11=$t0,$Sigma0[1] } // ROTR(a,34) 230{ .mib; mov D=C 231 mov C=B };; 232{ .mib; add T1=T1,X[15] // T1+=X[i] 233 _rotr r8=$t0,$Sigma0[2] } // ROTR(a,39) 234{ .mib; xor r10=r10,r11 235 mux2 X[15]=X[15],0x44 };; // eliminated in 64-bit 236{ .mmi; xor r10=r8,r10 // r10=Sigma0(a) 237 mov B=A 238 add A=T1,T2 };; 239.L_first16_ctop: 240{ .mib; add E=E,T1 241 add A=A,r10 // T2=Maj(a,b,c)+Sigma0(a) 242 br.ctop.sptk .L_first16 };; 243 244{ .mib; mov ar.lc=$rounds-17 } 245{ .mib; mov ar.ec=1 };; 246.align 32 247.L_rest: 248.rotr X[16] 249{ .mib; $LDW K=[Ktbl],$SZ 250 _rotr r8=X[15-1],$sigma0[0] } // ROTR(s0,1) 251{ .mib; $ADD X[15]=X[15],X[15-9] // X[i&0xF]+=X[(i+9)&0xF] 252 $SHRU s0=X[15-1],sgm0 };; // s0=X[(i+1)&0xF]>>7 253{ .mib; and T1=F,E 254 _rotr r9=X[15-1],$sigma0[1] } // ROTR(s0,8) 255{ .mib; andcm r10=G,E 256 $SHRU s1=X[15-14],sgm1 };; // s1=X[(i+14)&0xF]>>6 257{ .mmi; xor T1=T1,r10 // T1=((e & f) ^ (~e & g)) 258 xor r9=r8,r9 259 _rotr r10=X[15-14],$sigma1[0] };;// ROTR(s1,19) 260{ .mib; and T2=A,B 261 _rotr r11=X[15-14],$sigma1[1] }// ROTR(s1,61) 262{ .mib; and r8=A,C };; 263___ 264$t0="t0", $t1="t1", $code.=<<___ if ($BITS==32); 265// I adhere to mmi; in order to hold Itanium 1 back and avoid 6 cycle 266// pipeline flush in last bundle. Note that even on Itanium2 the 267// latter stalls for one clock cycle... 268{ .mmi; xor s0=s0,r9 // s0=sigma0(X[(i+1)&0xF]) 269 dep.z $t1=E,32,32 } 270{ .mmi; xor r10=r11,r10 271 zxt4 E=E };; 272{ .mmi; or $t1=$t1,E 273 xor s1=s1,r10 // s1=sigma1(X[(i+14)&0xF]) 274 mux2 $t0=A,0x44 };; // copy lower half to upper 275{ .mmi; xor T2=T2,r8 276 _rotr r9=$t1,$Sigma1[0] } // ROTR(e,14) 277{ .mmi; and r10=B,C 278 add T1=T1,H // T1=Ch(e,f,g)+h 279 $ADD X[15]=X[15],s0 };; // X[i&0xF]+=sigma0(X[(i+1)&0xF]) 280___ 281$t0="A", $t1="E", $code.=<<___ if ($BITS==64); 282{ .mib; xor s0=s0,r9 // s0=sigma0(X[(i+1)&0xF]) 283 _rotr r9=$t1,$Sigma1[0] } // ROTR(e,14) 284{ .mib; xor r10=r11,r10 285 xor T2=T2,r8 };; 286{ .mib; xor s1=s1,r10 // s1=sigma1(X[(i+14)&0xF]) 287 add T1=T1,H } 288{ .mib; and r10=B,C 289 $ADD X[15]=X[15],s0 };; // X[i&0xF]+=sigma0(X[(i+1)&0xF]) 290___ 291$code.=<<___; 292{ .mmi; xor T2=T2,r10 // T2=((a & b) ^ (a & c) ^ (b & c)) 293 mov H=G 294 _rotr r8=$t1,$Sigma1[1] };; // ROTR(e,18) 295{ .mmi; xor r11=r8,r9 296 $ADD X[15]=X[15],s1 // X[i&0xF]+=sigma1(X[(i+14)&0xF]) 297 _rotr r9=$t1,$Sigma1[2] } // ROTR(e,41) 298{ .mmi; mov G=F 299 mov F=E };; 300{ .mib; xor r9=r9,r11 // r9=Sigma1(e) 301 _rotr r10=$t0,$Sigma0[0] } // ROTR(a,28) 302{ .mib; add T1=T1,K // T1=Ch(e,f,g)+h+K512[i] 303 mov E=D };; 304{ .mib; add T1=T1,r9 // T1+=Sigma1(e) 305 _rotr r11=$t0,$Sigma0[1] } // ROTR(a,34) 306{ .mib; mov D=C 307 mov C=B };; 308{ .mmi; add T1=T1,X[15] // T1+=X[i] 309 xor r10=r10,r11 310 _rotr r8=$t0,$Sigma0[2] };; // ROTR(a,39) 311{ .mmi; xor r10=r8,r10 // r10=Sigma0(a) 312 mov B=A 313 add A=T1,T2 };; 314.L_rest_ctop: 315{ .mib; add E=E,T1 316 add A=A,r10 // T2=Maj(a,b,c)+Sigma0(a) 317 br.ctop.sptk .L_rest };; 318 319{ .mib; add r8=0*$SZ,ctx 320 add r9=1*$SZ,ctx } 321{ .mib; add r10=2*$SZ,ctx 322 add r11=3*$SZ,ctx };; 323{ .mmi; $LDW r32=[r8],4*$SZ 324 $LDW r33=[r9],4*$SZ } 325{ .mmi; $LDW r34=[r10],4*$SZ 326 $LDW r35=[r11],4*$SZ 327 cmp.ltu p6,p7=1,num };; 328{ .mmi; $LDW r36=[r8],-4*$SZ 329 $LDW r37=[r9],-4*$SZ 330(p6) add Ktbl=-$SZ*$rounds,Ktbl } 331{ .mmi; $LDW r38=[r10],-4*$SZ 332 $LDW r39=[r11],-4*$SZ 333(p7) mov ar.lc=r3 };; 334{ .mmi; add A=A,r32 335 add B=B,r33 336 add C=C,r34 } 337{ .mmi; add D=D,r35 338 add E=E,r36 339 add F=F,r37 };; 340{ .mmi; $STW [r8]=A,4*$SZ 341 $STW [r9]=B,4*$SZ 342 add G=G,r38 } 343{ .mmi; $STW [r10]=C,4*$SZ 344 $STW [r11]=D,4*$SZ 345 add H=H,r39 };; 346{ .mmi; $STW [r8]=E 347 $STW [r9]=F 348(p6) add num=-1,num } 349{ .mmb; $STW [r10]=G 350 $STW [r11]=H 351(p6) br.dptk.many .L_outer };; 352 353{ .mib; mov pr=prsave,0x1ffff 354 br.ret.sptk.many b0 };; 355.endp $func# 356___ 357 358$code =~ s/\`([^\`]*)\`/eval $1/gem; 359$code =~ s/_rotr(\s+)([^=]+)=([^,]+),([0-9]+)/shrp$1$2=$3,$3,$4/gm; 360if ($BITS==64) { 361 $code =~ s/mux2(\s+)\S+/nop.i$1 0x0/gm; 362 $code =~ s/mux1(\s+)\S+/nop.i$1 0x0/gm if ($big_endian); 363} 364 365print $code; 366 367print<<___ if ($BITS==32); 368.align 64 369.type K256#,\@object 370K256: data4 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5 371 data4 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5 372 data4 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3 373 data4 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174 374 data4 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc 375 data4 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da 376 data4 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7 377 data4 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967 378 data4 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13 379 data4 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85 380 data4 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3 381 data4 0xd192e819,0xd6990624,0xf40e3585,0x106aa070 382 data4 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5 383 data4 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3 384 data4 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208 385 data4 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2 386.size K256#,$SZ*$rounds 387___ 388print<<___ if ($BITS==64); 389.align 64 390.type K512#,\@object 391K512: data8 0x428a2f98d728ae22,0x7137449123ef65cd 392 data8 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc 393 data8 0x3956c25bf348b538,0x59f111f1b605d019 394 data8 0x923f82a4af194f9b,0xab1c5ed5da6d8118 395 data8 0xd807aa98a3030242,0x12835b0145706fbe 396 data8 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2 397 data8 0x72be5d74f27b896f,0x80deb1fe3b1696b1 398 data8 0x9bdc06a725c71235,0xc19bf174cf692694 399 data8 0xe49b69c19ef14ad2,0xefbe4786384f25e3 400 data8 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65 401 data8 0x2de92c6f592b0275,0x4a7484aa6ea6e483 402 data8 0x5cb0a9dcbd41fbd4,0x76f988da831153b5 403 data8 0x983e5152ee66dfab,0xa831c66d2db43210 404 data8 0xb00327c898fb213f,0xbf597fc7beef0ee4 405 data8 0xc6e00bf33da88fc2,0xd5a79147930aa725 406 data8 0x06ca6351e003826f,0x142929670a0e6e70 407 data8 0x27b70a8546d22ffc,0x2e1b21385c26c926 408 data8 0x4d2c6dfc5ac42aed,0x53380d139d95b3df 409 data8 0x650a73548baf63de,0x766a0abb3c77b2a8 410 data8 0x81c2c92e47edaee6,0x92722c851482353b 411 data8 0xa2bfe8a14cf10364,0xa81a664bbc423001 412 data8 0xc24b8b70d0f89791,0xc76c51a30654be30 413 data8 0xd192e819d6ef5218,0xd69906245565a910 414 data8 0xf40e35855771202a,0x106aa07032bbd1b8 415 data8 0x19a4c116b8d2d0c8,0x1e376c085141ab53 416 data8 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8 417 data8 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb 418 data8 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3 419 data8 0x748f82ee5defb2fc,0x78a5636f43172f60 420 data8 0x84c87814a1f0ab72,0x8cc702081a6439ec 421 data8 0x90befffa23631e28,0xa4506cebde82bde9 422 data8 0xbef9a3f7b2c67915,0xc67178f2e372532b 423 data8 0xca273eceea26619c,0xd186b8c721c0c207 424 data8 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178 425 data8 0x06f067aa72176fba,0x0a637dc5a2c898a6 426 data8 0x113f9804bef90dae,0x1b710b35131c471b 427 data8 0x28db77f523047d84,0x32caab7b40c72493 428 data8 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c 429 data8 0x4cc5d4becb3e42b6,0x597f299cfc657e2a 430 data8 0x5fcb6fab3ad6faec,0x6c44198c4a475817 431.size K512#,$SZ*$rounds 432___ 433