WebAssemblyTargetMachine.cpp revision 314564 
1//===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// \brief This file defines the WebAssembly-specific subclass of TargetMachine.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssembly.h"
16#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17#include "WebAssemblyTargetMachine.h"
18#include "WebAssemblyTargetObjectFile.h"
19#include "WebAssemblyTargetTransformInfo.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/Passes.h"
22#include "llvm/CodeGen/RegAllocRegistry.h"
23#include "llvm/CodeGen/TargetPassConfig.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/TargetRegistry.h"
26#include "llvm/Target/TargetOptions.h"
27#include "llvm/Transforms/Scalar.h"
28using namespace llvm;
29
30#define DEBUG_TYPE "wasm"
31
32// Emscripten's asm.js-style exception handling
33static cl::opt<bool> EnableEmException(
34    "enable-emscripten-cxx-exceptions",
35    cl::desc("WebAssembly Emscripten-style exception handling"),
36    cl::init(false));
37
38// Emscripten's asm.js-style setjmp/longjmp handling
39static cl::opt<bool> EnableEmSjLj(
40    "enable-emscripten-sjlj",
41    cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
42    cl::init(false));
43
44extern "C" void LLVMInitializeWebAssemblyTarget() {
45  // Register the target.
46  RegisterTargetMachine<WebAssemblyTargetMachine> X(
47      getTheWebAssemblyTarget32());
48  RegisterTargetMachine<WebAssemblyTargetMachine> Y(
49      getTheWebAssemblyTarget64());
50
51  // Register exception handling pass to opt
52  initializeWebAssemblyLowerEmscriptenEHSjLjPass(
53      *PassRegistry::getPassRegistry());
54}
55
56//===----------------------------------------------------------------------===//
57// WebAssembly Lowering public interface.
58//===----------------------------------------------------------------------===//
59
60static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
61  if (!RM.hasValue())
62    return Reloc::PIC_;
63  return *RM;
64}
65
66/// Create an WebAssembly architecture model.
67///
68WebAssemblyTargetMachine::WebAssemblyTargetMachine(
69    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
70    const TargetOptions &Options, Optional<Reloc::Model> RM,
71    CodeModel::Model CM, CodeGenOpt::Level OL)
72    : LLVMTargetMachine(T,
73                        TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
74                                         : "e-m:e-p:32:32-i64:64-n32:64-S128",
75                        TT, CPU, FS, Options, getEffectiveRelocModel(RM),
76                        CM, OL),
77      TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
78  // WebAssembly type-checks instructions, but a noreturn function with a return
79  // type that doesn't match the context will cause a check failure. So we lower
80  // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
81  // 'unreachable' instructions which is meant for that case.
82  this->Options.TrapUnreachable = true;
83
84  initAsmInfo();
85
86  // Note that we don't use setRequiresStructuredCFG(true). It disables
87  // optimizations than we're ok with, and want, such as critical edge
88  // splitting and tail merging.
89}
90
91WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
92
93const WebAssemblySubtarget *
94WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
95  Attribute CPUAttr = F.getFnAttribute("target-cpu");
96  Attribute FSAttr = F.getFnAttribute("target-features");
97
98  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
99                        ? CPUAttr.getValueAsString().str()
100                        : TargetCPU;
101  std::string FS = !FSAttr.hasAttribute(Attribute::None)
102                       ? FSAttr.getValueAsString().str()
103                       : TargetFS;
104
105  auto &I = SubtargetMap[CPU + FS];
106  if (!I) {
107    // This needs to be done before we create a new subtarget since any
108    // creation will depend on the TM and the code generation flags on the
109    // function that reside in TargetOptions.
110    resetTargetOptions(F);
111    I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
112  }
113  return I.get();
114}
115
116namespace {
117/// WebAssembly Code Generator Pass Configuration Options.
118class WebAssemblyPassConfig final : public TargetPassConfig {
119public:
120  WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
121      : TargetPassConfig(TM, PM) {}
122
123  WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
124    return getTM<WebAssemblyTargetMachine>();
125  }
126
127  FunctionPass *createTargetRegisterAllocator(bool) override;
128
129  void addIRPasses() override;
130  bool addInstSelector() override;
131  void addPostRegAlloc() override;
132  bool addGCPasses() override { return false; }
133  void addPreEmitPass() override;
134};
135} // end anonymous namespace
136
137TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
138  return TargetIRAnalysis([this](const Function &F) {
139    return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
140  });
141}
142
143TargetPassConfig *
144WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
145  return new WebAssemblyPassConfig(this, PM);
146}
147
148FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
149  return nullptr; // No reg alloc
150}
151
152//===----------------------------------------------------------------------===//
153// The following functions are called from lib/CodeGen/Passes.cpp to modify
154// the CodeGen pass sequence.
155//===----------------------------------------------------------------------===//
156
157void WebAssemblyPassConfig::addIRPasses() {
158  if (TM->Options.ThreadModel == ThreadModel::Single)
159    // In "single" mode, atomics get lowered to non-atomics.
160    addPass(createLowerAtomicPass());
161  else
162    // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
163    // control specifically what gets lowered.
164    addPass(createAtomicExpandPass(TM));
165
166  // Fix function bitcasts, as WebAssembly requires caller and callee signatures
167  // to match.
168  addPass(createWebAssemblyFixFunctionBitcasts());
169
170  // Optimize "returned" function attributes.
171  if (getOptLevel() != CodeGenOpt::None)
172    addPass(createWebAssemblyOptimizeReturned());
173
174  // If exception handling is not enabled and setjmp/longjmp handling is
175  // enabled, we lower invokes into calls and delete unreachable landingpad
176  // blocks. Lowering invokes when there is no EH support is done in
177  // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
178  // function and SjLj handling expects all invokes to be lowered before.
179  if (!EnableEmException) {
180    addPass(createLowerInvokePass());
181    // The lower invoke pass may create unreachable code. Remove it in order not
182    // to process dead blocks in setjmp/longjmp handling.
183    addPass(createUnreachableBlockEliminationPass());
184  }
185
186  // Handle exceptions and setjmp/longjmp if enabled.
187  if (EnableEmException || EnableEmSjLj)
188    addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
189                                                   EnableEmSjLj));
190
191  TargetPassConfig::addIRPasses();
192}
193
194bool WebAssemblyPassConfig::addInstSelector() {
195  (void)TargetPassConfig::addInstSelector();
196  addPass(
197      createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
198  // Run the argument-move pass immediately after the ScheduleDAG scheduler
199  // so that we can fix up the ARGUMENT instructions before anything else
200  // sees them in the wrong place.
201  addPass(createWebAssemblyArgumentMove());
202  // Set the p2align operands. This information is present during ISel, however
203  // it's inconvenient to collect. Collect it now, and update the immediate
204  // operands.
205  addPass(createWebAssemblySetP2AlignOperands());
206  return false;
207}
208
209void WebAssemblyPassConfig::addPostRegAlloc() {
210  // TODO: The following CodeGen passes don't currently support code containing
211  // virtual registers. Consider removing their restrictions and re-enabling
212  // them.
213
214  // Has no asserts of its own, but was not written to handle virtual regs.
215  disablePass(&ShrinkWrapID);
216
217  // These functions all require the NoVRegs property.
218  disablePass(&MachineCopyPropagationID);
219  disablePass(&PostRASchedulerID);
220  disablePass(&FuncletLayoutID);
221  disablePass(&StackMapLivenessID);
222  disablePass(&LiveDebugValuesID);
223  disablePass(&PatchableFunctionID);
224
225  TargetPassConfig::addPostRegAlloc();
226}
227
228void WebAssemblyPassConfig::addPreEmitPass() {
229  TargetPassConfig::addPreEmitPass();
230
231  // Now that we have a prologue and epilogue and all frame indices are
232  // rewritten, eliminate SP and FP. This allows them to be stackified,
233  // colored, and numbered with the rest of the registers.
234  addPass(createWebAssemblyReplacePhysRegs());
235
236  // Rewrite pseudo call_indirect instructions as real instructions.
237  // This needs to run before register stackification, because we change the
238  // order of the arguments.
239  addPass(createWebAssemblyCallIndirectFixup());
240
241  if (getOptLevel() != CodeGenOpt::None) {
242    // LiveIntervals isn't commonly run this late. Re-establish preconditions.
243    addPass(createWebAssemblyPrepareForLiveIntervals());
244
245    // Depend on LiveIntervals and perform some optimizations on it.
246    addPass(createWebAssemblyOptimizeLiveIntervals());
247
248    // Prepare store instructions for register stackifying.
249    addPass(createWebAssemblyStoreResults());
250
251    // Mark registers as representing wasm's value stack. This is a key
252    // code-compression technique in WebAssembly. We run this pass (and
253    // StoreResults above) very late, so that it sees as much code as possible,
254    // including code emitted by PEI and expanded by late tail duplication.
255    addPass(createWebAssemblyRegStackify());
256
257    // Run the register coloring pass to reduce the total number of registers.
258    // This runs after stackification so that it doesn't consider registers
259    // that become stackified.
260    addPass(createWebAssemblyRegColoring());
261  }
262
263  // Insert explicit get_local and set_local operators.
264  addPass(createWebAssemblyExplicitLocals());
265
266  // Eliminate multiple-entry loops.
267  addPass(createWebAssemblyFixIrreducibleControlFlow());
268
269  // Put the CFG in structured form; insert BLOCK and LOOP markers.
270  addPass(createWebAssemblyCFGStackify());
271
272  // Lower br_unless into br_if.
273  addPass(createWebAssemblyLowerBrUnless());
274
275  // Perform the very last peephole optimizations on the code.
276  if (getOptLevel() != CodeGenOpt::None)
277    addPass(createWebAssemblyPeephole());
278
279  // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
280  addPass(createWebAssemblyRegNumbering());
281}
282