1//===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the WebAssembly-specific subclass of TargetMachine.
11///
12//===----------------------------------------------------------------------===//
13
14#include "WebAssemblyTargetMachine.h"
15#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
16#include "TargetInfo/WebAssemblyTargetInfo.h"
17#include "WebAssembly.h"
18#include "WebAssemblyMachineFunctionInfo.h"
19#include "WebAssemblyTargetObjectFile.h"
20#include "WebAssemblyTargetTransformInfo.h"
21#include "llvm/CodeGen/MIRParser/MIParser.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/Passes.h"
24#include "llvm/CodeGen/RegAllocRegistry.h"
25#include "llvm/CodeGen/TargetPassConfig.h"
26#include "llvm/IR/Function.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Target/TargetOptions.h"
29#include "llvm/Transforms/Scalar.h"
30#include "llvm/Transforms/Scalar/LowerAtomic.h"
31#include "llvm/Transforms/Utils.h"
32using namespace llvm;
33
34#define DEBUG_TYPE "wasm"
35
36// Emscripten's asm.js-style exception handling
37static cl::opt<bool> EnableEmException(
38    "enable-emscripten-cxx-exceptions",
39    cl::desc("WebAssembly Emscripten-style exception handling"),
40    cl::init(false));
41
42// Emscripten's asm.js-style setjmp/longjmp handling
43static cl::opt<bool> EnableEmSjLj(
44    "enable-emscripten-sjlj",
45    cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
46    cl::init(false));
47
48extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget() {
49  // Register the target.
50  RegisterTargetMachine<WebAssemblyTargetMachine> X(
51      getTheWebAssemblyTarget32());
52  RegisterTargetMachine<WebAssemblyTargetMachine> Y(
53      getTheWebAssemblyTarget64());
54
55  // Register backend passes
56  auto &PR = *PassRegistry::getPassRegistry();
57  initializeWebAssemblyAddMissingPrototypesPass(PR);
58  initializeWebAssemblyLowerEmscriptenEHSjLjPass(PR);
59  initializeLowerGlobalDtorsPass(PR);
60  initializeFixFunctionBitcastsPass(PR);
61  initializeOptimizeReturnedPass(PR);
62  initializeWebAssemblyArgumentMovePass(PR);
63  initializeWebAssemblySetP2AlignOperandsPass(PR);
64  initializeWebAssemblyReplacePhysRegsPass(PR);
65  initializeWebAssemblyPrepareForLiveIntervalsPass(PR);
66  initializeWebAssemblyOptimizeLiveIntervalsPass(PR);
67  initializeWebAssemblyMemIntrinsicResultsPass(PR);
68  initializeWebAssemblyRegStackifyPass(PR);
69  initializeWebAssemblyRegColoringPass(PR);
70  initializeWebAssemblyFixIrreducibleControlFlowPass(PR);
71  initializeWebAssemblyLateEHPreparePass(PR);
72  initializeWebAssemblyExceptionInfoPass(PR);
73  initializeWebAssemblyCFGSortPass(PR);
74  initializeWebAssemblyCFGStackifyPass(PR);
75  initializeWebAssemblyExplicitLocalsPass(PR);
76  initializeWebAssemblyLowerBrUnlessPass(PR);
77  initializeWebAssemblyRegNumberingPass(PR);
78  initializeWebAssemblyPeepholePass(PR);
79  initializeWebAssemblyCallIndirectFixupPass(PR);
80}
81
82//===----------------------------------------------------------------------===//
83// WebAssembly Lowering public interface.
84//===----------------------------------------------------------------------===//
85
86static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM,
87                                           const Triple &TT) {
88  if (!RM.hasValue()) {
89    // Default to static relocation model.  This should always be more optimial
90    // than PIC since the static linker can determine all global addresses and
91    // assume direct function calls.
92    return Reloc::Static;
93  }
94
95  if (!TT.isOSEmscripten()) {
96    // Relocation modes other than static are currently implemented in a way
97    // that only works for Emscripten, so disable them if we aren't targeting
98    // Emscripten.
99    return Reloc::Static;
100  }
101
102  return *RM;
103}
104
105/// Create an WebAssembly architecture model.
106///
107WebAssemblyTargetMachine::WebAssemblyTargetMachine(
108    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
109    const TargetOptions &Options, Optional<Reloc::Model> RM,
110    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
111    : LLVMTargetMachine(T,
112                        TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128"
113                                         : "e-m:e-p:32:32-i64:64-n32:64-S128",
114                        TT, CPU, FS, Options, getEffectiveRelocModel(RM, TT),
115                        getEffectiveCodeModel(CM, CodeModel::Large), OL),
116      TLOF(new WebAssemblyTargetObjectFile()) {
117  // WebAssembly type-checks instructions, but a noreturn function with a return
118  // type that doesn't match the context will cause a check failure. So we lower
119  // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
120  // 'unreachable' instructions which is meant for that case.
121  this->Options.TrapUnreachable = true;
122
123  // WebAssembly treats each function as an independent unit. Force
124  // -ffunction-sections, effectively, so that we can emit them independently.
125  this->Options.FunctionSections = true;
126  this->Options.DataSections = true;
127  this->Options.UniqueSectionNames = true;
128
129  initAsmInfo();
130
131  // Note that we don't use setRequiresStructuredCFG(true). It disables
132  // optimizations than we're ok with, and want, such as critical edge
133  // splitting and tail merging.
134}
135
136WebAssemblyTargetMachine::~WebAssemblyTargetMachine() = default; // anchor.
137
138const WebAssemblySubtarget *
139WebAssemblyTargetMachine::getSubtargetImpl(std::string CPU,
140                                           std::string FS) const {
141  auto &I = SubtargetMap[CPU + FS];
142  if (!I) {
143    I = std::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
144  }
145  return I.get();
146}
147
148const WebAssemblySubtarget *
149WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
150  Attribute CPUAttr = F.getFnAttribute("target-cpu");
151  Attribute FSAttr = F.getFnAttribute("target-features");
152
153  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
154                        ? CPUAttr.getValueAsString().str()
155                        : TargetCPU;
156  std::string FS = !FSAttr.hasAttribute(Attribute::None)
157                       ? FSAttr.getValueAsString().str()
158                       : TargetFS;
159
160  // This needs to be done before we create a new subtarget since any
161  // creation will depend on the TM and the code generation flags on the
162  // function that reside in TargetOptions.
163  resetTargetOptions(F);
164
165  return getSubtargetImpl(CPU, FS);
166}
167
168namespace {
169
170class CoalesceFeaturesAndStripAtomics final : public ModulePass {
171  // Take the union of all features used in the module and use it for each
172  // function individually, since having multiple feature sets in one module
173  // currently does not make sense for WebAssembly. If atomics are not enabled,
174  // also strip atomic operations and thread local storage.
175  static char ID;
176  WebAssemblyTargetMachine *WasmTM;
177
178public:
179  CoalesceFeaturesAndStripAtomics(WebAssemblyTargetMachine *WasmTM)
180      : ModulePass(ID), WasmTM(WasmTM) {}
181
182  bool runOnModule(Module &M) override {
183    FeatureBitset Features = coalesceFeatures(M);
184
185    std::string FeatureStr = getFeatureString(Features);
186    for (auto &F : M)
187      replaceFeatures(F, FeatureStr);
188
189    bool StrippedAtomics = false;
190    bool StrippedTLS = false;
191
192    if (!Features[WebAssembly::FeatureAtomics])
193      StrippedAtomics = stripAtomics(M);
194
195    if (!Features[WebAssembly::FeatureBulkMemory])
196      StrippedTLS = stripThreadLocals(M);
197
198    if (StrippedAtomics && !StrippedTLS)
199      stripThreadLocals(M);
200    else if (StrippedTLS && !StrippedAtomics)
201      stripAtomics(M);
202
203    recordFeatures(M, Features, StrippedAtomics || StrippedTLS);
204
205    // Conservatively assume we have made some change
206    return true;
207  }
208
209private:
210  FeatureBitset coalesceFeatures(const Module &M) {
211    FeatureBitset Features =
212        WasmTM
213            ->getSubtargetImpl(WasmTM->getTargetCPU(),
214                               WasmTM->getTargetFeatureString())
215            ->getFeatureBits();
216    for (auto &F : M)
217      Features |= WasmTM->getSubtargetImpl(F)->getFeatureBits();
218    return Features;
219  }
220
221  std::string getFeatureString(const FeatureBitset &Features) {
222    std::string Ret;
223    for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
224      if (Features[KV.Value])
225        Ret += (StringRef("+") + KV.Key + ",").str();
226    }
227    return Ret;
228  }
229
230  void replaceFeatures(Function &F, const std::string &Features) {
231    F.removeFnAttr("target-features");
232    F.removeFnAttr("target-cpu");
233    F.addFnAttr("target-features", Features);
234  }
235
236  bool stripAtomics(Module &M) {
237    // Detect whether any atomics will be lowered, since there is no way to tell
238    // whether the LowerAtomic pass lowers e.g. stores.
239    bool Stripped = false;
240    for (auto &F : M) {
241      for (auto &B : F) {
242        for (auto &I : B) {
243          if (I.isAtomic()) {
244            Stripped = true;
245            goto done;
246          }
247        }
248      }
249    }
250
251  done:
252    if (!Stripped)
253      return false;
254
255    LowerAtomicPass Lowerer;
256    FunctionAnalysisManager FAM;
257    for (auto &F : M)
258      Lowerer.run(F, FAM);
259
260    return true;
261  }
262
263  bool stripThreadLocals(Module &M) {
264    bool Stripped = false;
265    for (auto &GV : M.globals()) {
266      if (GV.getThreadLocalMode() !=
267          GlobalValue::ThreadLocalMode::NotThreadLocal) {
268        Stripped = true;
269        GV.setThreadLocalMode(GlobalValue::ThreadLocalMode::NotThreadLocal);
270      }
271    }
272    return Stripped;
273  }
274
275  void recordFeatures(Module &M, const FeatureBitset &Features, bool Stripped) {
276    for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
277      std::string MDKey = (StringRef("wasm-feature-") + KV.Key).str();
278      if (KV.Value == WebAssembly::FeatureAtomics && Stripped) {
279        // "atomics" is special: code compiled without atomics may have had its
280        // atomics lowered to nonatomic operations. In that case, atomics is
281        // disallowed to prevent unsafe linking with atomics-enabled objects.
282        assert(!Features[WebAssembly::FeatureAtomics] ||
283               !Features[WebAssembly::FeatureBulkMemory]);
284        M.addModuleFlag(Module::ModFlagBehavior::Error, MDKey,
285                        wasm::WASM_FEATURE_PREFIX_DISALLOWED);
286      } else if (Features[KV.Value]) {
287        // Otherwise features are marked Used or not mentioned
288        M.addModuleFlag(Module::ModFlagBehavior::Error, MDKey,
289                        wasm::WASM_FEATURE_PREFIX_USED);
290      }
291    }
292  }
293};
294char CoalesceFeaturesAndStripAtomics::ID = 0;
295
296/// WebAssembly Code Generator Pass Configuration Options.
297class WebAssemblyPassConfig final : public TargetPassConfig {
298public:
299  WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
300      : TargetPassConfig(TM, PM) {}
301
302  WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
303    return getTM<WebAssemblyTargetMachine>();
304  }
305
306  FunctionPass *createTargetRegisterAllocator(bool) override;
307
308  void addIRPasses() override;
309  bool addInstSelector() override;
310  void addPostRegAlloc() override;
311  bool addGCPasses() override { return false; }
312  void addPreEmitPass() override;
313
314  // No reg alloc
315  bool addRegAssignmentFast() override { return false; }
316
317  // No reg alloc
318  bool addRegAssignmentOptimized() override { return false; }
319};
320} // end anonymous namespace
321
322TargetTransformInfo
323WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) {
324  return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
325}
326
327TargetPassConfig *
328WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
329  return new WebAssemblyPassConfig(*this, PM);
330}
331
332FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
333  return nullptr; // No reg alloc
334}
335
336//===----------------------------------------------------------------------===//
337// The following functions are called from lib/CodeGen/Passes.cpp to modify
338// the CodeGen pass sequence.
339//===----------------------------------------------------------------------===//
340
341void WebAssemblyPassConfig::addIRPasses() {
342  // Runs LowerAtomicPass if necessary
343  addPass(new CoalesceFeaturesAndStripAtomics(&getWebAssemblyTargetMachine()));
344
345  // This is a no-op if atomics are not used in the module
346  addPass(createAtomicExpandPass());
347
348  // Add signatures to prototype-less function declarations
349  addPass(createWebAssemblyAddMissingPrototypes());
350
351  // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls.
352  addPass(createWebAssemblyLowerGlobalDtors());
353
354  // Fix function bitcasts, as WebAssembly requires caller and callee signatures
355  // to match.
356  addPass(createWebAssemblyFixFunctionBitcasts());
357
358  // Optimize "returned" function attributes.
359  if (getOptLevel() != CodeGenOpt::None)
360    addPass(createWebAssemblyOptimizeReturned());
361
362  // If exception handling is not enabled and setjmp/longjmp handling is
363  // enabled, we lower invokes into calls and delete unreachable landingpad
364  // blocks. Lowering invokes when there is no EH support is done in
365  // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
366  // function and SjLj handling expects all invokes to be lowered before.
367  if (!EnableEmException &&
368      TM->Options.ExceptionModel == ExceptionHandling::None) {
369    addPass(createLowerInvokePass());
370    // The lower invoke pass may create unreachable code. Remove it in order not
371    // to process dead blocks in setjmp/longjmp handling.
372    addPass(createUnreachableBlockEliminationPass());
373  }
374
375  // Handle exceptions and setjmp/longjmp if enabled.
376  if (EnableEmException || EnableEmSjLj)
377    addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
378                                                   EnableEmSjLj));
379
380  // Expand indirectbr instructions to switches.
381  addPass(createIndirectBrExpandPass());
382
383  TargetPassConfig::addIRPasses();
384}
385
386bool WebAssemblyPassConfig::addInstSelector() {
387  (void)TargetPassConfig::addInstSelector();
388  addPass(
389      createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
390  // Run the argument-move pass immediately after the ScheduleDAG scheduler
391  // so that we can fix up the ARGUMENT instructions before anything else
392  // sees them in the wrong place.
393  addPass(createWebAssemblyArgumentMove());
394  // Set the p2align operands. This information is present during ISel, however
395  // it's inconvenient to collect. Collect it now, and update the immediate
396  // operands.
397  addPass(createWebAssemblySetP2AlignOperands());
398  return false;
399}
400
401void WebAssemblyPassConfig::addPostRegAlloc() {
402  // TODO: The following CodeGen passes don't currently support code containing
403  // virtual registers. Consider removing their restrictions and re-enabling
404  // them.
405
406  // These functions all require the NoVRegs property.
407  disablePass(&MachineCopyPropagationID);
408  disablePass(&PostRAMachineSinkingID);
409  disablePass(&PostRASchedulerID);
410  disablePass(&FuncletLayoutID);
411  disablePass(&StackMapLivenessID);
412  disablePass(&LiveDebugValuesID);
413  disablePass(&PatchableFunctionID);
414  disablePass(&ShrinkWrapID);
415
416  // This pass hurts code size for wasm because it can generate irreducible
417  // control flow.
418  disablePass(&MachineBlockPlacementID);
419
420  TargetPassConfig::addPostRegAlloc();
421}
422
423void WebAssemblyPassConfig::addPreEmitPass() {
424  TargetPassConfig::addPreEmitPass();
425
426  // Rewrite pseudo call_indirect instructions as real instructions.
427  // This needs to run before register stackification, because we change the
428  // order of the arguments.
429  addPass(createWebAssemblyCallIndirectFixup());
430
431  // Eliminate multiple-entry loops.
432  addPass(createWebAssemblyFixIrreducibleControlFlow());
433
434  // Do various transformations for exception handling.
435  // Every CFG-changing optimizations should come before this.
436  addPass(createWebAssemblyLateEHPrepare());
437
438  // Now that we have a prologue and epilogue and all frame indices are
439  // rewritten, eliminate SP and FP. This allows them to be stackified,
440  // colored, and numbered with the rest of the registers.
441  addPass(createWebAssemblyReplacePhysRegs());
442
443  // Preparations and optimizations related to register stackification.
444  if (getOptLevel() != CodeGenOpt::None) {
445    // LiveIntervals isn't commonly run this late. Re-establish preconditions.
446    addPass(createWebAssemblyPrepareForLiveIntervals());
447
448    // Depend on LiveIntervals and perform some optimizations on it.
449    addPass(createWebAssemblyOptimizeLiveIntervals());
450
451    // Prepare memory intrinsic calls for register stackifying.
452    addPass(createWebAssemblyMemIntrinsicResults());
453
454    // Mark registers as representing wasm's value stack. This is a key
455    // code-compression technique in WebAssembly. We run this pass (and
456    // MemIntrinsicResults above) very late, so that it sees as much code as
457    // possible, including code emitted by PEI and expanded by late tail
458    // duplication.
459    addPass(createWebAssemblyRegStackify());
460
461    // Run the register coloring pass to reduce the total number of registers.
462    // This runs after stackification so that it doesn't consider registers
463    // that become stackified.
464    addPass(createWebAssemblyRegColoring());
465  }
466
467  // Sort the blocks of the CFG into topological order, a prerequisite for
468  // BLOCK and LOOP markers.
469  addPass(createWebAssemblyCFGSort());
470
471  // Insert BLOCK and LOOP markers.
472  addPass(createWebAssemblyCFGStackify());
473
474  // Insert explicit local.get and local.set operators.
475  addPass(createWebAssemblyExplicitLocals());
476
477  // Lower br_unless into br_if.
478  addPass(createWebAssemblyLowerBrUnless());
479
480  // Perform the very last peephole optimizations on the code.
481  if (getOptLevel() != CodeGenOpt::None)
482    addPass(createWebAssemblyPeephole());
483
484  // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
485  addPass(createWebAssemblyRegNumbering());
486}
487
488yaml::MachineFunctionInfo *
489WebAssemblyTargetMachine::createDefaultFuncInfoYAML() const {
490  return new yaml::WebAssemblyFunctionInfo();
491}
492
493yaml::MachineFunctionInfo *WebAssemblyTargetMachine::convertFuncInfoToYAML(
494    const MachineFunction &MF) const {
495  const auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
496  return new yaml::WebAssemblyFunctionInfo(*MFI);
497}
498
499bool WebAssemblyTargetMachine::parseMachineFunctionInfo(
500    const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
501    SMDiagnostic &Error, SMRange &SourceRange) const {
502  const auto &YamlMFI =
503      reinterpret_cast<const yaml::WebAssemblyFunctionInfo &>(MFI);
504  MachineFunction &MF = PFS.MF;
505  MF.getInfo<WebAssemblyFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
506  return false;
507}
508